| /linux-6.1.9/arch/alpha/lib/ |
| D | fpreg.c | 12 #define STT(reg,val) asm volatile ("ftoit $f"#reg",%0" : "=r"(val)); argument
14 #define STT(reg,val) asm volatile ("stt $f"#reg",%0" : "=m"(val)); argument
20 unsigned long val; in alpha_read_fp_reg() local
23 case 0: STT( 0, val); break; in alpha_read_fp_reg()
24 case 1: STT( 1, val); break; in alpha_read_fp_reg()
25 case 2: STT( 2, val); break; in alpha_read_fp_reg()
26 case 3: STT( 3, val); break; in alpha_read_fp_reg()
27 case 4: STT( 4, val); break; in alpha_read_fp_reg()
28 case 5: STT( 5, val); break; in alpha_read_fp_reg()
29 case 6: STT( 6, val); break; in alpha_read_fp_reg()
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| /linux-6.1.9/drivers/media/tuners/ |
| D | tda18271-maps.c | 19 u8 val; member
190 { .rfmax = 62000, .val = 0x00 },
191 { .rfmax = 84000, .val = 0x01 },
192 { .rfmax = 100000, .val = 0x02 },
193 { .rfmax = 140000, .val = 0x03 },
194 { .rfmax = 170000, .val = 0x04 },
195 { .rfmax = 180000, .val = 0x05 },
196 { .rfmax = 865000, .val = 0x06 },
197 { .rfmax = 0, .val = 0x00 }, /* end */
201 { .rfmax = 61100, .val = 0x74 },
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| /linux-6.1.9/drivers/hwtracing/coresight/ |
| D | coresight-etm-cp14.c | 15 int etm_readl_cp14(u32 reg, unsigned int *val) in etm_readl_cp14() argument
19 *val = etm_read(ETMCR); in etm_readl_cp14()
22 *val = etm_read(ETMCCR); in etm_readl_cp14()
25 *val = etm_read(ETMTRIGGER); in etm_readl_cp14()
28 *val = etm_read(ETMSR); in etm_readl_cp14()
31 *val = etm_read(ETMSCR); in etm_readl_cp14()
34 *val = etm_read(ETMTSSCR); in etm_readl_cp14()
37 *val = etm_read(ETMTEEVR); in etm_readl_cp14()
40 *val = etm_read(ETMTECR1); in etm_readl_cp14()
43 *val = etm_read(ETMFFLR); in etm_readl_cp14()
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| D | coresight-etm4x.h | 248 #define WRITE_ETM4x_REG(val, reg) \ argument
249 write_sysreg_s(val, ETM4x_REG_NUM_TO_SYSREG((reg)))
254 #define write_etm4x_sysreg_const_offset(val, offset) \ argument
255 WRITE_ETM4x_REG(val, ETM4x_OFFSET_TO_REG(offset))
260 #define CASE_WRITE(val, x) \ argument
261 case (x): { write_etm4x_sysreg_const_offset((val), (x)); break; }
266 #define ETE_ONLY_SYSREG_LIST(op, val) \ argument
267 CASE_##op((val), TRCRSR) \
268 CASE_##op((val), TRCEXTINSELRn(1)) \
269 CASE_##op((val), TRCEXTINSELRn(2)) \
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| /linux-6.1.9/arch/arm/include/asm/hardware/ |
| D | cp14.h | 12 #define dbg_write(val, reg) WCP14_##reg(val) argument
14 #define etm_write(val, reg) WCP14_##reg(val) argument
19 u32 val; \
20 asm volatile("mrc p14, "#op1", %0, "#crn", "#crm", "#op2 : "=r" (val)); \
21 val; \
24 #define MCR14(val, op1, crn, crm, op2) \ argument
26 asm volatile("mcr p14, "#op1", %0, "#crn", "#crm", "#op2 : : "r" (val));\
152 #define WCP14_DBGDTRTXint(val) MCR14(val, 0, c0, c5, 0) argument
153 #define WCP14_DBGWFAR(val) MCR14(val, 0, c0, c6, 0) argument
154 #define WCP14_DBGVCR(val) MCR14(val, 0, c0, c7, 0) argument
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| /linux-6.1.9/drivers/net/wireless/broadcom/brcm80211/brcmsmac/ |
| D | types.h | 133 #define CONF_HAS(config, val) ((config) & (1 << (val))) argument
138 #define CONF_IS(config, val) ((config) == (1 << (val))) argument
139 #define CONF_GE(config, val) ((config) & (0-(1 << (val)))) argument
140 #define CONF_GT(config, val) ((config) & (0-2*(1 << (val)))) argument
141 #define CONF_LT(config, val) ((config) & ((1 << (val))-1)) argument
142 #define CONF_LE(config, val) ((config) & (2*(1 << (val))-1)) argument
146 #define NCONF_HAS(val) CONF_HAS(NCONF, val) argument
148 #define NCONF_IS(val) CONF_IS(NCONF, val) argument
149 #define NCONF_GE(val) CONF_GE(NCONF, val) argument
150 #define NCONF_GT(val) CONF_GT(NCONF, val) argument
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| /linux-6.1.9/drivers/gpu/drm/msm/adreno/ |
| D | adreno_pm4.xml.h | 488 static inline uint32_t CP_LOAD_STATE_0_DST_OFF(uint32_t val) in CP_LOAD_STATE_0_DST_OFF() argument
490 return ((val) << CP_LOAD_STATE_0_DST_OFF__SHIFT) & CP_LOAD_STATE_0_DST_OFF__MASK; in CP_LOAD_STATE_0_DST_OFF()
494 static inline uint32_t CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val) in CP_LOAD_STATE_0_STATE_SRC() argument
496 return ((val) << CP_LOAD_STATE_0_STATE_SRC__SHIFT) & CP_LOAD_STATE_0_STATE_SRC__MASK; in CP_LOAD_STATE_0_STATE_SRC()
500 static inline uint32_t CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val) in CP_LOAD_STATE_0_STATE_BLOCK() argument
502 return ((val) << CP_LOAD_STATE_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE_0_STATE_BLOCK__MASK; in CP_LOAD_STATE_0_STATE_BLOCK()
506 static inline uint32_t CP_LOAD_STATE_0_NUM_UNIT(uint32_t val) in CP_LOAD_STATE_0_NUM_UNIT() argument
508 return ((val) << CP_LOAD_STATE_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE_0_NUM_UNIT__MASK; in CP_LOAD_STATE_0_NUM_UNIT()
514 static inline uint32_t CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val) in CP_LOAD_STATE_1_STATE_TYPE() argument
516 return ((val) << CP_LOAD_STATE_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE_1_STATE_TYPE__MASK; in CP_LOAD_STATE_1_STATE_TYPE()
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| D | a6xx.xml.h | 1079 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_RB_LO(uint32_t val) in A6XX_CP_ROQ_THRESHOLDS_1_RB_LO() argument
1081 …return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_RB_LO__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_RB_LO__MAS… in A6XX_CP_ROQ_THRESHOLDS_1_RB_LO()
1085 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_RB_HI(uint32_t val) in A6XX_CP_ROQ_THRESHOLDS_1_RB_HI() argument
1087 …return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_RB_HI__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_RB_HI__MAS… in A6XX_CP_ROQ_THRESHOLDS_1_RB_HI()
1091 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB1_START(uint32_t val) in A6XX_CP_ROQ_THRESHOLDS_1_IB1_START() argument
1093 …return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_IB1_ST… in A6XX_CP_ROQ_THRESHOLDS_1_IB1_START()
1097 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB2_START(uint32_t val) in A6XX_CP_ROQ_THRESHOLDS_1_IB2_START() argument
1099 …return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_IB2_ST… in A6XX_CP_ROQ_THRESHOLDS_1_IB2_START()
1105 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_2_SDS_START(uint32_t val) in A6XX_CP_ROQ_THRESHOLDS_2_SDS_START() argument
1107 …return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_2_SDS_ST… in A6XX_CP_ROQ_THRESHOLDS_2_SDS_START()
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| D | a3xx.xml.h | 947 static inline uint32_t A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES(uint32_t val) in A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES() argument
949 …return ((val) << A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES__SHIFT) & A3XX_GRAS_CL_CLIP_CNTL_NUM_… in A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES()
955 static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val) in A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ() argument
957 return ((val) << A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT) & A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK; in A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ()
961 static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val) in A3XX_GRAS_CL_GB_CLIP_ADJ_VERT() argument
963 return ((val) << A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT) & A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK; in A3XX_GRAS_CL_GB_CLIP_ADJ_VERT()
969 static inline uint32_t A3XX_GRAS_CL_VPORT_XOFFSET(float val) in A3XX_GRAS_CL_VPORT_XOFFSET() argument
971 return ((fui(val)) << A3XX_GRAS_CL_VPORT_XOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_XOFFSET__MASK; in A3XX_GRAS_CL_VPORT_XOFFSET()
977 static inline uint32_t A3XX_GRAS_CL_VPORT_XSCALE(float val) in A3XX_GRAS_CL_VPORT_XSCALE() argument
979 return ((fui(val)) << A3XX_GRAS_CL_VPORT_XSCALE__SHIFT) & A3XX_GRAS_CL_VPORT_XSCALE__MASK; in A3XX_GRAS_CL_VPORT_XSCALE()
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| D | a5xx.xml.h | 1043 static inline uint32_t A5XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val) in A5XX_CP_PROTECT_REG_BASE_ADDR() argument
1045 return ((val) << A5XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A5XX_CP_PROTECT_REG_BASE_ADDR__MASK; in A5XX_CP_PROTECT_REG_BASE_ADDR()
1049 static inline uint32_t A5XX_CP_PROTECT_REG_MASK_LEN(uint32_t val) in A5XX_CP_PROTECT_REG_MASK_LEN() argument
1051 return ((val) << A5XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A5XX_CP_PROTECT_REG_MASK_LEN__MASK; in A5XX_CP_PROTECT_REG_MASK_LEN()
1055 static inline uint32_t A5XX_CP_PROTECT_REG_TRAP_WRITE(uint32_t val) in A5XX_CP_PROTECT_REG_TRAP_WRITE() argument
1057 return ((val) << A5XX_CP_PROTECT_REG_TRAP_WRITE__SHIFT) & A5XX_CP_PROTECT_REG_TRAP_WRITE__MASK; in A5XX_CP_PROTECT_REG_TRAP_WRITE()
1061 static inline uint32_t A5XX_CP_PROTECT_REG_TRAP_READ(uint32_t val) in A5XX_CP_PROTECT_REG_TRAP_READ() argument
1063 return ((val) << A5XX_CP_PROTECT_REG_TRAP_READ__SHIFT) & A5XX_CP_PROTECT_REG_TRAP_READ__MASK; in A5XX_CP_PROTECT_REG_TRAP_READ()
1838 static inline uint32_t A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB(uint32_t val) in A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB() argument
1840 …return ((val) << A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB__SHIFT) & A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB__MA… in A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB()
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| D | a4xx.xml.h | 845 static inline uint32_t A4XX_CGC_HLSQ_EARLY_CYC(uint32_t val) in A4XX_CGC_HLSQ_EARLY_CYC() argument
847 return ((val) << A4XX_CGC_HLSQ_EARLY_CYC__SHIFT) & A4XX_CGC_HLSQ_EARLY_CYC__MASK; in A4XX_CGC_HLSQ_EARLY_CYC()
902 static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val) in A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH() argument
904 …return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_WID… in A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH()
908 static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val) in A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT() argument
910 …return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_HE… in A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT()
924 static inline uint32_t A4XX_RB_MODE_CONTROL_WIDTH(uint32_t val) in A4XX_RB_MODE_CONTROL_WIDTH() argument
926 return ((val >> 5) << A4XX_RB_MODE_CONTROL_WIDTH__SHIFT) & A4XX_RB_MODE_CONTROL_WIDTH__MASK; in A4XX_RB_MODE_CONTROL_WIDTH()
930 static inline uint32_t A4XX_RB_MODE_CONTROL_HEIGHT(uint32_t val) in A4XX_RB_MODE_CONTROL_HEIGHT() argument
932 return ((val >> 5) << A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT) & A4XX_RB_MODE_CONTROL_HEIGHT__MASK; in A4XX_RB_MODE_CONTROL_HEIGHT()
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| D | a2xx.xml.h | 1166 static inline uint32_t A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) in A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR() argument
1168 …return ((val) << A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHA… in A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR()
1172 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) in A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR() argument
1174 …return ((val) << A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHA… in A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR()
1178 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) in A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR() argument
1180 …return ((val) << A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BE… in A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR()
1184 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) in A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR() argument
1186 …return ((val) << A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BE… in A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR()
1190 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) in A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR() argument
1192 …return ((val) << A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BE… in A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR()
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| D | adreno_common.xml.h | 218 static inline uint32_t AXXX_CP_RB_CNTL_BUFSZ(uint32_t val) in AXXX_CP_RB_CNTL_BUFSZ() argument
220 return ((val) << AXXX_CP_RB_CNTL_BUFSZ__SHIFT) & AXXX_CP_RB_CNTL_BUFSZ__MASK; in AXXX_CP_RB_CNTL_BUFSZ()
224 static inline uint32_t AXXX_CP_RB_CNTL_BLKSZ(uint32_t val) in AXXX_CP_RB_CNTL_BLKSZ() argument
226 return ((val) << AXXX_CP_RB_CNTL_BLKSZ__SHIFT) & AXXX_CP_RB_CNTL_BLKSZ__MASK; in AXXX_CP_RB_CNTL_BLKSZ()
230 static inline uint32_t AXXX_CP_RB_CNTL_BUF_SWAP(uint32_t val) in AXXX_CP_RB_CNTL_BUF_SWAP() argument
232 return ((val) << AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT) & AXXX_CP_RB_CNTL_BUF_SWAP__MASK; in AXXX_CP_RB_CNTL_BUF_SWAP()
241 static inline uint32_t AXXX_CP_RB_RPTR_ADDR_SWAP(uint32_t val) in AXXX_CP_RB_RPTR_ADDR_SWAP() argument
243 return ((val) << AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT) & AXXX_CP_RB_RPTR_ADDR_SWAP__MASK; in AXXX_CP_RB_RPTR_ADDR_SWAP()
247 static inline uint32_t AXXX_CP_RB_RPTR_ADDR_ADDR(uint32_t val) in AXXX_CP_RB_RPTR_ADDR_ADDR() argument
249 return ((val >> 2) << AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT) & AXXX_CP_RB_RPTR_ADDR_ADDR__MASK; in AXXX_CP_RB_RPTR_ADDR_ADDR()
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| /linux-6.1.9/drivers/net/wireless/realtek/rtw89/ |
| D | fw.h | 26 #define RTW89_SET_H2CREG_HDR_FUNC(info, val) \ argument
27 u32p_replace_bits(info, val, GENMASK(6, 0))
28 #define RTW89_SET_H2CREG_HDR_LEN(info, val) \ argument
29 u32p_replace_bits(info, val, GENMASK(11, 8))
246 static inline void RTW89_SET_FWCMD_RA_IS_DIS(void *cmd, u32 val) in RTW89_SET_FWCMD_RA_IS_DIS() argument
248 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(0)); in RTW89_SET_FWCMD_RA_IS_DIS()
251 static inline void RTW89_SET_FWCMD_RA_MODE(void *cmd, u32 val) in RTW89_SET_FWCMD_RA_MODE() argument
253 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(5, 1)); in RTW89_SET_FWCMD_RA_MODE()
256 static inline void RTW89_SET_FWCMD_RA_BW_CAP(void *cmd, u32 val) in RTW89_SET_FWCMD_RA_BW_CAP() argument
258 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(7, 6)); in RTW89_SET_FWCMD_RA_BW_CAP()
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| /linux-6.1.9/drivers/phy/ |
| D | phy-xgene.c | 554 u32 val; in sds_wr() local
564 val = readl(csr_base + indirect_cmd_reg); in sds_wr()
565 } while (!(val & CFG_IND_CMD_DONE_MASK) && in sds_wr()
567 if (!(val & CFG_IND_CMD_DONE_MASK)) in sds_wr()
576 u32 val; in sds_rd() local
584 val = readl(csr_base + indirect_cmd_reg); in sds_rd()
585 } while (!(val & CFG_IND_CMD_DONE_MASK) && in sds_rd()
588 if (!(val & CFG_IND_CMD_DONE_MASK)) in sds_rd()
597 u32 val; in cmu_wr() local
606 SATA_ENET_SDS_IND_RDATA_REG, reg, &val); in cmu_wr()
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| /linux-6.1.9/drivers/gpu/drm/msm/dsi/ |
| D | dsi.xml.h | 146 static inline uint32_t DSI_6G_HW_VERSION_MAJOR(uint32_t val) in DSI_6G_HW_VERSION_MAJOR() argument
148 return ((val) << DSI_6G_HW_VERSION_MAJOR__SHIFT) & DSI_6G_HW_VERSION_MAJOR__MASK; in DSI_6G_HW_VERSION_MAJOR()
152 static inline uint32_t DSI_6G_HW_VERSION_MINOR(uint32_t val) in DSI_6G_HW_VERSION_MINOR() argument
154 return ((val) << DSI_6G_HW_VERSION_MINOR__SHIFT) & DSI_6G_HW_VERSION_MINOR__MASK; in DSI_6G_HW_VERSION_MINOR()
158 static inline uint32_t DSI_6G_HW_VERSION_STEP(uint32_t val) in DSI_6G_HW_VERSION_STEP() argument
160 return ((val) << DSI_6G_HW_VERSION_STEP__SHIFT) & DSI_6G_HW_VERSION_STEP__MASK; in DSI_6G_HW_VERSION_STEP()
213 static inline uint32_t DSI_VID_CFG0_VIRT_CHANNEL(uint32_t val) in DSI_VID_CFG0_VIRT_CHANNEL() argument
215 return ((val) << DSI_VID_CFG0_VIRT_CHANNEL__SHIFT) & DSI_VID_CFG0_VIRT_CHANNEL__MASK; in DSI_VID_CFG0_VIRT_CHANNEL()
219 static inline uint32_t DSI_VID_CFG0_DST_FORMAT(enum dsi_vid_dst_format val) in DSI_VID_CFG0_DST_FORMAT() argument
221 return ((val) << DSI_VID_CFG0_DST_FORMAT__SHIFT) & DSI_VID_CFG0_DST_FORMAT__MASK; in DSI_VID_CFG0_DST_FORMAT()
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| /linux-6.1.9/arch/mips/include/asm/ |
| D | mipsregs.h | 1383 #define write_r10k_perf_cntr(counter,val) \ argument
1388 : "r" (val), "i" (counter)); \
1402 #define write_r10k_perf_cntl(counter,val) \ argument
1407 : "r" (val), "i" (counter)); \
1509 #define __write_ulong_c0_register(reg, sel, val) \ argument
1512 __write_32bit_c0_register(reg, sel, val); \
1514 __write_64bit_c0_register(reg, sel, val); \
1568 #define __write_64bit_c0_split(source, sel, val) \ argument
1570 unsigned long long __tmp = (val); \
1655 #define write_c0_index(val) __write_32bit_c0_register($0, 0, val) argument
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| /linux-6.1.9/arch/mips/pci/ |
| D | pci-bcm63xx.c | 109 static void bcm63xx_int_cfg_writel(u32 val, u32 reg) in bcm63xx_int_cfg_writel() argument
116 bcm_mpi_writel(val, MPI_PCICFGDATA_REG); in bcm63xx_int_cfg_writel()
123 u32 val; in bcm63xx_reset_pcie() local
132 val = bcm_misc_readl(reg); in bcm63xx_reset_pcie()
133 val |= SERDES_PCIE_EN | SERDES_PCIE_EXD_EN; in bcm63xx_reset_pcie()
134 bcm_misc_writel(val, reg); in bcm63xx_reset_pcie()
152 u32 val; in bcm63xx_register_pcie() local
164 val = bcm_pcie_readl(PCIE_BRIDGE_OPT1_REG); in bcm63xx_register_pcie()
165 val |= OPT1_RD_BE_OPT_EN; in bcm63xx_register_pcie()
166 val |= OPT1_RD_REPLY_BE_FIX_EN; in bcm63xx_register_pcie()
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| /linux-6.1.9/drivers/net/ethernet/chelsio/cxgb4/ |
| D | cxgb4_tc_u32_parse.h | 41 int (*val)(struct ch_filter_specification *f, __be32 val, __be32 mask); member
46 __be32 val, __be32 mask) in cxgb4_fill_ipv4_tos() argument
48 f->val.tos = (ntohl(val) >> 16) & 0x000000FF; in cxgb4_fill_ipv4_tos()
55 __be32 val, __be32 mask) in cxgb4_fill_ipv4_frag() argument
60 frag_val = (ntohl(val) >> 13) & 0x00000007; in cxgb4_fill_ipv4_frag()
64 f->val.frag = 1; in cxgb4_fill_ipv4_frag()
67 f->val.frag = 0; in cxgb4_fill_ipv4_frag()
77 __be32 val, __be32 mask) in cxgb4_fill_ipv4_proto() argument
79 f->val.proto = (ntohl(val) >> 16) & 0x000000FF; in cxgb4_fill_ipv4_proto()
86 __be32 val, __be32 mask) in cxgb4_fill_ipv4_src_ip() argument
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| /linux-6.1.9/sound/pci/ac97/ |
| D | ac97_proc.c | 95 unsigned short val, tmp, ext, mext; in snd_ac97_proc_read_main() local
115 val = snd_ac97_read(ac97, AC97_INT_PAGING); in snd_ac97_proc_read_main()
126 AC97_PAGE_MASK, val & AC97_PAGE_MASK); in snd_ac97_proc_read_main()
130 val = ac97->caps; in snd_ac97_proc_read_main()
132 val & AC97_BC_DEDICATED_MIC ? " -dedicated MIC PCM IN channel-" : "", in snd_ac97_proc_read_main()
133 val & AC97_BC_RESERVED1 ? " -reserved1-" : "", in snd_ac97_proc_read_main()
134 val & AC97_BC_BASS_TREBLE ? " -bass & treble-" : "", in snd_ac97_proc_read_main()
135 val & AC97_BC_SIM_STEREO ? " -simulated stereo-" : "", in snd_ac97_proc_read_main()
136 val & AC97_BC_HEADPHONE ? " -headphone out-" : "", in snd_ac97_proc_read_main()
137 val & AC97_BC_LOUDNESS ? " -loudness-" : ""); in snd_ac97_proc_read_main()
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| /linux-6.1.9/arch/loongarch/include/asm/ |
| D | percpu.h | 32 unsigned long val, int size) \
41 : [val] "r" (val)); \
47 : [val] "r" (val)); \
54 return ret c_op val; \
99 static inline void __percpu_write(void *ptr, unsigned long val, int size) in __percpu_write() argument
105 : [val] "r" (val), [ptr] "r" (ptr) in __percpu_write()
111 : [val] "r" (val), [ptr] "r" (ptr) in __percpu_write()
117 : [val] "r" (val), [ptr] "r" (ptr) in __percpu_write()
123 : [val] "r" (val), [ptr] "r" (ptr) in __percpu_write()
131 static inline unsigned long __percpu_xchg(void *ptr, unsigned long val, in __percpu_xchg() argument
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| /linux-6.1.9/drivers/net/wireless/ath/ath5k/ |
| D | eeprom.c | 43 u16 val; in ath5k_eeprom_bin2freq() local
50 val = (5 * bin) + 4800; in ath5k_eeprom_bin2freq()
52 val = bin > 62 ? (10 * 62) + (5 * (bin - 62)) + 5100 : in ath5k_eeprom_bin2freq()
56 val = bin + 2300; in ath5k_eeprom_bin2freq()
58 val = bin + 2400; in ath5k_eeprom_bin2freq()
61 return val; in ath5k_eeprom_bin2freq()
76 u16 val; in ath5k_eeprom_init_header() local
96 AR5K_EEPROM_READ(AR5K_EEPROM_SIZE_UPPER, val); in ath5k_eeprom_init_header()
97 if (val) { in ath5k_eeprom_init_header()
98 eep_max = (val & AR5K_EEPROM_SIZE_UPPER_MASK) << in ath5k_eeprom_init_header()
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| /linux-6.1.9/drivers/gpu/drm/i915/ |
| D | i915_fixed.h | 15 u32 val; member
18 #define FP_16_16_MAX ((uint_fixed_16_16_t){ .val = UINT_MAX })
20 static inline bool is_fixed16_zero(uint_fixed_16_16_t val) in is_fixed16_zero() argument
22 return val.val == 0; in is_fixed16_zero()
25 static inline uint_fixed_16_16_t u32_to_fixed16(u32 val) in u32_to_fixed16() argument
27 uint_fixed_16_16_t fp = { .val = val << 16 }; in u32_to_fixed16()
29 WARN_ON(val > U16_MAX); in u32_to_fixed16()
36 return DIV_ROUND_UP(fp.val, 1 << 16); in fixed16_to_u32_round_up()
41 return fp.val >> 16; in fixed16_to_u32()
47 uint_fixed_16_16_t min = { .val = min(min1.val, min2.val) }; in min_fixed16()
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| /linux-6.1.9/drivers/usb/phy/ |
| D | phy-tegra-usb.c | 224 u32 val; in set_pts() local
227 val = readl_relaxed(base + TEGRA_USB_HOSTPC1_DEVLC); in set_pts()
228 val &= ~TEGRA_USB_HOSTPC1_DEVLC_PTS(~0); in set_pts()
229 val |= TEGRA_USB_HOSTPC1_DEVLC_PTS(pts_val); in set_pts()
230 writel_relaxed(val, base + TEGRA_USB_HOSTPC1_DEVLC); in set_pts()
232 val = readl_relaxed(base + TEGRA_USB_PORTSC1); in set_pts()
233 val &= ~TEGRA_PORTSC1_RWC_BITS; in set_pts()
234 val &= ~TEGRA_USB_PORTSC1_PTS(~0); in set_pts()
235 val |= TEGRA_USB_PORTSC1_PTS(pts_val); in set_pts()
236 writel_relaxed(val, base + TEGRA_USB_PORTSC1); in set_pts()
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| /linux-6.1.9/drivers/gpu/drm/msm/disp/mdp4/ |
| D | mdp4.xml.h | 120 static inline uint32_t MDP4_VERSION_MINOR(uint32_t val) in MDP4_VERSION_MINOR() argument
122 return ((val) << MDP4_VERSION_MINOR__SHIFT) & MDP4_VERSION_MINOR__MASK; in MDP4_VERSION_MINOR()
126 static inline uint32_t MDP4_VERSION_MAJOR(uint32_t val) in MDP4_VERSION_MAJOR() argument
128 return ((val) << MDP4_VERSION_MAJOR__SHIFT) & MDP4_VERSION_MAJOR__MASK; in MDP4_VERSION_MAJOR()
148 static inline uint32_t MDP4_DISP_INTF_SEL_PRIM(enum mdp4_intf val) in MDP4_DISP_INTF_SEL_PRIM() argument
150 return ((val) << MDP4_DISP_INTF_SEL_PRIM__SHIFT) & MDP4_DISP_INTF_SEL_PRIM__MASK; in MDP4_DISP_INTF_SEL_PRIM()
154 static inline uint32_t MDP4_DISP_INTF_SEL_SEC(enum mdp4_intf val) in MDP4_DISP_INTF_SEL_SEC() argument
156 return ((val) << MDP4_DISP_INTF_SEL_SEC__SHIFT) & MDP4_DISP_INTF_SEL_SEC__MASK; in MDP4_DISP_INTF_SEL_SEC()
160 static inline uint32_t MDP4_DISP_INTF_SEL_EXT(enum mdp4_intf val) in MDP4_DISP_INTF_SEL_EXT() argument
162 return ((val) << MDP4_DISP_INTF_SEL_EXT__SHIFT) & MDP4_DISP_INTF_SEL_EXT__MASK; in MDP4_DISP_INTF_SEL_EXT()
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