1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020  Realtek Corporation
3  */
4 
5 #ifndef __RTW89_FW_H__
6 #define __RTW89_FW_H__
7 
8 #include "core.h"
9 
10 enum rtw89_fw_dl_status {
11 	RTW89_FWDL_INITIAL_STATE = 0,
12 	RTW89_FWDL_FWDL_ONGOING = 1,
13 	RTW89_FWDL_CHECKSUM_FAIL = 2,
14 	RTW89_FWDL_SECURITY_FAIL = 3,
15 	RTW89_FWDL_CV_NOT_MATCH = 4,
16 	RTW89_FWDL_RSVD0 = 5,
17 	RTW89_FWDL_WCPU_FWDL_RDY = 6,
18 	RTW89_FWDL_WCPU_FW_INIT_RDY = 7
19 };
20 
21 #define RTW89_GET_C2H_HDR_FUNC(info) \
22 	u32_get_bits(info, GENMASK(6, 0))
23 #define RTW89_GET_C2H_HDR_LEN(info) \
24 	u32_get_bits(info, GENMASK(11, 8))
25 
26 #define RTW89_SET_H2CREG_HDR_FUNC(info, val) \
27 	u32p_replace_bits(info, val, GENMASK(6, 0))
28 #define RTW89_SET_H2CREG_HDR_LEN(info, val) \
29 	u32p_replace_bits(info, val, GENMASK(11, 8))
30 
31 #define RTW89_H2CREG_MAX 4
32 #define RTW89_C2HREG_MAX 4
33 #define RTW89_C2HREG_HDR_LEN 2
34 #define RTW89_H2CREG_HDR_LEN 2
35 #define RTW89_C2H_TIMEOUT 1000000
36 struct rtw89_mac_c2h_info {
37 	u8 id;
38 	u8 content_len;
39 	u32 c2hreg[RTW89_C2HREG_MAX];
40 };
41 
42 struct rtw89_mac_h2c_info {
43 	u8 id;
44 	u8 content_len;
45 	u32 h2creg[RTW89_H2CREG_MAX];
46 };
47 
48 enum rtw89_mac_h2c_type {
49 	RTW89_FWCMD_H2CREG_FUNC_H2CREG_LB = 0,
50 	RTW89_FWCMD_H2CREG_FUNC_CNSL_CMD,
51 	RTW89_FWCMD_H2CREG_FUNC_FWERR,
52 	RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE,
53 	RTW89_FWCMD_H2CREG_FUNC_GETPKT_INFORM,
54 	RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN
55 };
56 
57 enum rtw89_mac_c2h_type {
58 	RTW89_FWCMD_C2HREG_FUNC_C2HREG_LB = 0,
59 	RTW89_FWCMD_C2HREG_FUNC_ERR_RPT,
60 	RTW89_FWCMD_C2HREG_FUNC_ERR_MSG,
61 	RTW89_FWCMD_C2HREG_FUNC_PHY_CAP,
62 	RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT,
63 	RTW89_FWCMD_C2HREG_FUNC_NULL = 0xFF
64 };
65 
66 #define RTW89_GET_C2H_PHYCAP_FUNC(info) \
67 	u32_get_bits(*((const u32 *)(info)), GENMASK(6, 0))
68 #define RTW89_GET_C2H_PHYCAP_ACK(info) \
69 	u32_get_bits(*((const u32 *)(info)), BIT(7))
70 #define RTW89_GET_C2H_PHYCAP_LEN(info) \
71 	u32_get_bits(*((const u32 *)(info)), GENMASK(11, 8))
72 #define RTW89_GET_C2H_PHYCAP_SEQ(info) \
73 	u32_get_bits(*((const u32 *)(info)), GENMASK(15, 12))
74 #define RTW89_GET_C2H_PHYCAP_RX_NSS(info) \
75 	u32_get_bits(*((const u32 *)(info)), GENMASK(23, 16))
76 #define RTW89_GET_C2H_PHYCAP_BW(info) \
77 	u32_get_bits(*((const u32 *)(info)), GENMASK(31, 24))
78 #define RTW89_GET_C2H_PHYCAP_TX_NSS(info) \
79 	u32_get_bits(*((const u32 *)(info) + 1), GENMASK(7, 0))
80 #define RTW89_GET_C2H_PHYCAP_PROT(info) \
81 	u32_get_bits(*((const u32 *)(info) + 1), GENMASK(15, 8))
82 #define RTW89_GET_C2H_PHYCAP_NIC(info) \
83 	u32_get_bits(*((const u32 *)(info) + 1), GENMASK(23, 16))
84 #define RTW89_GET_C2H_PHYCAP_WL_FUNC(info) \
85 	u32_get_bits(*((const u32 *)(info) + 1), GENMASK(31, 24))
86 #define RTW89_GET_C2H_PHYCAP_HW_TYPE(info) \
87 	u32_get_bits(*((const u32 *)(info) + 2), GENMASK(7, 0))
88 #define RTW89_GET_C2H_PHYCAP_ANT_TX_NUM(info) \
89 	u32_get_bits(*((const u32 *)(info) + 3), GENMASK(15, 8))
90 #define RTW89_GET_C2H_PHYCAP_ANT_RX_NUM(info) \
91 	u32_get_bits(*((const u32 *)(info) + 3), GENMASK(23, 16))
92 
93 enum rtw89_fw_c2h_category {
94 	RTW89_C2H_CAT_TEST,
95 	RTW89_C2H_CAT_MAC,
96 	RTW89_C2H_CAT_OUTSRC,
97 };
98 
99 enum rtw89_fw_log_level {
100 	RTW89_FW_LOG_LEVEL_OFF,
101 	RTW89_FW_LOG_LEVEL_CRT,
102 	RTW89_FW_LOG_LEVEL_SER,
103 	RTW89_FW_LOG_LEVEL_WARN,
104 	RTW89_FW_LOG_LEVEL_LOUD,
105 	RTW89_FW_LOG_LEVEL_TR,
106 };
107 
108 enum rtw89_fw_log_path {
109 	RTW89_FW_LOG_LEVEL_UART,
110 	RTW89_FW_LOG_LEVEL_C2H,
111 	RTW89_FW_LOG_LEVEL_SNI,
112 };
113 
114 enum rtw89_fw_log_comp {
115 	RTW89_FW_LOG_COMP_VER,
116 	RTW89_FW_LOG_COMP_INIT,
117 	RTW89_FW_LOG_COMP_TASK,
118 	RTW89_FW_LOG_COMP_CNS,
119 	RTW89_FW_LOG_COMP_H2C,
120 	RTW89_FW_LOG_COMP_C2H,
121 	RTW89_FW_LOG_COMP_TX,
122 	RTW89_FW_LOG_COMP_RX,
123 	RTW89_FW_LOG_COMP_IPSEC,
124 	RTW89_FW_LOG_COMP_TIMER,
125 	RTW89_FW_LOG_COMP_DBGPKT,
126 	RTW89_FW_LOG_COMP_PS,
127 	RTW89_FW_LOG_COMP_ERROR,
128 	RTW89_FW_LOG_COMP_WOWLAN,
129 	RTW89_FW_LOG_COMP_SECURE_BOOT,
130 	RTW89_FW_LOG_COMP_BTC,
131 	RTW89_FW_LOG_COMP_BB,
132 	RTW89_FW_LOG_COMP_TWT,
133 	RTW89_FW_LOG_COMP_RF,
134 	RTW89_FW_LOG_COMP_MCC = 20,
135 };
136 
137 enum rtw89_pkt_offload_op {
138 	RTW89_PKT_OFLD_OP_ADD,
139 	RTW89_PKT_OFLD_OP_DEL,
140 	RTW89_PKT_OFLD_OP_READ,
141 };
142 
143 enum rtw89_scanofld_notify_reason {
144 	RTW89_SCAN_DWELL_NOTIFY,
145 	RTW89_SCAN_PRE_TX_NOTIFY,
146 	RTW89_SCAN_POST_TX_NOTIFY,
147 	RTW89_SCAN_ENTER_CH_NOTIFY,
148 	RTW89_SCAN_LEAVE_CH_NOTIFY,
149 	RTW89_SCAN_END_SCAN_NOTIFY,
150 };
151 
152 enum rtw89_chan_type {
153 	RTW89_CHAN_OPERATE = 0,
154 	RTW89_CHAN_ACTIVE,
155 	RTW89_CHAN_DFS,
156 };
157 
158 enum rtw89_p2pps_action {
159 	RTW89_P2P_ACT_INIT = 0,
160 	RTW89_P2P_ACT_UPDATE = 1,
161 	RTW89_P2P_ACT_REMOVE = 2,
162 	RTW89_P2P_ACT_TERMINATE = 3,
163 };
164 
165 #define FWDL_SECTION_MAX_NUM 10
166 #define FWDL_SECTION_CHKSUM_LEN	8
167 #define FWDL_SECTION_PER_PKT_LEN 2020
168 
169 struct rtw89_fw_hdr_section_info {
170 	u8 redl;
171 	const u8 *addr;
172 	u32 len;
173 	u32 dladdr;
174 };
175 
176 struct rtw89_fw_bin_info {
177 	u8 section_num;
178 	u32 hdr_len;
179 	struct rtw89_fw_hdr_section_info section_info[FWDL_SECTION_MAX_NUM];
180 };
181 
182 struct rtw89_fw_macid_pause_grp {
183 	__le32 pause_grp[4];
184 	__le32 mask_grp[4];
185 } __packed;
186 
187 struct rtw89_h2creg_sch_tx_en {
188 	u8 func:7;
189 	u8 ack:1;
190 	u8 total_len:4;
191 	u8 seq_num:4;
192 	u16 tx_en:16;
193 	u16 mask:16;
194 	u8 band:1;
195 	u16 rsvd:15;
196 } __packed;
197 
198 #define RTW89_H2C_MAX_SIZE 2048
199 #define RTW89_CHANNEL_TIME 45
200 #define RTW89_DFS_CHAN_TIME 105
201 #define RTW89_OFF_CHAN_TIME 100
202 #define RTW89_DWELL_TIME 20
203 #define RTW89_SCAN_WIDTH 0
204 #define RTW89_SCANOFLD_MAX_SSID 8
205 #define RTW89_SCANOFLD_MAX_IE_LEN 512
206 #define RTW89_SCANOFLD_PKT_NONE 0xFF
207 #define RTW89_SCANOFLD_DEBUG_MASK 0x1F
208 #define RTW89_MAC_CHINFO_SIZE 24
209 #define RTW89_SCAN_LIST_GUARD 4
210 #define RTW89_SCAN_LIST_LIMIT \
211 		((RTW89_H2C_MAX_SIZE / RTW89_MAC_CHINFO_SIZE) - RTW89_SCAN_LIST_GUARD)
212 
213 struct rtw89_mac_chinfo {
214 	u8 period;
215 	u8 dwell_time;
216 	u8 central_ch;
217 	u8 pri_ch;
218 	u8 bw:3;
219 	u8 notify_action:5;
220 	u8 num_pkt:4;
221 	u8 tx_pkt:1;
222 	u8 pause_data:1;
223 	u8 ch_band:2;
224 	u8 probe_id;
225 	u8 dfs_ch:1;
226 	u8 tx_null:1;
227 	u8 rand_seq_num:1;
228 	u8 cfg_tx_pwr:1;
229 	u8 rsvd0: 4;
230 	u8 pkt_id[RTW89_SCANOFLD_MAX_SSID];
231 	u16 tx_pwr_idx;
232 	u8 rsvd1;
233 	struct list_head list;
234 };
235 
236 struct rtw89_scan_option {
237 	bool enable;
238 	bool target_ch_mode;
239 };
240 
241 struct rtw89_pktofld_info {
242 	struct list_head list;
243 	u8 id;
244 };
245 
RTW89_SET_FWCMD_RA_IS_DIS(void * cmd,u32 val)246 static inline void RTW89_SET_FWCMD_RA_IS_DIS(void *cmd, u32 val)
247 {
248 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(0));
249 }
250 
RTW89_SET_FWCMD_RA_MODE(void * cmd,u32 val)251 static inline void RTW89_SET_FWCMD_RA_MODE(void *cmd, u32 val)
252 {
253 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(5, 1));
254 }
255 
RTW89_SET_FWCMD_RA_BW_CAP(void * cmd,u32 val)256 static inline void RTW89_SET_FWCMD_RA_BW_CAP(void *cmd, u32 val)
257 {
258 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(7, 6));
259 }
260 
RTW89_SET_FWCMD_RA_MACID(void * cmd,u32 val)261 static inline void RTW89_SET_FWCMD_RA_MACID(void *cmd, u32 val)
262 {
263 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(15, 8));
264 }
265 
RTW89_SET_FWCMD_RA_DCM(void * cmd,u32 val)266 static inline void RTW89_SET_FWCMD_RA_DCM(void *cmd, u32 val)
267 {
268 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(16));
269 }
270 
RTW89_SET_FWCMD_RA_ER(void * cmd,u32 val)271 static inline void RTW89_SET_FWCMD_RA_ER(void *cmd, u32 val)
272 {
273 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(17));
274 }
275 
RTW89_SET_FWCMD_RA_INIT_RATE_LV(void * cmd,u32 val)276 static inline void RTW89_SET_FWCMD_RA_INIT_RATE_LV(void *cmd, u32 val)
277 {
278 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(19, 18));
279 }
280 
RTW89_SET_FWCMD_RA_UPD_ALL(void * cmd,u32 val)281 static inline void RTW89_SET_FWCMD_RA_UPD_ALL(void *cmd, u32 val)
282 {
283 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(20));
284 }
285 
RTW89_SET_FWCMD_RA_SGI(void * cmd,u32 val)286 static inline void RTW89_SET_FWCMD_RA_SGI(void *cmd, u32 val)
287 {
288 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(21));
289 }
290 
RTW89_SET_FWCMD_RA_LDPC(void * cmd,u32 val)291 static inline void RTW89_SET_FWCMD_RA_LDPC(void *cmd, u32 val)
292 {
293 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(22));
294 }
295 
RTW89_SET_FWCMD_RA_STBC(void * cmd,u32 val)296 static inline void RTW89_SET_FWCMD_RA_STBC(void *cmd, u32 val)
297 {
298 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(23));
299 }
300 
RTW89_SET_FWCMD_RA_SS_NUM(void * cmd,u32 val)301 static inline void RTW89_SET_FWCMD_RA_SS_NUM(void *cmd, u32 val)
302 {
303 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(26, 24));
304 }
305 
RTW89_SET_FWCMD_RA_GILTF(void * cmd,u32 val)306 static inline void RTW89_SET_FWCMD_RA_GILTF(void *cmd, u32 val)
307 {
308 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(29, 27));
309 }
310 
RTW89_SET_FWCMD_RA_UPD_BW_NSS_MASK(void * cmd,u32 val)311 static inline void RTW89_SET_FWCMD_RA_UPD_BW_NSS_MASK(void *cmd, u32 val)
312 {
313 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(30));
314 }
315 
RTW89_SET_FWCMD_RA_UPD_MASK(void * cmd,u32 val)316 static inline void RTW89_SET_FWCMD_RA_UPD_MASK(void *cmd, u32 val)
317 {
318 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(31));
319 }
320 
RTW89_SET_FWCMD_RA_MASK_0(void * cmd,u32 val)321 static inline void RTW89_SET_FWCMD_RA_MASK_0(void *cmd, u32 val)
322 {
323 	le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(7, 0));
324 }
325 
RTW89_SET_FWCMD_RA_MASK_1(void * cmd,u32 val)326 static inline void RTW89_SET_FWCMD_RA_MASK_1(void *cmd, u32 val)
327 {
328 	le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(15, 8));
329 }
330 
RTW89_SET_FWCMD_RA_MASK_2(void * cmd,u32 val)331 static inline void RTW89_SET_FWCMD_RA_MASK_2(void *cmd, u32 val)
332 {
333 	le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(23, 16));
334 }
335 
RTW89_SET_FWCMD_RA_MASK_3(void * cmd,u32 val)336 static inline void RTW89_SET_FWCMD_RA_MASK_3(void *cmd, u32 val)
337 {
338 	le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(31, 24));
339 }
340 
RTW89_SET_FWCMD_RA_MASK_4(void * cmd,u32 val)341 static inline void RTW89_SET_FWCMD_RA_MASK_4(void *cmd, u32 val)
342 {
343 	le32p_replace_bits((__le32 *)(cmd) + 0x02, val, GENMASK(7, 0));
344 }
345 
RTW89_SET_FWCMD_RA_BFEE_CSI_CTL(void * cmd,u32 val)346 static inline void RTW89_SET_FWCMD_RA_BFEE_CSI_CTL(void *cmd, u32 val)
347 {
348 	le32p_replace_bits((__le32 *)(cmd) + 0x02, val, BIT(31));
349 }
350 
RTW89_SET_FWCMD_RA_BAND_NUM(void * cmd,u32 val)351 static inline void RTW89_SET_FWCMD_RA_BAND_NUM(void *cmd, u32 val)
352 {
353 	le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(7, 0));
354 }
355 
RTW89_SET_FWCMD_RA_RA_CSI_RATE_EN(void * cmd,u32 val)356 static inline void RTW89_SET_FWCMD_RA_RA_CSI_RATE_EN(void *cmd, u32 val)
357 {
358 	le32p_replace_bits((__le32 *)(cmd) + 0x03, val, BIT(8));
359 }
360 
RTW89_SET_FWCMD_RA_FIXED_CSI_RATE_EN(void * cmd,u32 val)361 static inline void RTW89_SET_FWCMD_RA_FIXED_CSI_RATE_EN(void *cmd, u32 val)
362 {
363 	le32p_replace_bits((__le32 *)(cmd) + 0x03, val, BIT(9));
364 }
365 
RTW89_SET_FWCMD_RA_CR_TBL_SEL(void * cmd,u32 val)366 static inline void RTW89_SET_FWCMD_RA_CR_TBL_SEL(void *cmd, u32 val)
367 {
368 	le32p_replace_bits((__le32 *)(cmd) + 0x03, val, BIT(10));
369 }
370 
RTW89_SET_FWCMD_RA_FIX_GILTF_EN(void * cmd,u32 val)371 static inline void RTW89_SET_FWCMD_RA_FIX_GILTF_EN(void *cmd, u32 val)
372 {
373 	le32p_replace_bits((__le32 *)(cmd) + 0x03, val, BIT(11));
374 }
375 
RTW89_SET_FWCMD_RA_FIX_GILTF(void * cmd,u32 val)376 static inline void RTW89_SET_FWCMD_RA_FIX_GILTF(void *cmd, u32 val)
377 {
378 	le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(14, 12));
379 }
380 
RTW89_SET_FWCMD_RA_FIXED_CSI_MCS_SS_IDX(void * cmd,u32 val)381 static inline void RTW89_SET_FWCMD_RA_FIXED_CSI_MCS_SS_IDX(void *cmd, u32 val)
382 {
383 	le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(23, 16));
384 }
385 
RTW89_SET_FWCMD_RA_FIXED_CSI_MODE(void * cmd,u32 val)386 static inline void RTW89_SET_FWCMD_RA_FIXED_CSI_MODE(void *cmd, u32 val)
387 {
388 	le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(25, 24));
389 }
390 
RTW89_SET_FWCMD_RA_FIXED_CSI_GI_LTF(void * cmd,u32 val)391 static inline void RTW89_SET_FWCMD_RA_FIXED_CSI_GI_LTF(void *cmd, u32 val)
392 {
393 	le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(28, 26));
394 }
395 
RTW89_SET_FWCMD_RA_FIXED_CSI_BW(void * cmd,u32 val)396 static inline void RTW89_SET_FWCMD_RA_FIXED_CSI_BW(void *cmd, u32 val)
397 {
398 	le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(31, 29));
399 }
400 
RTW89_SET_FWCMD_SEC_IDX(void * cmd,u32 val)401 static inline void RTW89_SET_FWCMD_SEC_IDX(void *cmd, u32 val)
402 {
403 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(7, 0));
404 }
405 
RTW89_SET_FWCMD_SEC_OFFSET(void * cmd,u32 val)406 static inline void RTW89_SET_FWCMD_SEC_OFFSET(void *cmd, u32 val)
407 {
408 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(15, 8));
409 }
410 
RTW89_SET_FWCMD_SEC_LEN(void * cmd,u32 val)411 static inline void RTW89_SET_FWCMD_SEC_LEN(void *cmd, u32 val)
412 {
413 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(23, 16));
414 }
415 
RTW89_SET_FWCMD_SEC_TYPE(void * cmd,u32 val)416 static inline void RTW89_SET_FWCMD_SEC_TYPE(void *cmd, u32 val)
417 {
418 	le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(3, 0));
419 }
420 
RTW89_SET_FWCMD_SEC_EXT_KEY(void * cmd,u32 val)421 static inline void RTW89_SET_FWCMD_SEC_EXT_KEY(void *cmd, u32 val)
422 {
423 	le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(4));
424 }
425 
RTW89_SET_FWCMD_SEC_SPP_MODE(void * cmd,u32 val)426 static inline void RTW89_SET_FWCMD_SEC_SPP_MODE(void *cmd, u32 val)
427 {
428 	le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(5));
429 }
430 
RTW89_SET_FWCMD_SEC_KEY0(void * cmd,u32 val)431 static inline void RTW89_SET_FWCMD_SEC_KEY0(void *cmd, u32 val)
432 {
433 	le32p_replace_bits((__le32 *)(cmd) + 0x02, val, GENMASK(31, 0));
434 }
435 
RTW89_SET_FWCMD_SEC_KEY1(void * cmd,u32 val)436 static inline void RTW89_SET_FWCMD_SEC_KEY1(void *cmd, u32 val)
437 {
438 	le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(31, 0));
439 }
440 
RTW89_SET_FWCMD_SEC_KEY2(void * cmd,u32 val)441 static inline void RTW89_SET_FWCMD_SEC_KEY2(void *cmd, u32 val)
442 {
443 	le32p_replace_bits((__le32 *)(cmd) + 0x04, val, GENMASK(31, 0));
444 }
445 
RTW89_SET_FWCMD_SEC_KEY3(void * cmd,u32 val)446 static inline void RTW89_SET_FWCMD_SEC_KEY3(void *cmd, u32 val)
447 {
448 	le32p_replace_bits((__le32 *)(cmd) + 0x05, val, GENMASK(31, 0));
449 }
450 
RTW89_SET_EDCA_SEL(void * cmd,u32 val)451 static inline void RTW89_SET_EDCA_SEL(void *cmd, u32 val)
452 {
453 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(1, 0));
454 }
455 
RTW89_SET_EDCA_BAND(void * cmd,u32 val)456 static inline void RTW89_SET_EDCA_BAND(void *cmd, u32 val)
457 {
458 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(3));
459 }
460 
RTW89_SET_EDCA_WMM(void * cmd,u32 val)461 static inline void RTW89_SET_EDCA_WMM(void *cmd, u32 val)
462 {
463 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(4));
464 }
465 
RTW89_SET_EDCA_AC(void * cmd,u32 val)466 static inline void RTW89_SET_EDCA_AC(void *cmd, u32 val)
467 {
468 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(6, 5));
469 }
470 
RTW89_SET_EDCA_PARAM(void * cmd,u32 val)471 static inline void RTW89_SET_EDCA_PARAM(void *cmd, u32 val)
472 {
473 	le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(31, 0));
474 }
475 #define FW_EDCA_PARAM_TXOPLMT_MSK GENMASK(26, 16)
476 #define FW_EDCA_PARAM_CWMAX_MSK GENMASK(15, 12)
477 #define FW_EDCA_PARAM_CWMIN_MSK GENMASK(11, 8)
478 #define FW_EDCA_PARAM_AIFS_MSK GENMASK(7, 0)
479 
480 #define GET_FWSECTION_HDR_SEC_SIZE(fwhdr)	\
481 	le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(23, 0))
482 #define GET_FWSECTION_HDR_CHECKSUM(fwhdr)	\
483 	le32_get_bits(*((const __le32 *)(fwhdr) + 1), BIT(28))
484 #define GET_FWSECTION_HDR_REDL(fwhdr)	\
485 	le32_get_bits(*((const __le32 *)(fwhdr) + 1), BIT(29))
486 #define GET_FWSECTION_HDR_DL_ADDR(fwhdr)	\
487 	le32_get_bits(*((const __le32 *)(fwhdr)), GENMASK(31, 0))
488 
489 #define GET_FW_HDR_MAJOR_VERSION(fwhdr)	\
490 	le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(7, 0))
491 #define GET_FW_HDR_MINOR_VERSION(fwhdr)	\
492 	le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(15, 8))
493 #define GET_FW_HDR_SUBVERSION(fwhdr)	\
494 	le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(23, 16))
495 #define GET_FW_HDR_SUBINDEX(fwhdr)	\
496 	le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(31, 24))
497 #define GET_FW_HDR_MONTH(fwhdr)		\
498 	le32_get_bits(*((const __le32 *)(fwhdr) + 4), GENMASK(7, 0))
499 #define GET_FW_HDR_DATE(fwhdr)		\
500 	le32_get_bits(*((const __le32 *)(fwhdr) + 4), GENMASK(15, 8))
501 #define GET_FW_HDR_HOUR(fwhdr)		\
502 	le32_get_bits(*((const __le32 *)(fwhdr) + 4), GENMASK(23, 16))
503 #define GET_FW_HDR_MIN(fwhdr)		\
504 	le32_get_bits(*((const __le32 *)(fwhdr) + 4), GENMASK(31, 24))
505 #define GET_FW_HDR_YEAR(fwhdr)		\
506 	le32_get_bits(*((const __le32 *)(fwhdr) + 5), GENMASK(31, 0))
507 #define GET_FW_HDR_SEC_NUM(fwhdr)	\
508 	le32_get_bits(*((const __le32 *)(fwhdr) + 6), GENMASK(15, 8))
509 #define GET_FW_HDR_CMD_VERSERION(fwhdr)	\
510 	le32_get_bits(*((const __le32 *)(fwhdr) + 7), GENMASK(31, 24))
SET_FW_HDR_PART_SIZE(void * fwhdr,u32 val)511 static inline void SET_FW_HDR_PART_SIZE(void *fwhdr, u32 val)
512 {
513 	le32p_replace_bits((__le32 *)fwhdr + 7, val, GENMASK(15, 0));
514 }
515 
SET_CTRL_INFO_MACID(void * table,u32 val)516 static inline void SET_CTRL_INFO_MACID(void *table, u32 val)
517 {
518 	le32p_replace_bits((__le32 *)(table) + 0, val, GENMASK(6, 0));
519 }
520 
SET_CTRL_INFO_OPERATION(void * table,u32 val)521 static inline void SET_CTRL_INFO_OPERATION(void *table, u32 val)
522 {
523 	le32p_replace_bits((__le32 *)(table) + 0, val, BIT(7));
524 }
525 #define SET_CMC_TBL_MASK_DATARATE GENMASK(8, 0)
SET_CMC_TBL_DATARATE(void * table,u32 val)526 static inline void SET_CMC_TBL_DATARATE(void *table, u32 val)
527 {
528 	le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(8, 0));
529 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATARATE,
530 			   GENMASK(8, 0));
531 }
532 #define SET_CMC_TBL_MASK_FORCE_TXOP BIT(0)
SET_CMC_TBL_FORCE_TXOP(void * table,u32 val)533 static inline void SET_CMC_TBL_FORCE_TXOP(void *table, u32 val)
534 {
535 	le32p_replace_bits((__le32 *)(table) + 1, val, BIT(9));
536 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_FORCE_TXOP,
537 			   BIT(9));
538 }
539 #define SET_CMC_TBL_MASK_DATA_BW GENMASK(1, 0)
SET_CMC_TBL_DATA_BW(void * table,u32 val)540 static inline void SET_CMC_TBL_DATA_BW(void *table, u32 val)
541 {
542 	le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(11, 10));
543 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATA_BW,
544 			   GENMASK(11, 10));
545 }
546 #define SET_CMC_TBL_MASK_DATA_GI_LTF GENMASK(2, 0)
SET_CMC_TBL_DATA_GI_LTF(void * table,u32 val)547 static inline void SET_CMC_TBL_DATA_GI_LTF(void *table, u32 val)
548 {
549 	le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(14, 12));
550 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATA_GI_LTF,
551 			   GENMASK(14, 12));
552 }
553 #define SET_CMC_TBL_MASK_DARF_TC_INDEX BIT(0)
SET_CMC_TBL_DARF_TC_INDEX(void * table,u32 val)554 static inline void SET_CMC_TBL_DARF_TC_INDEX(void *table, u32 val)
555 {
556 	le32p_replace_bits((__le32 *)(table) + 1, val, BIT(15));
557 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DARF_TC_INDEX,
558 			   BIT(15));
559 }
560 #define SET_CMC_TBL_MASK_ARFR_CTRL GENMASK(3, 0)
SET_CMC_TBL_ARFR_CTRL(void * table,u32 val)561 static inline void SET_CMC_TBL_ARFR_CTRL(void *table, u32 val)
562 {
563 	le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(19, 16));
564 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ARFR_CTRL,
565 			   GENMASK(19, 16));
566 }
567 #define SET_CMC_TBL_MASK_ACQ_RPT_EN BIT(0)
SET_CMC_TBL_ACQ_RPT_EN(void * table,u32 val)568 static inline void SET_CMC_TBL_ACQ_RPT_EN(void *table, u32 val)
569 {
570 	le32p_replace_bits((__le32 *)(table) + 1, val, BIT(20));
571 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ACQ_RPT_EN,
572 			   BIT(20));
573 }
574 #define SET_CMC_TBL_MASK_MGQ_RPT_EN BIT(0)
SET_CMC_TBL_MGQ_RPT_EN(void * table,u32 val)575 static inline void SET_CMC_TBL_MGQ_RPT_EN(void *table, u32 val)
576 {
577 	le32p_replace_bits((__le32 *)(table) + 1, val, BIT(21));
578 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_MGQ_RPT_EN,
579 			   BIT(21));
580 }
581 #define SET_CMC_TBL_MASK_ULQ_RPT_EN BIT(0)
SET_CMC_TBL_ULQ_RPT_EN(void * table,u32 val)582 static inline void SET_CMC_TBL_ULQ_RPT_EN(void *table, u32 val)
583 {
584 	le32p_replace_bits((__le32 *)(table) + 1, val, BIT(22));
585 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ULQ_RPT_EN,
586 			   BIT(22));
587 }
588 #define SET_CMC_TBL_MASK_TWTQ_RPT_EN BIT(0)
SET_CMC_TBL_TWTQ_RPT_EN(void * table,u32 val)589 static inline void SET_CMC_TBL_TWTQ_RPT_EN(void *table, u32 val)
590 {
591 	le32p_replace_bits((__le32 *)(table) + 1, val, BIT(23));
592 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_TWTQ_RPT_EN,
593 			   BIT(23));
594 }
595 #define SET_CMC_TBL_MASK_DISRTSFB BIT(0)
SET_CMC_TBL_DISRTSFB(void * table,u32 val)596 static inline void SET_CMC_TBL_DISRTSFB(void *table, u32 val)
597 {
598 	le32p_replace_bits((__le32 *)(table) + 1, val, BIT(25));
599 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DISRTSFB,
600 			   BIT(25));
601 }
602 #define SET_CMC_TBL_MASK_DISDATAFB BIT(0)
SET_CMC_TBL_DISDATAFB(void * table,u32 val)603 static inline void SET_CMC_TBL_DISDATAFB(void *table, u32 val)
604 {
605 	le32p_replace_bits((__le32 *)(table) + 1, val, BIT(26));
606 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DISDATAFB,
607 			   BIT(26));
608 }
609 #define SET_CMC_TBL_MASK_TRYRATE BIT(0)
SET_CMC_TBL_TRYRATE(void * table,u32 val)610 static inline void SET_CMC_TBL_TRYRATE(void *table, u32 val)
611 {
612 	le32p_replace_bits((__le32 *)(table) + 1, val, BIT(27));
613 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_TRYRATE,
614 			   BIT(27));
615 }
616 #define SET_CMC_TBL_MASK_AMPDU_DENSITY GENMASK(3, 0)
SET_CMC_TBL_AMPDU_DENSITY(void * table,u32 val)617 static inline void SET_CMC_TBL_AMPDU_DENSITY(void *table, u32 val)
618 {
619 	le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(31, 28));
620 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_AMPDU_DENSITY,
621 			   GENMASK(31, 28));
622 }
623 #define SET_CMC_TBL_MASK_DATA_RTY_LOWEST_RATE GENMASK(8, 0)
SET_CMC_TBL_DATA_RTY_LOWEST_RATE(void * table,u32 val)624 static inline void SET_CMC_TBL_DATA_RTY_LOWEST_RATE(void *table, u32 val)
625 {
626 	le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(8, 0));
627 	le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_DATA_RTY_LOWEST_RATE,
628 			   GENMASK(8, 0));
629 }
630 #define SET_CMC_TBL_MASK_AMPDU_TIME_SEL BIT(0)
SET_CMC_TBL_AMPDU_TIME_SEL(void * table,u32 val)631 static inline void SET_CMC_TBL_AMPDU_TIME_SEL(void *table, u32 val)
632 {
633 	le32p_replace_bits((__le32 *)(table) + 2, val, BIT(9));
634 	le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_AMPDU_TIME_SEL,
635 			   BIT(9));
636 }
637 #define SET_CMC_TBL_MASK_AMPDU_LEN_SEL BIT(0)
SET_CMC_TBL_AMPDU_LEN_SEL(void * table,u32 val)638 static inline void SET_CMC_TBL_AMPDU_LEN_SEL(void *table, u32 val)
639 {
640 	le32p_replace_bits((__le32 *)(table) + 2, val, BIT(10));
641 	le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_AMPDU_LEN_SEL,
642 			   BIT(10));
643 }
644 #define SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL BIT(0)
SET_CMC_TBL_RTS_TXCNT_LMT_SEL(void * table,u32 val)645 static inline void SET_CMC_TBL_RTS_TXCNT_LMT_SEL(void *table, u32 val)
646 {
647 	le32p_replace_bits((__le32 *)(table) + 2, val, BIT(11));
648 	le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL,
649 			   BIT(11));
650 }
651 #define SET_CMC_TBL_MASK_RTS_TXCNT_LMT GENMASK(3, 0)
SET_CMC_TBL_RTS_TXCNT_LMT(void * table,u32 val)652 static inline void SET_CMC_TBL_RTS_TXCNT_LMT(void *table, u32 val)
653 {
654 	le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(15, 12));
655 	le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_TXCNT_LMT,
656 			   GENMASK(15, 12));
657 }
658 #define SET_CMC_TBL_MASK_RTSRATE GENMASK(8, 0)
SET_CMC_TBL_RTSRATE(void * table,u32 val)659 static inline void SET_CMC_TBL_RTSRATE(void *table, u32 val)
660 {
661 	le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(24, 16));
662 	le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTSRATE,
663 			   GENMASK(24, 16));
664 }
665 #define SET_CMC_TBL_MASK_VCS_STBC BIT(0)
SET_CMC_TBL_VCS_STBC(void * table,u32 val)666 static inline void SET_CMC_TBL_VCS_STBC(void *table, u32 val)
667 {
668 	le32p_replace_bits((__le32 *)(table) + 2, val, BIT(27));
669 	le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_VCS_STBC,
670 			   BIT(27));
671 }
672 #define SET_CMC_TBL_MASK_RTS_RTY_LOWEST_RATE GENMASK(3, 0)
SET_CMC_TBL_RTS_RTY_LOWEST_RATE(void * table,u32 val)673 static inline void SET_CMC_TBL_RTS_RTY_LOWEST_RATE(void *table, u32 val)
674 {
675 	le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(31, 28));
676 	le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_RTY_LOWEST_RATE,
677 			   GENMASK(31, 28));
678 }
679 #define SET_CMC_TBL_MASK_DATA_TX_CNT_LMT GENMASK(5, 0)
SET_CMC_TBL_DATA_TX_CNT_LMT(void * table,u32 val)680 static inline void SET_CMC_TBL_DATA_TX_CNT_LMT(void *table, u32 val)
681 {
682 	le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(5, 0));
683 	le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_DATA_TX_CNT_LMT,
684 			   GENMASK(5, 0));
685 }
686 #define SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL BIT(0)
SET_CMC_TBL_DATA_TXCNT_LMT_SEL(void * table,u32 val)687 static inline void SET_CMC_TBL_DATA_TXCNT_LMT_SEL(void *table, u32 val)
688 {
689 	le32p_replace_bits((__le32 *)(table) + 3, val, BIT(6));
690 	le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL,
691 			   BIT(6));
692 }
693 #define SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL BIT(0)
SET_CMC_TBL_MAX_AGG_NUM_SEL(void * table,u32 val)694 static inline void SET_CMC_TBL_MAX_AGG_NUM_SEL(void *table, u32 val)
695 {
696 	le32p_replace_bits((__le32 *)(table) + 3, val, BIT(7));
697 	le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL,
698 			   BIT(7));
699 }
700 #define SET_CMC_TBL_MASK_RTS_EN BIT(0)
SET_CMC_TBL_RTS_EN(void * table,u32 val)701 static inline void SET_CMC_TBL_RTS_EN(void *table, u32 val)
702 {
703 	le32p_replace_bits((__le32 *)(table) + 3, val, BIT(8));
704 	le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_RTS_EN,
705 			   BIT(8));
706 }
707 #define SET_CMC_TBL_MASK_CTS2SELF_EN BIT(0)
SET_CMC_TBL_CTS2SELF_EN(void * table,u32 val)708 static inline void SET_CMC_TBL_CTS2SELF_EN(void *table, u32 val)
709 {
710 	le32p_replace_bits((__le32 *)(table) + 3, val, BIT(9));
711 	le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_CTS2SELF_EN,
712 			   BIT(9));
713 }
714 #define SET_CMC_TBL_MASK_CCA_RTS GENMASK(1, 0)
SET_CMC_TBL_CCA_RTS(void * table,u32 val)715 static inline void SET_CMC_TBL_CCA_RTS(void *table, u32 val)
716 {
717 	le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(11, 10));
718 	le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_CCA_RTS,
719 			   GENMASK(11, 10));
720 }
721 #define SET_CMC_TBL_MASK_HW_RTS_EN BIT(0)
SET_CMC_TBL_HW_RTS_EN(void * table,u32 val)722 static inline void SET_CMC_TBL_HW_RTS_EN(void *table, u32 val)
723 {
724 	le32p_replace_bits((__le32 *)(table) + 3, val, BIT(12));
725 	le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_HW_RTS_EN,
726 			   BIT(12));
727 }
728 #define SET_CMC_TBL_MASK_RTS_DROP_DATA_MODE GENMASK(1, 0)
SET_CMC_TBL_RTS_DROP_DATA_MODE(void * table,u32 val)729 static inline void SET_CMC_TBL_RTS_DROP_DATA_MODE(void *table, u32 val)
730 {
731 	le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(14, 13));
732 	le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_RTS_DROP_DATA_MODE,
733 			   GENMASK(14, 13));
734 }
735 #define SET_CMC_TBL_MASK_AMPDU_MAX_LEN GENMASK(10, 0)
SET_CMC_TBL_AMPDU_MAX_LEN(void * table,u32 val)736 static inline void SET_CMC_TBL_AMPDU_MAX_LEN(void *table, u32 val)
737 {
738 	le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(26, 16));
739 	le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_AMPDU_MAX_LEN,
740 			   GENMASK(26, 16));
741 }
742 #define SET_CMC_TBL_MASK_UL_MU_DIS BIT(0)
SET_CMC_TBL_UL_MU_DIS(void * table,u32 val)743 static inline void SET_CMC_TBL_UL_MU_DIS(void *table, u32 val)
744 {
745 	le32p_replace_bits((__le32 *)(table) + 3, val, BIT(27));
746 	le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_UL_MU_DIS,
747 			   BIT(27));
748 }
749 #define SET_CMC_TBL_MASK_AMPDU_MAX_TIME GENMASK(3, 0)
SET_CMC_TBL_AMPDU_MAX_TIME(void * table,u32 val)750 static inline void SET_CMC_TBL_AMPDU_MAX_TIME(void *table, u32 val)
751 {
752 	le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(31, 28));
753 	le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_AMPDU_MAX_TIME,
754 			   GENMASK(31, 28));
755 }
756 #define SET_CMC_TBL_MASK_MAX_AGG_NUM GENMASK(7, 0)
SET_CMC_TBL_MAX_AGG_NUM(void * table,u32 val)757 static inline void SET_CMC_TBL_MAX_AGG_NUM(void *table, u32 val)
758 {
759 	le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(7, 0));
760 	le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_MAX_AGG_NUM,
761 			   GENMASK(7, 0));
762 }
763 #define SET_CMC_TBL_MASK_BA_BMAP GENMASK(1, 0)
SET_CMC_TBL_BA_BMAP(void * table,u32 val)764 static inline void SET_CMC_TBL_BA_BMAP(void *table, u32 val)
765 {
766 	le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(9, 8));
767 	le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BA_BMAP,
768 			   GENMASK(9, 8));
769 }
770 #define SET_CMC_TBL_MASK_VO_LFTIME_SEL GENMASK(2, 0)
SET_CMC_TBL_VO_LFTIME_SEL(void * table,u32 val)771 static inline void SET_CMC_TBL_VO_LFTIME_SEL(void *table, u32 val)
772 {
773 	le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(18, 16));
774 	le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_VO_LFTIME_SEL,
775 			   GENMASK(18, 16));
776 }
777 #define SET_CMC_TBL_MASK_VI_LFTIME_SEL GENMASK(2, 0)
SET_CMC_TBL_VI_LFTIME_SEL(void * table,u32 val)778 static inline void SET_CMC_TBL_VI_LFTIME_SEL(void *table, u32 val)
779 {
780 	le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(21, 19));
781 	le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_VI_LFTIME_SEL,
782 			   GENMASK(21, 19));
783 }
784 #define SET_CMC_TBL_MASK_BE_LFTIME_SEL GENMASK(2, 0)
SET_CMC_TBL_BE_LFTIME_SEL(void * table,u32 val)785 static inline void SET_CMC_TBL_BE_LFTIME_SEL(void *table, u32 val)
786 {
787 	le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(24, 22));
788 	le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BE_LFTIME_SEL,
789 			   GENMASK(24, 22));
790 }
791 #define SET_CMC_TBL_MASK_BK_LFTIME_SEL GENMASK(2, 0)
SET_CMC_TBL_BK_LFTIME_SEL(void * table,u32 val)792 static inline void SET_CMC_TBL_BK_LFTIME_SEL(void *table, u32 val)
793 {
794 	le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(27, 25));
795 	le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BK_LFTIME_SEL,
796 			   GENMASK(27, 25));
797 }
798 #define SET_CMC_TBL_MASK_SECTYPE GENMASK(3, 0)
SET_CMC_TBL_SECTYPE(void * table,u32 val)799 static inline void SET_CMC_TBL_SECTYPE(void *table, u32 val)
800 {
801 	le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(31, 28));
802 	le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_SECTYPE,
803 			   GENMASK(31, 28));
804 }
805 #define SET_CMC_TBL_MASK_MULTI_PORT_ID GENMASK(2, 0)
SET_CMC_TBL_MULTI_PORT_ID(void * table,u32 val)806 static inline void SET_CMC_TBL_MULTI_PORT_ID(void *table, u32 val)
807 {
808 	le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(2, 0));
809 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_MULTI_PORT_ID,
810 			   GENMASK(2, 0));
811 }
812 #define SET_CMC_TBL_MASK_BMC BIT(0)
SET_CMC_TBL_BMC(void * table,u32 val)813 static inline void SET_CMC_TBL_BMC(void *table, u32 val)
814 {
815 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(3));
816 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_BMC,
817 			   BIT(3));
818 }
819 #define SET_CMC_TBL_MASK_MBSSID GENMASK(3, 0)
SET_CMC_TBL_MBSSID(void * table,u32 val)820 static inline void SET_CMC_TBL_MBSSID(void *table, u32 val)
821 {
822 	le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(7, 4));
823 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_MBSSID,
824 			   GENMASK(7, 4));
825 }
826 #define SET_CMC_TBL_MASK_NAVUSEHDR BIT(0)
SET_CMC_TBL_NAVUSEHDR(void * table,u32 val)827 static inline void SET_CMC_TBL_NAVUSEHDR(void *table, u32 val)
828 {
829 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(8));
830 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_NAVUSEHDR,
831 			   BIT(8));
832 }
833 #define SET_CMC_TBL_MASK_TXPWR_MODE GENMASK(2, 0)
SET_CMC_TBL_TXPWR_MODE(void * table,u32 val)834 static inline void SET_CMC_TBL_TXPWR_MODE(void *table, u32 val)
835 {
836 	le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(11, 9));
837 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_TXPWR_MODE,
838 			   GENMASK(11, 9));
839 }
840 #define SET_CMC_TBL_MASK_DATA_DCM BIT(0)
SET_CMC_TBL_DATA_DCM(void * table,u32 val)841 static inline void SET_CMC_TBL_DATA_DCM(void *table, u32 val)
842 {
843 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(12));
844 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_DCM,
845 			   BIT(12));
846 }
847 #define SET_CMC_TBL_MASK_DATA_ER BIT(0)
SET_CMC_TBL_DATA_ER(void * table,u32 val)848 static inline void SET_CMC_TBL_DATA_ER(void *table, u32 val)
849 {
850 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(13));
851 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_ER,
852 			   BIT(13));
853 }
854 #define SET_CMC_TBL_MASK_DATA_LDPC BIT(0)
SET_CMC_TBL_DATA_LDPC(void * table,u32 val)855 static inline void SET_CMC_TBL_DATA_LDPC(void *table, u32 val)
856 {
857 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(14));
858 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_LDPC,
859 			   BIT(14));
860 }
861 #define SET_CMC_TBL_MASK_DATA_STBC BIT(0)
SET_CMC_TBL_DATA_STBC(void * table,u32 val)862 static inline void SET_CMC_TBL_DATA_STBC(void *table, u32 val)
863 {
864 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(15));
865 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_STBC,
866 			   BIT(15));
867 }
868 #define SET_CMC_TBL_MASK_A_CTRL_BQR BIT(0)
SET_CMC_TBL_A_CTRL_BQR(void * table,u32 val)869 static inline void SET_CMC_TBL_A_CTRL_BQR(void *table, u32 val)
870 {
871 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(16));
872 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_BQR,
873 			   BIT(16));
874 }
875 #define SET_CMC_TBL_MASK_A_CTRL_UPH BIT(0)
SET_CMC_TBL_A_CTRL_UPH(void * table,u32 val)876 static inline void SET_CMC_TBL_A_CTRL_UPH(void *table, u32 val)
877 {
878 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(17));
879 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_UPH,
880 			   BIT(17));
881 }
882 #define SET_CMC_TBL_MASK_A_CTRL_BSR BIT(0)
SET_CMC_TBL_A_CTRL_BSR(void * table,u32 val)883 static inline void SET_CMC_TBL_A_CTRL_BSR(void *table, u32 val)
884 {
885 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(18));
886 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_BSR,
887 			   BIT(18));
888 }
889 #define SET_CMC_TBL_MASK_A_CTRL_CAS BIT(0)
SET_CMC_TBL_A_CTRL_CAS(void * table,u32 val)890 static inline void SET_CMC_TBL_A_CTRL_CAS(void *table, u32 val)
891 {
892 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(19));
893 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_CAS,
894 			   BIT(19));
895 }
896 #define SET_CMC_TBL_MASK_DATA_BW_ER BIT(0)
SET_CMC_TBL_DATA_BW_ER(void * table,u32 val)897 static inline void SET_CMC_TBL_DATA_BW_ER(void *table, u32 val)
898 {
899 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(20));
900 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_BW_ER,
901 			   BIT(20));
902 }
903 #define SET_CMC_TBL_MASK_LSIG_TXOP_EN BIT(0)
SET_CMC_TBL_LSIG_TXOP_EN(void * table,u32 val)904 static inline void SET_CMC_TBL_LSIG_TXOP_EN(void *table, u32 val)
905 {
906 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(21));
907 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_LSIG_TXOP_EN,
908 			   BIT(21));
909 }
910 #define SET_CMC_TBL_MASK_CTRL_CNT_VLD BIT(0)
SET_CMC_TBL_CTRL_CNT_VLD(void * table,u32 val)911 static inline void SET_CMC_TBL_CTRL_CNT_VLD(void *table, u32 val)
912 {
913 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(27));
914 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_CTRL_CNT_VLD,
915 			   BIT(27));
916 }
917 #define SET_CMC_TBL_MASK_CTRL_CNT GENMASK(3, 0)
SET_CMC_TBL_CTRL_CNT(void * table,u32 val)918 static inline void SET_CMC_TBL_CTRL_CNT(void *table, u32 val)
919 {
920 	le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(31, 28));
921 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_CTRL_CNT,
922 			   GENMASK(31, 28));
923 }
924 #define SET_CMC_TBL_MASK_RESP_REF_RATE GENMASK(8, 0)
SET_CMC_TBL_RESP_REF_RATE(void * table,u32 val)925 static inline void SET_CMC_TBL_RESP_REF_RATE(void *table, u32 val)
926 {
927 	le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(8, 0));
928 	le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_RESP_REF_RATE,
929 			   GENMASK(8, 0));
930 }
931 #define SET_CMC_TBL_MASK_ALL_ACK_SUPPORT BIT(0)
SET_CMC_TBL_ALL_ACK_SUPPORT(void * table,u32 val)932 static inline void SET_CMC_TBL_ALL_ACK_SUPPORT(void *table, u32 val)
933 {
934 	le32p_replace_bits((__le32 *)(table) + 6, val, BIT(12));
935 	le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ALL_ACK_SUPPORT,
936 			   BIT(12));
937 }
938 #define SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT BIT(0)
SET_CMC_TBL_BSR_QUEUE_SIZE_FORMAT(void * table,u32 val)939 static inline void SET_CMC_TBL_BSR_QUEUE_SIZE_FORMAT(void *table, u32 val)
940 {
941 	le32p_replace_bits((__le32 *)(table) + 6, val, BIT(13));
942 	le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT,
943 			   BIT(13));
944 }
945 #define SET_CMC_TBL_MASK_NTX_PATH_EN GENMASK(3, 0)
SET_CMC_TBL_NTX_PATH_EN(void * table,u32 val)946 static inline void SET_CMC_TBL_NTX_PATH_EN(void *table, u32 val)
947 {
948 	le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(19, 16));
949 	le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_NTX_PATH_EN,
950 			   GENMASK(19, 16));
951 }
952 #define SET_CMC_TBL_MASK_PATH_MAP_A GENMASK(1, 0)
SET_CMC_TBL_PATH_MAP_A(void * table,u32 val)953 static inline void SET_CMC_TBL_PATH_MAP_A(void *table, u32 val)
954 {
955 	le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(21, 20));
956 	le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_A,
957 			   GENMASK(21, 20));
958 }
959 #define SET_CMC_TBL_MASK_PATH_MAP_B GENMASK(1, 0)
SET_CMC_TBL_PATH_MAP_B(void * table,u32 val)960 static inline void SET_CMC_TBL_PATH_MAP_B(void *table, u32 val)
961 {
962 	le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(23, 22));
963 	le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_B,
964 			   GENMASK(23, 22));
965 }
966 #define SET_CMC_TBL_MASK_PATH_MAP_C GENMASK(1, 0)
SET_CMC_TBL_PATH_MAP_C(void * table,u32 val)967 static inline void SET_CMC_TBL_PATH_MAP_C(void *table, u32 val)
968 {
969 	le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(25, 24));
970 	le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_C,
971 			   GENMASK(25, 24));
972 }
973 #define SET_CMC_TBL_MASK_PATH_MAP_D GENMASK(1, 0)
SET_CMC_TBL_PATH_MAP_D(void * table,u32 val)974 static inline void SET_CMC_TBL_PATH_MAP_D(void *table, u32 val)
975 {
976 	le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(27, 26));
977 	le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_D,
978 			   GENMASK(27, 26));
979 }
980 #define SET_CMC_TBL_MASK_ANTSEL_A BIT(0)
SET_CMC_TBL_ANTSEL_A(void * table,u32 val)981 static inline void SET_CMC_TBL_ANTSEL_A(void *table, u32 val)
982 {
983 	le32p_replace_bits((__le32 *)(table) + 6, val, BIT(28));
984 	le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_A,
985 			   BIT(28));
986 }
987 #define SET_CMC_TBL_MASK_ANTSEL_B BIT(0)
SET_CMC_TBL_ANTSEL_B(void * table,u32 val)988 static inline void SET_CMC_TBL_ANTSEL_B(void *table, u32 val)
989 {
990 	le32p_replace_bits((__le32 *)(table) + 6, val, BIT(29));
991 	le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_B,
992 			   BIT(29));
993 }
994 #define SET_CMC_TBL_MASK_ANTSEL_C BIT(0)
SET_CMC_TBL_ANTSEL_C(void * table,u32 val)995 static inline void SET_CMC_TBL_ANTSEL_C(void *table, u32 val)
996 {
997 	le32p_replace_bits((__le32 *)(table) + 6, val, BIT(30));
998 	le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_C,
999 			   BIT(30));
1000 }
1001 #define SET_CMC_TBL_MASK_ANTSEL_D BIT(0)
SET_CMC_TBL_ANTSEL_D(void * table,u32 val)1002 static inline void SET_CMC_TBL_ANTSEL_D(void *table, u32 val)
1003 {
1004 	le32p_replace_bits((__le32 *)(table) + 6, val, BIT(31));
1005 	le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_D,
1006 			   BIT(31));
1007 }
1008 
1009 #define SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING GENMASK(1, 0)
SET_CMC_TBL_NOMINAL_PKT_PADDING_V1(void * table,u32 val)1010 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING_V1(void *table, u32 val)
1011 {
1012 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(1, 0));
1013 	le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1014 			   GENMASK(1, 0));
1015 }
1016 
SET_CMC_TBL_NOMINAL_PKT_PADDING40_V1(void * table,u32 val)1017 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING40_V1(void *table, u32 val)
1018 {
1019 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(3, 2));
1020 	le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1021 			   GENMASK(3, 2));
1022 }
1023 
SET_CMC_TBL_NOMINAL_PKT_PADDING80_V1(void * table,u32 val)1024 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING80_V1(void *table, u32 val)
1025 {
1026 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(5, 4));
1027 	le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1028 			   GENMASK(5, 4));
1029 }
1030 
SET_CMC_TBL_NOMINAL_PKT_PADDING160_V1(void * table,u32 val)1031 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING160_V1(void *table, u32 val)
1032 {
1033 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 6));
1034 	le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1035 			   GENMASK(7, 6));
1036 }
1037 
1038 #define SET_CMC_TBL_MASK_ADDR_CAM_INDEX GENMASK(7, 0)
SET_CMC_TBL_ADDR_CAM_INDEX(void * table,u32 val)1039 static inline void SET_CMC_TBL_ADDR_CAM_INDEX(void *table, u32 val)
1040 {
1041 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 0));
1042 	le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_ADDR_CAM_INDEX,
1043 			   GENMASK(7, 0));
1044 }
1045 #define SET_CMC_TBL_MASK_PAID GENMASK(8, 0)
SET_CMC_TBL_PAID(void * table,u32 val)1046 static inline void SET_CMC_TBL_PAID(void *table, u32 val)
1047 {
1048 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(16, 8));
1049 	le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_PAID,
1050 			   GENMASK(16, 8));
1051 }
1052 #define SET_CMC_TBL_MASK_ULDL BIT(0)
SET_CMC_TBL_ULDL(void * table,u32 val)1053 static inline void SET_CMC_TBL_ULDL(void *table, u32 val)
1054 {
1055 	le32p_replace_bits((__le32 *)(table) + 7, val, BIT(17));
1056 	le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_ULDL,
1057 			   BIT(17));
1058 }
1059 #define SET_CMC_TBL_MASK_DOPPLER_CTRL GENMASK(1, 0)
SET_CMC_TBL_DOPPLER_CTRL(void * table,u32 val)1060 static inline void SET_CMC_TBL_DOPPLER_CTRL(void *table, u32 val)
1061 {
1062 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(19, 18));
1063 	le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_DOPPLER_CTRL,
1064 			   GENMASK(19, 18));
1065 }
SET_CMC_TBL_NOMINAL_PKT_PADDING(void * table,u32 val)1066 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING(void *table, u32 val)
1067 {
1068 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(21, 20));
1069 	le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1070 			   GENMASK(21, 20));
1071 }
1072 
SET_CMC_TBL_NOMINAL_PKT_PADDING40(void * table,u32 val)1073 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING40(void *table, u32 val)
1074 {
1075 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(23, 22));
1076 	le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1077 			   GENMASK(23, 22));
1078 }
1079 #define SET_CMC_TBL_MASK_TXPWR_TOLERENCE GENMASK(3, 0)
SET_CMC_TBL_TXPWR_TOLERENCE(void * table,u32 val)1080 static inline void SET_CMC_TBL_TXPWR_TOLERENCE(void *table, u32 val)
1081 {
1082 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(27, 24));
1083 	le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_TXPWR_TOLERENCE,
1084 			   GENMASK(27, 24));
1085 }
1086 
SET_CMC_TBL_NOMINAL_PKT_PADDING80(void * table,u32 val)1087 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING80(void *table, u32 val)
1088 {
1089 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(31, 30));
1090 	le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1091 			   GENMASK(31, 30));
1092 }
1093 #define SET_CMC_TBL_MASK_NC GENMASK(2, 0)
SET_CMC_TBL_NC(void * table,u32 val)1094 static inline void SET_CMC_TBL_NC(void *table, u32 val)
1095 {
1096 	le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(2, 0));
1097 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NC,
1098 			   GENMASK(2, 0));
1099 }
1100 #define SET_CMC_TBL_MASK_NR GENMASK(2, 0)
SET_CMC_TBL_NR(void * table,u32 val)1101 static inline void SET_CMC_TBL_NR(void *table, u32 val)
1102 {
1103 	le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(5, 3));
1104 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NR,
1105 			   GENMASK(5, 3));
1106 }
1107 #define SET_CMC_TBL_MASK_NG GENMASK(1, 0)
SET_CMC_TBL_NG(void * table,u32 val)1108 static inline void SET_CMC_TBL_NG(void *table, u32 val)
1109 {
1110 	le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(7, 6));
1111 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NG,
1112 			   GENMASK(7, 6));
1113 }
1114 #define SET_CMC_TBL_MASK_CB GENMASK(1, 0)
SET_CMC_TBL_CB(void * table,u32 val)1115 static inline void SET_CMC_TBL_CB(void *table, u32 val)
1116 {
1117 	le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(9, 8));
1118 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CB,
1119 			   GENMASK(9, 8));
1120 }
1121 #define SET_CMC_TBL_MASK_CS GENMASK(1, 0)
SET_CMC_TBL_CS(void * table,u32 val)1122 static inline void SET_CMC_TBL_CS(void *table, u32 val)
1123 {
1124 	le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(11, 10));
1125 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CS,
1126 			   GENMASK(11, 10));
1127 }
1128 #define SET_CMC_TBL_MASK_CSI_TXBF_EN BIT(0)
SET_CMC_TBL_CSI_TXBF_EN(void * table,u32 val)1129 static inline void SET_CMC_TBL_CSI_TXBF_EN(void *table, u32 val)
1130 {
1131 	le32p_replace_bits((__le32 *)(table) + 8, val, BIT(12));
1132 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_TXBF_EN,
1133 			   BIT(12));
1134 }
1135 #define SET_CMC_TBL_MASK_CSI_STBC_EN BIT(0)
SET_CMC_TBL_CSI_STBC_EN(void * table,u32 val)1136 static inline void SET_CMC_TBL_CSI_STBC_EN(void *table, u32 val)
1137 {
1138 	le32p_replace_bits((__le32 *)(table) + 8, val, BIT(13));
1139 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_STBC_EN,
1140 			   BIT(13));
1141 }
1142 #define SET_CMC_TBL_MASK_CSI_LDPC_EN BIT(0)
SET_CMC_TBL_CSI_LDPC_EN(void * table,u32 val)1143 static inline void SET_CMC_TBL_CSI_LDPC_EN(void *table, u32 val)
1144 {
1145 	le32p_replace_bits((__le32 *)(table) + 8, val, BIT(14));
1146 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_LDPC_EN,
1147 			   BIT(14));
1148 }
1149 #define SET_CMC_TBL_MASK_CSI_PARA_EN BIT(0)
SET_CMC_TBL_CSI_PARA_EN(void * table,u32 val)1150 static inline void SET_CMC_TBL_CSI_PARA_EN(void *table, u32 val)
1151 {
1152 	le32p_replace_bits((__le32 *)(table) + 8, val, BIT(15));
1153 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_PARA_EN,
1154 			   BIT(15));
1155 }
1156 #define SET_CMC_TBL_MASK_CSI_FIX_RATE GENMASK(8, 0)
SET_CMC_TBL_CSI_FIX_RATE(void * table,u32 val)1157 static inline void SET_CMC_TBL_CSI_FIX_RATE(void *table, u32 val)
1158 {
1159 	le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(24, 16));
1160 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_FIX_RATE,
1161 			   GENMASK(24, 16));
1162 }
1163 #define SET_CMC_TBL_MASK_CSI_GI_LTF GENMASK(2, 0)
SET_CMC_TBL_CSI_GI_LTF(void * table,u32 val)1164 static inline void SET_CMC_TBL_CSI_GI_LTF(void *table, u32 val)
1165 {
1166 	le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(27, 25));
1167 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_GI_LTF,
1168 			   GENMASK(27, 25));
1169 }
1170 
SET_CMC_TBL_NOMINAL_PKT_PADDING160(void * table,u32 val)1171 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING160(void *table, u32 val)
1172 {
1173 	le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(29, 28));
1174 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1175 			   GENMASK(29, 28));
1176 }
1177 
1178 #define SET_CMC_TBL_MASK_CSI_BW GENMASK(1, 0)
SET_CMC_TBL_CSI_BW(void * table,u32 val)1179 static inline void SET_CMC_TBL_CSI_BW(void *table, u32 val)
1180 {
1181 	le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(31, 30));
1182 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_BW,
1183 			   GENMASK(31, 30));
1184 }
1185 
SET_DCTL_MACID_V1(void * table,u32 val)1186 static inline void SET_DCTL_MACID_V1(void *table, u32 val)
1187 {
1188 	le32p_replace_bits((__le32 *)(table) + 0, val, GENMASK(6, 0));
1189 }
1190 
SET_DCTL_OPERATION_V1(void * table,u32 val)1191 static inline void SET_DCTL_OPERATION_V1(void *table, u32 val)
1192 {
1193 	le32p_replace_bits((__le32 *)(table) + 0, val, BIT(7));
1194 }
1195 
1196 #define SET_DCTL_MASK_QOS_FIELD_V1 GENMASK(7, 0)
SET_DCTL_QOS_FIELD_V1(void * table,u32 val)1197 static inline void SET_DCTL_QOS_FIELD_V1(void *table, u32 val)
1198 {
1199 	le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(7, 0));
1200 	le32p_replace_bits((__le32 *)(table) + 9, SET_DCTL_MASK_QOS_FIELD_V1,
1201 			   GENMASK(7, 0));
1202 }
1203 
1204 #define SET_DCTL_MASK_SET_DCTL_HW_EXSEQ_MACID GENMASK(6, 0)
SET_DCTL_HW_EXSEQ_MACID_V1(void * table,u32 val)1205 static inline void SET_DCTL_HW_EXSEQ_MACID_V1(void *table, u32 val)
1206 {
1207 	le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(14, 8));
1208 	le32p_replace_bits((__le32 *)(table) + 9, SET_DCTL_MASK_SET_DCTL_HW_EXSEQ_MACID,
1209 			   GENMASK(14, 8));
1210 }
1211 
1212 #define SET_DCTL_MASK_QOS_DATA BIT(0)
SET_DCTL_QOS_DATA_V1(void * table,u32 val)1213 static inline void SET_DCTL_QOS_DATA_V1(void *table, u32 val)
1214 {
1215 	le32p_replace_bits((__le32 *)(table) + 1, val, BIT(15));
1216 	le32p_replace_bits((__le32 *)(table) + 9, SET_DCTL_MASK_QOS_DATA,
1217 			   BIT(15));
1218 }
1219 
1220 #define SET_DCTL_MASK_AES_IV_L GENMASK(15, 0)
SET_DCTL_AES_IV_L_V1(void * table,u32 val)1221 static inline void SET_DCTL_AES_IV_L_V1(void *table, u32 val)
1222 {
1223 	le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(31, 16));
1224 	le32p_replace_bits((__le32 *)(table) + 9, SET_DCTL_MASK_AES_IV_L,
1225 			   GENMASK(31, 16));
1226 }
1227 
1228 #define SET_DCTL_MASK_AES_IV_H GENMASK(31, 0)
SET_DCTL_AES_IV_H_V1(void * table,u32 val)1229 static inline void SET_DCTL_AES_IV_H_V1(void *table, u32 val)
1230 {
1231 	le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(31, 0));
1232 	le32p_replace_bits((__le32 *)(table) + 10, SET_DCTL_MASK_AES_IV_H,
1233 			   GENMASK(31, 0));
1234 }
1235 
1236 #define SET_DCTL_MASK_SEQ0 GENMASK(11, 0)
SET_DCTL_SEQ0_V1(void * table,u32 val)1237 static inline void SET_DCTL_SEQ0_V1(void *table, u32 val)
1238 {
1239 	le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(11, 0));
1240 	le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_SEQ0,
1241 			   GENMASK(11, 0));
1242 }
1243 
1244 #define SET_DCTL_MASK_SEQ1 GENMASK(11, 0)
SET_DCTL_SEQ1_V1(void * table,u32 val)1245 static inline void SET_DCTL_SEQ1_V1(void *table, u32 val)
1246 {
1247 	le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(23, 12));
1248 	le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_SEQ1,
1249 			   GENMASK(23, 12));
1250 }
1251 
1252 #define SET_DCTL_MASK_AMSDU_MAX_LEN GENMASK(2, 0)
SET_DCTL_AMSDU_MAX_LEN_V1(void * table,u32 val)1253 static inline void SET_DCTL_AMSDU_MAX_LEN_V1(void *table, u32 val)
1254 {
1255 	le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(26, 24));
1256 	le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_AMSDU_MAX_LEN,
1257 			   GENMASK(26, 24));
1258 }
1259 
1260 #define SET_DCTL_MASK_STA_AMSDU_EN BIT(0)
SET_DCTL_STA_AMSDU_EN_V1(void * table,u32 val)1261 static inline void SET_DCTL_STA_AMSDU_EN_V1(void *table, u32 val)
1262 {
1263 	le32p_replace_bits((__le32 *)(table) + 3, val, BIT(27));
1264 	le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_STA_AMSDU_EN,
1265 			   BIT(27));
1266 }
1267 
1268 #define SET_DCTL_MASK_CHKSUM_OFLD_EN BIT(0)
SET_DCTL_CHKSUM_OFLD_EN_V1(void * table,u32 val)1269 static inline void SET_DCTL_CHKSUM_OFLD_EN_V1(void *table, u32 val)
1270 {
1271 	le32p_replace_bits((__le32 *)(table) + 3, val, BIT(28));
1272 	le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_CHKSUM_OFLD_EN,
1273 			   BIT(28));
1274 }
1275 
1276 #define SET_DCTL_MASK_WITH_LLC BIT(0)
SET_DCTL_WITH_LLC_V1(void * table,u32 val)1277 static inline void SET_DCTL_WITH_LLC_V1(void *table, u32 val)
1278 {
1279 	le32p_replace_bits((__le32 *)(table) + 3, val, BIT(29));
1280 	le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_WITH_LLC,
1281 			   BIT(29));
1282 }
1283 
1284 #define SET_DCTL_MASK_SEQ2 GENMASK(11, 0)
SET_DCTL_SEQ2_V1(void * table,u32 val)1285 static inline void SET_DCTL_SEQ2_V1(void *table, u32 val)
1286 {
1287 	le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(11, 0));
1288 	le32p_replace_bits((__le32 *)(table) + 12, SET_DCTL_MASK_SEQ2,
1289 			   GENMASK(11, 0));
1290 }
1291 
1292 #define SET_DCTL_MASK_SEQ3 GENMASK(11, 0)
SET_DCTL_SEQ3_V1(void * table,u32 val)1293 static inline void SET_DCTL_SEQ3_V1(void *table, u32 val)
1294 {
1295 	le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(23, 12));
1296 	le32p_replace_bits((__le32 *)(table) + 12, SET_DCTL_MASK_SEQ3,
1297 			   GENMASK(23, 12));
1298 }
1299 
1300 #define SET_DCTL_MASK_TGT_IND GENMASK(3, 0)
SET_DCTL_TGT_IND_V1(void * table,u32 val)1301 static inline void SET_DCTL_TGT_IND_V1(void *table, u32 val)
1302 {
1303 	le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(27, 24));
1304 	le32p_replace_bits((__le32 *)(table) + 12, SET_DCTL_MASK_TGT_IND,
1305 			   GENMASK(27, 24));
1306 }
1307 
1308 #define SET_DCTL_MASK_TGT_IND_EN BIT(0)
SET_DCTL_TGT_IND_EN_V1(void * table,u32 val)1309 static inline void SET_DCTL_TGT_IND_EN_V1(void *table, u32 val)
1310 {
1311 	le32p_replace_bits((__le32 *)(table) + 4, val, BIT(28));
1312 	le32p_replace_bits((__le32 *)(table) + 12, SET_DCTL_MASK_TGT_IND_EN,
1313 			   BIT(28));
1314 }
1315 
1316 #define SET_DCTL_MASK_HTC_LB GENMASK(2, 0)
SET_DCTL_HTC_LB_V1(void * table,u32 val)1317 static inline void SET_DCTL_HTC_LB_V1(void *table, u32 val)
1318 {
1319 	le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(31, 29));
1320 	le32p_replace_bits((__le32 *)(table) + 12, SET_DCTL_MASK_HTC_LB,
1321 			   GENMASK(31, 29));
1322 }
1323 
1324 #define SET_DCTL_MASK_MHDR_LEN GENMASK(4, 0)
SET_DCTL_MHDR_LEN_V1(void * table,u32 val)1325 static inline void SET_DCTL_MHDR_LEN_V1(void *table, u32 val)
1326 {
1327 	le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(4, 0));
1328 	le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_MHDR_LEN,
1329 			   GENMASK(4, 0));
1330 }
1331 
1332 #define SET_DCTL_MASK_VLAN_TAG_VALID BIT(0)
SET_DCTL_VLAN_TAG_VALID_V1(void * table,u32 val)1333 static inline void SET_DCTL_VLAN_TAG_VALID_V1(void *table, u32 val)
1334 {
1335 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(5));
1336 	le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_VLAN_TAG_VALID,
1337 			   BIT(5));
1338 }
1339 
1340 #define SET_DCTL_MASK_VLAN_TAG_SEL GENMASK(1, 0)
SET_DCTL_VLAN_TAG_SEL_V1(void * table,u32 val)1341 static inline void SET_DCTL_VLAN_TAG_SEL_V1(void *table, u32 val)
1342 {
1343 	le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(7, 6));
1344 	le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_VLAN_TAG_SEL,
1345 			   GENMASK(7, 6));
1346 }
1347 
1348 #define SET_DCTL_MASK_HTC_ORDER BIT(0)
SET_DCTL_HTC_ORDER_V1(void * table,u32 val)1349 static inline void SET_DCTL_HTC_ORDER_V1(void *table, u32 val)
1350 {
1351 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(8));
1352 	le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_HTC_ORDER,
1353 			   BIT(8));
1354 }
1355 
1356 #define SET_DCTL_MASK_SEC_KEY_ID GENMASK(1, 0)
SET_DCTL_SEC_KEY_ID_V1(void * table,u32 val)1357 static inline void SET_DCTL_SEC_KEY_ID_V1(void *table, u32 val)
1358 {
1359 	le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(10, 9));
1360 	le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_KEY_ID,
1361 			   GENMASK(10, 9));
1362 }
1363 
1364 #define SET_DCTL_MASK_WAPI BIT(0)
SET_DCTL_WAPI_V1(void * table,u32 val)1365 static inline void SET_DCTL_WAPI_V1(void *table, u32 val)
1366 {
1367 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(15));
1368 	le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_WAPI,
1369 			   BIT(15));
1370 }
1371 
1372 #define SET_DCTL_MASK_SEC_ENT_MODE GENMASK(1, 0)
SET_DCTL_SEC_ENT_MODE_V1(void * table,u32 val)1373 static inline void SET_DCTL_SEC_ENT_MODE_V1(void *table, u32 val)
1374 {
1375 	le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(17, 16));
1376 	le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENT_MODE,
1377 			   GENMASK(17, 16));
1378 }
1379 
1380 #define SET_DCTL_MASK_SEC_ENTX_KEYID GENMASK(1, 0)
SET_DCTL_SEC_ENT0_KEYID_V1(void * table,u32 val)1381 static inline void SET_DCTL_SEC_ENT0_KEYID_V1(void *table, u32 val)
1382 {
1383 	le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(19, 18));
1384 	le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID,
1385 			   GENMASK(19, 18));
1386 }
1387 
SET_DCTL_SEC_ENT1_KEYID_V1(void * table,u32 val)1388 static inline void SET_DCTL_SEC_ENT1_KEYID_V1(void *table, u32 val)
1389 {
1390 	le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(21, 20));
1391 	le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID,
1392 			   GENMASK(21, 20));
1393 }
1394 
SET_DCTL_SEC_ENT2_KEYID_V1(void * table,u32 val)1395 static inline void SET_DCTL_SEC_ENT2_KEYID_V1(void *table, u32 val)
1396 {
1397 	le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(23, 22));
1398 	le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID,
1399 			   GENMASK(23, 22));
1400 }
1401 
SET_DCTL_SEC_ENT3_KEYID_V1(void * table,u32 val)1402 static inline void SET_DCTL_SEC_ENT3_KEYID_V1(void *table, u32 val)
1403 {
1404 	le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(25, 24));
1405 	le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID,
1406 			   GENMASK(25, 24));
1407 }
1408 
SET_DCTL_SEC_ENT4_KEYID_V1(void * table,u32 val)1409 static inline void SET_DCTL_SEC_ENT4_KEYID_V1(void *table, u32 val)
1410 {
1411 	le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(27, 26));
1412 	le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID,
1413 			   GENMASK(27, 26));
1414 }
1415 
SET_DCTL_SEC_ENT5_KEYID_V1(void * table,u32 val)1416 static inline void SET_DCTL_SEC_ENT5_KEYID_V1(void *table, u32 val)
1417 {
1418 	le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(29, 28));
1419 	le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID,
1420 			   GENMASK(29, 28));
1421 }
1422 
SET_DCTL_SEC_ENT6_KEYID_V1(void * table,u32 val)1423 static inline void SET_DCTL_SEC_ENT6_KEYID_V1(void *table, u32 val)
1424 {
1425 	le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(31, 30));
1426 	le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID,
1427 			   GENMASK(31, 30));
1428 }
1429 
1430 #define SET_DCTL_MASK_SEC_ENT_VALID GENMASK(7, 0)
SET_DCTL_SEC_ENT_VALID_V1(void * table,u32 val)1431 static inline void SET_DCTL_SEC_ENT_VALID_V1(void *table, u32 val)
1432 {
1433 	le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(7, 0));
1434 	le32p_replace_bits((__le32 *)(table) + 14, SET_DCTL_MASK_SEC_ENT_VALID,
1435 			   GENMASK(7, 0));
1436 }
1437 
1438 #define SET_DCTL_MASK_SEC_ENTX GENMASK(7, 0)
SET_DCTL_SEC_ENT0_V1(void * table,u32 val)1439 static inline void SET_DCTL_SEC_ENT0_V1(void *table, u32 val)
1440 {
1441 	le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(15, 8));
1442 	le32p_replace_bits((__le32 *)(table) + 14, SET_DCTL_MASK_SEC_ENTX,
1443 			   GENMASK(15, 8));
1444 }
1445 
SET_DCTL_SEC_ENT1_V1(void * table,u32 val)1446 static inline void SET_DCTL_SEC_ENT1_V1(void *table, u32 val)
1447 {
1448 	le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(23, 16));
1449 	le32p_replace_bits((__le32 *)(table) + 14, SET_DCTL_MASK_SEC_ENTX,
1450 			   GENMASK(23, 16));
1451 }
1452 
SET_DCTL_SEC_ENT2_V1(void * table,u32 val)1453 static inline void SET_DCTL_SEC_ENT2_V1(void *table, u32 val)
1454 {
1455 	le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(31, 24));
1456 	le32p_replace_bits((__le32 *)(table) + 14, SET_DCTL_MASK_SEC_ENTX,
1457 			   GENMASK(31, 24));
1458 }
1459 
SET_DCTL_SEC_ENT3_V1(void * table,u32 val)1460 static inline void SET_DCTL_SEC_ENT3_V1(void *table, u32 val)
1461 {
1462 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 0));
1463 	le32p_replace_bits((__le32 *)(table) + 15, SET_DCTL_MASK_SEC_ENTX,
1464 			   GENMASK(7, 0));
1465 }
1466 
SET_DCTL_SEC_ENT4_V1(void * table,u32 val)1467 static inline void SET_DCTL_SEC_ENT4_V1(void *table, u32 val)
1468 {
1469 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(15, 8));
1470 	le32p_replace_bits((__le32 *)(table) + 15, SET_DCTL_MASK_SEC_ENTX,
1471 			   GENMASK(15, 8));
1472 }
1473 
SET_DCTL_SEC_ENT5_V1(void * table,u32 val)1474 static inline void SET_DCTL_SEC_ENT5_V1(void *table, u32 val)
1475 {
1476 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(23, 16));
1477 	le32p_replace_bits((__le32 *)(table) + 15, SET_DCTL_MASK_SEC_ENTX,
1478 			   GENMASK(23, 16));
1479 }
1480 
SET_DCTL_SEC_ENT6_V1(void * table,u32 val)1481 static inline void SET_DCTL_SEC_ENT6_V1(void *table, u32 val)
1482 {
1483 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(31, 24));
1484 	le32p_replace_bits((__le32 *)(table) + 15, SET_DCTL_MASK_SEC_ENTX,
1485 			   GENMASK(31, 24));
1486 }
1487 
SET_BCN_UPD_PORT(void * h2c,u32 val)1488 static inline void SET_BCN_UPD_PORT(void *h2c, u32 val)
1489 {
1490 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1491 }
1492 
SET_BCN_UPD_MBSSID(void * h2c,u32 val)1493 static inline void SET_BCN_UPD_MBSSID(void *h2c, u32 val)
1494 {
1495 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1496 }
1497 
SET_BCN_UPD_BAND(void * h2c,u32 val)1498 static inline void SET_BCN_UPD_BAND(void *h2c, u32 val)
1499 {
1500 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16));
1501 }
1502 
SET_BCN_UPD_GRP_IE_OFST(void * h2c,u32 val)1503 static inline void SET_BCN_UPD_GRP_IE_OFST(void *h2c, u32 val)
1504 {
1505 	le32p_replace_bits((__le32 *)h2c, (val - 24) | BIT(7), GENMASK(31, 24));
1506 }
1507 
SET_BCN_UPD_MACID(void * h2c,u32 val)1508 static inline void SET_BCN_UPD_MACID(void *h2c, u32 val)
1509 {
1510 	le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0));
1511 }
1512 
SET_BCN_UPD_SSN_SEL(void * h2c,u32 val)1513 static inline void SET_BCN_UPD_SSN_SEL(void *h2c, u32 val)
1514 {
1515 	le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(9, 8));
1516 }
1517 
SET_BCN_UPD_SSN_MODE(void * h2c,u32 val)1518 static inline void SET_BCN_UPD_SSN_MODE(void *h2c, u32 val)
1519 {
1520 	le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(11, 10));
1521 }
1522 
SET_BCN_UPD_RATE(void * h2c,u32 val)1523 static inline void SET_BCN_UPD_RATE(void *h2c, u32 val)
1524 {
1525 	le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(20, 12));
1526 }
1527 
SET_BCN_UPD_TXPWR(void * h2c,u32 val)1528 static inline void SET_BCN_UPD_TXPWR(void *h2c, u32 val)
1529 {
1530 	le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(23, 21));
1531 }
1532 
SET_BCN_UPD_TXINFO_CTRL_EN(void * h2c,u32 val)1533 static inline void SET_BCN_UPD_TXINFO_CTRL_EN(void *h2c, u32 val)
1534 {
1535 	le32p_replace_bits((__le32 *)(h2c) + 2, val, BIT(0));
1536 }
1537 
SET_BCN_UPD_NTX_PATH_EN(void * h2c,u32 val)1538 static inline void SET_BCN_UPD_NTX_PATH_EN(void *h2c, u32 val)
1539 {
1540 	le32p_replace_bits((__le32 *)(h2c) + 2, val,  GENMASK(4, 1));
1541 }
1542 
SET_BCN_UPD_PATH_MAP_A(void * h2c,u32 val)1543 static inline void SET_BCN_UPD_PATH_MAP_A(void *h2c, u32 val)
1544 {
1545 	le32p_replace_bits((__le32 *)(h2c) + 2, val,  GENMASK(6, 5));
1546 }
1547 
SET_BCN_UPD_PATH_MAP_B(void * h2c,u32 val)1548 static inline void SET_BCN_UPD_PATH_MAP_B(void *h2c, u32 val)
1549 {
1550 	le32p_replace_bits((__le32 *)(h2c) + 2, val,  GENMASK(8, 7));
1551 }
1552 
SET_BCN_UPD_PATH_MAP_C(void * h2c,u32 val)1553 static inline void SET_BCN_UPD_PATH_MAP_C(void *h2c, u32 val)
1554 {
1555 	le32p_replace_bits((__le32 *)(h2c) + 2, val,  GENMASK(10, 9));
1556 }
1557 
SET_BCN_UPD_PATH_MAP_D(void * h2c,u32 val)1558 static inline void SET_BCN_UPD_PATH_MAP_D(void *h2c, u32 val)
1559 {
1560 	le32p_replace_bits((__le32 *)(h2c) + 2, val,  GENMASK(12, 11));
1561 }
1562 
SET_BCN_UPD_PATH_ANTSEL_A(void * h2c,u32 val)1563 static inline void SET_BCN_UPD_PATH_ANTSEL_A(void *h2c, u32 val)
1564 {
1565 	le32p_replace_bits((__le32 *)(h2c) + 2, val,  BIT(13));
1566 }
1567 
SET_BCN_UPD_PATH_ANTSEL_B(void * h2c,u32 val)1568 static inline void SET_BCN_UPD_PATH_ANTSEL_B(void *h2c, u32 val)
1569 {
1570 	le32p_replace_bits((__le32 *)(h2c) + 2, val,  BIT(14));
1571 }
1572 
SET_BCN_UPD_PATH_ANTSEL_C(void * h2c,u32 val)1573 static inline void SET_BCN_UPD_PATH_ANTSEL_C(void *h2c, u32 val)
1574 {
1575 	le32p_replace_bits((__le32 *)(h2c) + 2, val,  BIT(15));
1576 }
1577 
SET_BCN_UPD_PATH_ANTSEL_D(void * h2c,u32 val)1578 static inline void SET_BCN_UPD_PATH_ANTSEL_D(void *h2c, u32 val)
1579 {
1580 	le32p_replace_bits((__le32 *)(h2c) + 2, val,  BIT(16));
1581 }
1582 
SET_BCN_UPD_CSA_OFST(void * h2c,u32 val)1583 static inline void SET_BCN_UPD_CSA_OFST(void *h2c, u32 val)
1584 {
1585 	le32p_replace_bits((__le32 *)(h2c) + 2, val,  GENMASK(31, 17));
1586 }
1587 
SET_FWROLE_MAINTAIN_MACID(void * h2c,u32 val)1588 static inline void SET_FWROLE_MAINTAIN_MACID(void *h2c, u32 val)
1589 {
1590 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1591 }
1592 
SET_FWROLE_MAINTAIN_SELF_ROLE(void * h2c,u32 val)1593 static inline void SET_FWROLE_MAINTAIN_SELF_ROLE(void *h2c, u32 val)
1594 {
1595 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(9, 8));
1596 }
1597 
SET_FWROLE_MAINTAIN_UPD_MODE(void * h2c,u32 val)1598 static inline void SET_FWROLE_MAINTAIN_UPD_MODE(void *h2c, u32 val)
1599 {
1600 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(12, 10));
1601 }
1602 
SET_FWROLE_MAINTAIN_WIFI_ROLE(void * h2c,u32 val)1603 static inline void SET_FWROLE_MAINTAIN_WIFI_ROLE(void *h2c, u32 val)
1604 {
1605 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(16, 13));
1606 }
1607 
SET_JOININFO_MACID(void * h2c,u32 val)1608 static inline void SET_JOININFO_MACID(void *h2c, u32 val)
1609 {
1610 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1611 }
1612 
SET_JOININFO_OP(void * h2c,u32 val)1613 static inline void SET_JOININFO_OP(void *h2c, u32 val)
1614 {
1615 	le32p_replace_bits((__le32 *)h2c, val, BIT(8));
1616 }
1617 
SET_JOININFO_BAND(void * h2c,u32 val)1618 static inline void SET_JOININFO_BAND(void *h2c, u32 val)
1619 {
1620 	le32p_replace_bits((__le32 *)h2c, val, BIT(9));
1621 }
1622 
SET_JOININFO_WMM(void * h2c,u32 val)1623 static inline void SET_JOININFO_WMM(void *h2c, u32 val)
1624 {
1625 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(11, 10));
1626 }
1627 
SET_JOININFO_TGR(void * h2c,u32 val)1628 static inline void SET_JOININFO_TGR(void *h2c, u32 val)
1629 {
1630 	le32p_replace_bits((__le32 *)h2c, val, BIT(12));
1631 }
1632 
SET_JOININFO_ISHESTA(void * h2c,u32 val)1633 static inline void SET_JOININFO_ISHESTA(void *h2c, u32 val)
1634 {
1635 	le32p_replace_bits((__le32 *)h2c, val, BIT(13));
1636 }
1637 
SET_JOININFO_DLBW(void * h2c,u32 val)1638 static inline void SET_JOININFO_DLBW(void *h2c, u32 val)
1639 {
1640 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 14));
1641 }
1642 
SET_JOININFO_TF_MAC_PAD(void * h2c,u32 val)1643 static inline void SET_JOININFO_TF_MAC_PAD(void *h2c, u32 val)
1644 {
1645 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(17, 16));
1646 }
1647 
SET_JOININFO_DL_T_PE(void * h2c,u32 val)1648 static inline void SET_JOININFO_DL_T_PE(void *h2c, u32 val)
1649 {
1650 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(20, 18));
1651 }
1652 
SET_JOININFO_PORT_ID(void * h2c,u32 val)1653 static inline void SET_JOININFO_PORT_ID(void *h2c, u32 val)
1654 {
1655 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 21));
1656 }
1657 
SET_JOININFO_NET_TYPE(void * h2c,u32 val)1658 static inline void SET_JOININFO_NET_TYPE(void *h2c, u32 val)
1659 {
1660 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(25, 24));
1661 }
1662 
SET_JOININFO_WIFI_ROLE(void * h2c,u32 val)1663 static inline void SET_JOININFO_WIFI_ROLE(void *h2c, u32 val)
1664 {
1665 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(29, 26));
1666 }
1667 
SET_JOININFO_SELF_ROLE(void * h2c,u32 val)1668 static inline void SET_JOININFO_SELF_ROLE(void *h2c, u32 val)
1669 {
1670 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 30));
1671 }
1672 
SET_GENERAL_PKT_MACID(void * h2c,u32 val)1673 static inline void SET_GENERAL_PKT_MACID(void *h2c, u32 val)
1674 {
1675 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1676 }
1677 
SET_GENERAL_PKT_PROBRSP_ID(void * h2c,u32 val)1678 static inline void SET_GENERAL_PKT_PROBRSP_ID(void *h2c, u32 val)
1679 {
1680 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1681 }
1682 
SET_GENERAL_PKT_PSPOLL_ID(void * h2c,u32 val)1683 static inline void SET_GENERAL_PKT_PSPOLL_ID(void *h2c, u32 val)
1684 {
1685 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16));
1686 }
1687 
SET_GENERAL_PKT_NULL_ID(void * h2c,u32 val)1688 static inline void SET_GENERAL_PKT_NULL_ID(void *h2c, u32 val)
1689 {
1690 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
1691 }
1692 
SET_GENERAL_PKT_QOS_NULL_ID(void * h2c,u32 val)1693 static inline void SET_GENERAL_PKT_QOS_NULL_ID(void *h2c, u32 val)
1694 {
1695 	le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0));
1696 }
1697 
SET_GENERAL_PKT_CTS2SELF_ID(void * h2c,u32 val)1698 static inline void SET_GENERAL_PKT_CTS2SELF_ID(void *h2c, u32 val)
1699 {
1700 	le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(15, 8));
1701 }
1702 
SET_LOG_CFG_LEVEL(void * h2c,u32 val)1703 static inline void SET_LOG_CFG_LEVEL(void *h2c, u32 val)
1704 {
1705 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1706 }
1707 
SET_LOG_CFG_PATH(void * h2c,u32 val)1708 static inline void SET_LOG_CFG_PATH(void *h2c, u32 val)
1709 {
1710 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1711 }
1712 
SET_LOG_CFG_COMP(void * h2c,u32 val)1713 static inline void SET_LOG_CFG_COMP(void *h2c, u32 val)
1714 {
1715 	le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(31, 0));
1716 }
1717 
SET_LOG_CFG_COMP_EXT(void * h2c,u32 val)1718 static inline void SET_LOG_CFG_COMP_EXT(void *h2c, u32 val)
1719 {
1720 	le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(31, 0));
1721 }
1722 
SET_BA_CAM_VALID(void * h2c,u32 val)1723 static inline void SET_BA_CAM_VALID(void *h2c, u32 val)
1724 {
1725 	le32p_replace_bits((__le32 *)h2c, val, BIT(0));
1726 }
1727 
SET_BA_CAM_INIT_REQ(void * h2c,u32 val)1728 static inline void SET_BA_CAM_INIT_REQ(void *h2c, u32 val)
1729 {
1730 	le32p_replace_bits((__le32 *)h2c, val, BIT(1));
1731 }
1732 
SET_BA_CAM_ENTRY_IDX(void * h2c,u32 val)1733 static inline void SET_BA_CAM_ENTRY_IDX(void *h2c, u32 val)
1734 {
1735 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(3, 2));
1736 }
1737 
SET_BA_CAM_TID(void * h2c,u32 val)1738 static inline void SET_BA_CAM_TID(void *h2c, u32 val)
1739 {
1740 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 4));
1741 }
1742 
SET_BA_CAM_MACID(void * h2c,u32 val)1743 static inline void SET_BA_CAM_MACID(void *h2c, u32 val)
1744 {
1745 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1746 }
1747 
SET_BA_CAM_BMAP_SIZE(void * h2c,u32 val)1748 static inline void SET_BA_CAM_BMAP_SIZE(void *h2c, u32 val)
1749 {
1750 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(19, 16));
1751 }
1752 
SET_BA_CAM_SSN(void * h2c,u32 val)1753 static inline void SET_BA_CAM_SSN(void *h2c, u32 val)
1754 {
1755 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 20));
1756 }
1757 
SET_BA_CAM_UID(void * h2c,u32 val)1758 static inline void SET_BA_CAM_UID(void *h2c, u32 val)
1759 {
1760 	le32p_replace_bits((__le32 *)h2c + 1, val, GENMASK(7, 0));
1761 }
1762 
SET_BA_CAM_STD_EN(void * h2c,u32 val)1763 static inline void SET_BA_CAM_STD_EN(void *h2c, u32 val)
1764 {
1765 	le32p_replace_bits((__le32 *)h2c + 1, val, BIT(8));
1766 }
1767 
SET_BA_CAM_BAND(void * h2c,u32 val)1768 static inline void SET_BA_CAM_BAND(void *h2c, u32 val)
1769 {
1770 	le32p_replace_bits((__le32 *)h2c + 1, val, BIT(9));
1771 }
1772 
SET_BA_CAM_ENTRY_IDX_V1(void * h2c,u32 val)1773 static inline void SET_BA_CAM_ENTRY_IDX_V1(void *h2c, u32 val)
1774 {
1775 	le32p_replace_bits((__le32 *)h2c + 1, val, GENMASK(31, 28));
1776 }
1777 
SET_LPS_PARM_MACID(void * h2c,u32 val)1778 static inline void SET_LPS_PARM_MACID(void *h2c, u32 val)
1779 {
1780 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1781 }
1782 
SET_LPS_PARM_PSMODE(void * h2c,u32 val)1783 static inline void SET_LPS_PARM_PSMODE(void *h2c, u32 val)
1784 {
1785 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1786 }
1787 
SET_LPS_PARM_RLBM(void * h2c,u32 val)1788 static inline void SET_LPS_PARM_RLBM(void *h2c, u32 val)
1789 {
1790 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(19, 16));
1791 }
1792 
SET_LPS_PARM_SMARTPS(void * h2c,u32 val)1793 static inline void SET_LPS_PARM_SMARTPS(void *h2c, u32 val)
1794 {
1795 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 20));
1796 }
1797 
SET_LPS_PARM_AWAKEINTERVAL(void * h2c,u32 val)1798 static inline void SET_LPS_PARM_AWAKEINTERVAL(void *h2c, u32 val)
1799 {
1800 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
1801 }
1802 
SET_LPS_PARM_VOUAPSD(void * h2c,u32 val)1803 static inline void SET_LPS_PARM_VOUAPSD(void *h2c, u32 val)
1804 {
1805 	le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(0));
1806 }
1807 
SET_LPS_PARM_VIUAPSD(void * h2c,u32 val)1808 static inline void SET_LPS_PARM_VIUAPSD(void *h2c, u32 val)
1809 {
1810 	le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(1));
1811 }
1812 
SET_LPS_PARM_BEUAPSD(void * h2c,u32 val)1813 static inline void SET_LPS_PARM_BEUAPSD(void *h2c, u32 val)
1814 {
1815 	le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(2));
1816 }
1817 
SET_LPS_PARM_BKUAPSD(void * h2c,u32 val)1818 static inline void SET_LPS_PARM_BKUAPSD(void *h2c, u32 val)
1819 {
1820 	le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(3));
1821 }
1822 
SET_LPS_PARM_LASTRPWM(void * h2c,u32 val)1823 static inline void SET_LPS_PARM_LASTRPWM(void *h2c, u32 val)
1824 {
1825 	le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(15, 8));
1826 }
1827 
RTW89_SET_FWCMD_CPU_EXCEPTION_TYPE(void * cmd,u32 val)1828 static inline void RTW89_SET_FWCMD_CPU_EXCEPTION_TYPE(void *cmd, u32 val)
1829 {
1830 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 0));
1831 }
1832 
RTW89_SET_FWCMD_PKT_DROP_SEL(void * cmd,u32 val)1833 static inline void RTW89_SET_FWCMD_PKT_DROP_SEL(void *cmd, u32 val)
1834 {
1835 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0));
1836 }
1837 
RTW89_SET_FWCMD_PKT_DROP_MACID(void * cmd,u32 val)1838 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID(void *cmd, u32 val)
1839 {
1840 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
1841 }
1842 
RTW89_SET_FWCMD_PKT_DROP_BAND(void * cmd,u32 val)1843 static inline void RTW89_SET_FWCMD_PKT_DROP_BAND(void *cmd, u32 val)
1844 {
1845 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
1846 }
1847 
RTW89_SET_FWCMD_PKT_DROP_PORT(void * cmd,u32 val)1848 static inline void RTW89_SET_FWCMD_PKT_DROP_PORT(void *cmd, u32 val)
1849 {
1850 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
1851 }
1852 
RTW89_SET_FWCMD_PKT_DROP_MBSSID(void * cmd,u32 val)1853 static inline void RTW89_SET_FWCMD_PKT_DROP_MBSSID(void *cmd, u32 val)
1854 {
1855 	le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(7, 0));
1856 }
1857 
RTW89_SET_FWCMD_PKT_DROP_ROLE_A_INFO_TF_TRS(void * cmd,u32 val)1858 static inline void RTW89_SET_FWCMD_PKT_DROP_ROLE_A_INFO_TF_TRS(void *cmd, u32 val)
1859 {
1860 	le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(15, 8));
1861 }
1862 
1863 enum rtw89_btc_btf_h2c_class {
1864 	BTFC_SET = 0x10,
1865 	BTFC_GET = 0x11,
1866 	BTFC_FW_EVENT = 0x12,
1867 };
1868 
1869 enum rtw89_btc_btf_set {
1870 	SET_REPORT_EN = 0x0,
1871 	SET_SLOT_TABLE,
1872 	SET_MREG_TABLE,
1873 	SET_CX_POLICY,
1874 	SET_GPIO_DBG,
1875 	SET_DRV_INFO,
1876 	SET_DRV_EVENT,
1877 	SET_BT_WREG_ADDR,
1878 	SET_BT_WREG_VAL,
1879 	SET_BT_RREG_ADDR,
1880 	SET_BT_WL_CH_INFO,
1881 	SET_BT_INFO_REPORT,
1882 	SET_BT_IGNORE_WLAN_ACT,
1883 	SET_BT_TX_PWR,
1884 	SET_BT_LNA_CONSTRAIN,
1885 	SET_BT_GOLDEN_RX_RANGE,
1886 	SET_BT_PSD_REPORT,
1887 	SET_H2C_TEST,
1888 	SET_MAX1,
1889 };
1890 
1891 enum rtw89_btc_cxdrvinfo {
1892 	CXDRVINFO_INIT = 0,
1893 	CXDRVINFO_ROLE,
1894 	CXDRVINFO_DBCC,
1895 	CXDRVINFO_SMAP,
1896 	CXDRVINFO_RFK,
1897 	CXDRVINFO_RUN,
1898 	CXDRVINFO_CTRL,
1899 	CXDRVINFO_SCAN,
1900 	CXDRVINFO_MAX,
1901 };
1902 
1903 enum rtw89_scan_mode {
1904 	RTW89_SCAN_IMMEDIATE,
1905 };
1906 
1907 enum rtw89_scan_type {
1908 	RTW89_SCAN_ONCE,
1909 };
1910 
RTW89_SET_FWCMD_CXHDR_TYPE(void * cmd,u8 val)1911 static inline void RTW89_SET_FWCMD_CXHDR_TYPE(void *cmd, u8 val)
1912 {
1913 	u8p_replace_bits((u8 *)(cmd) + 0, val, GENMASK(7, 0));
1914 }
1915 
RTW89_SET_FWCMD_CXHDR_LEN(void * cmd,u8 val)1916 static inline void RTW89_SET_FWCMD_CXHDR_LEN(void *cmd, u8 val)
1917 {
1918 	u8p_replace_bits((u8 *)(cmd) + 1, val, GENMASK(7, 0));
1919 }
1920 
RTW89_SET_FWCMD_CXINIT_ANT_TYPE(void * cmd,u8 val)1921 static inline void RTW89_SET_FWCMD_CXINIT_ANT_TYPE(void *cmd, u8 val)
1922 {
1923 	u8p_replace_bits((u8 *)(cmd) + 2, val, GENMASK(7, 0));
1924 }
1925 
RTW89_SET_FWCMD_CXINIT_ANT_NUM(void * cmd,u8 val)1926 static inline void RTW89_SET_FWCMD_CXINIT_ANT_NUM(void *cmd, u8 val)
1927 {
1928 	u8p_replace_bits((u8 *)(cmd) + 3, val, GENMASK(7, 0));
1929 }
1930 
RTW89_SET_FWCMD_CXINIT_ANT_ISO(void * cmd,u8 val)1931 static inline void RTW89_SET_FWCMD_CXINIT_ANT_ISO(void *cmd, u8 val)
1932 {
1933 	u8p_replace_bits((u8 *)(cmd) + 4, val, GENMASK(7, 0));
1934 }
1935 
RTW89_SET_FWCMD_CXINIT_ANT_POS(void * cmd,u8 val)1936 static inline void RTW89_SET_FWCMD_CXINIT_ANT_POS(void *cmd, u8 val)
1937 {
1938 	u8p_replace_bits((u8 *)(cmd) + 5, val, BIT(0));
1939 }
1940 
RTW89_SET_FWCMD_CXINIT_ANT_DIVERSITY(void * cmd,u8 val)1941 static inline void RTW89_SET_FWCMD_CXINIT_ANT_DIVERSITY(void *cmd, u8 val)
1942 {
1943 	u8p_replace_bits((u8 *)(cmd) + 5, val, BIT(1));
1944 }
1945 
RTW89_SET_FWCMD_CXINIT_MOD_RFE(void * cmd,u8 val)1946 static inline void RTW89_SET_FWCMD_CXINIT_MOD_RFE(void *cmd, u8 val)
1947 {
1948 	u8p_replace_bits((u8 *)(cmd) + 6, val, GENMASK(7, 0));
1949 }
1950 
RTW89_SET_FWCMD_CXINIT_MOD_CV(void * cmd,u8 val)1951 static inline void RTW89_SET_FWCMD_CXINIT_MOD_CV(void *cmd, u8 val)
1952 {
1953 	u8p_replace_bits((u8 *)(cmd) + 7, val, GENMASK(7, 0));
1954 }
1955 
RTW89_SET_FWCMD_CXINIT_MOD_BT_SOLO(void * cmd,u8 val)1956 static inline void RTW89_SET_FWCMD_CXINIT_MOD_BT_SOLO(void *cmd, u8 val)
1957 {
1958 	u8p_replace_bits((u8 *)(cmd) + 8, val, BIT(0));
1959 }
1960 
RTW89_SET_FWCMD_CXINIT_MOD_BT_POS(void * cmd,u8 val)1961 static inline void RTW89_SET_FWCMD_CXINIT_MOD_BT_POS(void *cmd, u8 val)
1962 {
1963 	u8p_replace_bits((u8 *)(cmd) + 8, val, BIT(1));
1964 }
1965 
RTW89_SET_FWCMD_CXINIT_MOD_SW_TYPE(void * cmd,u8 val)1966 static inline void RTW89_SET_FWCMD_CXINIT_MOD_SW_TYPE(void *cmd, u8 val)
1967 {
1968 	u8p_replace_bits((u8 *)(cmd) + 8, val, BIT(2));
1969 }
1970 
RTW89_SET_FWCMD_CXINIT_WL_GCH(void * cmd,u8 val)1971 static inline void RTW89_SET_FWCMD_CXINIT_WL_GCH(void *cmd, u8 val)
1972 {
1973 	u8p_replace_bits((u8 *)(cmd) + 10, val, GENMASK(7, 0));
1974 }
1975 
RTW89_SET_FWCMD_CXINIT_WL_ONLY(void * cmd,u8 val)1976 static inline void RTW89_SET_FWCMD_CXINIT_WL_ONLY(void *cmd, u8 val)
1977 {
1978 	u8p_replace_bits((u8 *)(cmd) + 11, val, BIT(0));
1979 }
1980 
RTW89_SET_FWCMD_CXINIT_WL_INITOK(void * cmd,u8 val)1981 static inline void RTW89_SET_FWCMD_CXINIT_WL_INITOK(void *cmd, u8 val)
1982 {
1983 	u8p_replace_bits((u8 *)(cmd) + 11, val, BIT(1));
1984 }
1985 
RTW89_SET_FWCMD_CXINIT_DBCC_EN(void * cmd,u8 val)1986 static inline void RTW89_SET_FWCMD_CXINIT_DBCC_EN(void *cmd, u8 val)
1987 {
1988 	u8p_replace_bits((u8 *)(cmd) + 11, val, BIT(2));
1989 }
1990 
RTW89_SET_FWCMD_CXINIT_CX_OTHER(void * cmd,u8 val)1991 static inline void RTW89_SET_FWCMD_CXINIT_CX_OTHER(void *cmd, u8 val)
1992 {
1993 	u8p_replace_bits((u8 *)(cmd) + 11, val, BIT(3));
1994 }
1995 
RTW89_SET_FWCMD_CXINIT_BT_ONLY(void * cmd,u8 val)1996 static inline void RTW89_SET_FWCMD_CXINIT_BT_ONLY(void *cmd, u8 val)
1997 {
1998 	u8p_replace_bits((u8 *)(cmd) + 11, val, BIT(4));
1999 }
2000 
RTW89_SET_FWCMD_CXROLE_CONNECT_CNT(void * cmd,u8 val)2001 static inline void RTW89_SET_FWCMD_CXROLE_CONNECT_CNT(void *cmd, u8 val)
2002 {
2003 	u8p_replace_bits((u8 *)(cmd) + 2, val, GENMASK(7, 0));
2004 }
2005 
RTW89_SET_FWCMD_CXROLE_LINK_MODE(void * cmd,u8 val)2006 static inline void RTW89_SET_FWCMD_CXROLE_LINK_MODE(void *cmd, u8 val)
2007 {
2008 	u8p_replace_bits((u8 *)(cmd) + 3, val, GENMASK(7, 0));
2009 }
2010 
RTW89_SET_FWCMD_CXROLE_ROLE_NONE(void * cmd,u16 val)2011 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_NONE(void *cmd, u16 val)
2012 {
2013 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(0));
2014 }
2015 
RTW89_SET_FWCMD_CXROLE_ROLE_STA(void * cmd,u16 val)2016 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_STA(void *cmd, u16 val)
2017 {
2018 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(1));
2019 }
2020 
RTW89_SET_FWCMD_CXROLE_ROLE_AP(void * cmd,u16 val)2021 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_AP(void *cmd, u16 val)
2022 {
2023 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(2));
2024 }
2025 
RTW89_SET_FWCMD_CXROLE_ROLE_VAP(void * cmd,u16 val)2026 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_VAP(void *cmd, u16 val)
2027 {
2028 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(3));
2029 }
2030 
RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC(void * cmd,u16 val)2031 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC(void *cmd, u16 val)
2032 {
2033 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(4));
2034 }
2035 
RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC_MASTER(void * cmd,u16 val)2036 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC_MASTER(void *cmd, u16 val)
2037 {
2038 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(5));
2039 }
2040 
RTW89_SET_FWCMD_CXROLE_ROLE_MESH(void * cmd,u16 val)2041 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_MESH(void *cmd, u16 val)
2042 {
2043 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(6));
2044 }
2045 
RTW89_SET_FWCMD_CXROLE_ROLE_MONITOR(void * cmd,u16 val)2046 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_MONITOR(void *cmd, u16 val)
2047 {
2048 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(7));
2049 }
2050 
RTW89_SET_FWCMD_CXROLE_ROLE_P2P_DEV(void * cmd,u16 val)2051 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_DEV(void *cmd, u16 val)
2052 {
2053 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(8));
2054 }
2055 
RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GC(void * cmd,u16 val)2056 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GC(void *cmd, u16 val)
2057 {
2058 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(9));
2059 }
2060 
RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GO(void * cmd,u16 val)2061 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GO(void *cmd, u16 val)
2062 {
2063 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(10));
2064 }
2065 
RTW89_SET_FWCMD_CXROLE_ROLE_NAN(void * cmd,u16 val)2066 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_NAN(void *cmd, u16 val)
2067 {
2068 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(11));
2069 }
2070 
RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED(void * cmd,u8 val,int n,u8 offset)2071 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED(void *cmd, u8 val, int n, u8 offset)
2072 {
2073 	u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(0));
2074 }
2075 
RTW89_SET_FWCMD_CXROLE_ACT_PID(void * cmd,u8 val,int n,u8 offset)2076 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PID(void *cmd, u8 val, int n, u8 offset)
2077 {
2078 	u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(3, 1));
2079 }
2080 
RTW89_SET_FWCMD_CXROLE_ACT_PHY(void * cmd,u8 val,int n,u8 offset)2081 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PHY(void *cmd, u8 val, int n, u8 offset)
2082 {
2083 	u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(4));
2084 }
2085 
RTW89_SET_FWCMD_CXROLE_ACT_NOA(void * cmd,u8 val,int n,u8 offset)2086 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA(void *cmd, u8 val, int n, u8 offset)
2087 {
2088 	u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(5));
2089 }
2090 
RTW89_SET_FWCMD_CXROLE_ACT_BAND(void * cmd,u8 val,int n,u8 offset)2091 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BAND(void *cmd, u8 val, int n, u8 offset)
2092 {
2093 	u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(7, 6));
2094 }
2095 
RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS(void * cmd,u8 val,int n,u8 offset)2096 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS(void *cmd, u8 val, int n, u8 offset)
2097 {
2098 	u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, BIT(0));
2099 }
2100 
RTW89_SET_FWCMD_CXROLE_ACT_BW(void * cmd,u8 val,int n,u8 offset)2101 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BW(void *cmd, u8 val, int n, u8 offset)
2102 {
2103 	u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, GENMASK(7, 1));
2104 }
2105 
RTW89_SET_FWCMD_CXROLE_ACT_ROLE(void * cmd,u8 val,int n,u8 offset)2106 static inline void RTW89_SET_FWCMD_CXROLE_ACT_ROLE(void *cmd, u8 val, int n, u8 offset)
2107 {
2108 	u8p_replace_bits((u8 *)cmd + (8 + (12 + offset) * n), val, GENMASK(7, 0));
2109 }
2110 
RTW89_SET_FWCMD_CXROLE_ACT_CH(void * cmd,u8 val,int n,u8 offset)2111 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CH(void *cmd, u8 val, int n, u8 offset)
2112 {
2113 	u8p_replace_bits((u8 *)cmd + (9 + (12 + offset) * n), val, GENMASK(7, 0));
2114 }
2115 
RTW89_SET_FWCMD_CXROLE_ACT_TX_LVL(void * cmd,u16 val,int n,u8 offset)2116 static inline void RTW89_SET_FWCMD_CXROLE_ACT_TX_LVL(void *cmd, u16 val, int n, u8 offset)
2117 {
2118 	le16p_replace_bits((__le16 *)((u8 *)cmd + (10 + (12 + offset) * n)), val, GENMASK(15, 0));
2119 }
2120 
RTW89_SET_FWCMD_CXROLE_ACT_RX_LVL(void * cmd,u16 val,int n,u8 offset)2121 static inline void RTW89_SET_FWCMD_CXROLE_ACT_RX_LVL(void *cmd, u16 val, int n, u8 offset)
2122 {
2123 	le16p_replace_bits((__le16 *)((u8 *)cmd + (12 + (12 + offset) * n)), val, GENMASK(15, 0));
2124 }
2125 
RTW89_SET_FWCMD_CXROLE_ACT_TX_RATE(void * cmd,u16 val,int n,u8 offset)2126 static inline void RTW89_SET_FWCMD_CXROLE_ACT_TX_RATE(void *cmd, u16 val, int n, u8 offset)
2127 {
2128 	le16p_replace_bits((__le16 *)((u8 *)cmd + (14 + (12 + offset) * n)), val, GENMASK(15, 0));
2129 }
2130 
RTW89_SET_FWCMD_CXROLE_ACT_RX_RATE(void * cmd,u16 val,int n,u8 offset)2131 static inline void RTW89_SET_FWCMD_CXROLE_ACT_RX_RATE(void *cmd, u16 val, int n, u8 offset)
2132 {
2133 	le16p_replace_bits((__le16 *)((u8 *)cmd + (16 + (12 + offset) * n)), val, GENMASK(15, 0));
2134 }
2135 
RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR(void * cmd,u32 val,int n,u8 offset)2136 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR(void *cmd, u32 val, int n, u8 offset)
2137 {
2138 	le32p_replace_bits((__le32 *)((u8 *)cmd + (20 + (12 + offset) * n)), val, GENMASK(31, 0));
2139 }
2140 
RTW89_SET_FWCMD_CXROLE_MROLE_TYPE(void * cmd,u32 val,u8 offset)2141 static inline void RTW89_SET_FWCMD_CXROLE_MROLE_TYPE(void *cmd, u32 val, u8 offset)
2142 {
2143 	le32p_replace_bits((__le32 *)((u8 *)cmd + offset), val, GENMASK(31, 0));
2144 }
2145 
RTW89_SET_FWCMD_CXROLE_MROLE_NOA(void * cmd,u32 val,u8 offset)2146 static inline void RTW89_SET_FWCMD_CXROLE_MROLE_NOA(void *cmd, u32 val, u8 offset)
2147 {
2148 	le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 4), val, GENMASK(31, 0));
2149 }
2150 
RTW89_SET_FWCMD_CXROLE_DBCC_EN(void * cmd,u32 val,u8 offset)2151 static inline void RTW89_SET_FWCMD_CXROLE_DBCC_EN(void *cmd, u32 val, u8 offset)
2152 {
2153 	le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(0));
2154 }
2155 
RTW89_SET_FWCMD_CXROLE_DBCC_CHG(void * cmd,u32 val,u8 offset)2156 static inline void RTW89_SET_FWCMD_CXROLE_DBCC_CHG(void *cmd, u32 val, u8 offset)
2157 {
2158 	le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(1));
2159 }
2160 
RTW89_SET_FWCMD_CXROLE_DBCC_2G_PHY(void * cmd,u32 val,u8 offset)2161 static inline void RTW89_SET_FWCMD_CXROLE_DBCC_2G_PHY(void *cmd, u32 val, u8 offset)
2162 {
2163 	le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, GENMASK(3, 2));
2164 }
2165 
RTW89_SET_FWCMD_CXROLE_LINK_MODE_CHG(void * cmd,u32 val,u8 offset)2166 static inline void RTW89_SET_FWCMD_CXROLE_LINK_MODE_CHG(void *cmd, u32 val, u8 offset)
2167 {
2168 	le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(4));
2169 }
2170 
RTW89_SET_FWCMD_CXCTRL_MANUAL(void * cmd,u32 val)2171 static inline void RTW89_SET_FWCMD_CXCTRL_MANUAL(void *cmd, u32 val)
2172 {
2173 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(0));
2174 }
2175 
RTW89_SET_FWCMD_CXCTRL_IGNORE_BT(void * cmd,u32 val)2176 static inline void RTW89_SET_FWCMD_CXCTRL_IGNORE_BT(void *cmd, u32 val)
2177 {
2178 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(1));
2179 }
2180 
RTW89_SET_FWCMD_CXCTRL_ALWAYS_FREERUN(void * cmd,u32 val)2181 static inline void RTW89_SET_FWCMD_CXCTRL_ALWAYS_FREERUN(void *cmd, u32 val)
2182 {
2183 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(2));
2184 }
2185 
RTW89_SET_FWCMD_CXCTRL_TRACE_STEP(void * cmd,u32 val)2186 static inline void RTW89_SET_FWCMD_CXCTRL_TRACE_STEP(void *cmd, u32 val)
2187 {
2188 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(18, 3));
2189 }
2190 
RTW89_SET_FWCMD_CXRFK_STATE(void * cmd,u32 val)2191 static inline void RTW89_SET_FWCMD_CXRFK_STATE(void *cmd, u32 val)
2192 {
2193 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(1, 0));
2194 }
2195 
RTW89_SET_FWCMD_CXRFK_PATH_MAP(void * cmd,u32 val)2196 static inline void RTW89_SET_FWCMD_CXRFK_PATH_MAP(void *cmd, u32 val)
2197 {
2198 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(5, 2));
2199 }
2200 
RTW89_SET_FWCMD_CXRFK_PHY_MAP(void * cmd,u32 val)2201 static inline void RTW89_SET_FWCMD_CXRFK_PHY_MAP(void *cmd, u32 val)
2202 {
2203 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(7, 6));
2204 }
2205 
RTW89_SET_FWCMD_CXRFK_BAND(void * cmd,u32 val)2206 static inline void RTW89_SET_FWCMD_CXRFK_BAND(void *cmd, u32 val)
2207 {
2208 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(9, 8));
2209 }
2210 
RTW89_SET_FWCMD_CXRFK_TYPE(void * cmd,u32 val)2211 static inline void RTW89_SET_FWCMD_CXRFK_TYPE(void *cmd, u32 val)
2212 {
2213 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(17, 10));
2214 }
2215 
RTW89_SET_FWCMD_PACKET_OFLD_PKT_IDX(void * cmd,u32 val)2216 static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_IDX(void *cmd, u32 val)
2217 {
2218 	le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(7, 0));
2219 }
2220 
RTW89_SET_FWCMD_PACKET_OFLD_PKT_OP(void * cmd,u32 val)2221 static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_OP(void *cmd, u32 val)
2222 {
2223 	le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(10, 8));
2224 }
2225 
RTW89_SET_FWCMD_PACKET_OFLD_PKT_LENGTH(void * cmd,u32 val)2226 static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_LENGTH(void *cmd, u32 val)
2227 {
2228 	le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(31, 16));
2229 }
2230 
RTW89_SET_FWCMD_SCANOFLD_CH_NUM(void * cmd,u32 val)2231 static inline void RTW89_SET_FWCMD_SCANOFLD_CH_NUM(void *cmd, u32 val)
2232 {
2233 	le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(7, 0));
2234 }
2235 
RTW89_SET_FWCMD_SCANOFLD_CH_SIZE(void * cmd,u32 val)2236 static inline void RTW89_SET_FWCMD_SCANOFLD_CH_SIZE(void *cmd, u32 val)
2237 {
2238 	le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(15, 8));
2239 }
2240 
RTW89_SET_FWCMD_CHINFO_PERIOD(void * cmd,u32 val)2241 static inline void RTW89_SET_FWCMD_CHINFO_PERIOD(void *cmd, u32 val)
2242 {
2243 	le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(7, 0));
2244 }
2245 
RTW89_SET_FWCMD_CHINFO_DWELL(void * cmd,u32 val)2246 static inline void RTW89_SET_FWCMD_CHINFO_DWELL(void *cmd, u32 val)
2247 {
2248 	le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(15, 8));
2249 }
2250 
RTW89_SET_FWCMD_CHINFO_CENTER_CH(void * cmd,u32 val)2251 static inline void RTW89_SET_FWCMD_CHINFO_CENTER_CH(void *cmd, u32 val)
2252 {
2253 	le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(23, 16));
2254 }
2255 
RTW89_SET_FWCMD_CHINFO_PRI_CH(void * cmd,u32 val)2256 static inline void RTW89_SET_FWCMD_CHINFO_PRI_CH(void *cmd, u32 val)
2257 {
2258 	le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(31, 24));
2259 }
2260 
RTW89_SET_FWCMD_CHINFO_BW(void * cmd,u32 val)2261 static inline void RTW89_SET_FWCMD_CHINFO_BW(void *cmd, u32 val)
2262 {
2263 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(2, 0));
2264 }
2265 
RTW89_SET_FWCMD_CHINFO_ACTION(void * cmd,u32 val)2266 static inline void RTW89_SET_FWCMD_CHINFO_ACTION(void *cmd, u32 val)
2267 {
2268 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(7, 3));
2269 }
2270 
RTW89_SET_FWCMD_CHINFO_NUM_PKT(void * cmd,u32 val)2271 static inline void RTW89_SET_FWCMD_CHINFO_NUM_PKT(void *cmd, u32 val)
2272 {
2273 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(11, 8));
2274 }
2275 
RTW89_SET_FWCMD_CHINFO_TX(void * cmd,u32 val)2276 static inline void RTW89_SET_FWCMD_CHINFO_TX(void *cmd, u32 val)
2277 {
2278 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(12));
2279 }
2280 
RTW89_SET_FWCMD_CHINFO_PAUSE_DATA(void * cmd,u32 val)2281 static inline void RTW89_SET_FWCMD_CHINFO_PAUSE_DATA(void *cmd, u32 val)
2282 {
2283 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(13));
2284 }
2285 
RTW89_SET_FWCMD_CHINFO_BAND(void * cmd,u32 val)2286 static inline void RTW89_SET_FWCMD_CHINFO_BAND(void *cmd, u32 val)
2287 {
2288 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(15, 14));
2289 }
2290 
RTW89_SET_FWCMD_CHINFO_PKT_ID(void * cmd,u32 val)2291 static inline void RTW89_SET_FWCMD_CHINFO_PKT_ID(void *cmd, u32 val)
2292 {
2293 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(23, 16));
2294 }
2295 
RTW89_SET_FWCMD_CHINFO_DFS(void * cmd,u32 val)2296 static inline void RTW89_SET_FWCMD_CHINFO_DFS(void *cmd, u32 val)
2297 {
2298 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(24));
2299 }
2300 
RTW89_SET_FWCMD_CHINFO_TX_NULL(void * cmd,u32 val)2301 static inline void RTW89_SET_FWCMD_CHINFO_TX_NULL(void *cmd, u32 val)
2302 {
2303 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(25));
2304 }
2305 
RTW89_SET_FWCMD_CHINFO_RANDOM(void * cmd,u32 val)2306 static inline void RTW89_SET_FWCMD_CHINFO_RANDOM(void *cmd, u32 val)
2307 {
2308 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(26));
2309 }
2310 
RTW89_SET_FWCMD_CHINFO_CFG_TX(void * cmd,u32 val)2311 static inline void RTW89_SET_FWCMD_CHINFO_CFG_TX(void *cmd, u32 val)
2312 {
2313 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(27));
2314 }
2315 
RTW89_SET_FWCMD_CHINFO_PKT0(void * cmd,u32 val)2316 static inline void RTW89_SET_FWCMD_CHINFO_PKT0(void *cmd, u32 val)
2317 {
2318 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 8), val, GENMASK(7, 0));
2319 }
2320 
RTW89_SET_FWCMD_CHINFO_PKT1(void * cmd,u32 val)2321 static inline void RTW89_SET_FWCMD_CHINFO_PKT1(void *cmd, u32 val)
2322 {
2323 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 8), val, GENMASK(15, 8));
2324 }
2325 
RTW89_SET_FWCMD_CHINFO_PKT2(void * cmd,u32 val)2326 static inline void RTW89_SET_FWCMD_CHINFO_PKT2(void *cmd, u32 val)
2327 {
2328 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 8), val, GENMASK(23, 16));
2329 }
2330 
RTW89_SET_FWCMD_CHINFO_PKT3(void * cmd,u32 val)2331 static inline void RTW89_SET_FWCMD_CHINFO_PKT3(void *cmd, u32 val)
2332 {
2333 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 8), val, GENMASK(31, 24));
2334 }
2335 
RTW89_SET_FWCMD_CHINFO_PKT4(void * cmd,u32 val)2336 static inline void RTW89_SET_FWCMD_CHINFO_PKT4(void *cmd, u32 val)
2337 {
2338 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 12), val, GENMASK(7, 0));
2339 }
2340 
RTW89_SET_FWCMD_CHINFO_PKT5(void * cmd,u32 val)2341 static inline void RTW89_SET_FWCMD_CHINFO_PKT5(void *cmd, u32 val)
2342 {
2343 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 12), val, GENMASK(15, 8));
2344 }
2345 
RTW89_SET_FWCMD_CHINFO_PKT6(void * cmd,u32 val)2346 static inline void RTW89_SET_FWCMD_CHINFO_PKT6(void *cmd, u32 val)
2347 {
2348 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 12), val, GENMASK(23, 16));
2349 }
2350 
RTW89_SET_FWCMD_CHINFO_PKT7(void * cmd,u32 val)2351 static inline void RTW89_SET_FWCMD_CHINFO_PKT7(void *cmd, u32 val)
2352 {
2353 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 12), val, GENMASK(31, 24));
2354 }
2355 
RTW89_SET_FWCMD_CHINFO_POWER_IDX(void * cmd,u32 val)2356 static inline void RTW89_SET_FWCMD_CHINFO_POWER_IDX(void *cmd, u32 val)
2357 {
2358 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 16), val, GENMASK(15, 0));
2359 }
2360 
RTW89_SET_FWCMD_SCANOFLD_MACID(void * cmd,u32 val)2361 static inline void RTW89_SET_FWCMD_SCANOFLD_MACID(void *cmd, u32 val)
2362 {
2363 	le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(7, 0));
2364 }
2365 
RTW89_SET_FWCMD_SCANOFLD_NORM_CY(void * cmd,u32 val)2366 static inline void RTW89_SET_FWCMD_SCANOFLD_NORM_CY(void *cmd, u32 val)
2367 {
2368 	le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(15, 8));
2369 }
2370 
RTW89_SET_FWCMD_SCANOFLD_PORT_ID(void * cmd,u32 val)2371 static inline void RTW89_SET_FWCMD_SCANOFLD_PORT_ID(void *cmd, u32 val)
2372 {
2373 	le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(18, 16));
2374 }
2375 
RTW89_SET_FWCMD_SCANOFLD_BAND(void * cmd,u32 val)2376 static inline void RTW89_SET_FWCMD_SCANOFLD_BAND(void *cmd, u32 val)
2377 {
2378 	le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, BIT(19));
2379 }
2380 
RTW89_SET_FWCMD_SCANOFLD_OPERATION(void * cmd,u32 val)2381 static inline void RTW89_SET_FWCMD_SCANOFLD_OPERATION(void *cmd, u32 val)
2382 {
2383 	le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(21, 20));
2384 }
2385 
RTW89_SET_FWCMD_SCANOFLD_TARGET_CH_BAND(void * cmd,u32 val)2386 static inline void RTW89_SET_FWCMD_SCANOFLD_TARGET_CH_BAND(void *cmd, u32 val)
2387 {
2388 	le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(23, 22));
2389 }
2390 
RTW89_SET_FWCMD_SCANOFLD_NOTIFY_END(void * cmd,u32 val)2391 static inline void RTW89_SET_FWCMD_SCANOFLD_NOTIFY_END(void *cmd, u32 val)
2392 {
2393 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(0));
2394 }
2395 
RTW89_SET_FWCMD_SCANOFLD_TARGET_CH_MODE(void * cmd,u32 val)2396 static inline void RTW89_SET_FWCMD_SCANOFLD_TARGET_CH_MODE(void *cmd, u32 val)
2397 {
2398 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(1));
2399 }
2400 
RTW89_SET_FWCMD_SCANOFLD_START_MODE(void * cmd,u32 val)2401 static inline void RTW89_SET_FWCMD_SCANOFLD_START_MODE(void *cmd, u32 val)
2402 {
2403 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(2));
2404 }
2405 
RTW89_SET_FWCMD_SCANOFLD_SCAN_TYPE(void * cmd,u32 val)2406 static inline void RTW89_SET_FWCMD_SCANOFLD_SCAN_TYPE(void *cmd, u32 val)
2407 {
2408 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(4, 3));
2409 }
2410 
RTW89_SET_FWCMD_SCANOFLD_TARGET_CH_BW(void * cmd,u32 val)2411 static inline void RTW89_SET_FWCMD_SCANOFLD_TARGET_CH_BW(void *cmd, u32 val)
2412 {
2413 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(7, 5));
2414 }
2415 
RTW89_SET_FWCMD_SCANOFLD_TARGET_PRI_CH(void * cmd,u32 val)2416 static inline void RTW89_SET_FWCMD_SCANOFLD_TARGET_PRI_CH(void *cmd, u32 val)
2417 {
2418 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(15, 8));
2419 }
2420 
RTW89_SET_FWCMD_SCANOFLD_TARGET_CENTRAL_CH(void * cmd,u32 val)2421 static inline void RTW89_SET_FWCMD_SCANOFLD_TARGET_CENTRAL_CH(void *cmd,
2422 							      u32 val)
2423 {
2424 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(23, 16));
2425 }
2426 
RTW89_SET_FWCMD_SCANOFLD_PROBE_REQ_PKT_ID(void * cmd,u32 val)2427 static inline void RTW89_SET_FWCMD_SCANOFLD_PROBE_REQ_PKT_ID(void *cmd, u32 val)
2428 {
2429 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(31, 24));
2430 }
2431 
RTW89_SET_FWCMD_SCANOFLD_NORM_PD(void * cmd,u32 val)2432 static inline void RTW89_SET_FWCMD_SCANOFLD_NORM_PD(void *cmd, u32 val)
2433 {
2434 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 8), val, GENMASK(15, 0));
2435 }
2436 
RTW89_SET_FWCMD_SCANOFLD_SLOW_PD(void * cmd,u32 val)2437 static inline void RTW89_SET_FWCMD_SCANOFLD_SLOW_PD(void *cmd, u32 val)
2438 {
2439 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 8), val, GENMASK(23, 16));
2440 }
2441 
RTW89_SET_FWCMD_SCANOFLD_TSF_HIGH(void * cmd,u32 val)2442 static inline void RTW89_SET_FWCMD_SCANOFLD_TSF_HIGH(void *cmd, u32 val)
2443 {
2444 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 12), val, GENMASK(31, 0));
2445 }
2446 
RTW89_SET_FWCMD_SCANOFLD_TSF_SLOW(void * cmd,u32 val)2447 static inline void RTW89_SET_FWCMD_SCANOFLD_TSF_SLOW(void *cmd, u32 val)
2448 {
2449 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 16), val, GENMASK(31, 0));
2450 }
2451 
RTW89_SET_FWCMD_P2P_MACID(void * cmd,u32 val)2452 static inline void RTW89_SET_FWCMD_P2P_MACID(void *cmd, u32 val)
2453 {
2454 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0));
2455 }
2456 
RTW89_SET_FWCMD_P2P_P2PID(void * cmd,u32 val)2457 static inline void RTW89_SET_FWCMD_P2P_P2PID(void *cmd, u32 val)
2458 {
2459 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(11, 8));
2460 }
2461 
RTW89_SET_FWCMD_P2P_NOAID(void * cmd,u32 val)2462 static inline void RTW89_SET_FWCMD_P2P_NOAID(void *cmd, u32 val)
2463 {
2464 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 12));
2465 }
2466 
RTW89_SET_FWCMD_P2P_ACT(void * cmd,u32 val)2467 static inline void RTW89_SET_FWCMD_P2P_ACT(void *cmd, u32 val)
2468 {
2469 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(19, 16));
2470 }
2471 
RTW89_SET_FWCMD_P2P_TYPE(void * cmd,u32 val)2472 static inline void RTW89_SET_FWCMD_P2P_TYPE(void *cmd, u32 val)
2473 {
2474 	le32p_replace_bits((__le32 *)cmd, val, BIT(20));
2475 }
2476 
RTW89_SET_FWCMD_P2P_ALL_SLEP(void * cmd,u32 val)2477 static inline void RTW89_SET_FWCMD_P2P_ALL_SLEP(void *cmd, u32 val)
2478 {
2479 	le32p_replace_bits((__le32 *)cmd, val, BIT(21));
2480 }
2481 
RTW89_SET_FWCMD_NOA_START_TIME(void * cmd,__le32 val)2482 static inline void RTW89_SET_FWCMD_NOA_START_TIME(void *cmd, __le32 val)
2483 {
2484 	*((__le32 *)cmd + 1) = val;
2485 }
2486 
RTW89_SET_FWCMD_NOA_INTERVAL(void * cmd,__le32 val)2487 static inline void RTW89_SET_FWCMD_NOA_INTERVAL(void *cmd, __le32 val)
2488 {
2489 	*((__le32 *)cmd + 2) = val;
2490 }
2491 
RTW89_SET_FWCMD_NOA_DURATION(void * cmd,__le32 val)2492 static inline void RTW89_SET_FWCMD_NOA_DURATION(void *cmd, __le32 val)
2493 {
2494 	*((__le32 *)cmd + 3) = val;
2495 }
2496 
RTW89_SET_FWCMD_NOA_COUNT(void * cmd,u32 val)2497 static inline void RTW89_SET_FWCMD_NOA_COUNT(void *cmd, u32 val)
2498 {
2499 	le32p_replace_bits((__le32 *)(cmd) + 4, val, GENMASK(7, 0));
2500 }
2501 
RTW89_SET_FWCMD_NOA_CTWINDOW(void * cmd,u32 val)2502 static inline void RTW89_SET_FWCMD_NOA_CTWINDOW(void *cmd, u32 val)
2503 {
2504 	u8 ctwnd;
2505 
2506 	if (!(val & IEEE80211_P2P_OPPPS_ENABLE_BIT))
2507 		return;
2508 	ctwnd = FIELD_GET(IEEE80211_P2P_OPPPS_CTWINDOW_MASK, val);
2509 	le32p_replace_bits((__le32 *)(cmd) + 4, ctwnd, GENMASK(23, 8));
2510 }
2511 
RTW89_SET_FWCMD_TSF32_TOGL_BAND(void * cmd,u32 val)2512 static inline void RTW89_SET_FWCMD_TSF32_TOGL_BAND(void *cmd, u32 val)
2513 {
2514 	le32p_replace_bits((__le32 *)cmd, val, BIT(0));
2515 }
2516 
RTW89_SET_FWCMD_TSF32_TOGL_EN(void * cmd,u32 val)2517 static inline void RTW89_SET_FWCMD_TSF32_TOGL_EN(void *cmd, u32 val)
2518 {
2519 	le32p_replace_bits((__le32 *)cmd, val, BIT(1));
2520 }
2521 
RTW89_SET_FWCMD_TSF32_TOGL_PORT(void * cmd,u32 val)2522 static inline void RTW89_SET_FWCMD_TSF32_TOGL_PORT(void *cmd, u32 val)
2523 {
2524 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(4, 2));
2525 }
2526 
RTW89_SET_FWCMD_TSF32_TOGL_EARLY(void * cmd,u32 val)2527 static inline void RTW89_SET_FWCMD_TSF32_TOGL_EARLY(void *cmd, u32 val)
2528 {
2529 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 16));
2530 }
2531 
2532 #define RTW89_C2H_HEADER_LEN 8
2533 
2534 #define RTW89_GET_C2H_CATEGORY(c2h) \
2535 	le32_get_bits(*((const __le32 *)c2h), GENMASK(1, 0))
2536 #define RTW89_GET_C2H_CLASS(c2h) \
2537 	le32_get_bits(*((const __le32 *)c2h), GENMASK(7, 2))
2538 #define RTW89_GET_C2H_FUNC(c2h) \
2539 	le32_get_bits(*((const __le32 *)c2h), GENMASK(15, 8))
2540 #define RTW89_GET_C2H_LEN(c2h) \
2541 	le32_get_bits(*((const __le32 *)(c2h) + 1), GENMASK(13, 0))
2542 
2543 #define RTW89_GET_C2H_LOG_SRT_PRT(c2h) (char *)((__le32 *)(c2h) + 2)
2544 #define RTW89_GET_C2H_LOG_LEN(len) ((len) - RTW89_C2H_HEADER_LEN)
2545 
2546 #define RTW89_GET_MAC_C2H_DONE_ACK_CAT(c2h) \
2547 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0))
2548 #define RTW89_GET_MAC_C2H_DONE_ACK_CLASS(c2h) \
2549 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 2))
2550 #define RTW89_GET_MAC_C2H_DONE_ACK_FUNC(c2h) \
2551 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
2552 #define RTW89_GET_MAC_C2H_DONE_ACK_H2C_RETURN(c2h) \
2553 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(23, 16))
2554 #define RTW89_GET_MAC_C2H_DONE_ACK_H2C_SEQ(c2h) \
2555 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(31, 24))
2556 
2557 #define RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h) \
2558 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0))
2559 #define RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h) \
2560 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 2))
2561 #define RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h) \
2562 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
2563 #define RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h) \
2564 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(23, 16))
2565 
2566 #define RTW89_GET_PHY_C2H_RA_RPT_MACID(c2h) \
2567 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 0))
2568 #define RTW89_GET_PHY_C2H_RA_RPT_RETRY_RATIO(c2h) \
2569 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(23, 16))
2570 #define RTW89_GET_PHY_C2H_RA_RPT_MCSNSS(c2h) \
2571 	le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(6, 0))
2572 #define RTW89_GET_PHY_C2H_RA_RPT_MD_SEL(c2h) \
2573 	le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(9, 8))
2574 #define RTW89_GET_PHY_C2H_RA_RPT_GILTF(c2h) \
2575 	le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(12, 10))
2576 #define RTW89_GET_PHY_C2H_RA_RPT_BW(c2h) \
2577 	le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(14, 13))
2578 
2579 /* VHT, HE, HT-old: [6:4]: NSS, [3:0]: MCS
2580  * HT-new: [6:5]: NA, [4:0]: MCS
2581  */
2582 #define RTW89_RA_RATE_MASK_NSS GENMASK(6, 4)
2583 #define RTW89_RA_RATE_MASK_MCS GENMASK(3, 0)
2584 #define RTW89_RA_RATE_MASK_HT_MCS GENMASK(4, 0)
2585 #define RTW89_MK_HT_RATE(nss, mcs) (FIELD_PREP(GENMASK(4, 3), nss) | \
2586 				    FIELD_PREP(GENMASK(2, 0), mcs))
2587 
2588 #define RTW89_GET_MAC_C2H_PKTOFLD_ID(c2h) \
2589 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 0))
2590 #define RTW89_GET_MAC_C2H_PKTOFLD_OP(c2h) \
2591 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(10, 8))
2592 #define RTW89_GET_MAC_C2H_PKTOFLD_LEN(c2h) \
2593 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(31, 16))
2594 
2595 #define RTW89_GET_MAC_C2H_SCANOFLD_PRI_CH(c2h) \
2596 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 0))
2597 #define RTW89_GET_MAC_C2H_SCANOFLD_RSP(c2h) \
2598 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(19, 16))
2599 #define RTW89_GET_MAC_C2H_SCANOFLD_STATUS(c2h) \
2600 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(23, 20))
2601 #define RTW89_GET_MAC_C2H_ACTUAL_PERIOD(c2h) \
2602 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(31, 24))
2603 #define RTW89_GET_MAC_C2H_SCANOFLD_TX_FAIL(c2h) \
2604 	le32_get_bits(*((const __le32 *)(c2h) + 5), GENMASK(3, 0))
2605 #define RTW89_GET_MAC_C2H_SCANOFLD_AIR_DENSITY(c2h) \
2606 	le32_get_bits(*((const __le32 *)(c2h) + 5), GENMASK(7, 4))
2607 #define RTW89_GET_MAC_C2H_SCANOFLD_BAND(c2h) \
2608 	le32_get_bits(*((const __le32 *)(c2h) + 5), GENMASK(25, 24))
2609 
2610 #define RTW89_FW_HDR_SIZE 32
2611 #define RTW89_FW_SECTION_HDR_SIZE 16
2612 
2613 #define RTW89_MFW_SIG	0xFF
2614 
2615 struct rtw89_mfw_info {
2616 	u8 cv;
2617 	u8 type; /* enum rtw89_fw_type */
2618 	u8 mp;
2619 	u8 rsvd;
2620 	__le32 shift;
2621 	__le32 size;
2622 	u8 rsvd2[4];
2623 } __packed;
2624 
2625 struct rtw89_mfw_hdr {
2626 	u8 sig;	/* RTW89_MFW_SIG */
2627 	u8 fw_nr;
2628 	u8 rsvd0[2];
2629 	struct {
2630 		u8 major;
2631 		u8 minor;
2632 		u8 sub;
2633 		u8 idx;
2634 	} ver;
2635 	u8 rsvd1[8];
2636 	struct rtw89_mfw_info info[];
2637 } __packed;
2638 
2639 struct fwcmd_hdr {
2640 	__le32 hdr0;
2641 	__le32 hdr1;
2642 };
2643 
2644 #define RTW89_H2C_RF_PAGE_SIZE 500
2645 #define RTW89_H2C_RF_PAGE_NUM 3
2646 struct rtw89_fw_h2c_rf_reg_info {
2647 	enum rtw89_rf_path rf_path;
2648 	__le32 rtw89_phy_config_rf_h2c[RTW89_H2C_RF_PAGE_NUM][RTW89_H2C_RF_PAGE_SIZE];
2649 	u16 curr_idx;
2650 };
2651 
2652 #define H2C_SEC_CAM_LEN			24
2653 
2654 #define H2C_HEADER_LEN			8
2655 #define H2C_HDR_CAT			GENMASK(1, 0)
2656 #define H2C_HDR_CLASS			GENMASK(7, 2)
2657 #define H2C_HDR_FUNC			GENMASK(15, 8)
2658 #define H2C_HDR_DEL_TYPE		GENMASK(19, 16)
2659 #define H2C_HDR_H2C_SEQ			GENMASK(31, 24)
2660 #define H2C_HDR_TOTAL_LEN		GENMASK(13, 0)
2661 #define H2C_HDR_REC_ACK			BIT(14)
2662 #define H2C_HDR_DONE_ACK		BIT(15)
2663 
2664 #define FWCMD_TYPE_H2C			0
2665 
2666 #define H2C_CAT_TEST		0x0
2667 
2668 /* CLASS 5 - FW STATUS TEST */
2669 #define H2C_CL_FW_STATUS_TEST		0x5
2670 #define H2C_FUNC_CPU_EXCEPTION		0x1
2671 
2672 #define H2C_CAT_MAC		0x1
2673 
2674 /* CLASS 0 - FW INFO */
2675 #define H2C_CL_FW_INFO			0x0
2676 #define H2C_FUNC_LOG_CFG		0x0
2677 #define H2C_FUNC_MAC_GENERAL_PKT	0x1
2678 
2679 /* CLASS 2 - PS */
2680 #define H2C_CL_MAC_PS			0x2
2681 #define H2C_FUNC_MAC_LPS_PARM		0x0
2682 #define H2C_FUNC_P2P_ACT		0x1
2683 
2684 /* CLASS 3 - FW download */
2685 #define H2C_CL_MAC_FWDL		0x3
2686 #define H2C_FUNC_MAC_FWHDR_DL		0x0
2687 
2688 /* CLASS 5 - Frame Exchange */
2689 #define H2C_CL_MAC_FR_EXCHG		0x5
2690 #define H2C_FUNC_MAC_CCTLINFO_UD	0x2
2691 #define H2C_FUNC_MAC_BCN_UPD		0x5
2692 #define H2C_FUNC_MAC_DCTLINFO_UD_V1	0x9
2693 #define H2C_FUNC_MAC_CCTLINFO_UD_V1	0xa
2694 
2695 /* CLASS 6 - Address CAM */
2696 #define H2C_CL_MAC_ADDR_CAM_UPDATE	0x6
2697 #define H2C_FUNC_MAC_ADDR_CAM_UPD	0x0
2698 
2699 /* CLASS 8 - Media Status Report */
2700 #define H2C_CL_MAC_MEDIA_RPT		0x8
2701 #define H2C_FUNC_MAC_JOININFO		0x0
2702 #define H2C_FUNC_MAC_FWROLE_MAINTAIN	0x4
2703 
2704 /* CLASS 9 - FW offload */
2705 #define H2C_CL_MAC_FW_OFLD		0x9
2706 #define H2C_FUNC_PACKET_OFLD		0x1
2707 #define H2C_FUNC_MAC_MACID_PAUSE	0x8
2708 #define H2C_FUNC_USR_EDCA		0xF
2709 #define H2C_FUNC_TSF32_TOGL		0x10
2710 #define H2C_FUNC_OFLD_CFG		0x14
2711 #define H2C_FUNC_ADD_SCANOFLD_CH	0x16
2712 #define H2C_FUNC_SCANOFLD		0x17
2713 #define H2C_FUNC_PKT_DROP		0x1b
2714 
2715 /* CLASS 10 - Security CAM */
2716 #define H2C_CL_MAC_SEC_CAM		0xa
2717 #define H2C_FUNC_MAC_SEC_UPD		0x1
2718 
2719 /* CLASS 12 - BA CAM */
2720 #define H2C_CL_BA_CAM			0xc
2721 #define H2C_FUNC_MAC_BA_CAM		0x0
2722 
2723 #define H2C_CAT_OUTSRC			0x2
2724 
2725 #define H2C_CL_OUTSRC_RA		0x1
2726 #define H2C_FUNC_OUTSRC_RA_MACIDCFG	0x0
2727 
2728 #define H2C_CL_OUTSRC_RF_REG_A		0x8
2729 #define H2C_CL_OUTSRC_RF_REG_B		0x9
2730 #define H2C_CL_OUTSRC_RF_FW_NOTIFY	0xa
2731 #define H2C_FUNC_OUTSRC_RF_GET_MCCCH	0x2
2732 
2733 struct rtw89_fw_h2c_rf_get_mccch {
2734 	__le32 ch_0;
2735 	__le32 ch_1;
2736 	__le32 band_0;
2737 	__le32 band_1;
2738 	__le32 current_channel;
2739 	__le32 current_band_type;
2740 } __packed;
2741 
2742 #define RTW89_FW_RSVD_PLE_SIZE 0x800
2743 
2744 #define RTW89_WCPU_BASE_MASK GENMASK(27, 0)
2745 
2746 #define RTW89_FW_BACKTRACE_INFO_SIZE 8
2747 #define RTW89_VALID_FW_BACKTRACE_SIZE(_size) \
2748 	((_size) % RTW89_FW_BACKTRACE_INFO_SIZE == 0)
2749 
2750 #define RTW89_FW_BACKTRACE_MAX_SIZE 512 /* 8 * 64 (entries) */
2751 #define RTW89_FW_BACKTRACE_KEY 0xBACEBACE
2752 
2753 int rtw89_fw_check_rdy(struct rtw89_dev *rtwdev);
2754 int rtw89_fw_recognize(struct rtw89_dev *rtwdev);
2755 void rtw89_early_fw_feature_recognize(struct device *device,
2756 				      const struct rtw89_chip_info *chip,
2757 				      u32 *early_feat_map);
2758 int rtw89_fw_download(struct rtw89_dev *rtwdev, enum rtw89_fw_type type);
2759 int rtw89_load_firmware(struct rtw89_dev *rtwdev);
2760 void rtw89_unload_firmware(struct rtw89_dev *rtwdev);
2761 int rtw89_wait_firmware_completion(struct rtw89_dev *rtwdev);
2762 void rtw89_h2c_pkt_set_hdr(struct rtw89_dev *rtwdev, struct sk_buff *skb,
2763 			   u8 type, u8 cat, u8 class, u8 func,
2764 			   bool rack, bool dack, u32 len);
2765 int rtw89_fw_h2c_default_cmac_tbl(struct rtw89_dev *rtwdev,
2766 				  struct rtw89_vif *rtwvif);
2767 int rtw89_fw_h2c_assoc_cmac_tbl(struct rtw89_dev *rtwdev,
2768 				struct ieee80211_vif *vif,
2769 				struct ieee80211_sta *sta);
2770 int rtw89_fw_h2c_txtime_cmac_tbl(struct rtw89_dev *rtwdev,
2771 				 struct rtw89_sta *rtwsta);
2772 int rtw89_fw_h2c_txpath_cmac_tbl(struct rtw89_dev *rtwdev,
2773 				 struct rtw89_sta *rtwsta);
2774 int rtw89_fw_h2c_update_beacon(struct rtw89_dev *rtwdev,
2775 			       struct rtw89_vif *rtwvif);
2776 int rtw89_fw_h2c_cam(struct rtw89_dev *rtwdev, struct rtw89_vif *vif,
2777 		     struct rtw89_sta *rtwsta, const u8 *scan_mac_addr);
2778 int rtw89_fw_h2c_dctl_sec_cam_v1(struct rtw89_dev *rtwdev,
2779 				 struct rtw89_vif *rtwvif,
2780 				 struct rtw89_sta *rtwsta);
2781 void rtw89_fw_c2h_irqsafe(struct rtw89_dev *rtwdev, struct sk_buff *c2h);
2782 void rtw89_fw_c2h_work(struct work_struct *work);
2783 int rtw89_fw_h2c_role_maintain(struct rtw89_dev *rtwdev,
2784 			       struct rtw89_vif *rtwvif,
2785 			       struct rtw89_sta *rtwsta,
2786 			       enum rtw89_upd_mode upd_mode);
2787 int rtw89_fw_h2c_join_info(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
2788 			   struct rtw89_sta *rtwsta, bool dis_conn);
2789 int rtw89_fw_h2c_macid_pause(struct rtw89_dev *rtwdev, u8 sh, u8 grp,
2790 			     bool pause);
2791 int rtw89_fw_h2c_set_edca(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
2792 			  u8 ac, u32 val);
2793 int rtw89_fw_h2c_set_ofld_cfg(struct rtw89_dev *rtwdev);
2794 int rtw89_fw_h2c_ra(struct rtw89_dev *rtwdev, struct rtw89_ra_info *ra, bool csi);
2795 int rtw89_fw_h2c_cxdrv_init(struct rtw89_dev *rtwdev);
2796 int rtw89_fw_h2c_cxdrv_role(struct rtw89_dev *rtwdev);
2797 int rtw89_fw_h2c_cxdrv_role_v1(struct rtw89_dev *rtwdev);
2798 int rtw89_fw_h2c_cxdrv_ctrl(struct rtw89_dev *rtwdev);
2799 int rtw89_fw_h2c_cxdrv_rfk(struct rtw89_dev *rtwdev);
2800 int rtw89_fw_h2c_del_pkt_offload(struct rtw89_dev *rtwdev, u8 id);
2801 int rtw89_fw_h2c_add_pkt_offload(struct rtw89_dev *rtwdev, u8 *id,
2802 				 struct sk_buff *skb_ofld);
2803 int rtw89_fw_h2c_scan_list_offload(struct rtw89_dev *rtwdev, int len,
2804 				   struct list_head *chan_list);
2805 int rtw89_fw_h2c_scan_offload(struct rtw89_dev *rtwdev,
2806 			      struct rtw89_scan_option *opt,
2807 			      struct rtw89_vif *vif);
2808 int rtw89_fw_h2c_rf_reg(struct rtw89_dev *rtwdev,
2809 			struct rtw89_fw_h2c_rf_reg_info *info,
2810 			u16 len, u8 page);
2811 int rtw89_fw_h2c_rf_ntfy_mcc(struct rtw89_dev *rtwdev);
2812 int rtw89_fw_h2c_raw_with_hdr(struct rtw89_dev *rtwdev,
2813 			      u8 h2c_class, u8 h2c_func, u8 *buf, u16 len,
2814 			      bool rack, bool dack);
2815 int rtw89_fw_h2c_raw(struct rtw89_dev *rtwdev, const u8 *buf, u16 len);
2816 void rtw89_fw_send_all_early_h2c(struct rtw89_dev *rtwdev);
2817 void rtw89_fw_free_all_early_h2c(struct rtw89_dev *rtwdev);
2818 int rtw89_fw_h2c_general_pkt(struct rtw89_dev *rtwdev, u8 macid);
2819 int rtw89_fw_h2c_ba_cam(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
2820 			bool valid, struct ieee80211_ampdu_params *params);
2821 void rtw89_fw_h2c_init_ba_cam_v1(struct rtw89_dev *rtwdev);
2822 
2823 int rtw89_fw_h2c_lps_parm(struct rtw89_dev *rtwdev,
2824 			  struct rtw89_lps_parm *lps_param);
2825 struct sk_buff *rtw89_fw_h2c_alloc_skb_with_hdr(struct rtw89_dev *rtwdev, u32 len);
2826 struct sk_buff *rtw89_fw_h2c_alloc_skb_no_hdr(struct rtw89_dev *rtwdev, u32 len);
2827 int rtw89_fw_msg_reg(struct rtw89_dev *rtwdev,
2828 		     struct rtw89_mac_h2c_info *h2c_info,
2829 		     struct rtw89_mac_c2h_info *c2h_info);
2830 int rtw89_fw_h2c_fw_log(struct rtw89_dev *rtwdev, bool enable);
2831 void rtw89_fw_st_dbg_dump(struct rtw89_dev *rtwdev);
2832 void rtw89_store_op_chan(struct rtw89_dev *rtwdev, bool backup);
2833 void rtw89_hw_scan_start(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
2834 			 struct ieee80211_scan_request *req);
2835 void rtw89_hw_scan_complete(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
2836 			    bool aborted);
2837 int rtw89_hw_scan_offload(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
2838 			  bool enable);
2839 void rtw89_hw_scan_abort(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif);
2840 int rtw89_fw_h2c_trigger_cpu_exception(struct rtw89_dev *rtwdev);
2841 int rtw89_fw_h2c_pkt_drop(struct rtw89_dev *rtwdev,
2842 			  const struct rtw89_pkt_drop_params *params);
2843 int rtw89_fw_h2c_p2p_act(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
2844 			 struct ieee80211_p2p_noa_desc *desc,
2845 			 u8 act, u8 noa_id);
2846 int rtw89_fw_h2c_tsf32_toggle(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
2847 			      bool en);
2848 
rtw89_fw_h2c_init_ba_cam(struct rtw89_dev * rtwdev)2849 static inline void rtw89_fw_h2c_init_ba_cam(struct rtw89_dev *rtwdev)
2850 {
2851 	const struct rtw89_chip_info *chip = rtwdev->chip;
2852 
2853 	if (chip->bacam_v1)
2854 		rtw89_fw_h2c_init_ba_cam_v1(rtwdev);
2855 }
2856 
2857 #endif
2858