| /linux-3.4.99/drivers/clk/ |
| D | clk-divider.c | 38 unsigned int div; in clk_divider_recalc_rate() local
40 div = readl(divider->reg) >> divider->shift; in clk_divider_recalc_rate()
41 div &= div_mask(divider); in clk_divider_recalc_rate()
44 div++; in clk_divider_recalc_rate()
46 return parent_rate / div; in clk_divider_recalc_rate()
109 int div; in clk_divider_round_rate() local
110 div = clk_divider_bestdiv(hw, rate, prate); in clk_divider_round_rate()
113 return *prate / div; in clk_divider_round_rate()
117 return r / div; in clk_divider_round_rate()
125 unsigned int div; in clk_divider_set_rate() local
[all …]
|
| /linux-3.4.99/arch/arm/mach-omap2/ |
| D | clock_common_data.c | 23 { .div = 1, .val = 0, .flags = RATE_IN_24XX | RATE_IN_3XXX },
24 { .div = 0 }
28 { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_3XXX },
29 { .div = 0 }
33 { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_3XXX },
34 { .div = 2, .val = 2, .flags = RATE_IN_24XX | RATE_IN_3XXX },
35 { .div = 3, .val = 3, .flags = RATE_IN_243X | RATE_IN_3XXX },
36 { .div = 4, .val = 4, .flags = RATE_IN_243X | RATE_IN_3XXX },
37 { .div = 0 }
41 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
[all …]
|
| D | clkt_clksel.c | 117 for (clkr = clks->rates; clkr->div; clkr++) { in _get_div_and_fieldval()
121 if (clkr->div > max_div) { in _get_div_and_fieldval()
122 max_div = clkr->div; in _get_div_and_fieldval()
184 for (clkr = clks->rates; clkr->div; clkr++) { in _clksel_to_divisor()
192 if (!clkr->div) { in _clksel_to_divisor()
199 return clkr->div; in _clksel_to_divisor()
212 static u32 _divisor_to_clksel(struct clk *clk, u32 div) in _divisor_to_clksel() argument
218 WARN_ON(div == 0); in _divisor_to_clksel()
224 for (clkr = clks->rates; clkr->div; clkr++) { in _divisor_to_clksel()
228 if (clkr->div == div) in _divisor_to_clksel()
[all …]
|
| D | clock3xxx_data.c | 115 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
116 { .div = 0 }
120 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
121 { .div = 0 }
125 { .div = 1, .val = 5, .flags = RATE_IN_3430ES2PLUS_36XX },
126 { .div = 0 }
130 { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
131 { .div = 0 }
135 { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
136 { .div = 0 }
[all …]
|
| D | clock2420_data.c | 164 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
165 { .div = 0 },
169 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
170 { .div = 0 },
210 { .div = 2, .val = 0, .flags = RATE_IN_24XX },
211 { .div = 0 },
215 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
216 { .div = 0 },
265 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
266 { .div = 0 }
[all …]
|
| D | clkt2xxx_sys.c | 36 u32 div; in omap2xxx_get_sysclkdiv() local
38 div = __raw_readl(prcm_clksrc_ctrl); in omap2xxx_get_sysclkdiv()
39 div &= OMAP_SYSCLKDIV_MASK; in omap2xxx_get_sysclkdiv()
40 div >>= OMAP_SYSCLKDIV_SHIFT; in omap2xxx_get_sysclkdiv()
42 return div; in omap2xxx_get_sysclkdiv()
|
| /linux-3.4.99/arch/mips/ath79/ |
| D | clock.c | 40 u32 div; in ar71xx_clocks_init() local
46 div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1; in ar71xx_clocks_init()
47 freq = div * ath79_ref_clk.rate; in ar71xx_clocks_init()
49 div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1; in ar71xx_clocks_init()
50 ath79_cpu_clk.rate = freq / div; in ar71xx_clocks_init()
52 div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1; in ar71xx_clocks_init()
53 ath79_ddr_clk.rate = freq / div; in ar71xx_clocks_init()
55 div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2; in ar71xx_clocks_init()
56 ath79_ahb_clk.rate = ath79_cpu_clk.rate / div; in ar71xx_clocks_init()
66 u32 div; in ar724x_clocks_init() local
[all …]
|
| /linux-3.4.99/arch/mips/jz4740/ |
| D | clock.c | 243 int div; in jz_clk_main_round_rate() local
245 div = parent_rate / rate; in jz_clk_main_round_rate()
246 if (div > 32) in jz_clk_main_round_rate()
248 else if (div < 1) in jz_clk_main_round_rate()
251 div &= (0x3 << (ffs(div) - 1)); in jz_clk_main_round_rate()
253 return parent_rate / div; in jz_clk_main_round_rate()
259 uint32_t div; in jz_clk_main_get_rate() local
261 div = jz_clk_reg_read(JZ_REG_CLOCK_CTRL); in jz_clk_main_get_rate()
263 div >>= mclk->div_offset; in jz_clk_main_get_rate()
264 div &= 0xf; in jz_clk_main_get_rate()
[all …]
|
| /linux-3.4.99/arch/arm/mach-imx/ |
| D | clock-imx1.c | 101 int div; in _clk_simple_round_rate() local
106 div = parent_rate / rate; in _clk_simple_round_rate()
108 div++; in _clk_simple_round_rate()
110 if (div > limit) in _clk_simple_round_rate()
111 div = limit; in _clk_simple_round_rate()
113 return parent_rate / div; in _clk_simple_round_rate()
247 unsigned int div; in hclk_set_rate() local
253 div = parent_rate / rate; in hclk_set_rate()
255 if (div > 16 || div < 1 || ((parent_rate / div) != rate)) in hclk_set_rate()
258 div--; in hclk_set_rate()
[all …]
|
| D | clock-imx35.c | 33 static void calc_dividers(u32 div, u32 *pre, u32 *post, u32 maxpost) in calc_dividers() argument
37 min_pre = (div - 1) / maxpost + 1; in calc_dividers()
41 if (div > (temp_pre * maxpost)) in calc_dividers()
44 if (div < (temp_pre * temp_pre)) in calc_dividers()
47 err = div % temp_pre; in calc_dividers()
62 *post = (div + *pre - 1) / *pre; in calc_dividers()
66 static void calc_dividers_3_6(u32 div, u32 *pre, u32 *post) in calc_dividers_3_6() argument
68 if (div >= 512) { in calc_dividers_3_6()
71 } else if (div >= 64) { in calc_dividers_3_6()
72 calc_dividers(div, pre, post, 64); in calc_dividers_3_6()
[all …]
|
| /linux-3.4.99/arch/arm/plat-s3c24xx/ |
| D | clock-dclk.c | 75 unsigned long div; in s3c24xx_calc_div() local
80 div = clk_get_rate(clk->parent) / rate; in s3c24xx_calc_div()
81 if (div < 2) in s3c24xx_calc_div()
82 div = 2; in s3c24xx_calc_div()
83 else if (div > 16) in s3c24xx_calc_div()
84 div = 16; in s3c24xx_calc_div()
86 return div; in s3c24xx_calc_div()
92 unsigned long div = s3c24xx_calc_div(clk, rate); in s3c24xx_round_dclk_rate() local
94 if (div == 0) in s3c24xx_round_dclk_rate()
97 return clk_get_rate(clk->parent) / div; in s3c24xx_round_dclk_rate()
[all …]
|
| /linux-3.4.99/sound/aoa/soundbus/i2sbus/ |
| D | interface.h | 90 # define I2S_SF_MCLKDIV_OTHER(div) (((div/2-1)<<I2S_SF_MCLKDIV_SHIFT)&I2S_SF_MCLKDIV_MASK) argument
91 static inline int i2s_sf_mclkdiv(int div, int *out) in i2s_sf_mclkdiv() argument
95 switch(div) { in i2s_sf_mclkdiv()
101 if (div%2) return -1; in i2s_sf_mclkdiv()
102 d = div/2-1; in i2s_sf_mclkdiv()
105 *out |= I2S_SF_MCLKDIV_OTHER(div); in i2s_sf_mclkdiv()
117 # define I2S_SF_SCLKDIV_OTHER(div) (((div/2-1)<<I2S_SF_SCLKDIV_SHIFT)&I2S_SF_SCLKDIV_MASK) argument
118 static inline int i2s_sf_sclkdiv(int div, int *out) in i2s_sf_sclkdiv() argument
122 switch(div) { in i2s_sf_sclkdiv()
126 if (div%2) return -1; in i2s_sf_sclkdiv()
[all …]
|
| /linux-3.4.99/arch/h8300/include/asm/ |
| D | timer.h | 11 #define calc_param(cnt, div, rate, limit) \ argument
14 for (div = 0; div < ARRAY_SIZE(divide_rate); div++) { \
15 if (rate[div] == 0) \
17 if ((cnt / rate[div]) > limit) \
20 if (div == ARRAY_SIZE(divide_rate)) \
22 cnt /= divide_rate[div]; \
|
| /linux-3.4.99/drivers/media/video/ |
| D | aptina-pll.c | 38 unsigned int div; in aptina_pll_calculate() local
55 div = gcd(pll->pix_clock, pll->ext_clock); in aptina_pll_calculate()
56 pll->m = pll->pix_clock / div; in aptina_pll_calculate()
57 div = pll->ext_clock / div; in aptina_pll_calculate()
72 mf_min = max(mf_min, limits->n_min * limits->p1_min / div); in aptina_pll_calculate()
76 mf_max = min(mf_max, DIV_ROUND_UP(limits->n_max * limits->p1_max, div)); in aptina_pll_calculate()
141 p1_min = max(limits->p1_min, DIV_ROUND_UP(limits->out_clock_min * div, in aptina_pll_calculate()
143 p1_max = min(limits->p1_max, limits->out_clock_max * div / in aptina_pll_calculate()
147 unsigned int mf_inc = p1 / gcd(div, p1); in aptina_pll_calculate()
153 limits->int_clock_max * div)); in aptina_pll_calculate()
[all …]
|
| /linux-3.4.99/drivers/mmc/host/ |
| D | sdhci-cns3xxx.c | 30 int div = 1; in sdhci_cns3xxx_set_clock() local
42 while (host->max_clk / div > clock) { in sdhci_cns3xxx_set_clock()
47 if (div < 4) in sdhci_cns3xxx_set_clock()
48 div += 1; in sdhci_cns3xxx_set_clock()
49 else if (div < 256) in sdhci_cns3xxx_set_clock()
50 div *= 2; in sdhci_cns3xxx_set_clock()
56 clock, host->max_clk / div); in sdhci_cns3xxx_set_clock()
59 if (div != 3) in sdhci_cns3xxx_set_clock()
60 div >>= 1; in sdhci_cns3xxx_set_clock()
62 clk = div << SDHCI_DIVIDER_SHIFT; in sdhci_cns3xxx_set_clock()
|
| D | sdhci-esdhc.h | 48 int div = 1; in esdhc_set_clock() local
62 while (host->max_clk / pre_div / div > clock && div < 16) in esdhc_set_clock()
63 div++; in esdhc_set_clock()
66 clock, host->max_clk / pre_div / div); in esdhc_set_clock()
69 div--; in esdhc_set_clock()
73 | (div << ESDHC_DIVIDER_SHIFT) in esdhc_set_clock()
|
| /linux-3.4.99/drivers/media/common/tuners/ |
| D | tea5767.c | 136 unsigned int div, frq; in tea5767_status_dump() local
148 div = ((buffer[0] & 0x3f) << 8) | buffer[1]; in tea5767_status_dump()
152 frq = (div * 50000 - 700000 - 225000) / 4; /* Freq in KHz */ in tea5767_status_dump()
155 frq = (div * 50000 + 700000 + 225000) / 4; /* Freq in KHz */ in tea5767_status_dump()
158 frq = (div * 32768 + 700000 + 225000) / 4; /* Freq in KHz */ in tea5767_status_dump()
162 frq = (div * 32768 - 700000 - 225000) / 4; /* Freq in KHz */ in tea5767_status_dump()
165 buffer[0] = (div >> 8) & 0x3f; in tea5767_status_dump()
166 buffer[1] = div & 0xff; in tea5767_status_dump()
169 frq / 1000, frq % 1000, div); in tea5767_status_dump()
194 unsigned div; in set_radio_freq() local
[all …]
|
| /linux-3.4.99/drivers/gpu/drm/nouveau/ |
| D | nouveau_backlight.c | 103 u32 div = 1025; in nv50_get_intensity() local
108 return ((val * 100) + (div / 2)) / div; in nv50_get_intensity()
117 u32 div = 1025; in nv50_set_intensity() local
118 u32 val = (bd->props.brightness * div) / 100; in nv50_set_intensity()
137 u32 div, val; in nva3_get_intensity() local
139 div = nv_rd32(dev, NV50_PDISP_SOR_PWM_DIV(or)); in nva3_get_intensity()
142 if (div && div >= val) in nva3_get_intensity()
143 return ((val * 100) + (div / 2)) / div; in nva3_get_intensity()
154 u32 div, val; in nva3_set_intensity() local
156 div = nv_rd32(dev, NV50_PDISP_SOR_PWM_DIV(or)); in nva3_set_intensity()
[all …]
|
| /linux-3.4.99/arch/arm/mach-s3c24xx/ |
| D | s3c2442.c | 60 int div; in s3c2442_camif_upll_round() local
65 div = parent_rate / rate; in s3c2442_camif_upll_round()
67 if (div == 3) in s3c2442_camif_upll_round()
72 div /= 2; in s3c2442_camif_upll_round()
74 if (div < 1) in s3c2442_camif_upll_round()
75 div = 1; in s3c2442_camif_upll_round()
76 else if (div > 16) in s3c2442_camif_upll_round()
77 div = 16; in s3c2442_camif_upll_round()
79 return parent_rate / (div * 2); in s3c2442_camif_upll_round()
|
| D | clock-s3c2412.c | 160 int div; in s3c2412_roundrate_usbsrc() local
165 div = parent_rate / rate; in s3c2412_roundrate_usbsrc()
166 if (div > 2) in s3c2412_roundrate_usbsrc()
167 div = 2; in s3c2412_roundrate_usbsrc()
169 return parent_rate / div; in s3c2412_roundrate_usbsrc()
175 unsigned long div = __raw_readl(S3C2410_CLKDIVN); in s3c2412_getrate_usbsrc() local
177 return parent_rate / ((div & S3C2412_CLKDIVN_USB48DIV) ? 2 : 1); in s3c2412_getrate_usbsrc()
278 int div; in s3c2412_roundrate_clksrc() local
285 div = (rate / parent_rate); in s3c2412_roundrate_clksrc()
287 if (div < 1) in s3c2412_roundrate_clksrc()
[all …]
|
| /linux-3.4.99/arch/c6x/platforms/ |
| D | plldata.c | 178 sysclks[2].div = 3; in c6455_setup_clocks()
180 sysclks[3].div = 6; in c6455_setup_clocks()
181 sysclks[4].div = PLLDIV4; in c6455_setup_clocks()
182 sysclks[5].div = PLLDIV5; in c6455_setup_clocks()
216 sysclks[1].div = 1; in c6457_setup_clocks()
218 sysclks[2].div = 3; in c6457_setup_clocks()
220 sysclks[3].div = 6; in c6457_setup_clocks()
221 sysclks[4].div = PLLDIV4; in c6457_setup_clocks()
222 sysclks[5].div = PLLDIV5; in c6457_setup_clocks()
268 sysclks[i].div = 1; in c6472_setup_clocks()
[all …]
|
| /linux-3.4.99/drivers/video/omap2/dss/ |
| D | rfbi.c | 378 static inline unsigned long round_to_extif_ticks(unsigned long ps, int div) in round_to_extif_ticks() argument
380 int bus_tick = extif_clk_period * div; in round_to_extif_ticks()
384 static int calc_reg_timing(struct rfbi_timings *t, int div) in calc_reg_timing() argument
386 t->clk_div = div; in calc_reg_timing()
388 t->cs_on_time = round_to_extif_ticks(t->cs_on_time, div); in calc_reg_timing()
390 t->we_on_time = round_to_extif_ticks(t->we_on_time, div); in calc_reg_timing()
391 t->we_off_time = round_to_extif_ticks(t->we_off_time, div); in calc_reg_timing()
392 t->we_cycle_time = round_to_extif_ticks(t->we_cycle_time, div); in calc_reg_timing()
394 t->re_on_time = round_to_extif_ticks(t->re_on_time, div); in calc_reg_timing()
395 t->re_off_time = round_to_extif_ticks(t->re_off_time, div); in calc_reg_timing()
[all …]
|
| /linux-3.4.99/arch/arm/mach-rpc/include/mach/ |
| D | acornfb.h | 85 u_int div; in acornfb_vidc20_find_rates() local
88 div = var->pixclock / 9090; /*9921*/ in acornfb_vidc20_find_rates()
91 if (div == 0) in acornfb_vidc20_find_rates()
92 div = 1; in acornfb_vidc20_find_rates()
93 if (div > 8) in acornfb_vidc20_find_rates()
94 div = 8; in acornfb_vidc20_find_rates()
97 switch (div) { in acornfb_vidc20_find_rates()
136 vidc->pll_ctl = acornfb_vidc20_find_pll(var->pixclock / div); in acornfb_vidc20_find_rates()
|
| /linux-3.4.99/arch/arm/mach-mxs/ |
| D | clock-mx23.c | 120 u32 reg, div; \
123 div = (reg >> BP_CLKCTRL_##sr##_##ss##FRAC) & 0x3f; \
127 div, PARENT_RATE_SHIFT); \
169 u32 reg, div; \
174 div = (reg & BM_CLKCTRL_##rs##_DIV_XTAL) >> \
177 div = (reg & BM_CLKCTRL_##rs##_DIV_##rs) >> \
180 if (!div) \
183 return clk_get_rate(clk->parent) / div; \
192 u32 reg, div; \ in _CLK_GET_RATE()
195 div = (reg & BM_CLKCTRL_##rs##_DIV) >> BP_CLKCTRL_##rs##_DIV; \ in _CLK_GET_RATE()
[all …]
|
| /linux-3.4.99/drivers/usb/host/ |
| D | octeon2-common.c | 22 u64 div; in octeon2_usb_clocks_start() local
75 div = octeon_get_io_clock_rate() / 130000000ull; in octeon2_usb_clocks_start()
77 switch (div) { in octeon2_usb_clocks_start()
79 div = 1; in octeon2_usb_clocks_start()
87 div = 4; in octeon2_usb_clocks_start()
91 div = 6; in octeon2_usb_clocks_start()
97 div = 8; in octeon2_usb_clocks_start()
100 div = 12; in octeon2_usb_clocks_start()
103 clk_rst_ctl.s.h_div = div; in octeon2_usb_clocks_start()
|