Lines Matching refs:div
120 u32 reg, div; \
123 div = (reg >> BP_CLKCTRL_##sr##_##ss##FRAC) & 0x3f; \
127 div, PARENT_RATE_SHIFT); \
169 u32 reg, div; \
174 div = (reg & BM_CLKCTRL_##rs##_DIV_XTAL) >> \
177 div = (reg & BM_CLKCTRL_##rs##_DIV_##rs) >> \
180 if (!div) \
183 return clk_get_rate(clk->parent) / div; \
192 u32 reg, div; \ in _CLK_GET_RATE()
195 div = (reg & BM_CLKCTRL_##rs##_DIV) >> BP_CLKCTRL_##rs##_DIV; \ in _CLK_GET_RATE()
197 if (!div) \ in _CLK_GET_RATE()
200 return clk_get_rate(clk->parent) / div; \ in _CLK_GET_RATE()
224 u32 reg, bm_busy, div_max, d, f, div, frac; local
232 div = DIV_ROUND_UP(parent_rate, rate);
233 if (div == 0 || div > div_max)
241 div = frac = 1;
255 div = d;
274 reg |= div << BP_CLKCTRL_CPU_DIV_CPU;
285 u32 reg, div_max, div; \
291 div = DIV_ROUND_UP(parent_rate, rate); \
292 if (div == 0 || div > div_max) \
297 reg |= div << BP_CLKCTRL_##dr##_DIV; \