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Searched refs:SM (Results 1 – 25 of 31) sorted by relevance

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/linux-3.4.99/drivers/net/wireless/ath/ath9k/
Dar9003_rtt.c76 val = SM(data28, AR_PHY_RTT_SW_RTT_TABLE_DATA); in ar9003_hw_rtt_load_hist_entry()
79 val = SM(0, AR_PHY_RTT_SW_RTT_TABLE_ACCESS) | in ar9003_hw_rtt_load_hist_entry()
80 SM(1, AR_PHY_RTT_SW_RTT_TABLE_WRITE) | in ar9003_hw_rtt_load_hist_entry()
81 SM(index, AR_PHY_RTT_SW_RTT_TABLE_ADDR); in ar9003_hw_rtt_load_hist_entry()
85 val |= SM(1, AR_PHY_RTT_SW_RTT_TABLE_ACCESS); in ar9003_hw_rtt_load_hist_entry()
94 val &= ~SM(1, AR_PHY_RTT_SW_RTT_TABLE_WRITE); in ar9003_hw_rtt_load_hist_entry()
115 val = SM(0, AR_PHY_RTT_SW_RTT_TABLE_ACCESS) | in ar9003_hw_rtt_fill_hist_entry()
116 SM(0, AR_PHY_RTT_SW_RTT_TABLE_WRITE) | in ar9003_hw_rtt_fill_hist_entry()
117 SM(index, AR_PHY_RTT_SW_RTT_TABLE_ADDR); in ar9003_hw_rtt_fill_hist_entry()
122 val |= SM(1, AR_PHY_RTT_SW_RTT_TABLE_ACCESS); in ar9003_hw_rtt_fill_hist_entry()
Dbtcoex.c76 SM(ath_bt_config.bt_time_extend, AR_BT_TIME_EXTEND) | in ath9k_hw_init_btcoex_hw()
77 SM(ath_bt_config.bt_txstate_extend, AR_BT_TXSTATE_EXTEND) | in ath9k_hw_init_btcoex_hw()
78 SM(ath_bt_config.bt_txframe_extend, AR_BT_TX_FRAME_EXTEND) | in ath9k_hw_init_btcoex_hw()
79 SM(ath_bt_config.bt_mode, AR_BT_MODE) | in ath9k_hw_init_btcoex_hw()
80 SM(ath_bt_config.bt_quiet_collision, AR_BT_QUIET) | in ath9k_hw_init_btcoex_hw()
81 SM(rxclear_polarity, AR_BT_RX_CLEAR_POLARITY) | in ath9k_hw_init_btcoex_hw()
82 SM(ath_bt_config.bt_priority_time, AR_BT_PRIORITY_TIME) | in ath9k_hw_init_btcoex_hw()
83 SM(ath_bt_config.bt_first_slot_time, AR_BT_FIRST_SLOT_TIME) | in ath9k_hw_init_btcoex_hw()
84 SM(qnum, AR_BT_QCU_THRESH); in ath9k_hw_init_btcoex_hw()
87 SM(ath_bt_config.bt_hold_rx_clear, AR_BT_HOLD_RX_CLEAR) | in ath9k_hw_init_btcoex_hw()
[all …]
Dmac.c33 SM(ah->txok_interrupt_mask, AR_IMR_S0_QCU_TXOK) in ath9k_hw_set_txq_interrupts()
34 | SM(ah->txdesc_interrupt_mask, AR_IMR_S0_QCU_TXDESC)); in ath9k_hw_set_txq_interrupts()
36 SM(ah->txerr_interrupt_mask, AR_IMR_S1_QCU_TXERR) in ath9k_hw_set_txq_interrupts()
37 | SM(ah->txeol_interrupt_mask, AR_IMR_S1_QCU_TXEOL)); in ath9k_hw_set_txq_interrupts()
124 (txcfg & ~AR_FTRIG) | SM(newLevel, AR_FTRIG)); in ath9k_hw_updatetxtriglevel()
394 SM(cwMin, AR_D_LCL_IFS_CWMIN) | in ath9k_hw_resettxqueue()
395 SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX) | in ath9k_hw_resettxqueue()
396 SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS)); in ath9k_hw_resettxqueue()
399 SM(INIT_SSH_RETRY, AR_D_RETRY_LIMIT_STA_SH) | in ath9k_hw_resettxqueue()
400 SM(INIT_SLG_RETRY, AR_D_RETRY_LIMIT_STA_LG) | in ath9k_hw_resettxqueue()
[all …]
Deeprom_9287.c504 regval = SM(pdGainOverlap_t2, in ath9k_hw_set_ar9287_power_cal_table()
506 | SM(gainBoundaries[0], in ath9k_hw_set_ar9287_power_cal_table()
508 | SM(gainBoundaries[1], in ath9k_hw_set_ar9287_power_cal_table()
510 | SM(gainBoundaries[2], in ath9k_hw_set_ar9287_power_cal_table()
512 | SM(gainBoundaries[3], in ath9k_hw_set_ar9287_power_cal_table()
946 SM(pModal->iqCalICh[i], in ath9k_hw_ar9287_set_board_values()
948 SM(pModal->iqCalQCh[i], in ath9k_hw_ar9287_set_board_values()
979 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) in ath9k_hw_ar9287_set_board_values()
980 | SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF) in ath9k_hw_ar9287_set_board_values()
981 | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON) in ath9k_hw_ar9287_set_board_values()
[all …]
Dar9003_mci.c857 regval = SM(1, AR_BTCOEX_CTRL_AR9462_MODE) | in ar9003_mci_reset()
858 SM(1, AR_BTCOEX_CTRL_WBTIMER_EN) | in ar9003_mci_reset()
859 SM(1, AR_BTCOEX_CTRL_PA_SHARED) | in ar9003_mci_reset()
860 SM(1, AR_BTCOEX_CTRL_LNA_SHARED) | in ar9003_mci_reset()
861 SM(2, AR_BTCOEX_CTRL_NUM_ANTENNAS) | in ar9003_mci_reset()
862 SM(3, AR_BTCOEX_CTRL_RX_CHAIN_MASK) | in ar9003_mci_reset()
863 SM(0, AR_BTCOEX_CTRL_1_CHAIN_ACK) | in ar9003_mci_reset()
864 SM(0, AR_BTCOEX_CTRL_1_CHAIN_BCN) | in ar9003_mci_reset()
865 SM(0, AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN); in ar9003_mci_reset()
888 regval |= SM(1, AR_MCI_COMMAND2_RESET_TX); in ar9003_mci_reset()
[all …]
Dar9002_mac.c224 ctl6 = SM(i->keytype, AR_EncrType); in ar9002_set_txdesc()
240 | SM(0, AR_BurstDur); in ar9002_set_txdesc()
258 ctl1 |= (i->keyix != ATH9K_TXKEYIX_INVALID ? SM(i->keyix, AR_DestIdx) : 0) in ar9002_set_txdesc()
259 | SM(i->type, AR_FrameType) in ar9002_set_txdesc()
266 ctl6 |= SM(i->aggr_len, AR_AggrLen); in ar9002_set_txdesc()
270 ctl6 |= SM(i->ndelim, AR_PadDelim); in ar9002_set_txdesc()
281 | SM(i->txpower, AR_XmitPower) in ar9002_set_txdesc()
305 | SM(i->rtscts_rate, AR_RTSCTSRate); in ar9002_set_txdesc()
Deeprom_4k.c420 SM(pdGainOverlap_t2, in ath9k_hw_set_4k_power_cal_table()
422 | SM(gainBoundaries[0], in ath9k_hw_set_4k_power_cal_table()
424 | SM(gainBoundaries[1], in ath9k_hw_set_4k_power_cal_table()
426 | SM(gainBoundaries[2], in ath9k_hw_set_4k_power_cal_table()
428 | SM(gainBoundaries[3], in ath9k_hw_set_4k_power_cal_table()
771 SM(pModal->iqCalICh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) | in ath9k_hw_4k_set_gain()
772 SM(pModal->iqCalQCh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF)); in ath9k_hw_4k_set_gain()
845 regVal |= SM(ant_div_control1, in ath9k_hw_4k_set_board_values()
847 regVal |= SM(ant_div_control2, in ath9k_hw_4k_set_board_values()
849 regVal |= SM((ant_div_control2 >> 2), in ath9k_hw_4k_set_board_values()
[all …]
Dar5008_phy.c320 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); in ar5008_hw_spur_mitigate()
330 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | in ar5008_hw_spur_mitigate()
331 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); in ar5008_hw_spur_mitigate()
977 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV); in ar9160_hw_compute_pll_control()
980 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL); in ar9160_hw_compute_pll_control()
982 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL); in ar9160_hw_compute_pll_control()
985 pll |= SM(0x50, AR_RTC_9160_PLL_DIV); in ar9160_hw_compute_pll_control()
987 pll |= SM(0x58, AR_RTC_9160_PLL_DIV); in ar9160_hw_compute_pll_control()
1000 pll |= SM(0x1, AR_RTC_PLL_CLKSEL); in ar5008_hw_compute_pll_control()
1002 pll |= SM(0x2, AR_RTC_PLL_CLKSEL); in ar5008_hw_compute_pll_control()
[all …]
Dar9002_phy.c257 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); in ar9002_hw_spur_mitigate()
286 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | in ar9002_hw_spur_mitigate()
287 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); in ar9002_hw_spur_mitigate()
466 pll = SM(ref_div, AR_RTC_9160_PLL_REFDIV); in ar9002_hw_compute_pll_control()
467 pll |= SM(pll_div, AR_RTC_9160_PLL_DIV); in ar9002_hw_compute_pll_control()
470 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL); in ar9002_hw_compute_pll_control()
472 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL); in ar9002_hw_compute_pll_control()
Dar9003_mac.c74 | SM(0, AR_BurstDur); in ar9003_set_txdesc()
90 ctl17 = SM(i->keytype, AR_EncrType); in ar9003_set_txdesc()
104 | SM(i->txpower, AR_XmitPower) in ar9003_set_txdesc()
113 SM(i->keyix, AR_DestIdx) : 0) in ar9003_set_txdesc()
114 | SM(i->type, AR_FrameType) in ar9003_set_txdesc()
122 ctl17 |= SM(i->aggr_len, AR_AggrLen); in ar9003_set_txdesc()
126 ctl17 |= SM(i->ndelim, AR_PadDelim); in ar9003_set_txdesc()
136 ctl12 |= SM(val, AR_PAPRDChainMask); in ar9003_set_txdesc()
151 | SM(i->rtscts_rate, AR_RTSCTSRate); in ar9003_set_txdesc()
Dar9003_phy.c466 pll = SM(0x5, AR_RTC_9300_PLL_REFDIV); in ar9003_hw_compute_pll_control()
469 pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL); in ar9003_hw_compute_pll_control()
471 pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL); in ar9003_hw_compute_pll_control()
473 pll |= SM(0x2c, AR_RTC_9300_PLL_DIV); in ar9003_hw_compute_pll_control()
1177 radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR); in ar9003_hw_set_radar_params()
1178 radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI); in ar9003_hw_set_radar_params()
1179 radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT); in ar9003_hw_set_radar_params()
1180 radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI); in ar9003_hw_set_radar_params()
1181 radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND); in ar9003_hw_set_radar_params()
1185 radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN); in ar9003_hw_set_radar_params()
[all …]
Deeprom_def.c505 | SM(pModal-> bswMargin[i], in ath9k_hw_def_set_gain()
510 | SM(pModal->bswAtten[i], in ath9k_hw_def_set_gain()
527 | SM(txRxAttenLocal, AR_PHY_RXGAIN_TXRX_ATTEN)); in ath9k_hw_def_set_gain()
532 SM(pModal->rxTxMarginCh[i], AR_PHY_GAIN_2GHZ_RXTX_MARGIN)); in ath9k_hw_def_set_gain()
567 SM(pModal->iqCalICh[i], in ath9k_hw_def_set_board_values()
569 SM(pModal->iqCalQCh[i], in ath9k_hw_def_set_board_values()
636 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) in ath9k_hw_def_set_board_values()
637 | SM(pModal->txEndToXpaOff, in ath9k_hw_def_set_board_values()
639 | SM(pModal->txFrameToXpaOn, in ath9k_hw_def_set_board_values()
641 | SM(pModal->txFrameToXpaOn, in ath9k_hw_def_set_board_values()
[all …]
Dmac.h21 (SM((_series)[_index].Tries, AR_XmitDataTries##_index))
24 (SM((_series)[_index].Rate, AR_XmitRate##_index))
27 (SM((_series)[_index].PktDuration, AR_PacketDur##_index) | \
38 |SM((_series)[_index].ChSel, AR_ChainSel##_index))
Dhw.c709 SM(2, AR_QOS_NO_ACK_TWO_BIT) | in ath9k_hw_init_qos()
710 SM(5, AR_QOS_NO_ACK_BIT_OFF) | in ath9k_hw_init_qos()
711 SM(0, AR_QOS_NO_ACK_BYTE_OFF)); in ath9k_hw_init_qos()
1073 SM(rx_lat, AR_USEC_RX_LAT) | in ath9k_hw_init_global_settings()
1074 SM(tx_lat, AR_USEC_TX_LAT), in ath9k_hw_init_global_settings()
2180 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT) in ath9k_hw_set_sta_beacon_timers()
2189 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT)); in ath9k_hw_set_sta_beacon_timers()
2924 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | in ath9k_hw_gen_timer_start()
2925 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); in ath9k_hw_gen_timer_start()
2944 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | in ath9k_hw_gen_timer_stop()
[all …]
/linux-3.4.99/drivers/net/wireless/ath/ath6kl/
Dhif.c216 SM(INT_STATUS_ENABLE_MBOX_DATA, 0x01); in ath6kl_hif_rx_control()
219 ~SM(INT_STATUS_ENABLE_MBOX_DATA, 0x01); in ath6kl_hif_rx_control()
580 SM(INT_STATUS_ENABLE_ERROR, 0x01) | in ath6kl_hif_enable_intrs()
581 SM(INT_STATUS_ENABLE_CPU, 0x01) | in ath6kl_hif_enable_intrs()
582 SM(INT_STATUS_ENABLE_COUNTER, 0x01); in ath6kl_hif_enable_intrs()
588 dev->irq_en_reg.int_status_en |= SM(INT_STATUS_ENABLE_MBOX_DATA, 0x01); in ath6kl_hif_enable_intrs()
595 SM(ERROR_STATUS_ENABLE_RX_UNDERFLOW, 0x01) | in ath6kl_hif_enable_intrs()
596 SM(ERROR_STATUS_ENABLE_TX_OVERFLOW, 0x1); in ath6kl_hif_enable_intrs()
602 dev->irq_en_reg.cntr_int_status_en = SM(COUNTER_INT_STATUS_ENABLE_BIT, in ath6kl_hif_enable_intrs()
Dtarget.h132 #define SM(f, v) (((v) << f##_S) & f) macro
Dinit.c1321 param |= SM(SYSTEM_SLEEP_DISABLE, 1); in ath6kl_init_upload()
1339 param = SM(CPU_CLOCK_STANDARD, 1); in ath6kl_init_upload()
1349 param = SM(LPO_CAL_ENABLE, 1); in ath6kl_init_upload()
/linux-3.4.99/drivers/staging/keucr/
DKconfig2 tristate "USB ENE SM card reader support"
5 Say Y here if you wish to control a ENE SM Card reader.
/linux-3.4.99/Documentation/devicetree/bindings/fb/
Dsm501fb.txt1 * SM SM501
3 The SM SM501 is a LCD controller, with proper hardware, it can also
/linux-3.4.99/arch/m68k/fpsp040/
Ddecbin.S31 | adds and muls in FP0. Set the sign according to SM.
40 | added if SM = 1 and subtracted if SM = 0. Scale the
43 | SM = 0 a non-zero digit in the integer position
44 | SM = 1 a non-zero digit in Mant0, lsd of the fraction
435 bfextu %d4{#0:#2},%d0 | {FPCR[6],FPCR[5],SM,SE}
Dbindec.S903 bges mant_p |if pos, don't set SM
904 moveql #2,%d0 |move 2 in to d0 for SM
/linux-3.4.99/Documentation/filesystems/nfs/
Dnfs-rdma.txt175 If you are using InfiniBand, make sure there is a Subnet Manager (SM)
176 running on the network. If your IB switch has an embedded SM, you can
177 use it. Otherwise, you will need to run an SM, such as OpenSM, on one
180 If an SM is running on your network, you should see the following:
/linux-3.4.99/net/ipv4/
DKconfig240 bool "IP: PIM-SM version 1 support"
249 Say Y if you want to use PIM-SM v1. Note that you can say N here if
253 bool "IP: PIM-SM version 2 support"
/linux-3.4.99/net/ipv6/
DKconfig247 bool "IPv6: PIM-SM version 2 support (EXPERIMENTAL)"
/linux-3.4.99/Documentation/sound/oss/
DREADME.OSS492 SM Wave and AudioTrix Pro) support the OPL4 mode using MPU401
764 SM Games). If your card was in the list of supported cards (above),
925 NOTE! Don't enable the SM Games option (asked by the configuration program)
927 (not a SM Wave or SM16).
937 I know just Thunderboard and SM Games. Other cards require some kind of
1230 The Logitech SoundMan Wave (don't confuse this with the SM16 or SM Games) is
1234 you have a SM Wave immediately after asking the second DMA channel of jazz16.
1246 NOTE! Don't answer 'y' when the driver asks about SM Games support

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