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Searched refs:REG_WRITE (Results 1 – 25 of 127) sorted by relevance

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/linux-3.4.99/drivers/gpu/drm/gma500/
Dmdfld_dsi_dpi.c134 REG_WRITE(pipeconf_reg, BIT(31)); in dsi_set_pipe_plane_enable_state()
141 REG_WRITE(dspcntr_reg, dspcntr); in dsi_set_pipe_plane_enable_state()
157 REG_WRITE(dspbase_reg, REG_READ(dspbase_reg)); in dsi_set_pipe_plane_enable_state()
243 REG_WRITE(gen_data_reg, 0x00008036); in mdfld_dsi_tpo_ic_init()
245 REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x02 << WORD_COUNTS_POS)); in mdfld_dsi_tpo_ic_init()
249 REG_WRITE(gen_data_reg, 0x005a5af0); in mdfld_dsi_tpo_ic_init()
251 REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x03 << WORD_COUNTS_POS)); in mdfld_dsi_tpo_ic_init()
255 REG_WRITE(gen_data_reg, 0x005a5af1); in mdfld_dsi_tpo_ic_init()
257 REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x03 << WORD_COUNTS_POS)); in mdfld_dsi_tpo_ic_init()
261 REG_WRITE(gen_data_reg, 0x005a5afc); in mdfld_dsi_tpo_ic_init()
[all …]
Doaktrail_crtc.c186 REG_WRITE(dpll_reg, temp); in oaktrail_crtc_dpms()
190 REG_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE); in oaktrail_crtc_dpms()
194 REG_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE); in oaktrail_crtc_dpms()
202 REG_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE); in oaktrail_crtc_dpms()
206 REG_WRITE(dspcntr_reg, in oaktrail_crtc_dpms()
209 REG_WRITE(dspbase_reg, REG_READ(dspbase_reg)); in oaktrail_crtc_dpms()
224 REG_WRITE(VGACNTRL, VGA_DISP_DISABLE); in oaktrail_crtc_dpms()
228 REG_WRITE(dspcntr_reg, in oaktrail_crtc_dpms()
231 REG_WRITE(dspbase_reg, REG_READ(dspbase_reg)); in oaktrail_crtc_dpms()
238 REG_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE); in oaktrail_crtc_dpms()
[all …]
Dmdfld_intel_display.c168 REG_WRITE(dspcntr_reg, dspcntr); in mdfld__intel_plane_set_alpha()
245 REG_WRITE(dspstride, crtc->fb->pitches[0]); in mdfld__intel_pipe_set_base()
264 REG_WRITE(dspcntr_reg, dspcntr); in mdfld__intel_pipe_set_base()
268 REG_WRITE(dsplinoff, offset); in mdfld__intel_pipe_set_base()
270 REG_WRITE(dspsurf, start); in mdfld__intel_pipe_set_base()
320 REG_WRITE(dspcntr_reg, in mdfld_disable_crtc()
323 REG_WRITE(dspbase_reg, REG_READ(dspbase_reg)); in mdfld_disable_crtc()
334 REG_WRITE(pipeconf_reg, temp); in mdfld_disable_crtc()
347 REG_WRITE(dpll_reg, temp); in mdfld_disable_crtc()
355 REG_WRITE(dpll_reg, temp | MDFLD_PWR_GATE_EN); in mdfld_disable_crtc()
[all …]
Dcdv_device.c45 REG_WRITE(vga_reg, VGA_DISP_DISABLE); in cdv_disable_vga()
311 REG_WRITE(DSPCLK_GATE_D, regs->cdv.saveDSPCLK_GATE_D); in cdv_restore_display_registers()
312 REG_WRITE(RAMCLK_GATE_D, regs->cdv.saveRAMCLK_GATE_D); in cdv_restore_display_registers()
315 REG_WRITE(DPIO_CFG, 0); in cdv_restore_display_registers()
316 REG_WRITE(DPIO_CFG, DPIO_MODE_SELECT_0 | DPIO_CMN_RESET_N); in cdv_restore_display_registers()
320 REG_WRITE(DPLL_A, temp | DPLL_SYNCLOCK_ENABLE); in cdv_restore_display_registers()
326 REG_WRITE(DPLL_B, temp | DPLL_SYNCLOCK_ENABLE); in cdv_restore_display_registers()
332 REG_WRITE(DSPFW1, regs->cdv.saveDSPFW[0]); in cdv_restore_display_registers()
333 REG_WRITE(DSPFW2, regs->cdv.saveDSPFW[1]); in cdv_restore_display_registers()
334 REG_WRITE(DSPFW3, regs->cdv.saveDSPFW[2]); in cdv_restore_display_registers()
[all …]
Dcdv_intel_display.c145 REG_WRITE(SB_ADDR, reg); in cdv_sb_read()
146 REG_WRITE(SB_PCKT, in cdv_sb_read()
180 REG_WRITE(SB_ADDR, reg); in cdv_sb_write()
181 REG_WRITE(SB_DATA, val); in cdv_sb_write()
182 REG_WRITE(SB_PCKT, in cdv_sb_write()
207 REG_WRITE(DPIO_CFG, 0); in cdv_sb_reset()
209 REG_WRITE(DPIO_CFG, DPIO_MODE_SELECT_0 | DPIO_CMN_RESET_N); in cdv_sb_reset()
512 REG_WRITE(dspstride, crtc->fb->pitches[0]); in cdv_intel_pipe_set_base()
536 REG_WRITE(dspcntr_reg, dspcntr); in cdv_intel_pipe_set_base()
541 REG_WRITE(dspbase, offset); in cdv_intel_pipe_set_base()
[all …]
Dpsb_intel_display.c370 REG_WRITE(dspstride, crtc->fb->pitches[0]); in psb_intel_pipe_set_base()
395 REG_WRITE(dspcntr_reg, dspcntr); in psb_intel_pipe_set_base()
399 REG_WRITE(dspbase, offset); in psb_intel_pipe_set_base()
401 REG_WRITE(dspsurf, start); in psb_intel_pipe_set_base()
404 REG_WRITE(dspbase, start + offset); in psb_intel_pipe_set_base()
447 REG_WRITE(dpll_reg, temp); in psb_intel_crtc_dpms()
451 REG_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE); in psb_intel_crtc_dpms()
455 REG_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE); in psb_intel_crtc_dpms()
464 REG_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE); in psb_intel_crtc_dpms()
469 REG_WRITE(dspcntr_reg, in psb_intel_crtc_dpms()
[all …]
Dintel_gmbus.c75 REG_WRITE(GMBUS0, 0); in gma_intel_i2c_reset()
119 REG_WRITE(gpio->reg, reserved | GPIO_CLOCK_DIR_MASK); in get_clock()
120 REG_WRITE(gpio->reg, reserved); in get_clock()
130 REG_WRITE(gpio->reg, reserved | GPIO_DATA_DIR_MASK); in get_data()
131 REG_WRITE(gpio->reg, reserved); in get_data()
149 REG_WRITE(gpio->reg, reserved | clock_bits); in set_clock()
167 REG_WRITE(gpio->reg, reserved | data_bits); in set_data()
264 REG_WRITE(GMBUS0 + reg_offset, bus->reg0); in gmbus_xfer()
271 REG_WRITE(GMBUS1 + reg_offset, in gmbus_xfer()
299 REG_WRITE(GMBUS3 + reg_offset, val); in gmbus_xfer()
[all …]
Dpsb_intel_lvds.c159 REG_WRITE(BLC_PWM_CTL, in psb_lvds_pwm_set_brightness()
203 REG_WRITE(BLC_PWM_CTL, in psb_intel_lvds_set_backlight()
232 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | in psb_intel_lvds_set_power()
243 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & in psb_intel_lvds_set_power()
323 REG_WRITE(BLC_PWM_CTL, lvds_priv->saveBLC_PWM_CTL); in psb_intel_lvds_restore()
324 REG_WRITE(PFIT_CONTROL, lvds_priv->savePFIT_CONTROL); in psb_intel_lvds_restore()
325 REG_WRITE(PFIT_PGM_RATIOS, lvds_priv->savePFIT_PGM_RATIOS); in psb_intel_lvds_restore()
326 REG_WRITE(LVDSPP_ON, lvds_priv->savePP_ON); in psb_intel_lvds_restore()
327 REG_WRITE(LVDSPP_OFF, lvds_priv->savePP_OFF); in psb_intel_lvds_restore()
329 REG_WRITE(PP_CYCLE, lvds_priv->savePP_CYCLE); in psb_intel_lvds_restore()
[all …]
Doaktrail_lvds.c56 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | in oaktrail_lvds_set_power()
67 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & in oaktrail_lvds_set_power()
123 REG_WRITE(LVDS, lvds_port); in oaktrail_lvds_mode_set()
142 REG_WRITE(PFIT_CONTROL, 0); in oaktrail_lvds_mode_set()
148 REG_WRITE(PFIT_CONTROL, PFIT_ENABLE); in oaktrail_lvds_mode_set()
152 REG_WRITE(PFIT_CONTROL, PFIT_ENABLE | in oaktrail_lvds_mode_set()
155 REG_WRITE(PFIT_CONTROL, PFIT_ENABLE | in oaktrail_lvds_mode_set()
158 REG_WRITE(PFIT_CONTROL, PFIT_ENABLE); in oaktrail_lvds_mode_set()
160 REG_WRITE(PFIT_CONTROL, PFIT_ENABLE); in oaktrail_lvds_mode_set()
/linux-3.4.99/drivers/net/dsa/
Dmv88e6123_61_65.c59 REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc); in mv88e6123_61_65_switch_reset()
70 REG_WRITE(REG_GLOBAL, 0x04, 0xc400); in mv88e6123_61_65_switch_reset()
98 REG_WRITE(REG_GLOBAL, 0x04, 0x0000); in mv88e6123_61_65_setup_global()
105 REG_WRITE(REG_GLOBAL, 0x0a, 0x0148); in mv88e6123_61_65_setup_global()
119 REG_WRITE(REG_GLOBAL, 0x1a, (dsa_upstream_port(ds) * 0x1110)); in mv88e6123_61_65_setup_global()
125 REG_WRITE(REG_GLOBAL, 0x1c, ds->index & 0x1f); in mv88e6123_61_65_setup_global()
131 REG_WRITE(REG_GLOBAL2, 0x02, 0xffff); in mv88e6123_61_65_setup_global()
137 REG_WRITE(REG_GLOBAL2, 0x03, 0xffff); in mv88e6123_61_65_setup_global()
147 REG_WRITE(REG_GLOBAL2, 0x05, 0x00ff); in mv88e6123_61_65_setup_global()
159 REG_WRITE(REG_GLOBAL2, 0x06, 0x8000 | (i << 8) | nexthop); in mv88e6123_61_65_setup_global()
[all …]
Dmv88e6131.c53 REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc); in mv88e6131_switch_reset()
64 REG_WRITE(REG_GLOBAL, 0x04, 0xc400); in mv88e6131_switch_reset()
93 REG_WRITE(REG_GLOBAL, 0x04, 0x4400); in mv88e6131_setup_global()
100 REG_WRITE(REG_GLOBAL, 0x0a, 0x0148); in mv88e6131_setup_global()
112 REG_WRITE(REG_GLOBAL, 0x19, 0x8100); in mv88e6131_setup_global()
119 REG_WRITE(REG_GLOBAL, 0x1a, (dsa_upstream_port(ds) * 0x1100) | 0x00f0); in mv88e6131_setup_global()
127 REG_WRITE(REG_GLOBAL, 0x1c, 0xf000 | (ds->index & 0x1f)); in mv88e6131_setup_global()
129 REG_WRITE(REG_GLOBAL, 0x1c, 0xe000 | (ds->index & 0x1f)); in mv88e6131_setup_global()
135 REG_WRITE(REG_GLOBAL2, 0x03, 0xffff); in mv88e6131_setup_global()
143 REG_WRITE(REG_GLOBAL2, 0x05, 0x00ff); in mv88e6131_setup_global()
[all …]
Dmv88e6060.c42 #define REG_WRITE(addr, reg, val) \ macro
75 REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc); in mv88e6060_switch_reset()
86 REG_WRITE(REG_GLOBAL, 0x0a, 0xa130); in mv88e6060_switch_reset()
111 REG_WRITE(REG_GLOBAL, 0x04, 0x0800); in mv88e6060_setup_global()
118 REG_WRITE(REG_GLOBAL, 0x0a, 0x2130); in mv88e6060_setup_global()
133 REG_WRITE(addr, 0x04, dsa_is_cpu_port(ds, p) ? 0x4103 : 0x0003); in mv88e6060_setup_port()
141 REG_WRITE(addr, 0x06, in mv88e6060_setup_port()
153 REG_WRITE(addr, 0x0b, 1 << p); in mv88e6060_setup_port()
184 REG_WRITE(REG_GLOBAL, 0x01, (addr[0] << 8) | addr[1]); in mv88e6060_set_addr()
185 REG_WRITE(REG_GLOBAL, 0x02, (addr[2] << 8) | addr[3]); in mv88e6060_set_addr()
[all …]
Dmv88e6xxx.c152 REG_WRITE(REG_GLOBAL, 0x10, 0x0000); in mv88e6xxx_config_prio()
153 REG_WRITE(REG_GLOBAL, 0x11, 0x0000); in mv88e6xxx_config_prio()
154 REG_WRITE(REG_GLOBAL, 0x12, 0x5555); in mv88e6xxx_config_prio()
155 REG_WRITE(REG_GLOBAL, 0x13, 0x5555); in mv88e6xxx_config_prio()
156 REG_WRITE(REG_GLOBAL, 0x14, 0xaaaa); in mv88e6xxx_config_prio()
157 REG_WRITE(REG_GLOBAL, 0x15, 0xaaaa); in mv88e6xxx_config_prio()
158 REG_WRITE(REG_GLOBAL, 0x16, 0xffff); in mv88e6xxx_config_prio()
159 REG_WRITE(REG_GLOBAL, 0x17, 0xffff); in mv88e6xxx_config_prio()
164 REG_WRITE(REG_GLOBAL, 0x18, 0xfa41); in mv88e6xxx_config_prio()
171 REG_WRITE(REG_GLOBAL, 0x01, (addr[0] << 8) | addr[1]); in mv88e6xxx_set_addr_direct()
[all …]
/linux-3.4.99/drivers/net/wireless/ath/
Dkey.c26 #define REG_WRITE(_ah, _reg, _val) (common->ops->write)(_ah, _val, _reg) macro
56 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0); in ath_hw_keyreset()
57 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0); in ath_hw_keyreset()
58 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0); in ath_hw_keyreset()
59 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0); in ath_hw_keyreset()
60 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0); in ath_hw_keyreset()
61 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR); in ath_hw_keyreset()
62 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0); in ath_hw_keyreset()
63 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0); in ath_hw_keyreset()
68 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0); in ath_hw_keyreset()
[all …]
Dhw.c24 #define REG_WRITE (common->ops->write) macro
122 REG_WRITE(ah, get_unaligned_le32(common->bssidmask), AR_BSSMSKL); in ath_hw_setbssidmask()
123 REG_WRITE(ah, get_unaligned_le16(common->bssidmask + 4), AR_BSSMSKU); in ath_hw_setbssidmask()
142 REG_WRITE(ah, AR_MIBC_FMC, AR_MIBC); in ath_hw_cycle_counters_update()
151 REG_WRITE(ah, 0, AR_CCCNT); in ath_hw_cycle_counters_update()
152 REG_WRITE(ah, 0, AR_RFCNT); in ath_hw_cycle_counters_update()
153 REG_WRITE(ah, 0, AR_RCCNT); in ath_hw_cycle_counters_update()
154 REG_WRITE(ah, 0, AR_TFCNT); in ath_hw_cycle_counters_update()
157 REG_WRITE(ah, 0, AR_MIBC); in ath_hw_cycle_counters_update()
/linux-3.4.99/drivers/net/wireless/ath/ath9k/
Dhw.c152 REG_WRITE(ah, INI_RA(array, r, 0), in ath9k_hw_write_array()
315 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); in ath9k_hw_disablepcie()
316 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); in ath9k_hw_disablepcie()
317 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); in ath9k_hw_disablepcie()
318 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); in ath9k_hw_disablepcie()
319 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); in ath9k_hw_disablepcie()
320 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); in ath9k_hw_disablepcie()
321 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); in ath9k_hw_disablepcie()
322 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); in ath9k_hw_disablepcie()
323 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); in ath9k_hw_disablepcie()
[all …]
Dar9002_phy.c101 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, in ar9002_hw_set_channel()
104 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, in ar9002_hw_set_channel()
152 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32); in ar9002_hw_set_channel()
251 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal); in ar9002_hw_spur_mitigate()
258 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal); in ar9002_hw_spur_mitigate()
288 REG_WRITE(ah, AR_PHY_TIMING11, newVal); in ar9002_hw_spur_mitigate()
291 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal); in ar9002_hw_spur_mitigate()
309 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); in ar9002_hw_spur_mitigate()
310 REG_WRITE(ah, chan_mask_reg[i], chan_mask); in ar9002_hw_spur_mitigate()
343 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); in ar9002_hw_spur_mitigate()
[all …]
Dar9003_mci.c39 REG_WRITE(ah, address, bit_position); in ar9003_mci_wait_for_interrupt()
49 REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, in ar9003_mci_wait_for_interrupt()
52 REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, in ar9003_mci_wait_for_interrupt()
235 REG_WRITE(ah, AR_MCI_INTERRUPT_EN, 0); in ar9003_mci_prep_interface()
236 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW, in ar9003_mci_prep_interface()
238 REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, in ar9003_mci_prep_interface()
272 REG_WRITE(ah, AR_MCI_BT_PRI0, 0xFFFFFFFF); in ar9003_mci_prep_interface()
273 REG_WRITE(ah, AR_MCI_BT_PRI1, 0xFFFFFFFF); in ar9003_mci_prep_interface()
274 REG_WRITE(ah, AR_MCI_BT_PRI2, 0xFFFFFFFF); in ar9003_mci_prep_interface()
275 REG_WRITE(ah, AR_MCI_BT_PRI3, 0xFFFFFFFF); in ar9003_mci_prep_interface()
[all …]
Dar9003_rtt.c39 REG_WRITE(ah, AR_PHY_RTT_CTRL, 1); in ar9003_hw_rtt_enable()
44 REG_WRITE(ah, AR_PHY_RTT_CTRL, 0); in ar9003_hw_rtt_disable()
77 REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_1_B(chain), val); in ar9003_hw_rtt_load_hist_entry()
82 REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val); in ar9003_hw_rtt_load_hist_entry()
86 REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val); in ar9003_hw_rtt_load_hist_entry()
95 REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val); in ar9003_hw_rtt_load_hist_entry()
119 REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val); in ar9003_hw_rtt_fill_hist_entry()
123 REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val); in ar9003_hw_rtt_fill_hist_entry()
Dar9002_hw.c291 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0), in ar9002_hw_configpcipowersave()
297 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); in ar9002_hw_configpcipowersave()
298 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); in ar9002_hw_configpcipowersave()
301 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039); in ar9002_hw_configpcipowersave()
302 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824); in ar9002_hw_configpcipowersave()
303 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579); in ar9002_hw_configpcipowersave()
309 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff); in ar9002_hw_configpcipowersave()
311 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); in ar9002_hw_configpcipowersave()
312 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); in ar9002_hw_configpcipowersave()
313 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007); in ar9002_hw_configpcipowersave()
[all …]
Dmac.c32 REG_WRITE(ah, AR_IMR_S0, in ath9k_hw_set_txq_interrupts()
35 REG_WRITE(ah, AR_IMR_S1, in ath9k_hw_set_txq_interrupts()
41 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); in ath9k_hw_set_txq_interrupts()
54 REG_WRITE(ah, AR_QTXDP(q), txdp); in ath9k_hw_puttxbuf()
61 REG_WRITE(ah, AR_Q_TXE, 1 << q); in ath9k_hw_txstart()
123 REG_WRITE(ah, AR_TXCFG, in ath9k_hw_updatetxtriglevel()
138 REG_WRITE(ah, AR_Q_TXD, AR_Q_TXD_M); in ath9k_hw_abort_tx_dma()
158 REG_WRITE(ah, AR_Q_TXD, 0); in ath9k_hw_abort_tx_dma()
169 REG_WRITE(ah, AR_Q_TXD, 1 << q); in ath9k_hw_stop_dma_queue()
179 REG_WRITE(ah, AR_Q_TXD, 0); in ath9k_hw_stop_dma_queue()
[all …]
Dbtcoex.c235 REG_WRITE(ah, AR_BT_COEX_MODE, btcoex->bt_coex_mode); in ath9k_hw_btcoex_enable_3wire()
236 REG_WRITE(ah, AR_BT_COEX_MODE2, btcoex->bt_coex_mode2); in ath9k_hw_btcoex_enable_3wire()
240 REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS0, btcoex->wlan_weight[0]); in ath9k_hw_btcoex_enable_3wire()
241 REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS1, btcoex->wlan_weight[1]); in ath9k_hw_btcoex_enable_3wire()
243 REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS(i), in ath9k_hw_btcoex_enable_3wire()
246 REG_WRITE(ah, AR_BT_COEX_WEIGHT, btcoex->bt_coex_weights); in ath9k_hw_btcoex_enable_3wire()
253 REG_WRITE(ah, 0x50040, val); in ath9k_hw_btcoex_enable_3wire()
269 REG_WRITE(ah, AR_MCI_COEX_WL_WEIGHTS(i), in ath9k_hw_btcoex_enable_mci()
311 REG_WRITE(ah, AR_MCI_COEX_WL_WEIGHTS(i), in ath9k_hw_btcoex_disable()
320 REG_WRITE(ah, AR_BT_COEX_MODE, AR_BT_QUIET | AR_BT_MODE); in ath9k_hw_btcoex_disable()
[all …]
Dar5008_phy.c68 REG_WRITE(ah, INI_RA(array, r, 0), data[r]); in ar5008_write_rf_array()
213 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, in ar5008_hw_set_channel()
216 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, in ar5008_hw_set_channel()
245 REG_WRITE(ah, AR_PHY(0x37), reg32); in ar5008_hw_set_channel()
314 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new); in ar5008_hw_spur_mitigate()
321 REG_WRITE(ah, AR_PHY_SPUR_REG, new); in ar5008_hw_spur_mitigate()
332 REG_WRITE(ah, AR_PHY_TIMING11, new); in ar5008_hw_spur_mitigate()
350 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); in ar5008_hw_spur_mitigate()
351 REG_WRITE(ah, chan_mask_reg[i], chan_mask); in ar5008_hw_spur_mitigate()
384 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); in ar5008_hw_spur_mitigate()
[all …]
Dani.c144 REG_WRITE(ah, AR_PHY_ERR_1, ofdm_base); in ath9k_ani_restart()
145 REG_WRITE(ah, AR_PHY_ERR_2, cck_base); in ath9k_ani_restart()
146 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); in ath9k_ani_restart()
147 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); in ath9k_ani_restart()
529 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); in ath9k_ani_reset_old()
530 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); in ath9k_ani_reset_old()
623 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); in ath9k_ani_reset()
624 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); in ath9k_ani_reset()
665 REG_WRITE(ah, AR_PHY_ERR_1, ofdm_base); in ath9k_hw_ani_read_counters()
666 REG_WRITE(ah, AR_PHY_ERR_MASK_1, in ath9k_hw_ani_read_counters()
[all …]
Dar9002_calib.c63 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ); in ar9002_hw_setup_calibration()
68 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN); in ar9002_hw_setup_calibration()
72 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER); in ar9002_hw_setup_calibration()
305 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val); in ar9002_hw_adc_gaincal_calibrate()
312 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0), in ar9002_hw_adc_gaincal_calibrate()
360 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val); in ar9002_hw_adc_dccal_calibrate()
366 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0), in ar9002_hw_adc_dccal_calibrate()
451 REG_WRITE(ah, 0x7834, regVal); in ar9271_hw_pa_cal()
454 REG_WRITE(ah, 0x9808, regVal); in ar9271_hw_pa_cal()
490 REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0); in ar9271_hw_pa_cal()
[all …]

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