Lines Matching refs:REG_WRITE
152 REG_WRITE(ah, INI_RA(array, r, 0), in ath9k_hw_write_array()
315 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); in ath9k_hw_disablepcie()
316 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); in ath9k_hw_disablepcie()
317 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); in ath9k_hw_disablepcie()
318 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); in ath9k_hw_disablepcie()
319 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); in ath9k_hw_disablepcie()
320 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); in ath9k_hw_disablepcie()
321 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); in ath9k_hw_disablepcie()
322 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); in ath9k_hw_disablepcie()
323 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); in ath9k_hw_disablepcie()
325 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); in ath9k_hw_disablepcie()
360 REG_WRITE(ah, addr, wrData); in ath9k_hw_chip_test()
371 REG_WRITE(ah, addr, wrData); in ath9k_hw_chip_test()
380 REG_WRITE(ah, regAddr[i], regHold[i]); in ath9k_hw_chip_test()
705 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); in ath9k_hw_init_qos()
706 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); in ath9k_hw_init_qos()
708 REG_WRITE(ah, AR_QOS_NO_ACK, in ath9k_hw_init_qos()
713 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL); in ath9k_hw_init_qos()
714 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF); in ath9k_hw_init_qos()
715 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); in ath9k_hw_init_qos()
716 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); in ath9k_hw_init_qos()
717 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); in ath9k_hw_init_qos()
797 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2); in ath9k_hw_init_pll()
803 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c); in ath9k_hw_init_pll()
807 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2); in ath9k_hw_init_pll()
819 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c); in ath9k_hw_init_pll()
837 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); in ath9k_hw_init_pll()
840 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) | in ath9k_hw_init_pll()
847 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); in ath9k_hw_init_pll()
848 REG_WRITE(ah, AR_PHY_PLL_MODE, in ath9k_hw_init_pll()
855 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); in ath9k_hw_init_pll()
863 REG_WRITE(ah, 0x50040, 0x304); in ath9k_hw_init_pll()
868 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); in ath9k_hw_init_pll()
872 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1); in ath9k_hw_init_pll()
873 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7); in ath9k_hw_init_pll()
874 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae); in ath9k_hw_init_pll()
876 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1); in ath9k_hw_init_pll()
877 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400); in ath9k_hw_init_pll()
878 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800); in ath9k_hw_init_pll()
921 REG_WRITE(ah, AR_IMR, imr_reg); in ath9k_hw_init_interrupt_masks()
923 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); in ath9k_hw_init_interrupt_masks()
926 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF); in ath9k_hw_init_interrupt_masks()
927 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default); in ath9k_hw_init_interrupt_masks()
928 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0); in ath9k_hw_init_interrupt_masks()
934 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0); in ath9k_hw_init_interrupt_masks()
935 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0); in ath9k_hw_init_interrupt_masks()
936 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0); in ath9k_hw_init_interrupt_masks()
937 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0); in ath9k_hw_init_interrupt_masks()
945 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val); in ath9k_hw_set_sifs_time()
952 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val); in ath9k_hw_setslottime()
1070 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs)); in ath9k_hw_init_global_settings()
1153 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); in ath9k_hw_set_dma()
1172 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, in ath9k_hw_set_dma()
1175 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, in ath9k_hw_set_dma()
1241 REG_WRITE(ah, AR_WA, ah->WARegVal); in ath9k_hw_set_reset()
1245 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | in ath9k_hw_set_reset()
1257 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); in ath9k_hw_set_reset()
1262 REG_WRITE(ah, AR_RC, val); in ath9k_hw_set_reset()
1265 REG_WRITE(ah, AR_RC, AR_RC_AHB); in ath9k_hw_set_reset()
1303 REG_WRITE(ah, AR_RTC_RESET, 1); in ath9k_hw_set_reset()
1307 REG_WRITE(ah, AR_RTC_RC, rst_flags); in ath9k_hw_set_reset()
1313 REG_WRITE(ah, AR_RTC_RC, 0); in ath9k_hw_set_reset()
1320 REG_WRITE(ah, AR_RC, 0); in ath9k_hw_set_reset()
1333 REG_WRITE(ah, AR_WA, ah->WARegVal); in ath9k_hw_set_reset_power_on()
1337 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | in ath9k_hw_set_reset_power_on()
1341 REG_WRITE(ah, AR_RC, AR_RC_AHB); in ath9k_hw_set_reset_power_on()
1343 REG_WRITE(ah, AR_RTC_RESET, 0); in ath9k_hw_set_reset_power_on()
1351 REG_WRITE(ah, AR_RC, 0); in ath9k_hw_set_reset_power_on()
1353 REG_WRITE(ah, AR_RTC_RESET, 1); in ath9k_hw_set_reset_power_on()
1372 REG_WRITE(ah, AR_WA, ah->WARegVal); in ath9k_hw_set_reset_reg()
1376 REG_WRITE(ah, AR_RTC_FORCE_WAKE, in ath9k_hw_set_reset_reg()
1392 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2); in ath9k_hw_set_reset_reg()
1669 REG_WRITE(ah, in ath9k_hw_reset()
1683 REG_WRITE(ah, in ath9k_hw_reset()
1742 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr)); in ath9k_hw_reset()
1743 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4) in ath9k_hw_reset()
1750 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); in ath9k_hw_reset()
1752 REG_WRITE(ah, AR_ISR, ~0); in ath9k_hw_reset()
1753 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); in ath9k_hw_reset()
1768 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); in ath9k_hw_reset()
1798 REG_WRITE(ah, AR_OBS, 8); in ath9k_hw_reset()
1829 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ); in ath9k_hw_reset()
1845 REG_WRITE(ah, AR_CFG, mask); in ath9k_hw_reset()
1853 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB); in ath9k_hw_reset()
1855 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); in ath9k_hw_reset()
1861 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); in ath9k_hw_reset()
1896 REG_WRITE(ah, AR_TIMER_MODE, in ath9k_set_power_sleep()
1898 REG_WRITE(ah, AR_NDP2_TIMER_MODE, REG_READ(ah, in ath9k_set_power_sleep()
1900 REG_WRITE(ah, AR_SLP32_INC, in ath9k_set_power_sleep()
1903 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0); in ath9k_set_power_sleep()
1917 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); in ath9k_set_power_sleep()
1928 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); in ath9k_set_power_sleep()
1946 REG_WRITE(ah, AR_RTC_FORCE_WAKE, in ath9k_set_power_network_sleep()
1962 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, val); in ath9k_set_power_network_sleep()
1978 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); in ath9k_set_power_network_sleep()
1988 REG_WRITE(ah, AR_WA, ah->WARegVal); in ath9k_hw_set_power_awake()
2052 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2); in ath9k_hw_setpower()
2065 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2); in ath9k_hw_setpower()
2103 REG_WRITE(ah, AR_NEXT_NDP_TIMER, next_beacon + in ath9k_hw_beaconinit()
2107 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon); in ath9k_hw_beaconinit()
2108 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon - in ath9k_hw_beaconinit()
2110 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon - in ath9k_hw_beaconinit()
2122 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period); in ath9k_hw_beaconinit()
2123 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period); in ath9k_hw_beaconinit()
2124 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period); in ath9k_hw_beaconinit()
2125 REG_WRITE(ah, AR_NDP_PERIOD, beacon_period); in ath9k_hw_beaconinit()
2142 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt)); in ath9k_hw_set_sta_beacon_timers()
2144 REG_WRITE(ah, AR_BEACON_PERIOD, in ath9k_hw_set_sta_beacon_timers()
2146 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, in ath9k_hw_set_sta_beacon_timers()
2175 REG_WRITE(ah, AR_NEXT_DTIM, in ath9k_hw_set_sta_beacon_timers()
2177 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP)); in ath9k_hw_set_sta_beacon_timers()
2179 REG_WRITE(ah, AR_SLEEP1, in ath9k_hw_set_sta_beacon_timers()
2188 REG_WRITE(ah, AR_SLEEP2, in ath9k_hw_set_sta_beacon_timers()
2191 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval)); in ath9k_hw_set_sta_beacon_timers()
2192 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod)); in ath9k_hw_set_sta_beacon_timers()
2201 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold); in ath9k_hw_set_sta_beacon_timers()
2491 REG_WRITE(ah, addr, tmp); in ath9k_hw_gpio_cfg_output_mux()
2586 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); in ath9k_hw_setantenna()
2617 REG_WRITE(ah, AR_RX_FILTER, bits); in ath9k_hw_setrxfilter()
2624 REG_WRITE(ah, AR_PHY_ERR, phybits); in ath9k_hw_setrxfilter()
2721 REG_WRITE(ah, AR_MCAST_FIL0, filter0); in ath9k_hw_setmcastfilter()
2722 REG_WRITE(ah, AR_MCAST_FIL1, filter1); in ath9k_hw_setmcastfilter()
2730 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid)); in ath9k_hw_write_associd()
2731 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) | in ath9k_hw_write_associd()
2760 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff); in ath9k_hw_settsf64()
2761 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff); in ath9k_hw_settsf64()
2772 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); in ath9k_hw_reset_tsf()
2795 REG_WRITE(ah, AR_2040_MODE, macmode); in ath9k_hw_set11nmac2040()
2901 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr, in ath9k_hw_gen_timer_start()
2903 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr, in ath9k_hw_gen_timer_start()