Searched refs:PLL_BASE (Results 1 – 3 of 3) sorted by relevance
81 #define PLL_BASE 0x0 macro619 u32 val = clk_readl(c->reg + PLL_BASE); in tegra2_pll_clk_init()645 val = clk_readl(c->reg + PLL_BASE); in tegra2_pll_clk_enable()648 clk_writel(val, c->reg + PLL_BASE); in tegra2_pll_clk_enable()679 val = clk_readl(c->reg + PLL_BASE); in tegra2_pll_clk_set_rate()694 clk_writel(val, c->reg + PLL_BASE); in tegra2_pll_clk_set_rate()742 val = clk_readl(c->reg + PLL_BASE); in tegra2_plle_clk_enable()746 val = clk_readl(c->reg + PLL_BASE); in tegra2_plle_clk_enable()748 clk_writel(val, c->reg + PLL_BASE); in tegra2_plle_clk_enable()2347 *ctx++ = clk_readl(tegra_pll_c.reg + PLL_BASE); in tegra_clk_suspend()[all …]
144 #define PLL_BASE 0x0 macro891 u32 val = clk_readl(c->reg + PLL_BASE); in tegra30_pll_clk_init()939 val = clk_readl(c->reg + PLL_BASE); in tegra30_pll_clk_enable()942 clk_writel(val, c->reg + PLL_BASE); in tegra30_pll_clk_enable()950 tegra30_pll_clk_wait_for_lock(c, c->reg + PLL_BASE, PLL_BASE_LOCK); in tegra30_pll_clk_enable()1067 old_base = val = clk_readl(c->reg + PLL_BASE); in tegra30_pll_clk_set_rate()1079 clk_writel(val, c->reg + PLL_BASE); in tegra30_pll_clk_set_rate()1118 reg = c->reg + PLL_BASE; in tegra30_plld_clk_cfg_ex()1127 reg = c->reg + PLL_BASE; in tegra30_plld_clk_cfg_ex()1161 val = clk_readl(c->reg + PLL_BASE); in tegra30_plle_clk_init()[all …]
27 #define PLL_BASE IMX_IO_ADDRESS(MX6Q_ANATOP_BASE_ADDR) macro28 #define PLL1_SYS (PLL_BASE + 0x000)29 #define PLL2_BUS (PLL_BASE + 0x030)30 #define PLL3_USB_OTG (PLL_BASE + 0x010)31 #define PLL4_AUDIO (PLL_BASE + 0x070)32 #define PLL5_VIDEO (PLL_BASE + 0x0a0)33 #define PLL6_MLB (PLL_BASE + 0x0d0)34 #define PLL7_USB_HOST (PLL_BASE + 0x020)35 #define PLL8_ENET (PLL_BASE + 0x0e0)36 #define PFD_480 (PLL_BASE + 0x0f0)[all …]