Lines Matching refs:PLL_BASE
81 #define PLL_BASE 0x0 macro
619 u32 val = clk_readl(c->reg + PLL_BASE); in tegra2_pll_clk_init()
645 val = clk_readl(c->reg + PLL_BASE); in tegra2_pll_clk_enable()
648 clk_writel(val, c->reg + PLL_BASE); in tegra2_pll_clk_enable()
679 val = clk_readl(c->reg + PLL_BASE); in tegra2_pll_clk_set_rate()
694 clk_writel(val, c->reg + PLL_BASE); in tegra2_pll_clk_set_rate()
742 val = clk_readl(c->reg + PLL_BASE); in tegra2_plle_clk_enable()
746 val = clk_readl(c->reg + PLL_BASE); in tegra2_plle_clk_enable()
748 clk_writel(val, c->reg + PLL_BASE); in tegra2_plle_clk_enable()
2347 *ctx++ = clk_readl(tegra_pll_c.reg + PLL_BASE); in tegra_clk_suspend()
2349 *ctx++ = clk_readl(tegra_pll_a.reg + PLL_BASE); in tegra_clk_suspend()
2351 *ctx++ = clk_readl(tegra_pll_s.reg + PLL_BASE); in tegra_clk_suspend()
2353 *ctx++ = clk_readl(tegra_pll_d.reg + PLL_BASE); in tegra_clk_suspend()
2355 *ctx++ = clk_readl(tegra_pll_u.reg + PLL_BASE); in tegra_clk_suspend()
2402 clk_writel(*ctx++, tegra_pll_c.reg + PLL_BASE); in tegra_clk_resume()
2404 clk_writel(*ctx++, tegra_pll_a.reg + PLL_BASE); in tegra_clk_resume()
2406 clk_writel(*ctx++, tegra_pll_s.reg + PLL_BASE); in tegra_clk_resume()
2408 clk_writel(*ctx++, tegra_pll_d.reg + PLL_BASE); in tegra_clk_resume()
2410 clk_writel(*ctx++, tegra_pll_u.reg + PLL_BASE); in tegra_clk_resume()