1 /*
2 * arch/arm/mach-tegra/tegra2_clocks.c
3 *
4 * Copyright (C) 2010 Google, Inc.
5 *
6 * Author:
7 * Colin Cross <ccross@google.com>
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/list.h>
23 #include <linux/spinlock.h>
24 #include <linux/delay.h>
25 #include <linux/io.h>
26 #include <linux/clkdev.h>
27 #include <linux/clk.h>
28
29 #include <mach/iomap.h>
30 #include <mach/suspend.h>
31
32 #include "clock.h"
33 #include "fuse.h"
34 #include "tegra2_emc.h"
35
36 #define RST_DEVICES 0x004
37 #define RST_DEVICES_SET 0x300
38 #define RST_DEVICES_CLR 0x304
39 #define RST_DEVICES_NUM 3
40
41 #define CLK_OUT_ENB 0x010
42 #define CLK_OUT_ENB_SET 0x320
43 #define CLK_OUT_ENB_CLR 0x324
44 #define CLK_OUT_ENB_NUM 3
45
46 #define CLK_MASK_ARM 0x44
47 #define MISC_CLK_ENB 0x48
48
49 #define OSC_CTRL 0x50
50 #define OSC_CTRL_OSC_FREQ_MASK (3<<30)
51 #define OSC_CTRL_OSC_FREQ_13MHZ (0<<30)
52 #define OSC_CTRL_OSC_FREQ_19_2MHZ (1<<30)
53 #define OSC_CTRL_OSC_FREQ_12MHZ (2<<30)
54 #define OSC_CTRL_OSC_FREQ_26MHZ (3<<30)
55 #define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)
56
57 #define OSC_FREQ_DET 0x58
58 #define OSC_FREQ_DET_TRIG (1<<31)
59
60 #define OSC_FREQ_DET_STATUS 0x5C
61 #define OSC_FREQ_DET_BUSY (1<<31)
62 #define OSC_FREQ_DET_CNT_MASK 0xFFFF
63
64 #define PERIPH_CLK_SOURCE_I2S1 0x100
65 #define PERIPH_CLK_SOURCE_EMC 0x19c
66 #define PERIPH_CLK_SOURCE_OSC 0x1fc
67 #define PERIPH_CLK_SOURCE_NUM \
68 ((PERIPH_CLK_SOURCE_OSC - PERIPH_CLK_SOURCE_I2S1) / 4)
69
70 #define PERIPH_CLK_SOURCE_MASK (3<<30)
71 #define PERIPH_CLK_SOURCE_SHIFT 30
72 #define PERIPH_CLK_SOURCE_ENABLE (1<<28)
73 #define PERIPH_CLK_SOURCE_DIVU71_MASK 0xFF
74 #define PERIPH_CLK_SOURCE_DIVU16_MASK 0xFFFF
75 #define PERIPH_CLK_SOURCE_DIV_SHIFT 0
76
77 #define SDMMC_CLK_INT_FB_SEL (1 << 23)
78 #define SDMMC_CLK_INT_FB_DLY_SHIFT 16
79 #define SDMMC_CLK_INT_FB_DLY_MASK (0xF << SDMMC_CLK_INT_FB_DLY_SHIFT)
80
81 #define PLL_BASE 0x0
82 #define PLL_BASE_BYPASS (1<<31)
83 #define PLL_BASE_ENABLE (1<<30)
84 #define PLL_BASE_REF_ENABLE (1<<29)
85 #define PLL_BASE_OVERRIDE (1<<28)
86 #define PLL_BASE_DIVP_MASK (0x7<<20)
87 #define PLL_BASE_DIVP_SHIFT 20
88 #define PLL_BASE_DIVN_MASK (0x3FF<<8)
89 #define PLL_BASE_DIVN_SHIFT 8
90 #define PLL_BASE_DIVM_MASK (0x1F)
91 #define PLL_BASE_DIVM_SHIFT 0
92
93 #define PLL_OUT_RATIO_MASK (0xFF<<8)
94 #define PLL_OUT_RATIO_SHIFT 8
95 #define PLL_OUT_OVERRIDE (1<<2)
96 #define PLL_OUT_CLKEN (1<<1)
97 #define PLL_OUT_RESET_DISABLE (1<<0)
98
99 #define PLL_MISC(c) (((c)->flags & PLL_ALT_MISC_REG) ? 0x4 : 0xc)
100
101 #define PLL_MISC_DCCON_SHIFT 20
102 #define PLL_MISC_CPCON_SHIFT 8
103 #define PLL_MISC_CPCON_MASK (0xF<<PLL_MISC_CPCON_SHIFT)
104 #define PLL_MISC_LFCON_SHIFT 4
105 #define PLL_MISC_LFCON_MASK (0xF<<PLL_MISC_LFCON_SHIFT)
106 #define PLL_MISC_VCOCON_SHIFT 0
107 #define PLL_MISC_VCOCON_MASK (0xF<<PLL_MISC_VCOCON_SHIFT)
108
109 #define PLLU_BASE_POST_DIV (1<<20)
110
111 #define PLLD_MISC_CLKENABLE (1<<30)
112 #define PLLD_MISC_DIV_RST (1<<23)
113 #define PLLD_MISC_DCCON_SHIFT 12
114
115 #define PLLE_MISC_READY (1 << 15)
116
117 #define PERIPH_CLK_TO_ENB_REG(c) ((c->u.periph.clk_num / 32) * 4)
118 #define PERIPH_CLK_TO_ENB_SET_REG(c) ((c->u.periph.clk_num / 32) * 8)
119 #define PERIPH_CLK_TO_ENB_BIT(c) (1 << (c->u.periph.clk_num % 32))
120
121 #define SUPER_CLK_MUX 0x00
122 #define SUPER_STATE_SHIFT 28
123 #define SUPER_STATE_MASK (0xF << SUPER_STATE_SHIFT)
124 #define SUPER_STATE_STANDBY (0x0 << SUPER_STATE_SHIFT)
125 #define SUPER_STATE_IDLE (0x1 << SUPER_STATE_SHIFT)
126 #define SUPER_STATE_RUN (0x2 << SUPER_STATE_SHIFT)
127 #define SUPER_STATE_IRQ (0x3 << SUPER_STATE_SHIFT)
128 #define SUPER_STATE_FIQ (0x4 << SUPER_STATE_SHIFT)
129 #define SUPER_SOURCE_MASK 0xF
130 #define SUPER_FIQ_SOURCE_SHIFT 12
131 #define SUPER_IRQ_SOURCE_SHIFT 8
132 #define SUPER_RUN_SOURCE_SHIFT 4
133 #define SUPER_IDLE_SOURCE_SHIFT 0
134
135 #define SUPER_CLK_DIVIDER 0x04
136
137 #define BUS_CLK_DISABLE (1<<3)
138 #define BUS_CLK_DIV_MASK 0x3
139
140 #define PMC_CTRL 0x0
141 #define PMC_CTRL_BLINK_ENB (1 << 7)
142
143 #define PMC_DPD_PADS_ORIDE 0x1c
144 #define PMC_DPD_PADS_ORIDE_BLINK_ENB (1 << 20)
145
146 #define PMC_BLINK_TIMER_DATA_ON_SHIFT 0
147 #define PMC_BLINK_TIMER_DATA_ON_MASK 0x7fff
148 #define PMC_BLINK_TIMER_ENB (1 << 15)
149 #define PMC_BLINK_TIMER_DATA_OFF_SHIFT 16
150 #define PMC_BLINK_TIMER_DATA_OFF_MASK 0xffff
151
152 static void __iomem *reg_clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
153 static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
154
155 /*
156 * Some clocks share a register with other clocks. Any clock op that
157 * non-atomically modifies a register used by another clock must lock
158 * clock_register_lock first.
159 */
160 static DEFINE_SPINLOCK(clock_register_lock);
161
162 /*
163 * Some peripheral clocks share an enable bit, so refcount the enable bits
164 * in registers CLK_ENABLE_L, CLK_ENABLE_H, and CLK_ENABLE_U
165 */
166 static int tegra_periph_clk_enable_refcount[3 * 32];
167
168 #define clk_writel(value, reg) \
169 __raw_writel(value, reg_clk_base + (reg))
170 #define clk_readl(reg) \
171 __raw_readl(reg_clk_base + (reg))
172 #define pmc_writel(value, reg) \
173 __raw_writel(value, reg_pmc_base + (reg))
174 #define pmc_readl(reg) \
175 __raw_readl(reg_pmc_base + (reg))
176
clk_measure_input_freq(void)177 static unsigned long clk_measure_input_freq(void)
178 {
179 u32 clock_autodetect;
180 clk_writel(OSC_FREQ_DET_TRIG | 1, OSC_FREQ_DET);
181 do {} while (clk_readl(OSC_FREQ_DET_STATUS) & OSC_FREQ_DET_BUSY);
182 clock_autodetect = clk_readl(OSC_FREQ_DET_STATUS);
183 if (clock_autodetect >= 732 - 3 && clock_autodetect <= 732 + 3) {
184 return 12000000;
185 } else if (clock_autodetect >= 794 - 3 && clock_autodetect <= 794 + 3) {
186 return 13000000;
187 } else if (clock_autodetect >= 1172 - 3 && clock_autodetect <= 1172 + 3) {
188 return 19200000;
189 } else if (clock_autodetect >= 1587 - 3 && clock_autodetect <= 1587 + 3) {
190 return 26000000;
191 } else {
192 pr_err("%s: Unexpected clock autodetect value %d", __func__, clock_autodetect);
193 BUG();
194 return 0;
195 }
196 }
197
clk_div71_get_divider(unsigned long parent_rate,unsigned long rate)198 static int clk_div71_get_divider(unsigned long parent_rate, unsigned long rate)
199 {
200 s64 divider_u71 = parent_rate * 2;
201 divider_u71 += rate - 1;
202 do_div(divider_u71, rate);
203
204 if (divider_u71 - 2 < 0)
205 return 0;
206
207 if (divider_u71 - 2 > 255)
208 return -EINVAL;
209
210 return divider_u71 - 2;
211 }
212
clk_div16_get_divider(unsigned long parent_rate,unsigned long rate)213 static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate)
214 {
215 s64 divider_u16;
216
217 divider_u16 = parent_rate;
218 divider_u16 += rate - 1;
219 do_div(divider_u16, rate);
220
221 if (divider_u16 - 1 < 0)
222 return 0;
223
224 if (divider_u16 - 1 > 255)
225 return -EINVAL;
226
227 return divider_u16 - 1;
228 }
229
230 /* clk_m functions */
tegra2_clk_m_autodetect_rate(struct clk * c)231 static unsigned long tegra2_clk_m_autodetect_rate(struct clk *c)
232 {
233 u32 auto_clock_control = clk_readl(OSC_CTRL) & ~OSC_CTRL_OSC_FREQ_MASK;
234
235 c->rate = clk_measure_input_freq();
236 switch (c->rate) {
237 case 12000000:
238 auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ;
239 break;
240 case 13000000:
241 auto_clock_control |= OSC_CTRL_OSC_FREQ_13MHZ;
242 break;
243 case 19200000:
244 auto_clock_control |= OSC_CTRL_OSC_FREQ_19_2MHZ;
245 break;
246 case 26000000:
247 auto_clock_control |= OSC_CTRL_OSC_FREQ_26MHZ;
248 break;
249 default:
250 pr_err("%s: Unexpected clock rate %ld", __func__, c->rate);
251 BUG();
252 }
253 clk_writel(auto_clock_control, OSC_CTRL);
254 return c->rate;
255 }
256
tegra2_clk_m_init(struct clk * c)257 static void tegra2_clk_m_init(struct clk *c)
258 {
259 pr_debug("%s on clock %s\n", __func__, c->name);
260 tegra2_clk_m_autodetect_rate(c);
261 }
262
tegra2_clk_m_enable(struct clk * c)263 static int tegra2_clk_m_enable(struct clk *c)
264 {
265 pr_debug("%s on clock %s\n", __func__, c->name);
266 return 0;
267 }
268
tegra2_clk_m_disable(struct clk * c)269 static void tegra2_clk_m_disable(struct clk *c)
270 {
271 pr_debug("%s on clock %s\n", __func__, c->name);
272 BUG();
273 }
274
275 static struct clk_ops tegra_clk_m_ops = {
276 .init = tegra2_clk_m_init,
277 .enable = tegra2_clk_m_enable,
278 .disable = tegra2_clk_m_disable,
279 };
280
281 /* super clock functions */
282 /* "super clocks" on tegra have two-stage muxes and a clock skipping
283 * super divider. We will ignore the clock skipping divider, since we
284 * can't lower the voltage when using the clock skip, but we can if we
285 * lower the PLL frequency.
286 */
tegra2_super_clk_init(struct clk * c)287 static void tegra2_super_clk_init(struct clk *c)
288 {
289 u32 val;
290 int source;
291 int shift;
292 const struct clk_mux_sel *sel;
293 val = clk_readl(c->reg + SUPER_CLK_MUX);
294 c->state = ON;
295 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
296 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
297 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
298 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
299 source = (val >> shift) & SUPER_SOURCE_MASK;
300 for (sel = c->inputs; sel->input != NULL; sel++) {
301 if (sel->value == source)
302 break;
303 }
304 BUG_ON(sel->input == NULL);
305 c->parent = sel->input;
306 }
307
tegra2_super_clk_enable(struct clk * c)308 static int tegra2_super_clk_enable(struct clk *c)
309 {
310 clk_writel(0, c->reg + SUPER_CLK_DIVIDER);
311 return 0;
312 }
313
tegra2_super_clk_disable(struct clk * c)314 static void tegra2_super_clk_disable(struct clk *c)
315 {
316 pr_debug("%s on clock %s\n", __func__, c->name);
317
318 /* oops - don't disable the CPU clock! */
319 BUG();
320 }
321
tegra2_super_clk_set_parent(struct clk * c,struct clk * p)322 static int tegra2_super_clk_set_parent(struct clk *c, struct clk *p)
323 {
324 u32 val;
325 const struct clk_mux_sel *sel;
326 int shift;
327
328 val = clk_readl(c->reg + SUPER_CLK_MUX);
329 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
330 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
331 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
332 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
333 for (sel = c->inputs; sel->input != NULL; sel++) {
334 if (sel->input == p) {
335 val &= ~(SUPER_SOURCE_MASK << shift);
336 val |= sel->value << shift;
337
338 if (c->refcnt)
339 clk_enable(p);
340
341 clk_writel(val, c->reg);
342
343 if (c->refcnt && c->parent)
344 clk_disable(c->parent);
345
346 clk_reparent(c, p);
347 return 0;
348 }
349 }
350 return -EINVAL;
351 }
352
353 /*
354 * Super clocks have "clock skippers" instead of dividers. Dividing using
355 * a clock skipper does not allow the voltage to be scaled down, so instead
356 * adjust the rate of the parent clock. This requires that the parent of a
357 * super clock have no other children, otherwise the rate will change
358 * underneath the other children.
359 */
tegra2_super_clk_set_rate(struct clk * c,unsigned long rate)360 static int tegra2_super_clk_set_rate(struct clk *c, unsigned long rate)
361 {
362 return clk_set_rate(c->parent, rate);
363 }
364
365 static struct clk_ops tegra_super_ops = {
366 .init = tegra2_super_clk_init,
367 .enable = tegra2_super_clk_enable,
368 .disable = tegra2_super_clk_disable,
369 .set_parent = tegra2_super_clk_set_parent,
370 .set_rate = tegra2_super_clk_set_rate,
371 };
372
373 /* virtual cpu clock functions */
374 /* some clocks can not be stopped (cpu, memory bus) while the SoC is running.
375 To change the frequency of these clocks, the parent pll may need to be
376 reprogrammed, so the clock must be moved off the pll, the pll reprogrammed,
377 and then the clock moved back to the pll. To hide this sequence, a virtual
378 clock handles it.
379 */
tegra2_cpu_clk_init(struct clk * c)380 static void tegra2_cpu_clk_init(struct clk *c)
381 {
382 }
383
tegra2_cpu_clk_enable(struct clk * c)384 static int tegra2_cpu_clk_enable(struct clk *c)
385 {
386 return 0;
387 }
388
tegra2_cpu_clk_disable(struct clk * c)389 static void tegra2_cpu_clk_disable(struct clk *c)
390 {
391 pr_debug("%s on clock %s\n", __func__, c->name);
392
393 /* oops - don't disable the CPU clock! */
394 BUG();
395 }
396
tegra2_cpu_clk_set_rate(struct clk * c,unsigned long rate)397 static int tegra2_cpu_clk_set_rate(struct clk *c, unsigned long rate)
398 {
399 int ret;
400 /*
401 * Take an extra reference to the main pll so it doesn't turn
402 * off when we move the cpu off of it
403 */
404 clk_enable(c->u.cpu.main);
405
406 ret = clk_set_parent(c->parent, c->u.cpu.backup);
407 if (ret) {
408 pr_err("Failed to switch cpu to clock %s\n", c->u.cpu.backup->name);
409 goto out;
410 }
411
412 if (rate == clk_get_rate(c->u.cpu.backup))
413 goto out;
414
415 ret = clk_set_rate(c->u.cpu.main, rate);
416 if (ret) {
417 pr_err("Failed to change cpu pll to %lu\n", rate);
418 goto out;
419 }
420
421 ret = clk_set_parent(c->parent, c->u.cpu.main);
422 if (ret) {
423 pr_err("Failed to switch cpu to clock %s\n", c->u.cpu.main->name);
424 goto out;
425 }
426
427 out:
428 clk_disable(c->u.cpu.main);
429 return ret;
430 }
431
432 static struct clk_ops tegra_cpu_ops = {
433 .init = tegra2_cpu_clk_init,
434 .enable = tegra2_cpu_clk_enable,
435 .disable = tegra2_cpu_clk_disable,
436 .set_rate = tegra2_cpu_clk_set_rate,
437 };
438
439 /* virtual cop clock functions. Used to acquire the fake 'cop' clock to
440 * reset the COP block (i.e. AVP) */
tegra2_cop_clk_reset(struct clk * c,bool assert)441 static void tegra2_cop_clk_reset(struct clk *c, bool assert)
442 {
443 unsigned long reg = assert ? RST_DEVICES_SET : RST_DEVICES_CLR;
444
445 pr_debug("%s %s\n", __func__, assert ? "assert" : "deassert");
446 clk_writel(1 << 1, reg);
447 }
448
449 static struct clk_ops tegra_cop_ops = {
450 .reset = tegra2_cop_clk_reset,
451 };
452
453 /* bus clock functions */
tegra2_bus_clk_init(struct clk * c)454 static void tegra2_bus_clk_init(struct clk *c)
455 {
456 u32 val = clk_readl(c->reg);
457 c->state = ((val >> c->reg_shift) & BUS_CLK_DISABLE) ? OFF : ON;
458 c->div = ((val >> c->reg_shift) & BUS_CLK_DIV_MASK) + 1;
459 c->mul = 1;
460 }
461
tegra2_bus_clk_enable(struct clk * c)462 static int tegra2_bus_clk_enable(struct clk *c)
463 {
464 u32 val;
465 unsigned long flags;
466
467 spin_lock_irqsave(&clock_register_lock, flags);
468
469 val = clk_readl(c->reg);
470 val &= ~(BUS_CLK_DISABLE << c->reg_shift);
471 clk_writel(val, c->reg);
472
473 spin_unlock_irqrestore(&clock_register_lock, flags);
474
475 return 0;
476 }
477
tegra2_bus_clk_disable(struct clk * c)478 static void tegra2_bus_clk_disable(struct clk *c)
479 {
480 u32 val;
481 unsigned long flags;
482
483 spin_lock_irqsave(&clock_register_lock, flags);
484
485 val = clk_readl(c->reg);
486 val |= BUS_CLK_DISABLE << c->reg_shift;
487 clk_writel(val, c->reg);
488
489 spin_unlock_irqrestore(&clock_register_lock, flags);
490 }
491
tegra2_bus_clk_set_rate(struct clk * c,unsigned long rate)492 static int tegra2_bus_clk_set_rate(struct clk *c, unsigned long rate)
493 {
494 u32 val;
495 unsigned long parent_rate = clk_get_rate(c->parent);
496 unsigned long flags;
497 int ret = -EINVAL;
498 int i;
499
500 spin_lock_irqsave(&clock_register_lock, flags);
501
502 val = clk_readl(c->reg);
503 for (i = 1; i <= 4; i++) {
504 if (rate == parent_rate / i) {
505 val &= ~(BUS_CLK_DIV_MASK << c->reg_shift);
506 val |= (i - 1) << c->reg_shift;
507 clk_writel(val, c->reg);
508 c->div = i;
509 c->mul = 1;
510 ret = 0;
511 break;
512 }
513 }
514
515 spin_unlock_irqrestore(&clock_register_lock, flags);
516
517 return ret;
518 }
519
520 static struct clk_ops tegra_bus_ops = {
521 .init = tegra2_bus_clk_init,
522 .enable = tegra2_bus_clk_enable,
523 .disable = tegra2_bus_clk_disable,
524 .set_rate = tegra2_bus_clk_set_rate,
525 };
526
527 /* Blink output functions */
528
tegra2_blink_clk_init(struct clk * c)529 static void tegra2_blink_clk_init(struct clk *c)
530 {
531 u32 val;
532
533 val = pmc_readl(PMC_CTRL);
534 c->state = (val & PMC_CTRL_BLINK_ENB) ? ON : OFF;
535 c->mul = 1;
536 val = pmc_readl(c->reg);
537
538 if (val & PMC_BLINK_TIMER_ENB) {
539 unsigned int on_off;
540
541 on_off = (val >> PMC_BLINK_TIMER_DATA_ON_SHIFT) &
542 PMC_BLINK_TIMER_DATA_ON_MASK;
543 val >>= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
544 val &= PMC_BLINK_TIMER_DATA_OFF_MASK;
545 on_off += val;
546 /* each tick in the blink timer is 4 32KHz clocks */
547 c->div = on_off * 4;
548 } else {
549 c->div = 1;
550 }
551 }
552
tegra2_blink_clk_enable(struct clk * c)553 static int tegra2_blink_clk_enable(struct clk *c)
554 {
555 u32 val;
556
557 val = pmc_readl(PMC_DPD_PADS_ORIDE);
558 pmc_writel(val | PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
559
560 val = pmc_readl(PMC_CTRL);
561 pmc_writel(val | PMC_CTRL_BLINK_ENB, PMC_CTRL);
562
563 return 0;
564 }
565
tegra2_blink_clk_disable(struct clk * c)566 static void tegra2_blink_clk_disable(struct clk *c)
567 {
568 u32 val;
569
570 val = pmc_readl(PMC_CTRL);
571 pmc_writel(val & ~PMC_CTRL_BLINK_ENB, PMC_CTRL);
572
573 val = pmc_readl(PMC_DPD_PADS_ORIDE);
574 pmc_writel(val & ~PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
575 }
576
tegra2_blink_clk_set_rate(struct clk * c,unsigned long rate)577 static int tegra2_blink_clk_set_rate(struct clk *c, unsigned long rate)
578 {
579 unsigned long parent_rate = clk_get_rate(c->parent);
580 if (rate >= parent_rate) {
581 c->div = 1;
582 pmc_writel(0, c->reg);
583 } else {
584 unsigned int on_off;
585 u32 val;
586
587 on_off = DIV_ROUND_UP(parent_rate / 8, rate);
588 c->div = on_off * 8;
589
590 val = (on_off & PMC_BLINK_TIMER_DATA_ON_MASK) <<
591 PMC_BLINK_TIMER_DATA_ON_SHIFT;
592 on_off &= PMC_BLINK_TIMER_DATA_OFF_MASK;
593 on_off <<= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
594 val |= on_off;
595 val |= PMC_BLINK_TIMER_ENB;
596 pmc_writel(val, c->reg);
597 }
598
599 return 0;
600 }
601
602 static struct clk_ops tegra_blink_clk_ops = {
603 .init = &tegra2_blink_clk_init,
604 .enable = &tegra2_blink_clk_enable,
605 .disable = &tegra2_blink_clk_disable,
606 .set_rate = &tegra2_blink_clk_set_rate,
607 };
608
609 /* PLL Functions */
tegra2_pll_clk_wait_for_lock(struct clk * c)610 static int tegra2_pll_clk_wait_for_lock(struct clk *c)
611 {
612 udelay(c->u.pll.lock_delay);
613
614 return 0;
615 }
616
tegra2_pll_clk_init(struct clk * c)617 static void tegra2_pll_clk_init(struct clk *c)
618 {
619 u32 val = clk_readl(c->reg + PLL_BASE);
620
621 c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
622
623 if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) {
624 pr_warning("Clock %s has unknown fixed frequency\n", c->name);
625 c->mul = 1;
626 c->div = 1;
627 } else if (val & PLL_BASE_BYPASS) {
628 c->mul = 1;
629 c->div = 1;
630 } else {
631 c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
632 c->div = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
633 if (c->flags & PLLU)
634 c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2;
635 else
636 c->div *= (val & PLL_BASE_DIVP_MASK) ? 2 : 1;
637 }
638 }
639
tegra2_pll_clk_enable(struct clk * c)640 static int tegra2_pll_clk_enable(struct clk *c)
641 {
642 u32 val;
643 pr_debug("%s on clock %s\n", __func__, c->name);
644
645 val = clk_readl(c->reg + PLL_BASE);
646 val &= ~PLL_BASE_BYPASS;
647 val |= PLL_BASE_ENABLE;
648 clk_writel(val, c->reg + PLL_BASE);
649
650 tegra2_pll_clk_wait_for_lock(c);
651
652 return 0;
653 }
654
tegra2_pll_clk_disable(struct clk * c)655 static void tegra2_pll_clk_disable(struct clk *c)
656 {
657 u32 val;
658 pr_debug("%s on clock %s\n", __func__, c->name);
659
660 val = clk_readl(c->reg);
661 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
662 clk_writel(val, c->reg);
663 }
664
tegra2_pll_clk_set_rate(struct clk * c,unsigned long rate)665 static int tegra2_pll_clk_set_rate(struct clk *c, unsigned long rate)
666 {
667 u32 val;
668 unsigned long input_rate;
669 const struct clk_pll_freq_table *sel;
670
671 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
672
673 input_rate = clk_get_rate(c->parent);
674 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
675 if (sel->input_rate == input_rate && sel->output_rate == rate) {
676 c->mul = sel->n;
677 c->div = sel->m * sel->p;
678
679 val = clk_readl(c->reg + PLL_BASE);
680 if (c->flags & PLL_FIXED)
681 val |= PLL_BASE_OVERRIDE;
682 val &= ~(PLL_BASE_DIVP_MASK | PLL_BASE_DIVN_MASK |
683 PLL_BASE_DIVM_MASK);
684 val |= (sel->m << PLL_BASE_DIVM_SHIFT) |
685 (sel->n << PLL_BASE_DIVN_SHIFT);
686 BUG_ON(sel->p < 1 || sel->p > 2);
687 if (c->flags & PLLU) {
688 if (sel->p == 1)
689 val |= PLLU_BASE_POST_DIV;
690 } else {
691 if (sel->p == 2)
692 val |= 1 << PLL_BASE_DIVP_SHIFT;
693 }
694 clk_writel(val, c->reg + PLL_BASE);
695
696 if (c->flags & PLL_HAS_CPCON) {
697 val = clk_readl(c->reg + PLL_MISC(c));
698 val &= ~PLL_MISC_CPCON_MASK;
699 val |= sel->cpcon << PLL_MISC_CPCON_SHIFT;
700 clk_writel(val, c->reg + PLL_MISC(c));
701 }
702
703 if (c->state == ON)
704 tegra2_pll_clk_enable(c);
705
706 return 0;
707 }
708 }
709 return -EINVAL;
710 }
711
712 static struct clk_ops tegra_pll_ops = {
713 .init = tegra2_pll_clk_init,
714 .enable = tegra2_pll_clk_enable,
715 .disable = tegra2_pll_clk_disable,
716 .set_rate = tegra2_pll_clk_set_rate,
717 };
718
tegra2_pllx_clk_init(struct clk * c)719 static void tegra2_pllx_clk_init(struct clk *c)
720 {
721 tegra2_pll_clk_init(c);
722
723 if (tegra_sku_id == 7)
724 c->max_rate = 750000000;
725 }
726
727 static struct clk_ops tegra_pllx_ops = {
728 .init = tegra2_pllx_clk_init,
729 .enable = tegra2_pll_clk_enable,
730 .disable = tegra2_pll_clk_disable,
731 .set_rate = tegra2_pll_clk_set_rate,
732 };
733
tegra2_plle_clk_enable(struct clk * c)734 static int tegra2_plle_clk_enable(struct clk *c)
735 {
736 u32 val;
737
738 pr_debug("%s on clock %s\n", __func__, c->name);
739
740 mdelay(1);
741
742 val = clk_readl(c->reg + PLL_BASE);
743 if (!(val & PLLE_MISC_READY))
744 return -EBUSY;
745
746 val = clk_readl(c->reg + PLL_BASE);
747 val |= PLL_BASE_ENABLE | PLL_BASE_BYPASS;
748 clk_writel(val, c->reg + PLL_BASE);
749
750 return 0;
751 }
752
753 static struct clk_ops tegra_plle_ops = {
754 .init = tegra2_pll_clk_init,
755 .enable = tegra2_plle_clk_enable,
756 .set_rate = tegra2_pll_clk_set_rate,
757 };
758
759 /* Clock divider ops */
tegra2_pll_div_clk_init(struct clk * c)760 static void tegra2_pll_div_clk_init(struct clk *c)
761 {
762 u32 val = clk_readl(c->reg);
763 u32 divu71;
764 val >>= c->reg_shift;
765 c->state = (val & PLL_OUT_CLKEN) ? ON : OFF;
766 if (!(val & PLL_OUT_RESET_DISABLE))
767 c->state = OFF;
768
769 if (c->flags & DIV_U71) {
770 divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT;
771 c->div = (divu71 + 2);
772 c->mul = 2;
773 } else if (c->flags & DIV_2) {
774 c->div = 2;
775 c->mul = 1;
776 } else {
777 c->div = 1;
778 c->mul = 1;
779 }
780 }
781
tegra2_pll_div_clk_enable(struct clk * c)782 static int tegra2_pll_div_clk_enable(struct clk *c)
783 {
784 u32 val;
785 u32 new_val;
786 unsigned long flags;
787
788 pr_debug("%s: %s\n", __func__, c->name);
789 if (c->flags & DIV_U71) {
790 spin_lock_irqsave(&clock_register_lock, flags);
791 val = clk_readl(c->reg);
792 new_val = val >> c->reg_shift;
793 new_val &= 0xFFFF;
794
795 new_val |= PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE;
796
797 val &= ~(0xFFFF << c->reg_shift);
798 val |= new_val << c->reg_shift;
799 clk_writel(val, c->reg);
800 spin_unlock_irqrestore(&clock_register_lock, flags);
801 return 0;
802 } else if (c->flags & DIV_2) {
803 BUG_ON(!(c->flags & PLLD));
804 spin_lock_irqsave(&clock_register_lock, flags);
805 val = clk_readl(c->reg);
806 val &= ~PLLD_MISC_DIV_RST;
807 clk_writel(val, c->reg);
808 spin_unlock_irqrestore(&clock_register_lock, flags);
809 return 0;
810 }
811 return -EINVAL;
812 }
813
tegra2_pll_div_clk_disable(struct clk * c)814 static void tegra2_pll_div_clk_disable(struct clk *c)
815 {
816 u32 val;
817 u32 new_val;
818 unsigned long flags;
819
820 pr_debug("%s: %s\n", __func__, c->name);
821 if (c->flags & DIV_U71) {
822 spin_lock_irqsave(&clock_register_lock, flags);
823 val = clk_readl(c->reg);
824 new_val = val >> c->reg_shift;
825 new_val &= 0xFFFF;
826
827 new_val &= ~(PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE);
828
829 val &= ~(0xFFFF << c->reg_shift);
830 val |= new_val << c->reg_shift;
831 clk_writel(val, c->reg);
832 spin_unlock_irqrestore(&clock_register_lock, flags);
833 } else if (c->flags & DIV_2) {
834 BUG_ON(!(c->flags & PLLD));
835 spin_lock_irqsave(&clock_register_lock, flags);
836 val = clk_readl(c->reg);
837 val |= PLLD_MISC_DIV_RST;
838 clk_writel(val, c->reg);
839 spin_unlock_irqrestore(&clock_register_lock, flags);
840 }
841 }
842
tegra2_pll_div_clk_set_rate(struct clk * c,unsigned long rate)843 static int tegra2_pll_div_clk_set_rate(struct clk *c, unsigned long rate)
844 {
845 u32 val;
846 u32 new_val;
847 int divider_u71;
848 unsigned long parent_rate = clk_get_rate(c->parent);
849 unsigned long flags;
850
851 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
852 if (c->flags & DIV_U71) {
853 divider_u71 = clk_div71_get_divider(parent_rate, rate);
854 if (divider_u71 >= 0) {
855 spin_lock_irqsave(&clock_register_lock, flags);
856 val = clk_readl(c->reg);
857 new_val = val >> c->reg_shift;
858 new_val &= 0xFFFF;
859 if (c->flags & DIV_U71_FIXED)
860 new_val |= PLL_OUT_OVERRIDE;
861 new_val &= ~PLL_OUT_RATIO_MASK;
862 new_val |= divider_u71 << PLL_OUT_RATIO_SHIFT;
863
864 val &= ~(0xFFFF << c->reg_shift);
865 val |= new_val << c->reg_shift;
866 clk_writel(val, c->reg);
867 c->div = divider_u71 + 2;
868 c->mul = 2;
869 spin_unlock_irqrestore(&clock_register_lock, flags);
870 return 0;
871 }
872 } else if (c->flags & DIV_2) {
873 if (parent_rate == rate * 2)
874 return 0;
875 }
876 return -EINVAL;
877 }
878
tegra2_pll_div_clk_round_rate(struct clk * c,unsigned long rate)879 static long tegra2_pll_div_clk_round_rate(struct clk *c, unsigned long rate)
880 {
881 int divider;
882 unsigned long parent_rate = clk_get_rate(c->parent);
883 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
884
885 if (c->flags & DIV_U71) {
886 divider = clk_div71_get_divider(parent_rate, rate);
887 if (divider < 0)
888 return divider;
889 return DIV_ROUND_UP(parent_rate * 2, divider + 2);
890 } else if (c->flags & DIV_2) {
891 return DIV_ROUND_UP(parent_rate, 2);
892 }
893 return -EINVAL;
894 }
895
896 static struct clk_ops tegra_pll_div_ops = {
897 .init = tegra2_pll_div_clk_init,
898 .enable = tegra2_pll_div_clk_enable,
899 .disable = tegra2_pll_div_clk_disable,
900 .set_rate = tegra2_pll_div_clk_set_rate,
901 .round_rate = tegra2_pll_div_clk_round_rate,
902 };
903
904 /* Periph clk ops */
905
tegra2_periph_clk_init(struct clk * c)906 static void tegra2_periph_clk_init(struct clk *c)
907 {
908 u32 val = clk_readl(c->reg);
909 const struct clk_mux_sel *mux = NULL;
910 const struct clk_mux_sel *sel;
911 if (c->flags & MUX) {
912 for (sel = c->inputs; sel->input != NULL; sel++) {
913 if (val >> PERIPH_CLK_SOURCE_SHIFT == sel->value)
914 mux = sel;
915 }
916 BUG_ON(!mux);
917
918 c->parent = mux->input;
919 } else {
920 c->parent = c->inputs[0].input;
921 }
922
923 if (c->flags & DIV_U71) {
924 u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK;
925 c->div = divu71 + 2;
926 c->mul = 2;
927 } else if (c->flags & DIV_U16) {
928 u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK;
929 c->div = divu16 + 1;
930 c->mul = 1;
931 } else {
932 c->div = 1;
933 c->mul = 1;
934 }
935
936 c->state = ON;
937
938 if (!c->u.periph.clk_num)
939 return;
940
941 if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
942 PERIPH_CLK_TO_ENB_BIT(c)))
943 c->state = OFF;
944
945 if (!(c->flags & PERIPH_NO_RESET))
946 if (clk_readl(RST_DEVICES + PERIPH_CLK_TO_ENB_REG(c)) &
947 PERIPH_CLK_TO_ENB_BIT(c))
948 c->state = OFF;
949 }
950
tegra2_periph_clk_enable(struct clk * c)951 static int tegra2_periph_clk_enable(struct clk *c)
952 {
953 u32 val;
954 unsigned long flags;
955 int refcount;
956 pr_debug("%s on clock %s\n", __func__, c->name);
957
958 if (!c->u.periph.clk_num)
959 return 0;
960
961 spin_lock_irqsave(&clock_register_lock, flags);
962
963 refcount = tegra_periph_clk_enable_refcount[c->u.periph.clk_num]++;
964
965 if (refcount > 1)
966 goto out;
967
968 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
969 CLK_OUT_ENB_SET + PERIPH_CLK_TO_ENB_SET_REG(c));
970 if (!(c->flags & PERIPH_NO_RESET) && !(c->flags & PERIPH_MANUAL_RESET))
971 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
972 RST_DEVICES_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
973 if (c->flags & PERIPH_EMC_ENB) {
974 /* The EMC peripheral clock has 2 extra enable bits */
975 /* FIXME: Do they need to be disabled? */
976 val = clk_readl(c->reg);
977 val |= 0x3 << 24;
978 clk_writel(val, c->reg);
979 }
980
981 out:
982 spin_unlock_irqrestore(&clock_register_lock, flags);
983
984 return 0;
985 }
986
tegra2_periph_clk_disable(struct clk * c)987 static void tegra2_periph_clk_disable(struct clk *c)
988 {
989 unsigned long flags;
990
991 pr_debug("%s on clock %s\n", __func__, c->name);
992
993 if (!c->u.periph.clk_num)
994 return;
995
996 spin_lock_irqsave(&clock_register_lock, flags);
997
998 if (c->refcnt)
999 tegra_periph_clk_enable_refcount[c->u.periph.clk_num]--;
1000
1001 if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] == 0)
1002 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1003 CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
1004
1005 spin_unlock_irqrestore(&clock_register_lock, flags);
1006 }
1007
tegra2_periph_clk_reset(struct clk * c,bool assert)1008 static void tegra2_periph_clk_reset(struct clk *c, bool assert)
1009 {
1010 unsigned long base = assert ? RST_DEVICES_SET : RST_DEVICES_CLR;
1011
1012 pr_debug("%s %s on clock %s\n", __func__,
1013 assert ? "assert" : "deassert", c->name);
1014
1015 BUG_ON(!c->u.periph.clk_num);
1016
1017 if (!(c->flags & PERIPH_NO_RESET))
1018 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1019 base + PERIPH_CLK_TO_ENB_SET_REG(c));
1020 }
1021
tegra2_periph_clk_set_parent(struct clk * c,struct clk * p)1022 static int tegra2_periph_clk_set_parent(struct clk *c, struct clk *p)
1023 {
1024 u32 val;
1025 const struct clk_mux_sel *sel;
1026 pr_debug("%s: %s %s\n", __func__, c->name, p->name);
1027 for (sel = c->inputs; sel->input != NULL; sel++) {
1028 if (sel->input == p) {
1029 val = clk_readl(c->reg);
1030 val &= ~PERIPH_CLK_SOURCE_MASK;
1031 val |= (sel->value) << PERIPH_CLK_SOURCE_SHIFT;
1032
1033 if (c->refcnt)
1034 clk_enable(p);
1035
1036 clk_writel(val, c->reg);
1037
1038 if (c->refcnt && c->parent)
1039 clk_disable(c->parent);
1040
1041 clk_reparent(c, p);
1042 return 0;
1043 }
1044 }
1045
1046 return -EINVAL;
1047 }
1048
tegra2_periph_clk_set_rate(struct clk * c,unsigned long rate)1049 static int tegra2_periph_clk_set_rate(struct clk *c, unsigned long rate)
1050 {
1051 u32 val;
1052 int divider;
1053 unsigned long parent_rate = clk_get_rate(c->parent);
1054
1055 if (c->flags & DIV_U71) {
1056 divider = clk_div71_get_divider(parent_rate, rate);
1057 if (divider >= 0) {
1058 val = clk_readl(c->reg);
1059 val &= ~PERIPH_CLK_SOURCE_DIVU71_MASK;
1060 val |= divider;
1061 clk_writel(val, c->reg);
1062 c->div = divider + 2;
1063 c->mul = 2;
1064 return 0;
1065 }
1066 } else if (c->flags & DIV_U16) {
1067 divider = clk_div16_get_divider(parent_rate, rate);
1068 if (divider >= 0) {
1069 val = clk_readl(c->reg);
1070 val &= ~PERIPH_CLK_SOURCE_DIVU16_MASK;
1071 val |= divider;
1072 clk_writel(val, c->reg);
1073 c->div = divider + 1;
1074 c->mul = 1;
1075 return 0;
1076 }
1077 } else if (parent_rate <= rate) {
1078 c->div = 1;
1079 c->mul = 1;
1080 return 0;
1081 }
1082 return -EINVAL;
1083 }
1084
tegra2_periph_clk_round_rate(struct clk * c,unsigned long rate)1085 static long tegra2_periph_clk_round_rate(struct clk *c,
1086 unsigned long rate)
1087 {
1088 int divider;
1089 unsigned long parent_rate = clk_get_rate(c->parent);
1090 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
1091
1092 if (c->flags & DIV_U71) {
1093 divider = clk_div71_get_divider(parent_rate, rate);
1094 if (divider < 0)
1095 return divider;
1096
1097 return DIV_ROUND_UP(parent_rate * 2, divider + 2);
1098 } else if (c->flags & DIV_U16) {
1099 divider = clk_div16_get_divider(parent_rate, rate);
1100 if (divider < 0)
1101 return divider;
1102 return DIV_ROUND_UP(parent_rate, divider + 1);
1103 }
1104 return -EINVAL;
1105 }
1106
1107 static struct clk_ops tegra_periph_clk_ops = {
1108 .init = &tegra2_periph_clk_init,
1109 .enable = &tegra2_periph_clk_enable,
1110 .disable = &tegra2_periph_clk_disable,
1111 .set_parent = &tegra2_periph_clk_set_parent,
1112 .set_rate = &tegra2_periph_clk_set_rate,
1113 .round_rate = &tegra2_periph_clk_round_rate,
1114 .reset = &tegra2_periph_clk_reset,
1115 };
1116
1117 /* The SDMMC controllers have extra bits in the clock source register that
1118 * adjust the delay between the clock and data to compenstate for delays
1119 * on the PCB. */
tegra2_sdmmc_tap_delay(struct clk * c,int delay)1120 void tegra2_sdmmc_tap_delay(struct clk *c, int delay)
1121 {
1122 u32 reg;
1123 unsigned long flags;
1124
1125 spin_lock_irqsave(&c->spinlock, flags);
1126
1127 delay = clamp(delay, 0, 15);
1128 reg = clk_readl(c->reg);
1129 reg &= ~SDMMC_CLK_INT_FB_DLY_MASK;
1130 reg |= SDMMC_CLK_INT_FB_SEL;
1131 reg |= delay << SDMMC_CLK_INT_FB_DLY_SHIFT;
1132 clk_writel(reg, c->reg);
1133
1134 spin_unlock_irqrestore(&c->spinlock, flags);
1135 }
1136
1137 /* External memory controller clock ops */
tegra2_emc_clk_init(struct clk * c)1138 static void tegra2_emc_clk_init(struct clk *c)
1139 {
1140 tegra2_periph_clk_init(c);
1141 c->max_rate = clk_get_rate_locked(c);
1142 }
1143
tegra2_emc_clk_round_rate(struct clk * c,unsigned long rate)1144 static long tegra2_emc_clk_round_rate(struct clk *c, unsigned long rate)
1145 {
1146 long emc_rate;
1147 long clk_rate;
1148
1149 /*
1150 * The slowest entry in the EMC clock table that is at least as
1151 * fast as rate.
1152 */
1153 emc_rate = tegra_emc_round_rate(rate);
1154 if (emc_rate < 0)
1155 return c->max_rate;
1156
1157 /*
1158 * The fastest rate the PLL will generate that is at most the
1159 * requested rate.
1160 */
1161 clk_rate = tegra2_periph_clk_round_rate(c, emc_rate);
1162
1163 /*
1164 * If this fails, and emc_rate > clk_rate, it's because the maximum
1165 * rate in the EMC tables is larger than the maximum rate of the EMC
1166 * clock. The EMC clock's max rate is the rate it was running when the
1167 * kernel booted. Such a mismatch is probably due to using the wrong
1168 * BCT, i.e. using a Tegra20 BCT with an EMC table written for Tegra25.
1169 */
1170 WARN_ONCE(emc_rate != clk_rate,
1171 "emc_rate %ld != clk_rate %ld",
1172 emc_rate, clk_rate);
1173
1174 return emc_rate;
1175 }
1176
tegra2_emc_clk_set_rate(struct clk * c,unsigned long rate)1177 static int tegra2_emc_clk_set_rate(struct clk *c, unsigned long rate)
1178 {
1179 int ret;
1180 /*
1181 * The Tegra2 memory controller has an interlock with the clock
1182 * block that allows memory shadowed registers to be updated,
1183 * and then transfer them to the main registers at the same
1184 * time as the clock update without glitches.
1185 */
1186 ret = tegra_emc_set_rate(rate);
1187 if (ret < 0)
1188 return ret;
1189
1190 ret = tegra2_periph_clk_set_rate(c, rate);
1191 udelay(1);
1192
1193 return ret;
1194 }
1195
1196 static struct clk_ops tegra_emc_clk_ops = {
1197 .init = &tegra2_emc_clk_init,
1198 .enable = &tegra2_periph_clk_enable,
1199 .disable = &tegra2_periph_clk_disable,
1200 .set_parent = &tegra2_periph_clk_set_parent,
1201 .set_rate = &tegra2_emc_clk_set_rate,
1202 .round_rate = &tegra2_emc_clk_round_rate,
1203 .reset = &tegra2_periph_clk_reset,
1204 };
1205
1206 /* Clock doubler ops */
tegra2_clk_double_init(struct clk * c)1207 static void tegra2_clk_double_init(struct clk *c)
1208 {
1209 c->mul = 2;
1210 c->div = 1;
1211 c->state = ON;
1212
1213 if (!c->u.periph.clk_num)
1214 return;
1215
1216 if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
1217 PERIPH_CLK_TO_ENB_BIT(c)))
1218 c->state = OFF;
1219 };
1220
tegra2_clk_double_set_rate(struct clk * c,unsigned long rate)1221 static int tegra2_clk_double_set_rate(struct clk *c, unsigned long rate)
1222 {
1223 if (rate != 2 * clk_get_rate(c->parent))
1224 return -EINVAL;
1225 c->mul = 2;
1226 c->div = 1;
1227 return 0;
1228 }
1229
1230 static struct clk_ops tegra_clk_double_ops = {
1231 .init = &tegra2_clk_double_init,
1232 .enable = &tegra2_periph_clk_enable,
1233 .disable = &tegra2_periph_clk_disable,
1234 .set_rate = &tegra2_clk_double_set_rate,
1235 };
1236
1237 /* Audio sync clock ops */
tegra2_audio_sync_clk_init(struct clk * c)1238 static void tegra2_audio_sync_clk_init(struct clk *c)
1239 {
1240 int source;
1241 const struct clk_mux_sel *sel;
1242 u32 val = clk_readl(c->reg);
1243 c->state = (val & (1<<4)) ? OFF : ON;
1244 source = val & 0xf;
1245 for (sel = c->inputs; sel->input != NULL; sel++)
1246 if (sel->value == source)
1247 break;
1248 BUG_ON(sel->input == NULL);
1249 c->parent = sel->input;
1250 }
1251
tegra2_audio_sync_clk_enable(struct clk * c)1252 static int tegra2_audio_sync_clk_enable(struct clk *c)
1253 {
1254 clk_writel(0, c->reg);
1255 return 0;
1256 }
1257
tegra2_audio_sync_clk_disable(struct clk * c)1258 static void tegra2_audio_sync_clk_disable(struct clk *c)
1259 {
1260 clk_writel(1, c->reg);
1261 }
1262
tegra2_audio_sync_clk_set_parent(struct clk * c,struct clk * p)1263 static int tegra2_audio_sync_clk_set_parent(struct clk *c, struct clk *p)
1264 {
1265 u32 val;
1266 const struct clk_mux_sel *sel;
1267 for (sel = c->inputs; sel->input != NULL; sel++) {
1268 if (sel->input == p) {
1269 val = clk_readl(c->reg);
1270 val &= ~0xf;
1271 val |= sel->value;
1272
1273 if (c->refcnt)
1274 clk_enable(p);
1275
1276 clk_writel(val, c->reg);
1277
1278 if (c->refcnt && c->parent)
1279 clk_disable(c->parent);
1280
1281 clk_reparent(c, p);
1282 return 0;
1283 }
1284 }
1285
1286 return -EINVAL;
1287 }
1288
1289 static struct clk_ops tegra_audio_sync_clk_ops = {
1290 .init = tegra2_audio_sync_clk_init,
1291 .enable = tegra2_audio_sync_clk_enable,
1292 .disable = tegra2_audio_sync_clk_disable,
1293 .set_parent = tegra2_audio_sync_clk_set_parent,
1294 };
1295
1296 /* cdev1 and cdev2 (dap_mclk1 and dap_mclk2) ops */
1297
tegra2_cdev_clk_init(struct clk * c)1298 static void tegra2_cdev_clk_init(struct clk *c)
1299 {
1300 /* We could un-tristate the cdev1 or cdev2 pingroup here; this is
1301 * currently done in the pinmux code. */
1302 c->state = ON;
1303
1304 BUG_ON(!c->u.periph.clk_num);
1305
1306 if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
1307 PERIPH_CLK_TO_ENB_BIT(c)))
1308 c->state = OFF;
1309 }
1310
tegra2_cdev_clk_enable(struct clk * c)1311 static int tegra2_cdev_clk_enable(struct clk *c)
1312 {
1313 BUG_ON(!c->u.periph.clk_num);
1314
1315 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1316 CLK_OUT_ENB_SET + PERIPH_CLK_TO_ENB_SET_REG(c));
1317 return 0;
1318 }
1319
tegra2_cdev_clk_disable(struct clk * c)1320 static void tegra2_cdev_clk_disable(struct clk *c)
1321 {
1322 BUG_ON(!c->u.periph.clk_num);
1323
1324 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1325 CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
1326 }
1327
1328 static struct clk_ops tegra_cdev_clk_ops = {
1329 .init = &tegra2_cdev_clk_init,
1330 .enable = &tegra2_cdev_clk_enable,
1331 .disable = &tegra2_cdev_clk_disable,
1332 };
1333
1334 /* shared bus ops */
1335 /*
1336 * Some clocks may have multiple downstream users that need to request a
1337 * higher clock rate. Shared bus clocks provide a unique shared_bus_user
1338 * clock to each user. The frequency of the bus is set to the highest
1339 * enabled shared_bus_user clock, with a minimum value set by the
1340 * shared bus.
1341 */
tegra_clk_shared_bus_update(struct clk * bus)1342 static int tegra_clk_shared_bus_update(struct clk *bus)
1343 {
1344 struct clk *c;
1345 unsigned long rate = bus->min_rate;
1346
1347 list_for_each_entry(c, &bus->shared_bus_list, u.shared_bus_user.node)
1348 if (c->u.shared_bus_user.enabled)
1349 rate = max(c->u.shared_bus_user.rate, rate);
1350
1351 if (rate == clk_get_rate_locked(bus))
1352 return 0;
1353
1354 return clk_set_rate_locked(bus, rate);
1355 };
1356
tegra_clk_shared_bus_init(struct clk * c)1357 static void tegra_clk_shared_bus_init(struct clk *c)
1358 {
1359 unsigned long flags;
1360
1361 c->max_rate = c->parent->max_rate;
1362 c->u.shared_bus_user.rate = c->parent->max_rate;
1363 c->state = OFF;
1364 c->set = true;
1365
1366 spin_lock_irqsave(&c->parent->spinlock, flags);
1367
1368 list_add_tail(&c->u.shared_bus_user.node,
1369 &c->parent->shared_bus_list);
1370
1371 spin_unlock_irqrestore(&c->parent->spinlock, flags);
1372 }
1373
tegra_clk_shared_bus_set_rate(struct clk * c,unsigned long rate)1374 static int tegra_clk_shared_bus_set_rate(struct clk *c, unsigned long rate)
1375 {
1376 unsigned long flags;
1377 int ret;
1378 long new_rate = rate;
1379
1380 new_rate = clk_round_rate(c->parent, new_rate);
1381 if (new_rate < 0)
1382 return new_rate;
1383
1384 spin_lock_irqsave(&c->parent->spinlock, flags);
1385
1386 c->u.shared_bus_user.rate = new_rate;
1387 ret = tegra_clk_shared_bus_update(c->parent);
1388
1389 spin_unlock_irqrestore(&c->parent->spinlock, flags);
1390
1391 return ret;
1392 }
1393
tegra_clk_shared_bus_round_rate(struct clk * c,unsigned long rate)1394 static long tegra_clk_shared_bus_round_rate(struct clk *c, unsigned long rate)
1395 {
1396 return clk_round_rate(c->parent, rate);
1397 }
1398
tegra_clk_shared_bus_enable(struct clk * c)1399 static int tegra_clk_shared_bus_enable(struct clk *c)
1400 {
1401 unsigned long flags;
1402 int ret;
1403
1404 spin_lock_irqsave(&c->parent->spinlock, flags);
1405
1406 c->u.shared_bus_user.enabled = true;
1407 ret = tegra_clk_shared_bus_update(c->parent);
1408
1409 spin_unlock_irqrestore(&c->parent->spinlock, flags);
1410
1411 return ret;
1412 }
1413
tegra_clk_shared_bus_disable(struct clk * c)1414 static void tegra_clk_shared_bus_disable(struct clk *c)
1415 {
1416 unsigned long flags;
1417 int ret;
1418
1419 spin_lock_irqsave(&c->parent->spinlock, flags);
1420
1421 c->u.shared_bus_user.enabled = false;
1422 ret = tegra_clk_shared_bus_update(c->parent);
1423 WARN_ON_ONCE(ret);
1424
1425 spin_unlock_irqrestore(&c->parent->spinlock, flags);
1426 }
1427
1428 static struct clk_ops tegra_clk_shared_bus_ops = {
1429 .init = tegra_clk_shared_bus_init,
1430 .enable = tegra_clk_shared_bus_enable,
1431 .disable = tegra_clk_shared_bus_disable,
1432 .set_rate = tegra_clk_shared_bus_set_rate,
1433 .round_rate = tegra_clk_shared_bus_round_rate,
1434 };
1435
1436
1437 /* Clock definitions */
1438 static struct clk tegra_clk_32k = {
1439 .name = "clk_32k",
1440 .rate = 32768,
1441 .ops = NULL,
1442 .max_rate = 32768,
1443 };
1444
1445 static struct clk_pll_freq_table tegra_pll_s_freq_table[] = {
1446 {32768, 12000000, 366, 1, 1, 0},
1447 {32768, 13000000, 397, 1, 1, 0},
1448 {32768, 19200000, 586, 1, 1, 0},
1449 {32768, 26000000, 793, 1, 1, 0},
1450 {0, 0, 0, 0, 0, 0},
1451 };
1452
1453 static struct clk tegra_pll_s = {
1454 .name = "pll_s",
1455 .flags = PLL_ALT_MISC_REG,
1456 .ops = &tegra_pll_ops,
1457 .parent = &tegra_clk_32k,
1458 .max_rate = 26000000,
1459 .reg = 0xf0,
1460 .u.pll = {
1461 .input_min = 32768,
1462 .input_max = 32768,
1463 .cf_min = 0, /* FIXME */
1464 .cf_max = 0, /* FIXME */
1465 .vco_min = 12000000,
1466 .vco_max = 26000000,
1467 .freq_table = tegra_pll_s_freq_table,
1468 .lock_delay = 300,
1469 },
1470 };
1471
1472 static struct clk_mux_sel tegra_clk_m_sel[] = {
1473 { .input = &tegra_clk_32k, .value = 0},
1474 { .input = &tegra_pll_s, .value = 1},
1475 { NULL , 0},
1476 };
1477
1478 static struct clk tegra_clk_m = {
1479 .name = "clk_m",
1480 .flags = ENABLE_ON_INIT,
1481 .ops = &tegra_clk_m_ops,
1482 .inputs = tegra_clk_m_sel,
1483 .reg = 0x1fc,
1484 .reg_shift = 28,
1485 .max_rate = 26000000,
1486 };
1487
1488 static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
1489 { 0, 0, 0, 0, 0, 0 },
1490 };
1491
1492 static struct clk tegra_pll_c = {
1493 .name = "pll_c",
1494 .flags = PLL_HAS_CPCON,
1495 .ops = &tegra_pll_ops,
1496 .reg = 0x80,
1497 .parent = &tegra_clk_m,
1498 .max_rate = 600000000,
1499 .u.pll = {
1500 .input_min = 2000000,
1501 .input_max = 31000000,
1502 .cf_min = 1000000,
1503 .cf_max = 6000000,
1504 .vco_min = 20000000,
1505 .vco_max = 1400000000,
1506 .freq_table = tegra_pll_c_freq_table,
1507 .lock_delay = 300,
1508 },
1509 };
1510
1511 static struct clk tegra_pll_c_out1 = {
1512 .name = "pll_c_out1",
1513 .ops = &tegra_pll_div_ops,
1514 .flags = DIV_U71,
1515 .parent = &tegra_pll_c,
1516 .reg = 0x84,
1517 .reg_shift = 0,
1518 .max_rate = 600000000,
1519 };
1520
1521 static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
1522 { 12000000, 666000000, 666, 12, 1, 8},
1523 { 13000000, 666000000, 666, 13, 1, 8},
1524 { 19200000, 666000000, 555, 16, 1, 8},
1525 { 26000000, 666000000, 666, 26, 1, 8},
1526 { 12000000, 600000000, 600, 12, 1, 8},
1527 { 13000000, 600000000, 600, 13, 1, 8},
1528 { 19200000, 600000000, 375, 12, 1, 6},
1529 { 26000000, 600000000, 600, 26, 1, 8},
1530 { 0, 0, 0, 0, 0, 0 },
1531 };
1532
1533 static struct clk tegra_pll_m = {
1534 .name = "pll_m",
1535 .flags = PLL_HAS_CPCON,
1536 .ops = &tegra_pll_ops,
1537 .reg = 0x90,
1538 .parent = &tegra_clk_m,
1539 .max_rate = 800000000,
1540 .u.pll = {
1541 .input_min = 2000000,
1542 .input_max = 31000000,
1543 .cf_min = 1000000,
1544 .cf_max = 6000000,
1545 .vco_min = 20000000,
1546 .vco_max = 1200000000,
1547 .freq_table = tegra_pll_m_freq_table,
1548 .lock_delay = 300,
1549 },
1550 };
1551
1552 static struct clk tegra_pll_m_out1 = {
1553 .name = "pll_m_out1",
1554 .ops = &tegra_pll_div_ops,
1555 .flags = DIV_U71,
1556 .parent = &tegra_pll_m,
1557 .reg = 0x94,
1558 .reg_shift = 0,
1559 .max_rate = 600000000,
1560 };
1561
1562 static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
1563 { 12000000, 216000000, 432, 12, 2, 8},
1564 { 13000000, 216000000, 432, 13, 2, 8},
1565 { 19200000, 216000000, 90, 4, 2, 1},
1566 { 26000000, 216000000, 432, 26, 2, 8},
1567 { 12000000, 432000000, 432, 12, 1, 8},
1568 { 13000000, 432000000, 432, 13, 1, 8},
1569 { 19200000, 432000000, 90, 4, 1, 1},
1570 { 26000000, 432000000, 432, 26, 1, 8},
1571 { 0, 0, 0, 0, 0, 0 },
1572 };
1573
1574 static struct clk tegra_pll_p = {
1575 .name = "pll_p",
1576 .flags = ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON,
1577 .ops = &tegra_pll_ops,
1578 .reg = 0xa0,
1579 .parent = &tegra_clk_m,
1580 .max_rate = 432000000,
1581 .u.pll = {
1582 .input_min = 2000000,
1583 .input_max = 31000000,
1584 .cf_min = 1000000,
1585 .cf_max = 6000000,
1586 .vco_min = 20000000,
1587 .vco_max = 1400000000,
1588 .freq_table = tegra_pll_p_freq_table,
1589 .lock_delay = 300,
1590 },
1591 };
1592
1593 static struct clk tegra_pll_p_out1 = {
1594 .name = "pll_p_out1",
1595 .ops = &tegra_pll_div_ops,
1596 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
1597 .parent = &tegra_pll_p,
1598 .reg = 0xa4,
1599 .reg_shift = 0,
1600 .max_rate = 432000000,
1601 };
1602
1603 static struct clk tegra_pll_p_out2 = {
1604 .name = "pll_p_out2",
1605 .ops = &tegra_pll_div_ops,
1606 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
1607 .parent = &tegra_pll_p,
1608 .reg = 0xa4,
1609 .reg_shift = 16,
1610 .max_rate = 432000000,
1611 };
1612
1613 static struct clk tegra_pll_p_out3 = {
1614 .name = "pll_p_out3",
1615 .ops = &tegra_pll_div_ops,
1616 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
1617 .parent = &tegra_pll_p,
1618 .reg = 0xa8,
1619 .reg_shift = 0,
1620 .max_rate = 432000000,
1621 };
1622
1623 static struct clk tegra_pll_p_out4 = {
1624 .name = "pll_p_out4",
1625 .ops = &tegra_pll_div_ops,
1626 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
1627 .parent = &tegra_pll_p,
1628 .reg = 0xa8,
1629 .reg_shift = 16,
1630 .max_rate = 432000000,
1631 };
1632
1633 static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
1634 { 28800000, 56448000, 49, 25, 1, 1},
1635 { 28800000, 73728000, 64, 25, 1, 1},
1636 { 28800000, 24000000, 5, 6, 1, 1},
1637 { 0, 0, 0, 0, 0, 0 },
1638 };
1639
1640 static struct clk tegra_pll_a = {
1641 .name = "pll_a",
1642 .flags = PLL_HAS_CPCON,
1643 .ops = &tegra_pll_ops,
1644 .reg = 0xb0,
1645 .parent = &tegra_pll_p_out1,
1646 .max_rate = 73728000,
1647 .u.pll = {
1648 .input_min = 2000000,
1649 .input_max = 31000000,
1650 .cf_min = 1000000,
1651 .cf_max = 6000000,
1652 .vco_min = 20000000,
1653 .vco_max = 1400000000,
1654 .freq_table = tegra_pll_a_freq_table,
1655 .lock_delay = 300,
1656 },
1657 };
1658
1659 static struct clk tegra_pll_a_out0 = {
1660 .name = "pll_a_out0",
1661 .ops = &tegra_pll_div_ops,
1662 .flags = DIV_U71,
1663 .parent = &tegra_pll_a,
1664 .reg = 0xb4,
1665 .reg_shift = 0,
1666 .max_rate = 73728000,
1667 };
1668
1669 static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
1670 { 12000000, 216000000, 216, 12, 1, 4},
1671 { 13000000, 216000000, 216, 13, 1, 4},
1672 { 19200000, 216000000, 135, 12, 1, 3},
1673 { 26000000, 216000000, 216, 26, 1, 4},
1674
1675 { 12000000, 594000000, 594, 12, 1, 8},
1676 { 13000000, 594000000, 594, 13, 1, 8},
1677 { 19200000, 594000000, 495, 16, 1, 8},
1678 { 26000000, 594000000, 594, 26, 1, 8},
1679
1680 { 12000000, 1000000000, 1000, 12, 1, 12},
1681 { 13000000, 1000000000, 1000, 13, 1, 12},
1682 { 19200000, 1000000000, 625, 12, 1, 8},
1683 { 26000000, 1000000000, 1000, 26, 1, 12},
1684
1685 { 0, 0, 0, 0, 0, 0 },
1686 };
1687
1688 static struct clk tegra_pll_d = {
1689 .name = "pll_d",
1690 .flags = PLL_HAS_CPCON | PLLD,
1691 .ops = &tegra_pll_ops,
1692 .reg = 0xd0,
1693 .parent = &tegra_clk_m,
1694 .max_rate = 1000000000,
1695 .u.pll = {
1696 .input_min = 2000000,
1697 .input_max = 40000000,
1698 .cf_min = 1000000,
1699 .cf_max = 6000000,
1700 .vco_min = 40000000,
1701 .vco_max = 1000000000,
1702 .freq_table = tegra_pll_d_freq_table,
1703 .lock_delay = 1000,
1704 },
1705 };
1706
1707 static struct clk tegra_pll_d_out0 = {
1708 .name = "pll_d_out0",
1709 .ops = &tegra_pll_div_ops,
1710 .flags = DIV_2 | PLLD,
1711 .parent = &tegra_pll_d,
1712 .max_rate = 500000000,
1713 };
1714
1715 static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
1716 { 12000000, 480000000, 960, 12, 2, 0},
1717 { 13000000, 480000000, 960, 13, 2, 0},
1718 { 19200000, 480000000, 200, 4, 2, 0},
1719 { 26000000, 480000000, 960, 26, 2, 0},
1720 { 0, 0, 0, 0, 0, 0 },
1721 };
1722
1723 static struct clk tegra_pll_u = {
1724 .name = "pll_u",
1725 .flags = PLLU,
1726 .ops = &tegra_pll_ops,
1727 .reg = 0xc0,
1728 .parent = &tegra_clk_m,
1729 .max_rate = 480000000,
1730 .u.pll = {
1731 .input_min = 2000000,
1732 .input_max = 40000000,
1733 .cf_min = 1000000,
1734 .cf_max = 6000000,
1735 .vco_min = 480000000,
1736 .vco_max = 960000000,
1737 .freq_table = tegra_pll_u_freq_table,
1738 .lock_delay = 1000,
1739 },
1740 };
1741
1742 static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
1743 /* 1 GHz */
1744 { 12000000, 1000000000, 1000, 12, 1, 12},
1745 { 13000000, 1000000000, 1000, 13, 1, 12},
1746 { 19200000, 1000000000, 625, 12, 1, 8},
1747 { 26000000, 1000000000, 1000, 26, 1, 12},
1748
1749 /* 912 MHz */
1750 { 12000000, 912000000, 912, 12, 1, 12},
1751 { 13000000, 912000000, 912, 13, 1, 12},
1752 { 19200000, 912000000, 760, 16, 1, 8},
1753 { 26000000, 912000000, 912, 26, 1, 12},
1754
1755 /* 816 MHz */
1756 { 12000000, 816000000, 816, 12, 1, 12},
1757 { 13000000, 816000000, 816, 13, 1, 12},
1758 { 19200000, 816000000, 680, 16, 1, 8},
1759 { 26000000, 816000000, 816, 26, 1, 12},
1760
1761 /* 760 MHz */
1762 { 12000000, 760000000, 760, 12, 1, 12},
1763 { 13000000, 760000000, 760, 13, 1, 12},
1764 { 19200000, 760000000, 950, 24, 1, 8},
1765 { 26000000, 760000000, 760, 26, 1, 12},
1766
1767 /* 608 MHz */
1768 { 12000000, 608000000, 608, 12, 1, 12},
1769 { 13000000, 608000000, 608, 13, 1, 12},
1770 { 19200000, 608000000, 380, 12, 1, 8},
1771 { 26000000, 608000000, 608, 26, 1, 12},
1772
1773 /* 456 MHz */
1774 { 12000000, 456000000, 456, 12, 1, 12},
1775 { 13000000, 456000000, 456, 13, 1, 12},
1776 { 19200000, 456000000, 380, 16, 1, 8},
1777 { 26000000, 456000000, 456, 26, 1, 12},
1778
1779 /* 312 MHz */
1780 { 12000000, 312000000, 312, 12, 1, 12},
1781 { 13000000, 312000000, 312, 13, 1, 12},
1782 { 19200000, 312000000, 260, 16, 1, 8},
1783 { 26000000, 312000000, 312, 26, 1, 12},
1784
1785 { 0, 0, 0, 0, 0, 0 },
1786 };
1787
1788 static struct clk tegra_pll_x = {
1789 .name = "pll_x",
1790 .flags = PLL_HAS_CPCON | PLL_ALT_MISC_REG,
1791 .ops = &tegra_pllx_ops,
1792 .reg = 0xe0,
1793 .parent = &tegra_clk_m,
1794 .max_rate = 1000000000,
1795 .u.pll = {
1796 .input_min = 2000000,
1797 .input_max = 31000000,
1798 .cf_min = 1000000,
1799 .cf_max = 6000000,
1800 .vco_min = 20000000,
1801 .vco_max = 1200000000,
1802 .freq_table = tegra_pll_x_freq_table,
1803 .lock_delay = 300,
1804 },
1805 };
1806
1807 static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
1808 { 12000000, 100000000, 200, 24, 1, 0 },
1809 { 0, 0, 0, 0, 0, 0 },
1810 };
1811
1812 static struct clk tegra_pll_e = {
1813 .name = "pll_e",
1814 .flags = PLL_ALT_MISC_REG,
1815 .ops = &tegra_plle_ops,
1816 .parent = &tegra_clk_m,
1817 .reg = 0xe8,
1818 .max_rate = 100000000,
1819 .u.pll = {
1820 .input_min = 12000000,
1821 .input_max = 12000000,
1822 .freq_table = tegra_pll_e_freq_table,
1823 },
1824 };
1825
1826 static struct clk tegra_clk_d = {
1827 .name = "clk_d",
1828 .flags = PERIPH_NO_RESET,
1829 .ops = &tegra_clk_double_ops,
1830 .reg = 0x34,
1831 .reg_shift = 12,
1832 .parent = &tegra_clk_m,
1833 .max_rate = 52000000,
1834 .u.periph = {
1835 .clk_num = 90,
1836 },
1837 };
1838
1839 /* dap_mclk1, belongs to the cdev1 pingroup. */
1840 static struct clk tegra_clk_cdev1 = {
1841 .name = "cdev1",
1842 .ops = &tegra_cdev_clk_ops,
1843 .rate = 26000000,
1844 .max_rate = 26000000,
1845 .u.periph = {
1846 .clk_num = 94,
1847 },
1848 };
1849
1850 /* dap_mclk2, belongs to the cdev2 pingroup. */
1851 static struct clk tegra_clk_cdev2 = {
1852 .name = "cdev2",
1853 .ops = &tegra_cdev_clk_ops,
1854 .rate = 26000000,
1855 .max_rate = 26000000,
1856 .u.periph = {
1857 .clk_num = 93,
1858 },
1859 };
1860
1861 /* initialized before peripheral clocks */
1862 static struct clk_mux_sel mux_audio_sync_clk[8+1];
1863 static const struct audio_sources {
1864 const char *name;
1865 int value;
1866 } mux_audio_sync_clk_sources[] = {
1867 { .name = "spdif_in", .value = 0 },
1868 { .name = "i2s1", .value = 1 },
1869 { .name = "i2s2", .value = 2 },
1870 { .name = "pll_a_out0", .value = 4 },
1871 #if 0 /* FIXME: not implemented */
1872 { .name = "ac97", .value = 3 },
1873 { .name = "ext_audio_clk2", .value = 5 },
1874 { .name = "ext_audio_clk1", .value = 6 },
1875 { .name = "ext_vimclk", .value = 7 },
1876 #endif
1877 { NULL, 0 }
1878 };
1879
1880 static struct clk tegra_clk_audio = {
1881 .name = "audio",
1882 .inputs = mux_audio_sync_clk,
1883 .reg = 0x38,
1884 .max_rate = 73728000,
1885 .ops = &tegra_audio_sync_clk_ops
1886 };
1887
1888 static struct clk tegra_clk_audio_2x = {
1889 .name = "audio_2x",
1890 .flags = PERIPH_NO_RESET,
1891 .max_rate = 48000000,
1892 .ops = &tegra_clk_double_ops,
1893 .reg = 0x34,
1894 .reg_shift = 8,
1895 .parent = &tegra_clk_audio,
1896 .u.periph = {
1897 .clk_num = 89,
1898 },
1899 };
1900
1901 static struct clk_lookup tegra_audio_clk_lookups[] = {
1902 { .con_id = "audio", .clk = &tegra_clk_audio },
1903 { .con_id = "audio_2x", .clk = &tegra_clk_audio_2x }
1904 };
1905
1906 /* This is called after peripheral clocks are initialized, as the
1907 * audio_sync clock depends on some of the peripheral clocks.
1908 */
1909
init_audio_sync_clock_mux(void)1910 static void init_audio_sync_clock_mux(void)
1911 {
1912 int i;
1913 struct clk_mux_sel *sel = mux_audio_sync_clk;
1914 const struct audio_sources *src = mux_audio_sync_clk_sources;
1915 struct clk_lookup *lookup;
1916
1917 for (i = 0; src->name; i++, sel++, src++) {
1918 sel->input = tegra_get_clock_by_name(src->name);
1919 if (!sel->input)
1920 pr_err("%s: could not find clk %s\n", __func__,
1921 src->name);
1922 sel->value = src->value;
1923 }
1924
1925 lookup = tegra_audio_clk_lookups;
1926 for (i = 0; i < ARRAY_SIZE(tegra_audio_clk_lookups); i++, lookup++) {
1927 clk_init(lookup->clk);
1928 clkdev_add(lookup);
1929 }
1930 }
1931
1932 static struct clk_mux_sel mux_cclk[] = {
1933 { .input = &tegra_clk_m, .value = 0},
1934 { .input = &tegra_pll_c, .value = 1},
1935 { .input = &tegra_clk_32k, .value = 2},
1936 { .input = &tegra_pll_m, .value = 3},
1937 { .input = &tegra_pll_p, .value = 4},
1938 { .input = &tegra_pll_p_out4, .value = 5},
1939 { .input = &tegra_pll_p_out3, .value = 6},
1940 { .input = &tegra_clk_d, .value = 7},
1941 { .input = &tegra_pll_x, .value = 8},
1942 { NULL, 0},
1943 };
1944
1945 static struct clk_mux_sel mux_sclk[] = {
1946 { .input = &tegra_clk_m, .value = 0},
1947 { .input = &tegra_pll_c_out1, .value = 1},
1948 { .input = &tegra_pll_p_out4, .value = 2},
1949 { .input = &tegra_pll_p_out3, .value = 3},
1950 { .input = &tegra_pll_p_out2, .value = 4},
1951 { .input = &tegra_clk_d, .value = 5},
1952 { .input = &tegra_clk_32k, .value = 6},
1953 { .input = &tegra_pll_m_out1, .value = 7},
1954 { NULL, 0},
1955 };
1956
1957 static struct clk tegra_clk_cclk = {
1958 .name = "cclk",
1959 .inputs = mux_cclk,
1960 .reg = 0x20,
1961 .ops = &tegra_super_ops,
1962 .max_rate = 1000000000,
1963 };
1964
1965 static struct clk tegra_clk_sclk = {
1966 .name = "sclk",
1967 .inputs = mux_sclk,
1968 .reg = 0x28,
1969 .ops = &tegra_super_ops,
1970 .max_rate = 240000000,
1971 .min_rate = 120000000,
1972 };
1973
1974 static struct clk tegra_clk_virtual_cpu = {
1975 .name = "cpu",
1976 .parent = &tegra_clk_cclk,
1977 .ops = &tegra_cpu_ops,
1978 .max_rate = 1000000000,
1979 .u.cpu = {
1980 .main = &tegra_pll_x,
1981 .backup = &tegra_pll_p,
1982 },
1983 };
1984
1985 static struct clk tegra_clk_cop = {
1986 .name = "cop",
1987 .parent = &tegra_clk_sclk,
1988 .ops = &tegra_cop_ops,
1989 .max_rate = 240000000,
1990 };
1991
1992 static struct clk tegra_clk_hclk = {
1993 .name = "hclk",
1994 .flags = DIV_BUS,
1995 .parent = &tegra_clk_sclk,
1996 .reg = 0x30,
1997 .reg_shift = 4,
1998 .ops = &tegra_bus_ops,
1999 .max_rate = 240000000,
2000 };
2001
2002 static struct clk tegra_clk_pclk = {
2003 .name = "pclk",
2004 .flags = DIV_BUS,
2005 .parent = &tegra_clk_hclk,
2006 .reg = 0x30,
2007 .reg_shift = 0,
2008 .ops = &tegra_bus_ops,
2009 .max_rate = 120000000,
2010 };
2011
2012 static struct clk tegra_clk_blink = {
2013 .name = "blink",
2014 .parent = &tegra_clk_32k,
2015 .reg = 0x40,
2016 .ops = &tegra_blink_clk_ops,
2017 .max_rate = 32768,
2018 };
2019
2020 static struct clk_mux_sel mux_pllm_pllc_pllp_plla[] = {
2021 { .input = &tegra_pll_m, .value = 0},
2022 { .input = &tegra_pll_c, .value = 1},
2023 { .input = &tegra_pll_p, .value = 2},
2024 { .input = &tegra_pll_a_out0, .value = 3},
2025 { NULL, 0},
2026 };
2027
2028 static struct clk_mux_sel mux_pllm_pllc_pllp_clkm[] = {
2029 { .input = &tegra_pll_m, .value = 0},
2030 { .input = &tegra_pll_c, .value = 1},
2031 { .input = &tegra_pll_p, .value = 2},
2032 { .input = &tegra_clk_m, .value = 3},
2033 { NULL, 0},
2034 };
2035
2036 static struct clk_mux_sel mux_pllp_pllc_pllm_clkm[] = {
2037 { .input = &tegra_pll_p, .value = 0},
2038 { .input = &tegra_pll_c, .value = 1},
2039 { .input = &tegra_pll_m, .value = 2},
2040 { .input = &tegra_clk_m, .value = 3},
2041 { NULL, 0},
2042 };
2043
2044 static struct clk_mux_sel mux_pllaout0_audio2x_pllp_clkm[] = {
2045 {.input = &tegra_pll_a_out0, .value = 0},
2046 {.input = &tegra_clk_audio_2x, .value = 1},
2047 {.input = &tegra_pll_p, .value = 2},
2048 {.input = &tegra_clk_m, .value = 3},
2049 { NULL, 0},
2050 };
2051
2052 static struct clk_mux_sel mux_pllp_plld_pllc_clkm[] = {
2053 {.input = &tegra_pll_p, .value = 0},
2054 {.input = &tegra_pll_d_out0, .value = 1},
2055 {.input = &tegra_pll_c, .value = 2},
2056 {.input = &tegra_clk_m, .value = 3},
2057 { NULL, 0},
2058 };
2059
2060 static struct clk_mux_sel mux_pllp_pllc_audio_clkm_clk32[] = {
2061 {.input = &tegra_pll_p, .value = 0},
2062 {.input = &tegra_pll_c, .value = 1},
2063 {.input = &tegra_clk_audio, .value = 2},
2064 {.input = &tegra_clk_m, .value = 3},
2065 {.input = &tegra_clk_32k, .value = 4},
2066 { NULL, 0},
2067 };
2068
2069 static struct clk_mux_sel mux_pllp_pllc_pllm[] = {
2070 {.input = &tegra_pll_p, .value = 0},
2071 {.input = &tegra_pll_c, .value = 1},
2072 {.input = &tegra_pll_m, .value = 2},
2073 { NULL, 0},
2074 };
2075
2076 static struct clk_mux_sel mux_clk_m[] = {
2077 { .input = &tegra_clk_m, .value = 0},
2078 { NULL, 0},
2079 };
2080
2081 static struct clk_mux_sel mux_pllp_out3[] = {
2082 { .input = &tegra_pll_p_out3, .value = 0},
2083 { NULL, 0},
2084 };
2085
2086 static struct clk_mux_sel mux_plld[] = {
2087 { .input = &tegra_pll_d, .value = 0},
2088 { NULL, 0},
2089 };
2090
2091 static struct clk_mux_sel mux_clk_32k[] = {
2092 { .input = &tegra_clk_32k, .value = 0},
2093 { NULL, 0},
2094 };
2095
2096 static struct clk_mux_sel mux_pclk[] = {
2097 { .input = &tegra_clk_pclk, .value = 0},
2098 { NULL, 0},
2099 };
2100
2101 static struct clk tegra_clk_emc = {
2102 .name = "emc",
2103 .ops = &tegra_emc_clk_ops,
2104 .reg = 0x19c,
2105 .max_rate = 800000000,
2106 .inputs = mux_pllm_pllc_pllp_clkm,
2107 .flags = MUX | DIV_U71 | PERIPH_EMC_ENB,
2108 .u.periph = {
2109 .clk_num = 57,
2110 },
2111 };
2112
2113 #define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, _max, _inputs, _flags) \
2114 { \
2115 .name = _name, \
2116 .lookup = { \
2117 .dev_id = _dev, \
2118 .con_id = _con, \
2119 }, \
2120 .ops = &tegra_periph_clk_ops, \
2121 .reg = _reg, \
2122 .inputs = _inputs, \
2123 .flags = _flags, \
2124 .max_rate = _max, \
2125 .u.periph = { \
2126 .clk_num = _clk_num, \
2127 }, \
2128 }
2129
2130 #define SHARED_CLK(_name, _dev, _con, _parent) \
2131 { \
2132 .name = _name, \
2133 .lookup = { \
2134 .dev_id = _dev, \
2135 .con_id = _con, \
2136 }, \
2137 .ops = &tegra_clk_shared_bus_ops, \
2138 .parent = _parent, \
2139 }
2140
2141 static struct clk tegra_list_clks[] = {
2142 PERIPH_CLK("apbdma", "tegra-dma", NULL, 34, 0, 108000000, mux_pclk, 0),
2143 PERIPH_CLK("rtc", "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET),
2144 PERIPH_CLK("timer", "timer", NULL, 5, 0, 26000000, mux_clk_m, 0),
2145 PERIPH_CLK("i2s1", "tegra-i2s.0", NULL, 11, 0x100, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71),
2146 PERIPH_CLK("i2s2", "tegra-i2s.1", NULL, 18, 0x104, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71),
2147 PERIPH_CLK("spdif_out", "spdif_out", NULL, 10, 0x108, 100000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71),
2148 PERIPH_CLK("spdif_in", "spdif_in", NULL, 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71),
2149 PERIPH_CLK("pwm", "pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_audio_clkm_clk32, MUX | DIV_U71),
2150 PERIPH_CLK("spi", "spi", NULL, 43, 0x114, 40000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2151 PERIPH_CLK("xio", "xio", NULL, 45, 0x120, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2152 PERIPH_CLK("twc", "twc", NULL, 16, 0x12c, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2153 PERIPH_CLK("sbc1", "spi_tegra.0", NULL, 41, 0x134, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2154 PERIPH_CLK("sbc2", "spi_tegra.1", NULL, 44, 0x118, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2155 PERIPH_CLK("sbc3", "spi_tegra.2", NULL, 46, 0x11c, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2156 PERIPH_CLK("sbc4", "spi_tegra.3", NULL, 68, 0x1b4, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2157 PERIPH_CLK("ide", "ide", NULL, 25, 0x144, 100000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */
2158 PERIPH_CLK("ndflash", "tegra_nand", NULL, 13, 0x160, 164000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2159 PERIPH_CLK("vfir", "vfir", NULL, 7, 0x168, 72000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2160 PERIPH_CLK("sdmmc1", "sdhci-tegra.0", NULL, 14, 0x150, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2161 PERIPH_CLK("sdmmc2", "sdhci-tegra.1", NULL, 9, 0x154, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2162 PERIPH_CLK("sdmmc3", "sdhci-tegra.2", NULL, 69, 0x1bc, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2163 PERIPH_CLK("sdmmc4", "sdhci-tegra.3", NULL, 15, 0x164, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2164 PERIPH_CLK("vcp", "tegra-avp", "vcp", 29, 0, 250000000, mux_clk_m, 0),
2165 PERIPH_CLK("bsea", "tegra-avp", "bsea", 62, 0, 250000000, mux_clk_m, 0),
2166 PERIPH_CLK("bsev", "tegra-aes", "bsev", 63, 0, 250000000, mux_clk_m, 0),
2167 PERIPH_CLK("vde", "tegra-avp", "vde", 61, 0x1c8, 250000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage and process_id */
2168 PERIPH_CLK("csite", "csite", NULL, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* max rate ??? */
2169 /* FIXME: what is la? */
2170 PERIPH_CLK("la", "la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2171 PERIPH_CLK("owr", "tegra_w1", NULL, 71, 0x1cc, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2172 PERIPH_CLK("nor", "nor", NULL, 42, 0x1d0, 92000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */
2173 PERIPH_CLK("mipi", "mipi", NULL, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2174 PERIPH_CLK("i2c1", "tegra-i2c.0", NULL, 12, 0x124, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16),
2175 PERIPH_CLK("i2c2", "tegra-i2c.1", NULL, 54, 0x198, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16),
2176 PERIPH_CLK("i2c3", "tegra-i2c.2", NULL, 67, 0x1b8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16),
2177 PERIPH_CLK("dvc", "tegra-i2c.3", NULL, 47, 0x128, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16),
2178 PERIPH_CLK("i2c1_i2c", "tegra-i2c.0", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
2179 PERIPH_CLK("i2c2_i2c", "tegra-i2c.1", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
2180 PERIPH_CLK("i2c3_i2c", "tegra-i2c.2", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
2181 PERIPH_CLK("dvc_i2c", "tegra-i2c.3", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
2182 PERIPH_CLK("uarta", "uart.0", NULL, 6, 0x178, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
2183 PERIPH_CLK("uartb", "uart.1", NULL, 7, 0x17c, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
2184 PERIPH_CLK("uartc", "uart.2", NULL, 55, 0x1a0, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
2185 PERIPH_CLK("uartd", "uart.3", NULL, 65, 0x1c0, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
2186 PERIPH_CLK("uarte", "uart.4", NULL, 66, 0x1c4, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
2187 PERIPH_CLK("3d", "3d", NULL, 24, 0x158, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_MANUAL_RESET), /* scales with voltage and process_id */
2188 PERIPH_CLK("2d", "2d", NULL, 21, 0x15c, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
2189 PERIPH_CLK("vi", "tegra_camera", "vi", 20, 0x148, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
2190 PERIPH_CLK("vi_sensor", "tegra_camera", "vi_sensor", 20, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET), /* scales with voltage and process_id */
2191 PERIPH_CLK("epp", "epp", NULL, 19, 0x16c, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
2192 PERIPH_CLK("mpe", "mpe", NULL, 60, 0x170, 250000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
2193 PERIPH_CLK("host1x", "host1x", NULL, 28, 0x180, 166000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
2194 PERIPH_CLK("cve", "cve", NULL, 49, 0x140, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
2195 PERIPH_CLK("tvo", "tvo", NULL, 49, 0x188, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
2196 PERIPH_CLK("hdmi", "hdmi", NULL, 51, 0x18c, 600000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
2197 PERIPH_CLK("tvdac", "tvdac", NULL, 53, 0x194, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
2198 PERIPH_CLK("disp1", "tegradc.0", NULL, 27, 0x138, 600000000, mux_pllp_plld_pllc_clkm, MUX), /* scales with voltage and process_id */
2199 PERIPH_CLK("disp2", "tegradc.1", NULL, 26, 0x13c, 600000000, mux_pllp_plld_pllc_clkm, MUX), /* scales with voltage and process_id */
2200 PERIPH_CLK("usbd", "fsl-tegra-udc", NULL, 22, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
2201 PERIPH_CLK("usb2", "tegra-ehci.1", NULL, 58, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
2202 PERIPH_CLK("usb3", "tegra-ehci.2", NULL, 59, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
2203 PERIPH_CLK("dsi", "dsi", NULL, 48, 0, 500000000, mux_plld, 0), /* scales with voltage */
2204 PERIPH_CLK("csi", "tegra_camera", "csi", 52, 0, 72000000, mux_pllp_out3, 0),
2205 PERIPH_CLK("isp", "tegra_camera", "isp", 23, 0, 150000000, mux_clk_m, 0), /* same frequency as VI */
2206 PERIPH_CLK("csus", "tegra_camera", "csus", 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET),
2207 PERIPH_CLK("pex", NULL, "pex", 70, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET),
2208 PERIPH_CLK("afi", NULL, "afi", 72, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET),
2209 PERIPH_CLK("pcie_xclk", NULL, "pcie_xclk", 74, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET),
2210
2211 SHARED_CLK("avp.sclk", "tegra-avp", "sclk", &tegra_clk_sclk),
2212 SHARED_CLK("avp.emc", "tegra-avp", "emc", &tegra_clk_emc),
2213 SHARED_CLK("cpu.emc", "cpu", "emc", &tegra_clk_emc),
2214 SHARED_CLK("disp1.emc", "tegradc.0", "emc", &tegra_clk_emc),
2215 SHARED_CLK("disp2.emc", "tegradc.1", "emc", &tegra_clk_emc),
2216 SHARED_CLK("hdmi.emc", "hdmi", "emc", &tegra_clk_emc),
2217 SHARED_CLK("host.emc", "tegra_grhost", "emc", &tegra_clk_emc),
2218 SHARED_CLK("usbd.emc", "fsl-tegra-udc", "emc", &tegra_clk_emc),
2219 SHARED_CLK("usb1.emc", "tegra-ehci.0", "emc", &tegra_clk_emc),
2220 SHARED_CLK("usb2.emc", "tegra-ehci.1", "emc", &tegra_clk_emc),
2221 SHARED_CLK("usb3.emc", "tegra-ehci.2", "emc", &tegra_clk_emc),
2222 };
2223
2224 #define CLK_DUPLICATE(_name, _dev, _con) \
2225 { \
2226 .name = _name, \
2227 .lookup = { \
2228 .dev_id = _dev, \
2229 .con_id = _con, \
2230 }, \
2231 }
2232
2233 /* Some clocks may be used by different drivers depending on the board
2234 * configuration. List those here to register them twice in the clock lookup
2235 * table under two names.
2236 */
2237 static struct clk_duplicate tegra_clk_duplicates[] = {
2238 CLK_DUPLICATE("uarta", "tegra_uart.0", NULL),
2239 CLK_DUPLICATE("uartb", "tegra_uart.1", NULL),
2240 CLK_DUPLICATE("uartc", "tegra_uart.2", NULL),
2241 CLK_DUPLICATE("uartd", "tegra_uart.3", NULL),
2242 CLK_DUPLICATE("uarte", "tegra_uart.4", NULL),
2243 CLK_DUPLICATE("usbd", "utmip-pad", NULL),
2244 CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
2245 CLK_DUPLICATE("usbd", "tegra-otg", NULL),
2246 CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"),
2247 CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
2248 CLK_DUPLICATE("pwm", "tegra_pwm.0", NULL),
2249 CLK_DUPLICATE("pwm", "tegra_pwm.1", NULL),
2250 CLK_DUPLICATE("pwm", "tegra_pwm.2", NULL),
2251 CLK_DUPLICATE("pwm", "tegra_pwm.3", NULL),
2252 CLK_DUPLICATE("host1x", "tegra_grhost", "host1x"),
2253 CLK_DUPLICATE("2d", "tegra_grhost", "gr2d"),
2254 CLK_DUPLICATE("3d", "tegra_grhost", "gr3d"),
2255 CLK_DUPLICATE("epp", "tegra_grhost", "epp"),
2256 CLK_DUPLICATE("mpe", "tegra_grhost", "mpe"),
2257 CLK_DUPLICATE("cop", "tegra-avp", "cop"),
2258 CLK_DUPLICATE("vde", "tegra-aes", "vde"),
2259 };
2260
2261 #define CLK(dev, con, ck) \
2262 { \
2263 .dev_id = dev, \
2264 .con_id = con, \
2265 .clk = ck, \
2266 }
2267
2268 static struct clk *tegra_ptr_clks[] = {
2269 &tegra_clk_32k,
2270 &tegra_pll_s,
2271 &tegra_clk_m,
2272 &tegra_pll_m,
2273 &tegra_pll_m_out1,
2274 &tegra_pll_c,
2275 &tegra_pll_c_out1,
2276 &tegra_pll_p,
2277 &tegra_pll_p_out1,
2278 &tegra_pll_p_out2,
2279 &tegra_pll_p_out3,
2280 &tegra_pll_p_out4,
2281 &tegra_pll_a,
2282 &tegra_pll_a_out0,
2283 &tegra_pll_d,
2284 &tegra_pll_d_out0,
2285 &tegra_pll_u,
2286 &tegra_pll_x,
2287 &tegra_pll_e,
2288 &tegra_clk_cclk,
2289 &tegra_clk_sclk,
2290 &tegra_clk_hclk,
2291 &tegra_clk_pclk,
2292 &tegra_clk_d,
2293 &tegra_clk_cdev1,
2294 &tegra_clk_cdev2,
2295 &tegra_clk_virtual_cpu,
2296 &tegra_clk_blink,
2297 &tegra_clk_cop,
2298 &tegra_clk_emc,
2299 };
2300
tegra2_init_one_clock(struct clk * c)2301 static void tegra2_init_one_clock(struct clk *c)
2302 {
2303 clk_init(c);
2304 INIT_LIST_HEAD(&c->shared_bus_list);
2305 if (!c->lookup.dev_id && !c->lookup.con_id)
2306 c->lookup.con_id = c->name;
2307 c->lookup.clk = c;
2308 clkdev_add(&c->lookup);
2309 }
2310
tegra2_init_clocks(void)2311 void __init tegra2_init_clocks(void)
2312 {
2313 int i;
2314 struct clk *c;
2315
2316 for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++)
2317 tegra2_init_one_clock(tegra_ptr_clks[i]);
2318
2319 for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
2320 tegra2_init_one_clock(&tegra_list_clks[i]);
2321
2322 for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
2323 c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
2324 if (!c) {
2325 pr_err("%s: Unknown duplicate clock %s\n", __func__,
2326 tegra_clk_duplicates[i].name);
2327 continue;
2328 }
2329
2330 tegra_clk_duplicates[i].lookup.clk = c;
2331 clkdev_add(&tegra_clk_duplicates[i].lookup);
2332 }
2333
2334 init_audio_sync_clock_mux();
2335 }
2336
2337 #ifdef CONFIG_PM
2338 static u32 clk_rst_suspend[RST_DEVICES_NUM + CLK_OUT_ENB_NUM +
2339 PERIPH_CLK_SOURCE_NUM + 22];
2340
tegra_clk_suspend(void)2341 void tegra_clk_suspend(void)
2342 {
2343 unsigned long off, i;
2344 u32 *ctx = clk_rst_suspend;
2345
2346 *ctx++ = clk_readl(OSC_CTRL) & OSC_CTRL_MASK;
2347 *ctx++ = clk_readl(tegra_pll_c.reg + PLL_BASE);
2348 *ctx++ = clk_readl(tegra_pll_c.reg + PLL_MISC(&tegra_pll_c));
2349 *ctx++ = clk_readl(tegra_pll_a.reg + PLL_BASE);
2350 *ctx++ = clk_readl(tegra_pll_a.reg + PLL_MISC(&tegra_pll_a));
2351 *ctx++ = clk_readl(tegra_pll_s.reg + PLL_BASE);
2352 *ctx++ = clk_readl(tegra_pll_s.reg + PLL_MISC(&tegra_pll_s));
2353 *ctx++ = clk_readl(tegra_pll_d.reg + PLL_BASE);
2354 *ctx++ = clk_readl(tegra_pll_d.reg + PLL_MISC(&tegra_pll_d));
2355 *ctx++ = clk_readl(tegra_pll_u.reg + PLL_BASE);
2356 *ctx++ = clk_readl(tegra_pll_u.reg + PLL_MISC(&tegra_pll_u));
2357
2358 *ctx++ = clk_readl(tegra_pll_m_out1.reg);
2359 *ctx++ = clk_readl(tegra_pll_a_out0.reg);
2360 *ctx++ = clk_readl(tegra_pll_c_out1.reg);
2361
2362 *ctx++ = clk_readl(tegra_clk_cclk.reg);
2363 *ctx++ = clk_readl(tegra_clk_cclk.reg + SUPER_CLK_DIVIDER);
2364
2365 *ctx++ = clk_readl(tegra_clk_sclk.reg);
2366 *ctx++ = clk_readl(tegra_clk_sclk.reg + SUPER_CLK_DIVIDER);
2367 *ctx++ = clk_readl(tegra_clk_pclk.reg);
2368
2369 *ctx++ = clk_readl(tegra_clk_audio.reg);
2370
2371 for (off = PERIPH_CLK_SOURCE_I2S1; off <= PERIPH_CLK_SOURCE_OSC;
2372 off += 4) {
2373 if (off == PERIPH_CLK_SOURCE_EMC)
2374 continue;
2375 *ctx++ = clk_readl(off);
2376 }
2377
2378 off = RST_DEVICES;
2379 for (i = 0; i < RST_DEVICES_NUM; i++, off += 4)
2380 *ctx++ = clk_readl(off);
2381
2382 off = CLK_OUT_ENB;
2383 for (i = 0; i < CLK_OUT_ENB_NUM; i++, off += 4)
2384 *ctx++ = clk_readl(off);
2385
2386 *ctx++ = clk_readl(MISC_CLK_ENB);
2387 *ctx++ = clk_readl(CLK_MASK_ARM);
2388
2389 BUG_ON(ctx - clk_rst_suspend != ARRAY_SIZE(clk_rst_suspend));
2390 }
2391
tegra_clk_resume(void)2392 void tegra_clk_resume(void)
2393 {
2394 unsigned long off, i;
2395 const u32 *ctx = clk_rst_suspend;
2396 u32 val;
2397
2398 val = clk_readl(OSC_CTRL) & ~OSC_CTRL_MASK;
2399 val |= *ctx++;
2400 clk_writel(val, OSC_CTRL);
2401
2402 clk_writel(*ctx++, tegra_pll_c.reg + PLL_BASE);
2403 clk_writel(*ctx++, tegra_pll_c.reg + PLL_MISC(&tegra_pll_c));
2404 clk_writel(*ctx++, tegra_pll_a.reg + PLL_BASE);
2405 clk_writel(*ctx++, tegra_pll_a.reg + PLL_MISC(&tegra_pll_a));
2406 clk_writel(*ctx++, tegra_pll_s.reg + PLL_BASE);
2407 clk_writel(*ctx++, tegra_pll_s.reg + PLL_MISC(&tegra_pll_s));
2408 clk_writel(*ctx++, tegra_pll_d.reg + PLL_BASE);
2409 clk_writel(*ctx++, tegra_pll_d.reg + PLL_MISC(&tegra_pll_d));
2410 clk_writel(*ctx++, tegra_pll_u.reg + PLL_BASE);
2411 clk_writel(*ctx++, tegra_pll_u.reg + PLL_MISC(&tegra_pll_u));
2412 udelay(1000);
2413
2414 clk_writel(*ctx++, tegra_pll_m_out1.reg);
2415 clk_writel(*ctx++, tegra_pll_a_out0.reg);
2416 clk_writel(*ctx++, tegra_pll_c_out1.reg);
2417
2418 clk_writel(*ctx++, tegra_clk_cclk.reg);
2419 clk_writel(*ctx++, tegra_clk_cclk.reg + SUPER_CLK_DIVIDER);
2420
2421 clk_writel(*ctx++, tegra_clk_sclk.reg);
2422 clk_writel(*ctx++, tegra_clk_sclk.reg + SUPER_CLK_DIVIDER);
2423 clk_writel(*ctx++, tegra_clk_pclk.reg);
2424
2425 clk_writel(*ctx++, tegra_clk_audio.reg);
2426
2427 /* enable all clocks before configuring clock sources */
2428 clk_writel(0xbffffff9ul, CLK_OUT_ENB);
2429 clk_writel(0xfefffff7ul, CLK_OUT_ENB + 4);
2430 clk_writel(0x77f01bfful, CLK_OUT_ENB + 8);
2431 wmb();
2432
2433 for (off = PERIPH_CLK_SOURCE_I2S1; off <= PERIPH_CLK_SOURCE_OSC;
2434 off += 4) {
2435 if (off == PERIPH_CLK_SOURCE_EMC)
2436 continue;
2437 clk_writel(*ctx++, off);
2438 }
2439 wmb();
2440
2441 off = RST_DEVICES;
2442 for (i = 0; i < RST_DEVICES_NUM; i++, off += 4)
2443 clk_writel(*ctx++, off);
2444 wmb();
2445
2446 off = CLK_OUT_ENB;
2447 for (i = 0; i < CLK_OUT_ENB_NUM; i++, off += 4)
2448 clk_writel(*ctx++, off);
2449 wmb();
2450
2451 clk_writel(*ctx++, MISC_CLK_ENB);
2452 clk_writel(*ctx++, CLK_MASK_ARM);
2453 }
2454 #endif
2455