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Searched refs:REG_WR (Results 1 – 25 of 104) sorted by relevance

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/linux-2.6.39/drivers/net/bnx2x/
Dbnx2x_init_ops.h29 REG_WR(bp, addr + i*4, data[i]); in bnx2x_init_str_wr()
228 REG_WR(bp, addr, op->write.val); in bnx2x_init_block()
441 REG_WR(bp, read_arb_addr[i].l, read_arb_data[i][r_order].l); in bnx2x_init_pxp_arb()
442 REG_WR(bp, read_arb_addr[i].add, in bnx2x_init_pxp_arb()
444 REG_WR(bp, read_arb_addr[i].ubound, in bnx2x_init_pxp_arb()
452 REG_WR(bp, write_arb_addr[i].l, in bnx2x_init_pxp_arb()
455 REG_WR(bp, write_arb_addr[i].add, in bnx2x_init_pxp_arb()
458 REG_WR(bp, write_arb_addr[i].ubound, in bnx2x_init_pxp_arb()
463 REG_WR(bp, write_arb_addr[i].l, in bnx2x_init_pxp_arb()
467 REG_WR(bp, write_arb_addr[i].add, in bnx2x_init_pxp_arb()
[all …]
Dbnx2x_main.c166 REG_WR(bp, addr, U64_LO(mapping)); in __storm_memset_dma_mapping()
167 REG_WR(bp, addr + 4, U64_HI(mapping)); in __storm_memset_dma_mapping()
175 REG_WR(bp, addr + (i * 4), val); in __storm_memset_fill()
509 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i)); in bnx2x_post_dmae()
514 REG_WR(bp, dmae_reg_go_c[idx], 1); in bnx2x_post_dmae()
1123 REG_WR(bp, addr, val); in bnx2x_hc_int_enable()
1130 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF); in bnx2x_hc_int_enable()
1135 REG_WR(bp, addr, val); in bnx2x_hc_int_enable()
1152 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); in bnx2x_hc_int_enable()
1153 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); in bnx2x_hc_int_enable()
[all …]
Dbnx2x_link.c191 REG_WR(bp, reg, val); in bnx2x_bits_en()
200 REG_WR(bp, reg, val); in bnx2x_bits_dis()
222 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688); in bnx2x_ets_disabled()
232 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7); in bnx2x_ets_disabled()
234 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0); in bnx2x_ets_disabled()
239 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); in bnx2x_ets_disabled()
244 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0); in bnx2x_ets_disabled()
245 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0); in bnx2x_ets_disabled()
246 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0); in bnx2x_ets_disabled()
248 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0); in bnx2x_ets_disabled()
[all …]
Dbnx2x_init.h317 REG_WR(bp, mcp_attn_ctl_regs[i], reg_val); in bnx2x_set_mcp_parity()
339 REG_WR(bp, bnx2x_blocks_parity_data[i].mask_addr, in bnx2x_disable_blocks_parity()
364 REG_WR(bp, XSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1); in bnx2x_clear_blocks_parity()
365 REG_WR(bp, TSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1); in bnx2x_clear_blocks_parity()
366 REG_WR(bp, USEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1); in bnx2x_clear_blocks_parity()
367 REG_WR(bp, CSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1); in bnx2x_clear_blocks_parity()
395 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x780); in bnx2x_clear_blocks_parity()
406 REG_WR(bp, bnx2x_blocks_parity_data[i].mask_addr, in bnx2x_enable_blocks_parity()
/linux-2.6.39/drivers/media/radio/wl128x/
Dfmdrv_tx.c39 ret = fmc_send_cmd(fmdev, MONO_SET, REG_WR, &payload, in fm_tx_set_stereo_mono()
54 ret = fmc_send_cmd(fmdev, RDS_DATA_SET, REG_WR, rds_text, in set_rds_text()
61 ret = fmc_send_cmd(fmdev, DISPLAY_MODE, REG_WR, &payload, in set_rds_text()
76 ret = fmc_send_cmd(fmdev, PI_SET, REG_WR, &payload, in set_rds_data_mode()
83 ret = fmc_send_cmd(fmdev, DI_SET, REG_WR, &payload, in set_rds_data_mode()
99 ret = fmc_send_cmd(fmdev, RDS_CONFIG_DATA_SET, REG_WR, &payload, in set_rds_len()
134 ret = fmc_send_cmd(fmdev, RDS_DATA_ENB, REG_WR, &payload, in fm_tx_set_rds_mode()
171 ret = fmc_send_cmd(fmdev, RDS_DATA_ENB, REG_WR, &payload, in fm_tx_set_radio_text()
191 ret = fmc_send_cmd(fmdev, TA_SET, REG_WR, &payload, in fm_tx_set_af()
211 ret = fmc_send_cmd(fmdev, TX_BAND_SET, REG_WR, &payload, in fm_tx_set_region()
[all …]
Dfmdrv_rx.c61 ret = fmc_send_cmd(fmdev, AUDIO_ENABLE_SET, REG_WR, &payload, in fm_rx_set_freq()
68 ret = fmc_send_cmd(fmdev, HILO_SET, REG_WR, &payload, in fm_rx_set_freq()
76 ret = fmc_send_cmd(fmdev, FREQ_SET, REG_WR, &payload, in fm_rx_set_freq()
90 ret = fmc_send_cmd(fmdev, INT_MASK_SET, REG_WR, &payload, in fm_rx_set_freq()
97 ret = fmc_send_cmd(fmdev, TUNER_MODE_SET, REG_WR, &payload, in fm_rx_set_freq()
132 ret = fmc_send_cmd(fmdev, INT_MASK_SET, REG_WR, &payload, in fm_rx_set_freq()
158 ret = fmc_send_cmd(fmdev, CHANL_BW_SET, REG_WR, &payload, in fm_rx_set_channel_spacing()
213 ret = fmc_send_cmd(fmdev, FREQ_SET, REG_WR, &payload, in fm_rx_seek()
220 ret = fmc_send_cmd(fmdev, SEARCH_DIR_SET, REG_WR, &payload, in fm_rx_seek()
234 ret = fmc_send_cmd(fmdev, INT_MASK_SET, REG_WR, &payload, in fm_rx_seek()
[all …]
/linux-2.6.39/arch/cris/arch-v32/kernel/
Dtime.c129 REG_WR(timer, regi_timer0, rw_wd_ctrl, wd_ctrl); in reset_watchdog()
144 REG_WR(timer, regi_timer0, rw_wd_ctrl, wd_ctrl); in stop_watchdog()
167 REG_WR(clkgen, regi_clkgen, rw_clk_ctrl, ctrl); in handle_watchdog_bite()
204 REG_WR(timer, timer_regs[cpu], rw_ack_intr, ack_intr); in timer_interrupt()
247 REG_WR(timer, timer_regs[cpu], rw_tmr0_div, tmr0_div); in cris_timer_init()
248 REG_WR(timer, timer_regs[cpu], rw_tmr0_ctrl, tmr0_ctrl); /* Load */ in cris_timer_init()
250 REG_WR(timer, timer_regs[cpu], rw_tmr0_ctrl, tmr0_ctrl); /* Start */ in cris_timer_init()
255 REG_WR(timer, timer_regs[cpu], rw_intr_mask, timer_intr_mask); in cris_timer_init()
324 REG_WR(timer, timer_regs[freqs->cpu], rw_tmr0_div, div); in cris_time_freq_notifier()
Ddebugport.c156 REG_WR (ser, p->instance, rw_tr_baud_div, tr_baud_div); in start_port()
157 REG_WR (ser, p->instance, rw_rec_baud_div, rec_baud_div); in start_port()
158 REG_WR (ser, p->instance, rw_tr_dma_en, tr_dma_en); in start_port()
159 REG_WR (ser, p->instance, rw_tr_ctrl, tr_ctrl); in start_port()
160 REG_WR (ser, p->instance, rw_rec_ctrl, rec_ctrl); in start_port()
177 REG_WR(ser, kgdb_port->instance, rw_ack_intr, ack_intr); in getDebugChar()
Dfasttimer.c146 REG_WR(timer, regi_timer0, rw_intr_mask, intr_mask); in start_timer_trig()
157 REG_WR(timer, regi_timer0, rw_ack_intr, ack_intr); in start_timer_trig()
160 REG_WR(timer, regi_timer0, rw_trig, trig); in start_timer_trig()
162 REG_WR(timer, regi_timer0, rw_trig_cfg, trig_cfg); in start_timer_trig()
172 REG_WR(timer, regi_timer0, rw_intr_mask, intr_mask); in start_timer_trig()
178 REG_WR(timer, regi_timer0, rw_trig_cfg, trig_cfg); in start_timer_trig()
179 REG_WR(timer, regi_timer0, rw_ack_intr, ack_intr); in start_timer_trig()
339 REG_WR(timer, regi_timer0, rw_intr_mask, intr_mask); in timer_trig_handler()
344 REG_WR(timer, regi_timer0, rw_trig_cfg, trig_cfg); in timer_trig_handler()
348 REG_WR(timer, regi_timer0, rw_ack_intr, ack_intr); in timer_trig_handler()
Dkgdb.c1565 REG_WR(intr_vect, regi_irq, rw_mask, intr_mask); in kgdb_init()
1569 REG_WR(ser, regi_ser0, rw_intr_mask, ser_intr_mask); in kgdb_init()
1577 REG_WR(intr_vect, regi_irq, rw_mask, intr_mask); in kgdb_init()
1581 REG_WR(ser, regi_ser1, rw_intr_mask, ser_intr_mask); in kgdb_init()
1589 REG_WR(intr_vect, regi_irq, rw_mask, intr_mask); in kgdb_init()
1593 REG_WR(ser, regi_ser2, rw_intr_mask, ser_intr_mask); in kgdb_init()
1601 REG_WR(intr_vect, regi_irq, rw_mask, intr_mask); in kgdb_init()
1605 REG_WR(ser, regi_ser3, rw_intr_mask, ser_intr_mask); in kgdb_init()
/linux-2.6.39/arch/cris/arch-v32/drivers/
Diop_fw_load.c89 REG_WR(iop_spu, regi_iop_spu0, rw_ctrl, spu_ctrl); in iop_fw_load_spu()
93 REG_WR(iop_spu, regi_iop_spu1, rw_ctrl, spu_ctrl); in iop_fw_load_spu()
98 REG_WR(iop_sw_cpu, regi_iop_sw_cpu, rw_mc_ctrl, mc_ctrl); in iop_fw_load_spu()
150 REG_WR(iop_mpu, regi_iop_mpu, rw_ctrl, mpu_ctrl); in iop_fw_load_mpu()
156 REG_WR(iop_mpu, regi_iop_mpu, rw_instr, MPU_SWX_IIR_INSTR(0, 4, 0)); in iop_fw_load_mpu()
177 REG_WR(iop_mpu, regi_iop_mpu, rw_instr, MPU_HALT()); in iop_start_mpu()
187 REG_WR(iop_mpu, regi_iop_mpu, rw_instr, MPU_DI()); in iop_start_mpu()
191 REG_WR(iop_mpu, regi_iop_mpu, rw_ctrl, mpu_ctrl); in iop_start_mpu()
Dsync_serial.c337 REG_WR(sser, port->regi_sser, rw_cfg, cfg); in initialize_port()
347 REG_WR(sser, port->regi_sser, rw_frm_cfg, frm_cfg); in initialize_port()
361 REG_WR(sser, port->regi_sser, rw_tr_cfg, tr_cfg); in initialize_port()
367 REG_WR(sser, port->regi_sser, rw_rec_cfg, rec_cfg); in initialize_port()
542 REG_WR(dma, port->regi_dmain, rw_cfg, cfg); in sync_serial_open()
543 REG_WR(dma, port->regi_dmaout, rw_cfg, cfg); in sync_serial_open()
545 REG_WR(dma, port->regi_dmain, rw_intr_mask, intr_mask); in sync_serial_open()
546 REG_WR(dma, port->regi_dmaout, rw_intr_mask, intr_mask); in sync_serial_open()
625 REG_WR(sser, port->regi_sser, rw_cfg, cfg); in sync_serial_poll()
626 REG_WR(sser, port->regi_sser, rw_rec_cfg, rec_cfg); in sync_serial_poll()
[all …]
/linux-2.6.39/arch/cris/include/arch-v32/arch/hwregs/
Ddma.h78 REG_WR( dma, inst, rw_cfg, e); } while( 0 )
84 REG_WR( dma, inst, rw_cfg, r); } while( 0 )
90 REG_WR( dma, inst, rw_cfg, s); } while( 0 )
96 REG_WR( dma, inst, rw_cfg, c); } while( 0 )
103 REG_WR(dma, inst, rw_stream_cmd, __x); \
125 REG_WR( dma, inst, rw_cmd, c ); } while( 0 )
Dmarb_defs.h23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
282 #ifndef REG_WR
283 #define REG_WR( scope, inst, reg, val ) \ macro
Dirq_nmi_defs.h23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
/linux-2.6.39/arch/cris/boot/compressed/
Dmisc.c138 REG_WR(ser, regi_ser, rw_dout, dout); in serout()
248 REG_WR(ser, regi_ser, rw_xoff, xoff); in serial_setup()
270 REG_WR(ser, regi_ser, rw_tr_ctrl, tr_ctrl); in serial_setup()
271 REG_WR(ser, regi_ser, rw_tr_baud_div, tr_baud); in serial_setup()
272 REG_WR(ser, regi_ser, rw_rec_ctrl, rec_ctrl); in serial_setup()
273 REG_WR(ser, regi_ser, rw_rec_baud_div, rec_baud); in serial_setup()
297 REG_WR(clkgen, regi_clkgen, rw_clk_ctrl, clk_ctrl); in decompress_kernel()
323 REG_WR(pinmux, regi_pinmux, rw_hwprot, hwprot); in decompress_kernel()
/linux-2.6.39/drivers/net/
Dbnx2.c275 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset); in bnx2_reg_rd_ind()
285 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset); in bnx2_reg_wr_ind()
286 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val); in bnx2_reg_wr_ind()
310 REG_WR(bp, BNX2_CTX_CTX_DATA, val); in bnx2_ctx_wr()
311 REG_WR(bp, BNX2_CTX_CTX_CTRL, in bnx2_ctx_wr()
320 REG_WR(bp, BNX2_CTX_DATA_ADR, offset); in bnx2_ctx_wr()
321 REG_WR(bp, BNX2_CTX_DATA, val); in bnx2_ctx_wr()
492 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1); in bnx2_read_phy()
501 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1); in bnx2_read_phy()
530 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1); in bnx2_read_phy()
[all …]
/linux-2.6.39/arch/cris/arch-v32/drivers/mach-a3/
Dnandflash.c83 REG_WR(pio, regi_pio, rw_dout, dout); in crisv32_hwcontrol()
133 REG_WR(pio, regi_pio, rw_man_ctrl, man_ctrl); in crisv32_nand_flash_probe()
134 REG_WR(pio, regi_pio, rw_dout, dout); in crisv32_nand_flash_probe()
135 REG_WR(pio, regi_pio, rw_oe, oe); in crisv32_nand_flash_probe()
/linux-2.6.39/arch/cris/arch-v32/mm/
Dl2cache.c19 REG_WR(l2cache, regi_l2cache, rw_ctrl, ctrl); in l2cache_init()
25 REG_WR(l2cache, regi_l2cache, rw_cfg, cfg); in l2cache_init()
/linux-2.6.39/arch/cris/arch-v32/drivers/mach-fs/
Dnandflash.c78 REG_WR(gio, regi_gio, rw_pa_dout, dout); in crisv32_hwcontrol()
138 REG_WR(gio, regi_gio, rw_pa_oe, pa_oe); in crisv32_nand_flash_probe()
142 REG_WR(bif_core, regi_bif_core, rw_grp3_cfg, bif_cfg); in crisv32_nand_flash_probe()
/linux-2.6.39/arch/cris/arch-v32/mach-fs/
Darbiter.c307 REG_WR(marb, regi_marb, rw_intr_mask, intr_mask); in crisv32_arbiter_watch()
341 REG_WR(marb, regi_marb, rw_intr_mask, intr_mask); in crisv32_arbiter_unwatch()
395 REG_WR(marb_bp, watch->instance, rw_ack, ack); in crisv32_arbiter_irq()
396 REG_WR(marb, regi_marb, rw_ack_intr, ack_intr); in crisv32_arbiter_irq()
Dcpufreq.c53 REG_WR(config, regi_config, rw_clk_ctrl, clk_ctrl); in cris_freq_set_cpu_state()
140 REG_WR(bif_core, regi_bif_core, rw_sdram_timing, timing); in cris_sdram_freq_notifier()
/linux-2.6.39/arch/cris/arch-v32/mach-a3/
Dcpufreq.c56 REG_WR(clkgen, regi_clkgen, rw_clk_ctrl, clk_ctrl); in cris_freq_set_cpu_state()
146 REG_WR(bif_core, regi_bif_core, rw_sdram_timing, timing); in cris_sdram_freq_notifier()
/linux-2.6.39/arch/cris/include/arch-v32/mach-fs/mach/hwregs/
Dmarb_defs.h23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
282 #ifndef REG_WR
283 #define REG_WR( scope, inst, reg, val ) \ macro
/linux-2.6.39/arch/cris/include/arch-v32/mach-a3/mach/hwregs/
Dmarb_bar_defs.h20 #ifndef REG_WR
21 #define REG_WR( scope, inst, reg, val ) \ macro
304 #ifndef REG_WR
305 #define REG_WR( scope, inst, reg, val ) \ macro

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