1 #include <linux/init.h>
2 #include <linux/module.h>
3 #include <linux/cpufreq.h>
4 #include <hwregs/reg_map.h>
5 #include <arch/hwregs/reg_rdwr.h>
6 #include <arch/hwregs/config_defs.h>
7 #include <arch/hwregs/bif_core_defs.h>
8 
9 static int
10 cris_sdram_freq_notifier(struct notifier_block *nb, unsigned long val,
11 			 void *data);
12 
13 static struct notifier_block cris_sdram_freq_notifier_block = {
14 	.notifier_call = cris_sdram_freq_notifier
15 };
16 
17 static struct cpufreq_frequency_table cris_freq_table[] = {
18 	{0x01, 6000},
19 	{0x02, 200000},
20 	{0, CPUFREQ_TABLE_END},
21 };
22 
cris_freq_get_cpu_frequency(unsigned int cpu)23 static unsigned int cris_freq_get_cpu_frequency(unsigned int cpu)
24 {
25 	reg_config_rw_clk_ctrl clk_ctrl;
26 	clk_ctrl = REG_RD(config, regi_config, rw_clk_ctrl);
27 	return clk_ctrl.pll ? 200000 : 6000;
28 }
29 
cris_freq_set_cpu_state(unsigned int state)30 static void cris_freq_set_cpu_state(unsigned int state)
31 {
32 	int i;
33 	struct cpufreq_freqs freqs;
34 	reg_config_rw_clk_ctrl clk_ctrl;
35 	clk_ctrl = REG_RD(config, regi_config, rw_clk_ctrl);
36 
37 	for_each_possible_cpu(i) {
38 		freqs.old = cris_freq_get_cpu_frequency(i);
39 		freqs.new = cris_freq_table[state].frequency;
40 		freqs.cpu = i;
41 	}
42 
43 	cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
44 
45 	local_irq_disable();
46 
47 	/* Even though we may be SMP they will share the same clock
48 	 * so all settings are made on CPU0. */
49 	if (cris_freq_table[state].frequency == 200000)
50 		clk_ctrl.pll = 1;
51 	else
52 		clk_ctrl.pll = 0;
53 	REG_WR(config, regi_config, rw_clk_ctrl, clk_ctrl);
54 
55 	local_irq_enable();
56 
57 	cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
58 };
59 
cris_freq_verify(struct cpufreq_policy * policy)60 static int cris_freq_verify(struct cpufreq_policy *policy)
61 {
62 	return cpufreq_frequency_table_verify(policy, &cris_freq_table[0]);
63 }
64 
cris_freq_target(struct cpufreq_policy * policy,unsigned int target_freq,unsigned int relation)65 static int cris_freq_target(struct cpufreq_policy *policy,
66 			    unsigned int target_freq, unsigned int relation)
67 {
68 	unsigned int newstate = 0;
69 
70 	if (cpufreq_frequency_table_target
71 	    (policy, cris_freq_table, target_freq, relation, &newstate))
72 		return -EINVAL;
73 
74 	cris_freq_set_cpu_state(newstate);
75 
76 	return 0;
77 }
78 
cris_freq_cpu_init(struct cpufreq_policy * policy)79 static int cris_freq_cpu_init(struct cpufreq_policy *policy)
80 {
81 	int result;
82 
83 	/* cpuinfo and default policy values */
84 	policy->cpuinfo.transition_latency = 1000000;	/* 1ms */
85 	policy->cur = cris_freq_get_cpu_frequency(0);
86 
87 	result = cpufreq_frequency_table_cpuinfo(policy, cris_freq_table);
88 	if (result)
89 		return (result);
90 
91 	cpufreq_frequency_table_get_attr(cris_freq_table, policy->cpu);
92 
93 	return 0;
94 }
95 
cris_freq_cpu_exit(struct cpufreq_policy * policy)96 static int cris_freq_cpu_exit(struct cpufreq_policy *policy)
97 {
98 	cpufreq_frequency_table_put_attr(policy->cpu);
99 	return 0;
100 }
101 
102 static struct freq_attr *cris_freq_attr[] = {
103 	&cpufreq_freq_attr_scaling_available_freqs,
104 	NULL,
105 };
106 
107 static struct cpufreq_driver cris_freq_driver = {
108 	.get = cris_freq_get_cpu_frequency,
109 	.verify = cris_freq_verify,
110 	.target = cris_freq_target,
111 	.init = cris_freq_cpu_init,
112 	.exit = cris_freq_cpu_exit,
113 	.name = "cris_freq",
114 	.owner = THIS_MODULE,
115 	.attr = cris_freq_attr,
116 };
117 
cris_freq_init(void)118 static int __init cris_freq_init(void)
119 {
120 	int ret;
121 	ret = cpufreq_register_driver(&cris_freq_driver);
122 	cpufreq_register_notifier(&cris_sdram_freq_notifier_block,
123 				  CPUFREQ_TRANSITION_NOTIFIER);
124 	return ret;
125 }
126 
127 static int
cris_sdram_freq_notifier(struct notifier_block * nb,unsigned long val,void * data)128 cris_sdram_freq_notifier(struct notifier_block *nb, unsigned long val,
129 			 void *data)
130 {
131 	int i;
132 	struct cpufreq_freqs *freqs = data;
133 	if (val == CPUFREQ_PRECHANGE) {
134 		reg_bif_core_rw_sdram_timing timing =
135 		    REG_RD(bif_core, regi_bif_core, rw_sdram_timing);
136 		timing.cpd = (freqs->new == 200000 ? 0 : 1);
137 
138 		if (freqs->new == 200000)
139 			for (i = 0; i < 50000; i++) ;
140 		REG_WR(bif_core, regi_bif_core, rw_sdram_timing, timing);
141 	}
142 	return 0;
143 }
144 
145 module_init(cris_freq_init);
146