Lines Matching refs:REG_WR
166 REG_WR(bp, addr, U64_LO(mapping)); in __storm_memset_dma_mapping()
167 REG_WR(bp, addr + 4, U64_HI(mapping)); in __storm_memset_dma_mapping()
175 REG_WR(bp, addr + (i * 4), val); in __storm_memset_fill()
509 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i)); in bnx2x_post_dmae()
514 REG_WR(bp, dmae_reg_go_c[idx], 1); in bnx2x_post_dmae()
1123 REG_WR(bp, addr, val); in bnx2x_hc_int_enable()
1130 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF); in bnx2x_hc_int_enable()
1135 REG_WR(bp, addr, val); in bnx2x_hc_int_enable()
1152 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); in bnx2x_hc_int_enable()
1153 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); in bnx2x_hc_int_enable()
1191 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); in bnx2x_igu_int_enable()
1204 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); in bnx2x_igu_int_enable()
1205 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); in bnx2x_igu_int_enable()
1235 REG_WR(bp, HC_REG_INT_MASK + port*4, 0); in bnx2x_hc_int_disable()
1252 REG_WR(bp, addr, val); in bnx2x_hc_int_disable()
1270 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); in bnx2x_igu_int_disable()
1344 REG_WR(bp, hw_lock_control_reg + 4, resource_bit); in bnx2x_trylock_hw_lock()
1512 REG_WR(bp, hw_lock_control_reg + 4, resource_bit); in bnx2x_acquire_hw_lock()
1555 REG_WR(bp, hw_lock_control_reg, resource_bit); in bnx2x_release_hw_lock()
1637 REG_WR(bp, MISC_REG_GPIO, gpio_reg); in bnx2x_set_gpio()
1683 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg); in bnx2x_set_gpio_int()
1729 REG_WR(bp, MISC_REG_SPIO, spio_reg); in bnx2x_set_spio()
2019 REG_WR(bp, BAR_XSTRORM_INTMEM + in bnx2x_init_vn_minmax()
2024 REG_WR(bp, BAR_XSTRORM_INTMEM + in bnx2x_init_vn_minmax()
2118 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 + in bnx2x_link_sync_notify()
2142 REG_WR(bp, BAR_USTRORM_INTMEM + in bnx2x_link_attn()
2210 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); in bnx2x_pmf_update()
2211 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); in bnx2x_pmf_update()
2213 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); in bnx2x_pmf_update()
2214 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); in bnx2x_pmf_update()
2410 REG_WR(bp, XSEM_REG_FAST_MEMORY + in bnx2x_func_init()
2544 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + in bnx2x_pf_init()
2549 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + in bnx2x_pf_init()
2620 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); in bnx2x_e1h_disable()
2629 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1); in bnx2x_e1h_enable()
2816 REG_WR(bp, GRCBASE_MCP + 0x9c, val); in bnx2x_acquire_alr()
2834 REG_WR(bp, GRCBASE_MCP + 0x9c, 0); in bnx2x_release_alr()
2887 REG_WR(bp, aeu_addr, aeu_mask); in bnx2x_attn_int_asserted()
2901 REG_WR(bp, nig_int_mask_addr, 0); in bnx2x_attn_int_asserted()
2922 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0); in bnx2x_attn_int_asserted()
2926 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0); in bnx2x_attn_int_asserted()
2930 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0); in bnx2x_attn_int_asserted()
2935 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0); in bnx2x_attn_int_asserted()
2939 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0); in bnx2x_attn_int_asserted()
2943 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0); in bnx2x_attn_int_asserted()
2957 REG_WR(bp, reg_addr, asserted); in bnx2x_attn_int_asserted()
2961 REG_WR(bp, nig_int_mask_addr, nig_mask); in bnx2x_attn_int_asserted()
2999 REG_WR(bp, reg_offset, val); in bnx2x_attn_int_deasserted0()
3019 REG_WR(bp, reg_offset, val); in bnx2x_attn_int_deasserted0()
3050 REG_WR(bp, reg_offset, val); in bnx2x_attn_int_deasserted1()
3094 REG_WR(bp, reg_offset, val); in bnx2x_attn_int_deasserted2()
3111 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); in bnx2x_attn_int_deasserted3()
3136 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0); in bnx2x_attn_int_deasserted3()
3137 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0); in bnx2x_attn_int_deasserted3()
3138 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0); in bnx2x_attn_int_deasserted3()
3139 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0); in bnx2x_attn_int_deasserted3()
3145 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0); in bnx2x_attn_int_deasserted3()
3164 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff); in bnx2x_attn_int_deasserted3()
3181 REG_WR(bp, BNX2X_MISC_GEN_REG, val); in bnx2x_set_reset_done()
3193 REG_WR(bp, BNX2X_MISC_GEN_REG, val); in bnx2x_set_reset_in_progress()
3218 REG_WR(bp, BNX2X_MISC_GEN_REG, (val & RESET_DONE_FLAG_MASK) | val1); in bnx2x_inc_load_cnt()
3233 REG_WR(bp, BNX2X_MISC_GEN_REG, (val & RESET_DONE_FLAG_MASK) | val1); in bnx2x_dec_load_cnt()
3251 REG_WR(bp, BNX2X_MISC_GEN_REG, val & (~LOAD_COUNTER_MASK)); in bnx2x_clear_load_cnt()
3608 REG_WR(bp, reg_addr, val); in bnx2x_attn_int_deasserted()
3624 REG_WR(bp, reg_addr, aeu_mask); in bnx2x_attn_int_deasserted()
3957 REG_WR(bp, addr + i, fill); in bnx2x_fill()
3972 REG_WR(bp, BAR_CSTRORM_INTMEM + in bnx2x_wr_fp_sb_data()
4019 REG_WR(bp, BAR_CSTRORM_INTMEM + in bnx2x_wr_sp_sb_data()
4191 REG_WR(bp, reg_offset, U64_LO(section)); in bnx2x_init_def_sb()
4192 REG_WR(bp, reg_offset + 4, U64_HI(section)); in bnx2x_init_def_sb()
4194 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section)); in bnx2x_init_def_sb()
4195 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section)); in bnx2x_init_def_sb()
4363 REG_WR(bp, in bnx2x_set_storm_rx_mode()
4413 REG_WR(bp, BAR_USTRORM_INTMEM + in bnx2x_init_internal_common()
4668 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); in bnx2x_int_mem_test()
4669 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); in bnx2x_int_mem_test()
4670 REG_WR(bp, CFC_REG_DEBUG0, 0x1); in bnx2x_int_mem_test()
4671 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); in bnx2x_int_mem_test()
4674 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); in bnx2x_int_mem_test()
4713 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); in bnx2x_int_mem_test()
4715 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); in bnx2x_int_mem_test()
4723 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); in bnx2x_int_mem_test()
4724 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); in bnx2x_int_mem_test()
4725 REG_WR(bp, CFC_REG_DEBUG0, 0x1); in bnx2x_int_mem_test()
4726 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); in bnx2x_int_mem_test()
4729 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); in bnx2x_int_mem_test()
4759 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1); in bnx2x_int_mem_test()
4778 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); in bnx2x_int_mem_test()
4780 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); in bnx2x_int_mem_test()
4786 REG_WR(bp, PRS_REG_NIC_MODE, 1); in bnx2x_int_mem_test()
4790 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff); in bnx2x_int_mem_test()
4791 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1); in bnx2x_int_mem_test()
4792 REG_WR(bp, CFC_REG_DEBUG0, 0x0); in bnx2x_int_mem_test()
4793 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1); in bnx2x_int_mem_test()
4802 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); in bnx2x_enable_blocks_attention()
4804 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40); in bnx2x_enable_blocks_attention()
4806 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0); in bnx2x_enable_blocks_attention()
4807 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); in bnx2x_enable_blocks_attention()
4808 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); in bnx2x_enable_blocks_attention()
4815 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00); in bnx2x_enable_blocks_attention()
4816 REG_WR(bp, QM_REG_QM_INT_MASK, 0); in bnx2x_enable_blocks_attention()
4817 REG_WR(bp, TM_REG_TM_INT_MASK, 0); in bnx2x_enable_blocks_attention()
4818 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0); in bnx2x_enable_blocks_attention()
4819 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0); in bnx2x_enable_blocks_attention()
4820 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0); in bnx2x_enable_blocks_attention()
4823 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0); in bnx2x_enable_blocks_attention()
4824 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0); in bnx2x_enable_blocks_attention()
4825 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0); in bnx2x_enable_blocks_attention()
4828 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0); in bnx2x_enable_blocks_attention()
4829 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0); in bnx2x_enable_blocks_attention()
4830 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0); in bnx2x_enable_blocks_attention()
4831 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0); in bnx2x_enable_blocks_attention()
4836 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000); in bnx2x_enable_blocks_attention()
4838 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, in bnx2x_enable_blocks_attention()
4845 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000); in bnx2x_enable_blocks_attention()
4846 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0); in bnx2x_enable_blocks_attention()
4847 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0); in bnx2x_enable_blocks_attention()
4848 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0); in bnx2x_enable_blocks_attention()
4851 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0); in bnx2x_enable_blocks_attention()
4852 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0); in bnx2x_enable_blocks_attention()
4854 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */ in bnx2x_enable_blocks_attention()
4860 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, in bnx2x_reset_common()
4862 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 0x1403); in bnx2x_reset_common()
4928 REG_WR(bp, MISC_REG_SPIO_INT, val); in bnx2x_setup_fan_failure_detection()
4933 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val); in bnx2x_setup_fan_failure_detection()
4974 REG_WR(bp, offset, pretend_func_num); in bnx2x_pretend_func()
4984 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); in bnx2x_pf_disable()
4985 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); in bnx2x_pf_disable()
4986 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0); in bnx2x_pf_disable()
4996 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff); in bnx2x_init_hw_common()
4997 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 0xfffc); in bnx2x_init_hw_common()
5001 REG_WR(bp, MISC_REG_E1HMF_MODE, IS_MF(bp)); in bnx2x_init_hw_common()
5015 REG_WR(bp, in bnx2x_init_hw_common()
5032 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); in bnx2x_init_hw_common()
5039 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1); in bnx2x_init_hw_common()
5040 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1); in bnx2x_init_hw_common()
5041 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1); in bnx2x_init_hw_common()
5042 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1); in bnx2x_init_hw_common()
5043 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1); in bnx2x_init_hw_common()
5045 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0); in bnx2x_init_hw_common()
5048 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1); in bnx2x_init_hw_common()
5049 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1); in bnx2x_init_hw_common()
5050 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1); in bnx2x_init_hw_common()
5051 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1); in bnx2x_init_hw_common()
5057 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1); in bnx2x_init_hw_common()
5104 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN); in bnx2x_init_hw_common()
5105 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN); in bnx2x_init_hw_common()
5106 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1); in bnx2x_init_hw_common()
5110 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0); in bnx2x_init_hw_common()
5111 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0); in bnx2x_init_hw_common()
5157 REG_WR(bp, QM_REG_SOFT_RESET, 1); in bnx2x_init_hw_common()
5158 REG_WR(bp, QM_REG_SOFT_RESET, 0); in bnx2x_init_hw_common()
5165 REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT); in bnx2x_init_hw_common()
5169 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); in bnx2x_init_hw_common()
5174 REG_WR(bp, BRB1_REG_FULL_LB_XOFF_THRESHOLD, 248); in bnx2x_init_hw_common()
5175 REG_WR(bp, BRB1_REG_FULL_LB_XON_THRESHOLD, 328); in bnx2x_init_hw_common()
5179 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf); in bnx2x_init_hw_common()
5182 REG_WR(bp, PRS_REG_NIC_MODE, 1); in bnx2x_init_hw_common()
5185 REG_WR(bp, PRS_REG_E1HOV_MODE, IS_MF_SD(bp)); in bnx2x_init_hw_common()
5191 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, (has_ovlan ? 7 : 6)); in bnx2x_init_hw_common()
5192 REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, (has_ovlan ? 1 : 0)); in bnx2x_init_hw_common()
5214 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, in bnx2x_init_hw_common()
5216 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, in bnx2x_init_hw_common()
5225 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, (has_ovlan ? 7 : 6)); in bnx2x_init_hw_common()
5226 REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, (has_ovlan ? 1 : 0)); in bnx2x_init_hw_common()
5229 REG_WR(bp, SRC_REG_SOFT_RST, 1); in bnx2x_init_hw_common()
5231 REG_WR(bp, i, random32()); in bnx2x_init_hw_common()
5235 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672); in bnx2x_init_hw_common()
5236 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc); in bnx2x_init_hw_common()
5237 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b); in bnx2x_init_hw_common()
5238 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a); in bnx2x_init_hw_common()
5239 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116); in bnx2x_init_hw_common()
5240 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b); in bnx2x_init_hw_common()
5241 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf); in bnx2x_init_hw_common()
5242 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09); in bnx2x_init_hw_common()
5243 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f); in bnx2x_init_hw_common()
5244 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7); in bnx2x_init_hw_common()
5246 REG_WR(bp, SRC_REG_SOFT_RST, 0); in bnx2x_init_hw_common()
5256 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val); in bnx2x_init_hw_common()
5259 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF); in bnx2x_init_hw_common()
5261 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); in bnx2x_init_hw_common()
5264 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000); in bnx2x_init_hw_common()
5269 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36); in bnx2x_init_hw_common()
5276 REG_WR(bp, 0x2814, 0xffffffff); in bnx2x_init_hw_common()
5277 REG_WR(bp, 0x3820, 0xffffffff); in bnx2x_init_hw_common()
5280 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5, in bnx2x_init_hw_common()
5283 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT, in bnx2x_init_hw_common()
5287 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT, in bnx2x_init_hw_common()
5300 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp)); in bnx2x_init_hw_common()
5301 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp)); in bnx2x_init_hw_common()
5306 REG_WR(bp, NIG_REG_P0_HDRS_AFTER_BASIC, (IS_MF_SD(bp) ? 7 : 6)); in bnx2x_init_hw_common()
5328 REG_WR(bp, CFC_REG_DEBUG0, 0); in bnx2x_init_hw_common()
5385 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); in bnx2x_init_hw_port()
5396 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); in bnx2x_init_hw_port()
5408 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20); in bnx2x_init_hw_port()
5409 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31); in bnx2x_init_hw_port()
5439 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low); in bnx2x_init_hw_port()
5440 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high); in bnx2x_init_hw_port()
5444 REG_WR(bp, BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 + port*8, 248); in bnx2x_init_hw_port()
5445 REG_WR(bp, BRB1_REG_PAUSE_0_XON_THRESHOLD_0 + port*8, 328); in bnx2x_init_hw_port()
5446 REG_WR(bp, (BP_PORT(bp) ? BRB1_REG_MAC_GUARANTIED_1 : in bnx2x_init_hw_port()
5471 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); in bnx2x_init_hw_port()
5474 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16)); in bnx2x_init_hw_port()
5476 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22); in bnx2x_init_hw_port()
5479 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1); in bnx2x_init_hw_port()
5481 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0); in bnx2x_init_hw_port()
5491 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); in bnx2x_init_hw_port()
5492 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); in bnx2x_init_hw_port()
5506 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val); in bnx2x_init_hw_port()
5516 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); in bnx2x_init_hw_port()
5520 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4, in bnx2x_init_hw_port()
5534 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE : in bnx2x_init_hw_port()
5538 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0); in bnx2x_init_hw_port()
5539 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0); in bnx2x_init_hw_port()
5540 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1); in bnx2x_init_hw_port()
5552 REG_WR(bp, reg_addr, val); in bnx2x_init_hw_port()
5600 REG_WR(bp, addr, val); in bnx2x_init_hw_func()
5620 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS); in bnx2x_init_hw_func()
5625 REG_WR(bp, PRS_REG_NIC_MODE, 1); in bnx2x_init_hw_func()
5648 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); in bnx2x_init_hw_func()
5650 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf); in bnx2x_init_hw_func()
5658 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func); in bnx2x_init_hw_func()
5671 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_PATH_ID_OFFSET, in bnx2x_init_hw_func()
5673 REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_PATH_ID_OFFSET, in bnx2x_init_hw_func()
5681 REG_WR(bp, QM_REG_PF_EN, 1); in bnx2x_init_hw_func()
5700 REG_WR(bp, PBF_REG_DISABLE_PF, 0); in bnx2x_init_hw_func()
5707 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1); in bnx2x_init_hw_func()
5710 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1); in bnx2x_init_hw_func()
5711 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov); in bnx2x_init_hw_func()
5719 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); in bnx2x_init_hw_func()
5721 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); in bnx2x_init_hw_func()
5722 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); in bnx2x_init_hw_func()
5729 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); in bnx2x_init_hw_func()
5732 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); in bnx2x_init_hw_func()
5733 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); in bnx2x_init_hw_func()
5770 REG_WR(bp, addr, 0); in bnx2x_init_hw_func()
5796 REG_WR(bp, addr, 0); in bnx2x_init_hw_func()
5820 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0); in bnx2x_init_hw_func()
5821 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0); in bnx2x_init_hw_func()
5822 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0); in bnx2x_init_hw_func()
5823 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0); in bnx2x_init_hw_func()
5824 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0); in bnx2x_init_hw_func()
5825 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0); in bnx2x_init_hw_func()
5830 REG_WR(bp, 0x2114, 0xffffffff); in bnx2x_init_hw_func()
5831 REG_WR(bp, 0x2120, 0xffffffff); in bnx2x_init_hw_func()
6383 REG_WR(bp, ena_offset + 4*mem_index, set); in bnx2x_set_mac_in_nig()
6551 REG_WR(bp, MC_HASH_OFFSET(bp, i), in bnx2x_set_e1h_mc_list()
6562 REG_WR(bp, MC_HASH_OFFSET(bp, i), 0); in bnx2x_invalidate_e1h_mc_list()
7085 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func), in bnx2x_reset_func()
7090 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); in bnx2x_reset_func()
7091 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); in bnx2x_reset_func()
7093 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); in bnx2x_reset_func()
7094 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); in bnx2x_reset_func()
7099 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0); in bnx2x_reset_func()
7139 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); in bnx2x_reset_port()
7142 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0); in bnx2x_reset_port()
7144 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP : in bnx2x_reset_port()
7148 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0); in bnx2x_reset_port()
7239 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); in bnx2x_chip_cleanup()
7349 REG_WR(bp, addr, val); in bnx2x_disable_close_the_gate()
7354 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val); in bnx2x_disable_close_the_gate()
7367 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, in bnx2x_set_234_gates()
7371 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, in bnx2x_set_234_gates()
7378 REG_WR(bp, addr, (!close) ? (val | 0x1) : (val & (~(u32)1))); in bnx2x_set_234_gates()
7431 REG_WR(bp, shmem + validity_offset, 0); in bnx2x_reset_mcp_prep()
7507 REG_WR(bp, PXP2_REG_RD_START_INIT, 0); in bnx2x_pxp_prep()
7508 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0); in bnx2x_pxp_prep()
7509 REG_WR(bp, PXP2_REG_RQ_CFG_DONE, 0); in bnx2x_pxp_prep()
7550 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, in bnx2x_process_kill_chip_reset()
7552 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, in bnx2x_process_kill_chip_reset()
7558 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1); in bnx2x_process_kill_chip_reset()
7559 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, reset_mask2); in bnx2x_process_kill_chip_reset()
7605 REG_WR(bp, MISC_REG_UNPREPARED, 0); in bnx2x_process_kill()
7822 REG_WR(bp, reg, 0); in bnx2x_undi_int_disable_e1h()
7832 REG_WR(bp, reg, BP_ABS_FUNC(bp)); in bnx2x_undi_int_disable_e1h()
7864 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0); in bnx2x_undi_unload()
7899 REG_WR(bp, in bnx2x_undi_unload()
7904 REG_WR(bp, in bnx2x_undi_unload()
7908 REG_WR(bp, in bnx2x_undi_unload()
7917 REG_WR(bp, in bnx2x_undi_unload()
7920 REG_WR(bp, in bnx2x_undi_unload()
7924 REG_WR(bp, in bnx2x_undi_unload()
7927 REG_WR(bp, NIG_REG_PORT_SWAP, swap_val); in bnx2x_undi_unload()
7928 REG_WR(bp, NIG_REG_STRAP_OVERRIDE, swap_en); in bnx2x_undi_unload()
9421 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0 + BP_PORT(bp)*16, 0); in bnx2x_init_dev()
9422 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0 + BP_PORT(bp)*16, 0); in bnx2x_init_dev()
9423 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0 + BP_PORT(bp)*16, 0); in bnx2x_init_dev()
9424 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0 + BP_PORT(bp)*16, 0); in bnx2x_init_dev()