| /linux-2.6.39/drivers/scsi/ |
| D | NCR5380.c | 603 NCR5380_write(TARGET_COMMAND_REG, 0); in NCR5380_probe_irq()
604 NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask); in NCR5380_probe_irq()
605 NCR5380_write(OUTPUT_DATA_REG, hostdata->id_mask); in NCR5380_probe_irq()
606 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_DATA | ICR_ASSERT_SEL); in NCR5380_probe_irq()
611 NCR5380_write(SELECT_ENABLE_REG, 0); in NCR5380_probe_irq()
612 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE); in NCR5380_probe_irq()
882 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE); in NCR5380_init()
883 NCR5380_write(MODE_REG, MR_BASE); in NCR5380_init()
884 NCR5380_write(TARGET_COMMAND_REG, 0); in NCR5380_init()
885 NCR5380_write(SELECT_ENABLE_REG, 0); in NCR5380_init()
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| D | sun3_NCR5380.c | 884 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE); in NCR5380_init()
885 NCR5380_write(MODE_REG, MR_BASE); in NCR5380_init()
886 NCR5380_write(TARGET_COMMAND_REG, 0); in NCR5380_init()
887 NCR5380_write(SELECT_ENABLE_REG, 0); in NCR5380_init()
1234 NCR5380_write(MODE_REG, MR_BASE); in NCR5380_dma_complete()
1235 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE); in NCR5380_dma_complete()
1429 NCR5380_write(TARGET_COMMAND_REG, 0); in NCR5380_select()
1436 NCR5380_write(OUTPUT_DATA_REG, hostdata->id_mask); in NCR5380_select()
1437 NCR5380_write(MODE_REG, MR_ARBITRATE); in NCR5380_select()
1452 NCR5380_write(MODE_REG, MR_BASE); in NCR5380_select()
[all …]
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| D | atari_NCR5380.c | 887 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE); in NCR5380_init()
888 NCR5380_write(MODE_REG, MR_BASE); in NCR5380_init()
889 NCR5380_write(TARGET_COMMAND_REG, 0); in NCR5380_init()
890 NCR5380_write(SELECT_ENABLE_REG, 0); in NCR5380_init()
1238 NCR5380_write(MODE_REG, MR_BASE); in NCR5380_dma_complete()
1239 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE); in NCR5380_dma_complete()
1434 NCR5380_write(TARGET_COMMAND_REG, 0); in NCR5380_select()
1440 NCR5380_write(OUTPUT_DATA_REG, hostdata->id_mask); in NCR5380_select()
1441 NCR5380_write(MODE_REG, MR_ARBITRATE); in NCR5380_select()
1455 NCR5380_write(MODE_REG, MR_BASE); in NCR5380_select()
[all …]
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| D | dtc.c | 270 NCR5380_write(DTC_CONTROL_REG, CSR_5380_INTR); /* Enable int's */ in dtc_detect()
371 NCR5380_write(MODE_REG, MR_ENABLE_EOP_INTR | MR_DMA_MODE); in NCR5380_pread()
373 NCR5380_write(DTC_CONTROL_REG, CSR_DIR_READ); in NCR5380_pread()
375 NCR5380_write(DTC_CONTROL_REG, CSR_DIR_READ | CSR_INT_BASE); in NCR5380_pread()
376 NCR5380_write(DTC_BLK_CNT, len >> 7); /* Block count */ in NCR5380_pread()
393 NCR5380_write(MODE_REG, 0); /* Clear the operating mode */ in NCR5380_pread()
421 NCR5380_write(MODE_REG, MR_ENABLE_EOP_INTR | MR_DMA_MODE); in NCR5380_pwrite()
424 NCR5380_write(DTC_CONTROL_REG, 0); in NCR5380_pwrite()
426 NCR5380_write(DTC_CONTROL_REG, CSR_5380_INTR); in NCR5380_pwrite()
427 NCR5380_write(DTC_BLK_CNT, len >> 7); /* Block count */ in NCR5380_pwrite()
[all …]
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| D | t128.h | 125 #define NCR5380_write(reg, value) writeb((value),(T128_address(reg))) macro
131 #define NCR5380_write(reg, value) { \ macro
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| D | dtc.h | 74 #define NCR5380_write(reg, value) (writeb(value, DTC_address(reg))) macro
81 #define NCR5380_write(reg, value) do { \ macro
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| D | pas16.h | 147 #define NCR5380_write(reg, value) ( outb((value),PAS16_io_port(reg)) ) macro
153 #define NCR5380_write(reg, value) \ macro
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| D | g_NCR5380.h | 82 #define NCR5380_write(reg, value) (outb((value), (NCR5380_map_name + (reg)))) macro
107 #define NCR5380_write(reg, value) writeb(value, iomem + NCR53C400_mem_base + (reg)) macro
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| D | g_NCR5380.c | 582 NCR5380_write(C400_CONTROL_STATUS_REG, CSR_BASE | CSR_TRANS_DIR); in NCR5380_pread()
583 NCR5380_write(C400_BLOCK_COUNTER_REG, blocks); in NCR5380_pread()
642 NCR5380_write(MODE_REG, MR_BASE); in NCR5380_pread()
667 NCR5380_write(C400_CONTROL_STATUS_REG, CSR_BASE); in NCR5380_pwrite()
668 NCR5380_write(C400_BLOCK_COUNTER_REG, blocks); in NCR5380_pwrite()
683 NCR5380_write(C400_HOST_BUFFER, src[start + i]); in NCR5380_pwrite()
699 NCR5380_write(C400_HOST_BUFFER, src[start + i]); in NCR5380_pwrite()
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| D | mac_scsi.c | 357 NCR5380_write( TARGET_COMMAND_REG, in mac_scsi_reset_boot()
361 NCR5380_write( INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_RST ); in mac_scsi_reset_boot()
365 NCR5380_write( INITIATOR_COMMAND_REG, ICR_BASE ); in mac_scsi_reset_boot()
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| D | sun3_scsi.c | 343 NCR5380_write( TARGET_COMMAND_REG, in sun3_scsi_reset_boot()
347 NCR5380_write( INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_RST ); in sun3_scsi_reset_boot()
353 NCR5380_write( INITIATOR_COMMAND_REG, ICR_BASE ); in sun3_scsi_reset_boot()
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| D | sun3_scsi_vme.c | 312 NCR5380_write( TARGET_COMMAND_REG, in sun3_scsi_reset_boot()
316 NCR5380_write( INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_RST ); in sun3_scsi_reset_boot()
322 NCR5380_write( INITIATOR_COMMAND_REG, ICR_BASE ); in sun3_scsi_reset_boot()
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| D | mac_scsi.h | 66 #define NCR5380_write(reg, value) macscsi_write(_instance, reg, value) macro
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| D | pas16.c | 330 NCR5380_write( MODE_REG, 0x20 ); /* Is it really SCSI? */ in pas16_hw_detect()
333 NCR5380_write( MODE_REG, 0x00 ); /* it back. */ in pas16_hw_detect()
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| D | atari_scsi.c | 834 NCR5380_write(TARGET_COMMAND_REG, in atari_scsi_reset_boot()
838 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_RST); in atari_scsi_reset_boot()
842 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE); in atari_scsi_reset_boot()
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| D | dmx3191d.c | 39 #define NCR5380_write(reg, value) outb(value, port + reg) macro
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| D | atari_scsi.h | 50 #define NCR5380_write(reg, value) atari_scsi_reg_write( reg, value ) macro
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| D | sun3_scsi.h | 97 #define NCR5380_write(reg, value) sun3scsi_write(reg, value) macro
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| /linux-2.6.39/drivers/scsi/arm/ |
| D | oak.c | 31 #define NCR5380_write(reg, value) writeb(value, _base + ((reg) << 2)) macro
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| D | cumana_1.c | 31 #define NCR5380_write(reg, value) cumanascsi_write(_instance, reg, value) macro
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