Lines Matching refs:NCR5380_write
887 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE); in NCR5380_init()
888 NCR5380_write(MODE_REG, MR_BASE); in NCR5380_init()
889 NCR5380_write(TARGET_COMMAND_REG, 0); in NCR5380_init()
890 NCR5380_write(SELECT_ENABLE_REG, 0); in NCR5380_init()
1238 NCR5380_write(MODE_REG, MR_BASE); in NCR5380_dma_complete()
1239 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE); in NCR5380_dma_complete()
1434 NCR5380_write(TARGET_COMMAND_REG, 0); in NCR5380_select()
1440 NCR5380_write(OUTPUT_DATA_REG, hostdata->id_mask); in NCR5380_select()
1441 NCR5380_write(MODE_REG, MR_ARBITRATE); in NCR5380_select()
1455 NCR5380_write(MODE_REG, MR_BASE); in NCR5380_select()
1456 NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask); in NCR5380_select()
1469 NCR5380_write(MODE_REG, MR_BASE); in NCR5380_select()
1486 NCR5380_write(MODE_REG, MR_BASE); in NCR5380_select()
1495 NCR5380_write(INITIATOR_COMMAND_REG, in NCR5380_select()
1500 NCR5380_write(MODE_REG, MR_BASE); in NCR5380_select()
1501 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE); in NCR5380_select()
1520 NCR5380_write(MODE_REG, MR_BASE); in NCR5380_select()
1521 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE); in NCR5380_select()
1532 NCR5380_write(OUTPUT_DATA_REG, (hostdata->id_mask | (1 << cmd->device->id))); in NCR5380_select()
1540 NCR5380_write(INITIATOR_COMMAND_REG, (ICR_BASE | ICR_ASSERT_BSY | in NCR5380_select()
1542 NCR5380_write(MODE_REG, MR_BASE); in NCR5380_select()
1550 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE); in NCR5380_select()
1554 NCR5380_write(SELECT_ENABLE_REG, 0); in NCR5380_select()
1563 NCR5380_write(INITIATOR_COMMAND_REG, (ICR_BASE | ICR_ASSERT_DATA | in NCR5380_select()
1613 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE); in NCR5380_select()
1617 NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask); in NCR5380_select()
1633 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_ATN); in NCR5380_select()
1636 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE); in NCR5380_select()
1642 NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask); in NCR5380_select()
1653 NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask); in NCR5380_select()
1655 NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask); in NCR5380_select()
1751 NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(p)); in NCR5380_transfer_pio()
1772 NCR5380_write(OUTPUT_DATA_REG, *d); in NCR5380_transfer_pio()
1787 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_DATA); in NCR5380_transfer_pio()
1789 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | in NCR5380_transfer_pio()
1792 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | in NCR5380_transfer_pio()
1795 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | in NCR5380_transfer_pio()
1800 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_ACK); in NCR5380_transfer_pio()
1821 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_ATN); in NCR5380_transfer_pio()
1823 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE); in NCR5380_transfer_pio()
1862 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_ATN); in do_abort()
1877 NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(tmp)); in do_abort()
1880 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_ATN | in do_abort()
1884 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_ATN); in do_abort()
1945 NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(p)); in NCR5380_transfer_dma()
1948 NCR5380_write(MODE_REG, MR_BASE | MR_DMA_MODE | MR_ENABLE_EOP_INTR | MR_MONITOR_BSY); in NCR5380_transfer_dma()
1963 NCR5380_write(START_DMA_INITIATOR_RECEIVE_REG, 0); in NCR5380_transfer_dma()
1965 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_DATA); in NCR5380_transfer_dma()
1966 NCR5380_write(START_DMA_SEND_REG, 0); in NCR5380_transfer_dma()
2025 NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(tmp)); in NCR5380_information_transfer()
2027 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_ATN | in NCR5380_information_transfer()
2031 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | in NCR5380_information_transfer()
2098 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | in NCR5380_information_transfer()
2126 NCR5380_write(SELECT_ENABLE_REG, 0); /* disable reselects */ in NCR5380_information_transfer()
2145 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE); in NCR5380_information_transfer()
2151 NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask); in NCR5380_information_transfer()
2185 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE); in NCR5380_information_transfer()
2214 NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask); in NCR5380_information_transfer()
2266 NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask); in NCR5380_information_transfer()
2271 NCR5380_write(TARGET_COMMAND_REG, 0); in NCR5380_information_transfer()
2285 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE); in NCR5380_information_transfer()
2287 NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask); in NCR5380_information_transfer()
2310 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE); in NCR5380_information_transfer()
2326 NCR5380_write(TARGET_COMMAND_REG, 0); in NCR5380_information_transfer()
2329 NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask); in NCR5380_information_transfer()
2347 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE); in NCR5380_information_transfer()
2349 NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask); in NCR5380_information_transfer()
2366 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE); in NCR5380_information_transfer()
2380 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE); in NCR5380_information_transfer()
2430 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_ATN); in NCR5380_information_transfer()
2451 NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask); in NCR5380_information_transfer()
2512 NCR5380_write(MODE_REG, MR_BASE); in NCR5380_reselect()
2528 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_BSY); in NCR5380_reselect()
2532 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE); in NCR5380_reselect()
2562 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE); in NCR5380_reselect()
2619 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE); in NCR5380_reselect()
2869 NCR5380_write(TARGET_COMMAND_REG, in NCR5380_bus_reset()
2872 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_RST); in NCR5380_bus_reset()
2875 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE); in NCR5380_bus_reset()
2876 NCR5380_write(MODE_REG, MR_BASE); in NCR5380_bus_reset()
2877 NCR5380_write(TARGET_COMMAND_REG, 0); in NCR5380_bus_reset()
2878 NCR5380_write(SELECT_ENABLE_REG, 0); in NCR5380_bus_reset()