884     NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);  in NCR5380_init()
885     NCR5380_write(MODE_REG, MR_BASE);  in NCR5380_init()
886     NCR5380_write(TARGET_COMMAND_REG, 0);  in NCR5380_init()
887     NCR5380_write(SELECT_ENABLE_REG, 0);  in NCR5380_init()
1234     NCR5380_write(MODE_REG, MR_BASE);  in NCR5380_dma_complete()
1235     NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);  in NCR5380_dma_complete()
1429     NCR5380_write(TARGET_COMMAND_REG, 0);  in NCR5380_select()
1436     NCR5380_write(OUTPUT_DATA_REG, hostdata->id_mask);  in NCR5380_select()
1437     NCR5380_write(MODE_REG, MR_ARBITRATE);  in NCR5380_select()
1452 	NCR5380_write(MODE_REG, MR_BASE);  in NCR5380_select()
1453 	NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask);  in NCR5380_select()
1465 	NCR5380_write(MODE_REG, MR_BASE);   in NCR5380_select()
1482 	NCR5380_write(MODE_REG, MR_BASE);   in NCR5380_select()
1491     NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_SEL |  in NCR5380_select()
1496 	NCR5380_write(MODE_REG, MR_BASE);  in NCR5380_select()
1497 	NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);  in NCR5380_select()
1516 	NCR5380_write(MODE_REG, MR_BASE);  in NCR5380_select()
1517 	NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);  in NCR5380_select()
1528     NCR5380_write(OUTPUT_DATA_REG, (hostdata->id_mask | (1 << cmd->device->id)));  in NCR5380_select()
1536     NCR5380_write(INITIATOR_COMMAND_REG, (ICR_BASE | ICR_ASSERT_BSY |   in NCR5380_select()
1538     NCR5380_write(MODE_REG, MR_BASE);  in NCR5380_select()
1546 	NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);  in NCR5380_select()
1550     NCR5380_write(SELECT_ENABLE_REG, 0);  in NCR5380_select()
1559     NCR5380_write(INITIATOR_COMMAND_REG, (ICR_BASE | ICR_ASSERT_DATA |   in NCR5380_select()
1609 	    NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);  in NCR5380_select()
1613 	    NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask);  in NCR5380_select()
1628     NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_ATN);  in NCR5380_select()
1631 	NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);  in NCR5380_select()
1637 	    NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask);  in NCR5380_select()
1648 	NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask);  in NCR5380_select()
1650 	NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask);  in NCR5380_select()
1748     NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(p));  in NCR5380_transfer_pio()
1768 	    NCR5380_write(OUTPUT_DATA_REG, *d);  in NCR5380_transfer_pio()
1783 		NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE |   in NCR5380_transfer_pio()
1786 		NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE |   in NCR5380_transfer_pio()
1789 		NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE |  in NCR5380_transfer_pio()
1792 		NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE |   in NCR5380_transfer_pio()
1797 	    NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_ACK);  in NCR5380_transfer_pio()
1817 		NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_ATN);  in NCR5380_transfer_pio()
1819 		NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);  in NCR5380_transfer_pio()
1857     NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_ATN);  in do_abort()
1871     NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(tmp));  in do_abort()
1874 	NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_ATN |   in do_abort()
1877 	NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_ATN);  in do_abort()
1942 	    NCR5380_write(TARGET_COMMAND_REG, 1);  in NCR5380_transfer_dma()
1944 	    NCR5380_write(INITIATOR_COMMAND_REG, 0);  in NCR5380_transfer_dma()
1945 	    NCR5380_write(MODE_REG, (NCR5380_read(MODE_REG) | MR_DMA_MODE | MR_ENABLE_EOP_INTR));  in NCR5380_transfer_dma()
1946 	    NCR5380_write(START_DMA_INITIATOR_RECEIVE_REG, 0);  in NCR5380_transfer_dma()
1948 	    NCR5380_write(TARGET_COMMAND_REG, 0);  in NCR5380_transfer_dma()
1950 	    NCR5380_write(INITIATOR_COMMAND_REG, ICR_ASSERT_DATA);  in NCR5380_transfer_dma()
1951 	    NCR5380_write(MODE_REG, (NCR5380_read(MODE_REG) | MR_DMA_MODE | MR_ENABLE_EOP_INTR));  in NCR5380_transfer_dma()
1952 	    NCR5380_write(START_DMA_SEND_REG, 0);  in NCR5380_transfer_dma()
2041 		NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(tmp));  in NCR5380_information_transfer()
2043 		NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_ATN |   in NCR5380_information_transfer()
2046 		NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE |   in NCR5380_information_transfer()
2115 			NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE |   in NCR5380_information_transfer()
2149 		NCR5380_write(SELECT_ENABLE_REG, 0); 	/* disable reselects */  in NCR5380_information_transfer()
2168 		    NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);  in NCR5380_information_transfer()
2174 		    NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask);  in NCR5380_information_transfer()
2208 		    NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);  in NCR5380_information_transfer()
2235 		    NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask);  in NCR5380_information_transfer()
2291 		    NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask);  in NCR5380_information_transfer()
2296 		    NCR5380_write(TARGET_COMMAND_REG, 0);  in NCR5380_information_transfer()
2304 		    NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);  in NCR5380_information_transfer()
2306 		    NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask);  in NCR5380_information_transfer()
2329 		    NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);  in NCR5380_information_transfer()
2345 		    NCR5380_write(TARGET_COMMAND_REG, 0);  in NCR5380_information_transfer()
2348 		    NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask);  in NCR5380_information_transfer()
2369 		    NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);  in NCR5380_information_transfer()
2371 		    NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask);  in NCR5380_information_transfer()
2388 		    NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);  in NCR5380_information_transfer()
2402 			NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);  in NCR5380_information_transfer()
2452 		    NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE |   in NCR5380_information_transfer()
2474 		    NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask);  in NCR5380_information_transfer()
2535     NCR5380_write(MODE_REG, MR_BASE);  in NCR5380_reselect()
2551     NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_BSY);  in NCR5380_reselect()
2554     NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);  in NCR5380_reselect()
2564     NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(PHASE_MSGIN));  in NCR5380_reselect()
2644     NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_ACK);  in NCR5380_reselect()
2646     NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);  in NCR5380_reselect()
2656 	NCR5380_write( INITIATOR_COMMAND_REG, ICR_BASE );  in NCR5380_reselect()
2894     NCR5380_write( TARGET_COMMAND_REG,  in NCR5380_bus_reset()
2897     NCR5380_write( INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_RST );  in NCR5380_bus_reset()
2900     NCR5380_write( INITIATOR_COMMAND_REG, ICR_BASE );  in NCR5380_bus_reset()
2901     NCR5380_write( MODE_REG, MR_BASE );  in NCR5380_bus_reset()
2902     NCR5380_write( TARGET_COMMAND_REG, 0 );  in NCR5380_bus_reset()
2903     NCR5380_write( SELECT_ENABLE_REG, 0 );  in NCR5380_bus_reset()