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/linux-2.4.37.9/fs/hfs/
Dbitops.c38 int bit = offset % 32; in hfs_find_zero_bit() local
42 if (bit != 0) { in hfs_find_zero_bit()
44 if (!hfs_test_bit(bit, curr)) { in hfs_find_zero_bit()
47 ++bit; in hfs_find_zero_bit()
48 } while (bit < 32); in hfs_find_zero_bit()
49 bit = 0; in hfs_find_zero_bit()
58 while (hfs_test_bit(bit, curr)) { in hfs_find_zero_bit()
59 ++bit; in hfs_find_zero_bit()
66 bit |= (curr - start) << 5; in hfs_find_zero_bit()
67 return bit; in hfs_find_zero_bit()
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/linux-2.4.37.9/drivers/scsi/aic7xxx_old/
Daic7xxx.reg49 * Each bit, when set starts a specific SCSI sequence on the bus
54 bit TEMODE 0x80
55 bit ENSELO 0x40
56 bit ENSELI 0x20
57 bit ENRSELI 0x10
58 bit ENAUTOATNO 0x08
59 bit ENAUTOATNI 0x04
60 bit ENAUTOATNP 0x02
61 bit SCSIRSTO 0x01
71 bit DFON 0x80
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/linux-2.4.37.9/arch/ppc/kernel/
Dppc4xx_pic.c106 int bit, word; in ppc403_aic_enable() local
108 bit = irq & 0x1f; in ppc403_aic_enable()
111 ppc_cached_irq_mask[word] |= (1 << (31 - bit)); in ppc403_aic_enable()
118 int bit, word; in ppc403_aic_disable() local
120 bit = irq & 0x1f; in ppc403_aic_disable()
123 ppc_cached_irq_mask[word] &= ~(1 << (31 - bit)); in ppc403_aic_disable()
130 int bit, word; in ppc403_aic_disable_and_ack() local
132 bit = irq & 0x1f; in ppc403_aic_disable_and_ack()
135 ppc_cached_irq_mask[word] &= ~(1 << (31 - bit)); in ppc403_aic_disable_and_ack()
137 mtdcr(DCRN_EXISR, (1 << (31 - bit))); in ppc403_aic_disable_and_ack()
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Dppc8xx_pic.c24 int bit, word; in m8xx_mask_irq() local
26 bit = irq_nr & 0x1f; in m8xx_mask_irq()
29 ppc_cached_irq_mask[word] &= ~(1 << (31-bit)); in m8xx_mask_irq()
36 int bit, word; in m8xx_unmask_irq() local
38 bit = irq_nr & 0x1f; in m8xx_unmask_irq()
41 ppc_cached_irq_mask[word] |= (1 << (31-bit)); in m8xx_unmask_irq()
49 int bit, word; in m8xx_end_irq() local
51 bit = irq_nr & 0x1f; in m8xx_end_irq()
54 ppc_cached_irq_mask[word] |= (1 << (31-bit)); in m8xx_end_irq()
63 int bit, word; in m8xx_mask_and_ack() local
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Dcpm2_pic.c45 int bit, word; in cpm2_mask_irq() local
48 bit = irq_to_siubit[irq_nr]; in cpm2_mask_irq()
52 ppc_cached_irq_mask[word] &= ~(1 << (31 - bit)); in cpm2_mask_irq()
58 int bit, word; in cpm2_unmask_irq() local
61 bit = irq_to_siubit[irq_nr]; in cpm2_unmask_irq()
65 ppc_cached_irq_mask[word] |= (1 << (31 - bit)); in cpm2_unmask_irq()
71 int bit, word; in cpm2_mask_and_ack() local
74 bit = irq_to_siubit[irq_nr]; in cpm2_mask_and_ack()
79 ppc_cached_irq_mask[word] &= ~(1 << (31 - bit)); in cpm2_mask_and_ack()
81 sipnr[word] = 1 << (31 - bit); in cpm2_mask_and_ack()
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/linux-2.4.37.9/include/asm-mips/
Dsmp.h55 #define CPUMASK_SETB(p, bit) (p) |= 1UL << (bit) argument
56 #define CPUMASK_CLRB(p, bit) (p) &= ~(1UL << (bit)) argument
57 #define CPUMASK_TSTB(p, bit) ((p) & (1UL << (bit))) argument
65 #define CPUMASK_INDEX(bit) ((bit) >> 6) argument
66 #define CPUMASK_SHFT(bit) ((bit) & 0x3f) argument
73 #define CPUMASK_SETB(p, bit) (p)._bits[CPUMASK_INDEX(bit)] |= \ argument
74 (1UL << CPUMASK_SHFT(bit))
75 #define CPUMASK_CLRB(p, bit) (p)._bits[CPUMASK_INDEX(bit)] &= \ argument
76 ~(1UL << CPUMASK_SHFT(bit))
77 #define CPUMASK_TSTB(p, bit) ((p)._bits[CPUMASK_INDEX(bit)] & \ argument
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/linux-2.4.37.9/include/asm-mips64/
Dsmp.h55 #define CPUMASK_SETB(p, bit) (p) |= 1UL << (bit) argument
56 #define CPUMASK_CLRB(p, bit) (p) &= ~(1UL << (bit)) argument
57 #define CPUMASK_TSTB(p, bit) ((p) & (1UL << (bit))) argument
65 #define CPUMASK_INDEX(bit) ((bit) >> 6) argument
66 #define CPUMASK_SHFT(bit) ((bit) & 0x3f) argument
73 #define CPUMASK_SETB(p, bit) (p)._bits[CPUMASK_INDEX(bit)] |= \ argument
74 (1UL << CPUMASK_SHFT(bit))
75 #define CPUMASK_CLRB(p, bit) (p)._bits[CPUMASK_INDEX(bit)] &= \ argument
76 ~(1UL << CPUMASK_SHFT(bit))
77 #define CPUMASK_TSTB(p, bit) ((p)._bits[CPUMASK_INDEX(bit)] & \ argument
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/linux-2.4.37.9/arch/ia64/sn/io/sn2/
Dml_SN_intr.c157 int bit, in do_intr_reserve_level() argument
165 if (bit < 0) { in do_intr_reserve_level()
168 bit = i; in do_intr_reserve_level()
173 if (bit < 0) { /* ran out of irqs. Have to share. This will be rare. */ in do_intr_reserve_level()
181 bit = i; in do_intr_reserve_level()
185 if (bit < 0) { /* didn't find a matching device, just pick one. This will be */ in do_intr_reserve_level()
190 bit = i; in do_intr_reserve_level()
194 irqpdaindr->share_count[bit]++; in do_intr_reserve_level()
196 if (irqs->irq_flags[bit] & SN2_IRQ_SHARED) { in do_intr_reserve_level()
197 irqs->irq_flags[bit] |= SN2_IRQ_RESERVED; in do_intr_reserve_level()
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Dshub_intr.c186 int bit = intr_hdl->i_bit; in hub_intr_disconnect() local
194 rv = intr_disconnect_level(cpu, bit); in hub_intr_disconnect()
205 unsigned long bit; in sn_shub_redirect_intr() local
224 for (bit = 0; bit < 8; bit++) { in sn_shub_redirect_intr()
225 if (intr->bi_ibits & (1 << bit) ) { in sn_shub_redirect_intr()
228 int_enable &= ~bit; in sn_shub_redirect_intr()
231 host_addr = bridge->p_int_addr_64[bit]; in sn_shub_redirect_intr()
234 bridge->p_int_addr_64[bit] = host_addr; in sn_shub_redirect_intr()
236 int_enable |= bit; in sn_shub_redirect_intr()
239 bridge->b_force_pin[bit].intr = 1; in sn_shub_redirect_intr()
/linux-2.4.37.9/arch/alpha/kernel/
Dsys_sable.c43 void (*update_irq_hw)(unsigned long bit, unsigned long mask);
44 void (*ack_irq_hw)(unsigned long bit);
94 sable_update_irq_hw(unsigned long bit, unsigned long mask) in sable_update_irq_hw() argument
98 if (bit >= 16) { in sable_update_irq_hw()
101 } else if (bit >= 8) { in sable_update_irq_hw()
110 sable_ack_irq_hw(unsigned long bit) in sable_ack_irq_hw() argument
114 if (bit >= 16) { in sable_ack_irq_hw()
116 val1 = 0xE0 | (bit - 16); in sable_ack_irq_hw()
118 } else if (bit >= 8) { in sable_ack_irq_hw()
120 val1 = 0xE0 | (bit - 8); in sable_ack_irq_hw()
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/linux-2.4.37.9/Documentation/i2c/
Dten-bit-addresses1 The I2C protocol knows about two kinds of device addresses: normal 7 bit
2 addresses, and an extended set of 10 bit addresses. The sets of addresses
3 do not intersect: the 7 bit address 0x10 is not the same as the 10 bit
5 select a 10 bit address by adding an extra byte after the address
10 S is the start bit, Rd/Wr the read/write bit, and if you count the number
11 of bits, you will see the there are 8 after the S bit for 7 bit addresses,
12 and 16 after the S bit for 10 bit addresses.
14 WARNING! The current 10 bit address support is EXPERIMENTAL. There are
15 several places in the code that will cause SEVERE PROBLEMS with 10 bit
17 almost no supported adapter handles the 10 bit addresses correctly.
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Di2c-protocol6 S (1 bit) : Start bit
7 P (1 bit) : Stop bit
8 Rd/Wr (1 bit) : Read/Write bit. Rd equals 1, Wr equals 0.
9 A, NA (1 bit) : Accept and reverse accept bit.
10 Addr (7 bits): I2C 7 bit address. Note that this can be expanded as usual to
11 get a 10 bit I2C address.
15 for 16 bit data.
42 They are just like the above transactions, but instead of a stop bit P
43 a start bit S is sent and the transaction continues. An example of
/linux-2.4.37.9/arch/m68k/math-emu/
Dfp_emu.h52 #define fp_set_sr(bit) ({ \ argument
53 FPDATA->fpsr |= 1 << (bit); \
132 .macro fp_set_sr bit
133 bset #(\bit&7),(FPD_FPSR+3-(\bit/8),FPDATA)
136 .macro fp_clr_sr bit
137 bclr #(\bit&7),(FPD_FPSR+3-(\bit/8),FPDATA)
140 .macro fp_tst_sr bit
141 btst #(\bit&7),(FPD_FPSR+3-(\bit/8),FPDATA)
/linux-2.4.37.9/arch/sh/kernel/
Dled_7751se.c35 static unsigned bit = 0, up = 1; in heartbeat_7751se() local
51 if (bit == 7) { in heartbeat_7751se()
52 bit--; in heartbeat_7751se()
55 bit ++; in heartbeat_7751se()
58 if (bit == 0) { in heartbeat_7751se()
59 bit++; in heartbeat_7751se()
62 bit--; in heartbeat_7751se()
65 *p = 1<<(bit+8); in heartbeat_7751se()
Dled_se.c42 static unsigned bit = 0, up = 1; in heartbeat_se() local
58 if (bit == 7) { in heartbeat_se()
59 bit--; in heartbeat_se()
62 bit ++; in heartbeat_se()
65 if (bit == 0) { in heartbeat_se()
66 bit++; in heartbeat_se()
69 bit--; in heartbeat_se()
72 *p = 1<<(bit+8); in heartbeat_se()
Dsetup_cqreek.c51 unsigned short bit; /* Value of the bit */ member
60 unsigned short bit = cqreek_irq_data[irq].bit; in disable_cqreek_irq() local
64 mask = inw(mask_port) & ~bit; in disable_cqreek_irq()
74 unsigned short bit = cqreek_irq_data[irq].bit; in enable_cqreek_irq() local
78 mask = inw(mask_port) | bit; in enable_cqreek_irq()
86 unsigned short bit = cqreek_irq_data[irq].bit; in mask_and_ack_cqreek() local
91 outw_p(bit, stat_port); in mask_and_ack_cqreek()
130 cqreek_irq_data[14].bit = 1; in init_cqreek_IRQ()
143 cqreek_irq_data[10].bit = (1 << 10); in init_cqreek_IRQ()
/linux-2.4.37.9/include/asm-s390/
Dsystem.h171 #define __ctl_set_bit(cr, bit) ({ \ argument
186 : "=m" (dummy) : "a" (cr*17), "a" (1<<(bit)) \
190 #define __ctl_clear_bit(cr, bit) ({ \ argument
205 : "=m" (dummy) : "a" (cr*17), "a" (~(1<<(bit))) \
233 extern void smp_ctl_set_bit(int cr, int bit);
234 extern void smp_ctl_clear_bit(int cr, int bit);
235 #define ctl_set_bit(cr, bit) smp_ctl_set_bit(cr, bit) argument
236 #define ctl_clear_bit(cr, bit) smp_ctl_clear_bit(cr, bit) argument
247 #define ctl_set_bit(cr, bit) __ctl_set_bit(cr, bit) argument
248 #define ctl_clear_bit(cr, bit) __ctl_clear_bit(cr, bit) argument
/linux-2.4.37.9/include/asm-s390x/
Dsystem.h183 #define __ctl_set_bit(cr, bit) ({ \ argument
197 : "=m" (dummy) : "a" (cr*17), "a" (1L<<(bit)) \
201 #define __ctl_clear_bit(cr, bit) ({ \ argument
215 : "=m" (dummy) : "a" (cr*17), "a" (~(1L<<(bit))) \
244 extern void smp_ctl_set_bit(int cr, int bit);
245 extern void smp_ctl_clear_bit(int cr, int bit);
246 #define ctl_set_bit(cr, bit) smp_ctl_set_bit(cr, bit) argument
247 #define ctl_clear_bit(cr, bit) smp_ctl_clear_bit(cr, bit) argument
258 #define ctl_set_bit(cr, bit) __ctl_set_bit(cr, bit) argument
259 #define ctl_clear_bit(cr, bit) __ctl_clear_bit(cr, bit) argument
/linux-2.4.37.9/include/asm-ia64/
Dbitops.h33 __u32 bit, old, new; in set_bit() local
38 bit = 1 << (nr & 31); in set_bit()
42 new = old | bit; in set_bit()
105 __u32 bit, old, new; in change_bit() local
110 bit = (1 << (nr & 31)); in change_bit()
114 new = old ^ bit; in change_bit()
144 __u32 bit, old, new; in test_and_set_bit() local
149 bit = 1 << (nr & 31); in test_and_set_bit()
153 new = old | bit; in test_and_set_bit()
155 return (old & bit) != 0; in test_and_set_bit()
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/linux-2.4.37.9/Documentation/
Dhighuid.txt1 Notes on the change from 16-bit UIDs to 32-bit UIDs:
10 What's left to be done for 32-bit UIDs on all Linux architectures:
17 properly with huge UIDs. If it can deal with 64-bit file offsets on all
22 (currently, the old 16-bit UID and GID are still written to disk, and
23 part of the former pad space is used to store separate 32-bit UID and
26 - Need to validate that OS emulation calls the 16-bit UID
27 compatibility syscalls, if the OS being emulated used 16-bit UIDs, or
28 uses the 32-bit UID system calls properly otherwise.
36 (need to support whatever new 32-bit UID system calls are added to
41 At present, 32-bit UIDs _should_ work for:
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/linux-2.4.37.9/arch/cris/drivers/
DConfig.in59 int ' Ser0 DTR on PA bit (-1 = not used)' CONFIG_ETRAX_SER0_DTR_ON_PA_BIT 4
60 int ' Ser0 RI on PA bit (-1 = not used)' CONFIG_ETRAX_SER0_RI_ON_PA_BIT 5
61 int ' Ser0 DSR on PA bit (-1 = not used)' CONFIG_ETRAX_SER0_DSR_ON_PA_BIT 6
62 int ' Ser0 CD on PA bit (-1 = not used)' CONFIG_ETRAX_SER0_CD_ON_PA_BIT 7
71 int ' Ser0 DTR on PB bit (-1 = not used)' CONFIG_ETRAX_SER0_DTR_ON_PB_BIT 4
72 int ' Ser0 RI on PB bit (-1 = not used)' CONFIG_ETRAX_SER0_RI_ON_PB_BIT 5
73 int ' Ser0 DSR on PB bit (-1 = not used)' CONFIG_ETRAX_SER0_DSR_ON_PB_BIT 6
74 int ' Ser0 CD on PB bit (-1 = not used)' CONFIG_ETRAX_SER0_CD_ON_PB_BIT 7
102 int ' Ser1 DTR on PA bit (-1 = not used)' CONFIG_ETRAX_SER1_DTR_ON_PA_BIT 4
103 int ' Ser1 RI on PA bit (-1 = not used)' CONFIG_ETRAX_SER1_RI_ON_PA_BIT 5
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/linux-2.4.37.9/include/asm-x86_64/
Dcpufeature.h82 #define boot_cpu_has(bit) test_bit(bit, boot_cpu_data.x86_capability) argument
83 #define cpu_has(c, bit) test_bit(bit, (c)->x86_capability) argument
86 #define cpu_has(c, bit) test_bit(bit, (c)->x86_capability) argument
87 #define boot_cpu_has(bit) test_bit(bit, boot_cpu_data.x86_capability) argument
/linux-2.4.37.9/include/asm-m68k/
Dmath-emu.h108 #define dprint(bit, fmt, args...) ({ \ argument
109 if (fp_debugprint & (1 << (bit))) \
113 #define dprint(bit, fmt, args...) argument
237 .macro printf bit=-1,string,nr=0,arg1,arg2,arg3,arg4,arg5
245 .if \bit+1
247 moveq #\bit,%d0
249 btst %d0,fp_debugprint+((31-\bit)/8)
251 btst #\bit,fp_debugprint+((31-\bit)/8)
264 .macro printx bit,fp
273 .Lx1\@: printf \bit," %c",1,%d0
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/linux-2.4.37.9/arch/m68k/ifpsp060/
DCHANGES38 Inexact FPSR bit. Emulation now does not set Inexact for
86 bit 27 = 1 (misaligned bit)
87 bit 24 = 1 (read)
88 bit 23 = 0 (write)
89 bit 22:21 = 10 (SIZE = word)
90 bit 20:19 = 00 (TT)
91 bit 18:16 = x10 (TM; x = 1 for supervisor mode)
92 bit 15 = 1 (IO)
93 bit 0 = 1 (Software Emulation Error)
97 stated that ONLY "bit 0" would be set. The 060SP attempts to set a few
[all …]
/linux-2.4.37.9/arch/arm/nwfpe/
Dsoftfloat-macros35 bits are shifted off, they are ``jammed'' into the least significant bit of
36 the result by setting the least significant bit to 1. The value of `count'
60 bits are shifted off, they are ``jammed'' into the least significant bit of
61 the result by setting the least significant bit to 1. The value of `count'
87 Shifts the 128-bit value formed by concatenating `a0' and `a1' right by 64
90 bits shifted off form a second 64-bit result as follows: The _last_ bit
91 shifted off is the most-significant bit of the extra result, and the other
134 Shifts the 128-bit value formed by concatenating `a0' and `a1' right by the
137 than 128, the result will be 0. The result is broken into two 64-bit pieces
167 Shifts the 128-bit value formed by concatenating `a0' and `a1' right by the
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