1 #include <linux/stddef.h>
2 #include <linux/init.h>
3 #include <linux/sched.h>
4 #include <linux/signal.h>
5 #include <asm/irq.h>
6 #include <asm/immap_cpm2.h>
7 #include <asm/mpc8260.h>
8 #include "cpm2_pic.h"
9
10 /* The CPM2 internal interrupt controller. It is usually
11 * the only interrupt controller.
12 * There are two 32-bit registers (high/low) for up to 64
13 * possible interrupts.
14 *
15 * Now, the fun starts.....Interrupt Numbers DO NOT MAP
16 * in a simple arithmetic fashion to mask or pending registers.
17 * That is, interrupt 4 does not map to bit position 4.
18 * We create two tables, indexed by vector number, to indicate
19 * which register to use and which bit in the register to use.
20 */
21 static u_char irq_to_siureg[] = {
22 1, 1, 1, 1, 1, 1, 1, 1,
23 1, 1, 1, 1, 1, 1, 1, 1,
24 0, 0, 0, 0, 0, 0, 0, 0,
25 0, 0, 0, 0, 0, 0, 0, 0,
26 1, 1, 1, 1, 1, 1, 1, 1,
27 1, 1, 1, 1, 1, 1, 1, 1,
28 0, 0, 0, 0, 0, 0, 0, 0,
29 0, 0, 0, 0, 0, 0, 0, 0
30 };
31
32 static u_char irq_to_siubit[] = {
33 31, 16, 17, 18, 19, 20, 21, 22,
34 23, 24, 25, 26, 27, 28, 29, 30,
35 29, 30, 16, 17, 18, 19, 20, 21,
36 22, 23, 24, 25, 26, 27, 28, 31,
37 0, 1, 2, 3, 4, 5, 6, 7,
38 8, 9, 10, 11, 12, 13, 14, 15,
39 15, 14, 13, 12, 11, 10, 9, 8,
40 7, 6, 5, 4, 3, 2, 1, 0
41 };
42
cpm2_mask_irq(unsigned int irq_nr)43 static void cpm2_mask_irq(unsigned int irq_nr)
44 {
45 int bit, word;
46 volatile uint *simr;
47
48 bit = irq_to_siubit[irq_nr];
49 word = irq_to_siureg[irq_nr];
50
51 simr = &(cpm2_immr->im_intctl.ic_simrh);
52 ppc_cached_irq_mask[word] &= ~(1 << (31 - bit));
53 simr[word] = ppc_cached_irq_mask[word];
54 }
55
cpm2_unmask_irq(unsigned int irq_nr)56 static void cpm2_unmask_irq(unsigned int irq_nr)
57 {
58 int bit, word;
59 volatile uint *simr;
60
61 bit = irq_to_siubit[irq_nr];
62 word = irq_to_siureg[irq_nr];
63
64 simr = &(cpm2_immr->im_intctl.ic_simrh);
65 ppc_cached_irq_mask[word] |= (1 << (31 - bit));
66 simr[word] = ppc_cached_irq_mask[word];
67 }
68
cpm2_mask_and_ack(unsigned int irq_nr)69 static void cpm2_mask_and_ack(unsigned int irq_nr)
70 {
71 int bit, word;
72 volatile uint *simr, *sipnr;
73
74 bit = irq_to_siubit[irq_nr];
75 word = irq_to_siureg[irq_nr];
76
77 simr = &(cpm2_immr->im_intctl.ic_simrh);
78 sipnr = &(cpm2_immr->im_intctl.ic_sipnrh);
79 ppc_cached_irq_mask[word] &= ~(1 << (31 - bit));
80 simr[word] = ppc_cached_irq_mask[word];
81 sipnr[word] = 1 << (31 - bit);
82 }
83
cpm2_end_irq(unsigned int irq_nr)84 static void cpm2_end_irq(unsigned int irq_nr)
85 {
86 int bit, word;
87 volatile uint *simr;
88
89 if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS))) {
90
91 bit = irq_to_siubit[irq_nr];
92 word = irq_to_siureg[irq_nr];
93
94 simr = &(cpm2_immr->im_intctl.ic_simrh);
95 ppc_cached_irq_mask[word] |= (1 << (31 - bit));
96 simr[word] = ppc_cached_irq_mask[word];
97 }
98 }
99
100 struct hw_interrupt_type cpm2_pic = {
101 " CPM2 SIU ",
102 NULL,
103 NULL,
104 cpm2_unmask_irq,
105 cpm2_mask_irq,
106 cpm2_mask_and_ack,
107 cpm2_end_irq,
108 0
109 };
110
111 /* Return an interrupt vector or -1 if no interrupt is pending. */
112 int
cpm2_get_irq(struct pt_regs * regs)113 cpm2_get_irq(struct pt_regs *regs)
114 {
115 int irq;
116 unsigned long bits;
117
118 /* For CPM2, read the SIVEC register and shift the bits down
119 * to get the irq number. */
120 bits = cpm2_immr->im_intctl.ic_sivec;
121 irq = bits >> 26;
122
123 if (irq == 0) /* 0 --> no irq is pending */
124 irq = -1;
125
126 return irq;
127 }
128
129