1 #ifndef _ASM_IA64_BITOPS_H
2 #define _ASM_IA64_BITOPS_H
3
4 /*
5 * Copyright (C) 1998-2003 Hewlett-Packard Co
6 * David Mosberger-Tang <davidm@hpl.hp.com>
7 */
8
9 #include <linux/types.h>
10
11 #include <asm/intrinsics.h>
12
13 /**
14 * set_bit - Atomically set a bit in memory
15 * @nr: the bit to set
16 * @addr: the address to start counting from
17 *
18 * This function is atomic and may not be reordered. See __set_bit()
19 * if you do not require the atomic guarantees.
20 * Note that @nr may be almost arbitrarily large; this function is not
21 * restricted to acting on a single-word quantity.
22 *
23 * The address must be (at least) "long" aligned.
24 * Note that there are driver (e.g., eepro100) which use these operations to operate on
25 * hw-defined data-structures, so we can't easily change these operations to force a
26 * bigger alignment.
27 *
28 * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
29 */
30 static __inline__ void
set_bit(int nr,volatile void * addr)31 set_bit (int nr, volatile void *addr)
32 {
33 __u32 bit, old, new;
34 volatile __u32 *m;
35 CMPXCHG_BUGCHECK_DECL
36
37 m = (volatile __u32 *) addr + (nr >> 5);
38 bit = 1 << (nr & 31);
39 do {
40 CMPXCHG_BUGCHECK(m);
41 old = *m;
42 new = old | bit;
43 } while (cmpxchg_acq(m, old, new) != old);
44 }
45
46 /**
47 * __set_bit - Set a bit in memory
48 * @nr: the bit to set
49 * @addr: the address to start counting from
50 *
51 * Unlike set_bit(), this function is non-atomic and may be reordered.
52 * If it's called on the same region of memory simultaneously, the effect
53 * may be that only one operation succeeds.
54 */
55 static __inline__ void
__set_bit(int nr,volatile void * addr)56 __set_bit (int nr, volatile void *addr)
57 {
58 *((__u32 *) addr + (nr >> 5)) |= (1 << (nr & 31));
59 }
60
61 /*
62 * clear_bit() has "acquire" semantics.
63 */
64 #define smp_mb__before_clear_bit() smp_mb()
65 #define smp_mb__after_clear_bit() do { /* skip */; } while (0)
66
67 /**
68 * clear_bit - Clears a bit in memory
69 * @nr: Bit to clear
70 * @addr: Address to start counting from
71 *
72 * clear_bit() is atomic and may not be reordered. However, it does
73 * not contain a memory barrier, so if it is used for locking purposes,
74 * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
75 * in order to ensure changes are visible on other processors.
76 */
77 static __inline__ void
clear_bit(int nr,volatile void * addr)78 clear_bit (int nr, volatile void *addr)
79 {
80 __u32 mask, old, new;
81 volatile __u32 *m;
82 CMPXCHG_BUGCHECK_DECL
83
84 m = (volatile __u32 *) addr + (nr >> 5);
85 mask = ~(1 << (nr & 31));
86 do {
87 CMPXCHG_BUGCHECK(m);
88 old = *m;
89 new = old & mask;
90 } while (cmpxchg_acq(m, old, new) != old);
91 }
92
93 /**
94 * change_bit - Toggle a bit in memory
95 * @nr: Bit to clear
96 * @addr: Address to start counting from
97 *
98 * change_bit() is atomic and may not be reordered.
99 * Note that @nr may be almost arbitrarily large; this function is not
100 * restricted to acting on a single-word quantity.
101 */
102 static __inline__ void
change_bit(int nr,volatile void * addr)103 change_bit (int nr, volatile void *addr)
104 {
105 __u32 bit, old, new;
106 volatile __u32 *m;
107 CMPXCHG_BUGCHECK_DECL
108
109 m = (volatile __u32 *) addr + (nr >> 5);
110 bit = (1 << (nr & 31));
111 do {
112 CMPXCHG_BUGCHECK(m);
113 old = *m;
114 new = old ^ bit;
115 } while (cmpxchg_acq(m, old, new) != old);
116 }
117
118 /**
119 * __change_bit - Toggle a bit in memory
120 * @nr: the bit to set
121 * @addr: the address to start counting from
122 *
123 * Unlike change_bit(), this function is non-atomic and may be reordered.
124 * If it's called on the same region of memory simultaneously, the effect
125 * may be that only one operation succeeds.
126 */
127 static __inline__ void
__change_bit(int nr,volatile void * addr)128 __change_bit (int nr, volatile void *addr)
129 {
130 *((__u32 *) addr + (nr >> 5)) ^= (1 << (nr & 31));
131 }
132
133 /**
134 * test_and_set_bit - Set a bit and return its old value
135 * @nr: Bit to set
136 * @addr: Address to count from
137 *
138 * This operation is atomic and cannot be reordered.
139 * It also implies a memory barrier.
140 */
141 static __inline__ int
test_and_set_bit(int nr,volatile void * addr)142 test_and_set_bit (int nr, volatile void *addr)
143 {
144 __u32 bit, old, new;
145 volatile __u32 *m;
146 CMPXCHG_BUGCHECK_DECL
147
148 m = (volatile __u32 *) addr + (nr >> 5);
149 bit = 1 << (nr & 31);
150 do {
151 CMPXCHG_BUGCHECK(m);
152 old = *m;
153 new = old | bit;
154 } while (cmpxchg_acq(m, old, new) != old);
155 return (old & bit) != 0;
156 }
157
158 /**
159 * __test_and_set_bit - Set a bit and return its old value
160 * @nr: Bit to set
161 * @addr: Address to count from
162 *
163 * This operation is non-atomic and can be reordered.
164 * If two examples of this operation race, one can appear to succeed
165 * but actually fail. You must protect multiple accesses with a lock.
166 */
167 static __inline__ int
__test_and_set_bit(int nr,volatile void * addr)168 __test_and_set_bit (int nr, volatile void *addr)
169 {
170 __u32 *p = (__u32 *) addr + (nr >> 5);
171 __u32 m = 1 << (nr & 31);
172 int oldbitset = (*p & m) != 0;
173
174 *p |= m;
175 return oldbitset;
176 }
177
178 /**
179 * test_and_clear_bit - Clear a bit and return its old value
180 * @nr: Bit to set
181 * @addr: Address to count from
182 *
183 * This operation is atomic and cannot be reordered.
184 * It also implies a memory barrier.
185 */
186 static __inline__ int
test_and_clear_bit(int nr,volatile void * addr)187 test_and_clear_bit (int nr, volatile void *addr)
188 {
189 __u32 mask, old, new;
190 volatile __u32 *m;
191 CMPXCHG_BUGCHECK_DECL
192
193 m = (volatile __u32 *) addr + (nr >> 5);
194 mask = ~(1 << (nr & 31));
195 do {
196 CMPXCHG_BUGCHECK(m);
197 old = *m;
198 new = old & mask;
199 } while (cmpxchg_acq(m, old, new) != old);
200 return (old & ~mask) != 0;
201 }
202
203 /**
204 * __test_and_clear_bit - Clear a bit and return its old value
205 * @nr: Bit to set
206 * @addr: Address to count from
207 *
208 * This operation is non-atomic and can be reordered.
209 * If two examples of this operation race, one can appear to succeed
210 * but actually fail. You must protect multiple accesses with a lock.
211 */
212 static __inline__ int
__test_and_clear_bit(int nr,volatile void * addr)213 __test_and_clear_bit(int nr, volatile void * addr)
214 {
215 __u32 *p = (__u32 *) addr + (nr >> 5);
216 __u32 m = 1 << (nr & 31);
217 int oldbitset = *p & m;
218
219 *p &= ~m;
220 return oldbitset;
221 }
222
223 /**
224 * test_and_change_bit - Change a bit and return its new value
225 * @nr: Bit to set
226 * @addr: Address to count from
227 *
228 * This operation is atomic and cannot be reordered.
229 * It also implies a memory barrier.
230 */
231 static __inline__ int
test_and_change_bit(int nr,volatile void * addr)232 test_and_change_bit (int nr, volatile void *addr)
233 {
234 __u32 bit, old, new;
235 volatile __u32 *m;
236 CMPXCHG_BUGCHECK_DECL
237
238 m = (volatile __u32 *) addr + (nr >> 5);
239 bit = (1 << (nr & 31));
240 do {
241 CMPXCHG_BUGCHECK(m);
242 old = *m;
243 new = old ^ bit;
244 } while (cmpxchg_acq(m, old, new) != old);
245 return (old & bit) != 0;
246 }
247
248 /*
249 * WARNING: non atomic version.
250 */
251 static __inline__ int
__test_and_change_bit(int nr,void * addr)252 __test_and_change_bit (int nr, void *addr)
253 {
254 __u32 old, bit = (1 << (nr & 31));
255 __u32 *m = (__u32 *) addr + (nr >> 5);
256
257 old = *m;
258 *m = old ^ bit;
259 return (old & bit) != 0;
260 }
261
262 static __inline__ int
test_bit(int nr,const volatile void * addr)263 test_bit (int nr, const volatile void *addr)
264 {
265 return 1 & (((const volatile __u32 *) addr)[nr >> 5] >> (nr & 31));
266 }
267
268 /**
269 * ffz - find the first zero bit in a memory region
270 * @x: The address to start the search at
271 *
272 * Returns the bit-number (0..63) of the first (least significant) zero bit, not
273 * the number of the byte containing a bit. Undefined if no zero exists, so
274 * code should check against ~0UL first...
275 */
276 static inline unsigned long
ffz(unsigned long x)277 ffz (unsigned long x)
278 {
279 unsigned long result;
280
281 __asm__ ("popcnt %0=%1" : "=r" (result) : "r" (x & (~x - 1)));
282 return result;
283 }
284
285 /**
286 * __ffs - find first bit in word.
287 * @x: The word to search
288 *
289 * Undefined if no bit exists, so code should check against 0 first.
290 */
291 static __inline__ unsigned long
__ffs(unsigned long x)292 __ffs (unsigned long x)
293 {
294 unsigned long result;
295
296 __asm__ ("popcnt %0=%1" : "=r" (result) : "r" ((x - 1) & ~x));
297 return result;
298 }
299
300 #ifdef __KERNEL__
301
302 /*
303 * find_last_zero_bit - find the last zero bit in a 64 bit quantity
304 * @x: The value to search
305 */
306 static inline unsigned long
ia64_fls(unsigned long x)307 ia64_fls (unsigned long x)
308 {
309 long double d = x;
310 long exp;
311
312 __asm__ ("getf.exp %0=%1" : "=r"(exp) : "f"(d));
313 return exp - 0xffff;
314 }
315
316 /*
317 * ffs: find first bit set. This is defined the same way as the libc and compiler builtin
318 * ffs routines, therefore differs in spirit from the above ffz (man ffs): it operates on
319 * "int" values only and the result value is the bit number + 1. ffs(0) is defined to
320 * return zero.
321 */
322 #define ffs(x) __builtin_ffs(x)
323
324 /*
325 * hweightN: returns the hamming weight (i.e. the number
326 * of bits set) of a N-bit word
327 */
328 static __inline__ unsigned long
hweight64(unsigned long x)329 hweight64 (unsigned long x)
330 {
331 unsigned long result;
332 __asm__ ("popcnt %0=%1" : "=r" (result) : "r" (x));
333 return result;
334 }
335
336 #define hweight32(x) hweight64 ((x) & 0xfffffffful)
337 #define hweight16(x) hweight64 ((x) & 0xfffful)
338 #define hweight8(x) hweight64 ((x) & 0xfful)
339
340 #endif /* __KERNEL__ */
341
342 /*
343 * Find next zero bit in a bitmap reasonably efficiently..
344 */
345 static inline unsigned long
find_next_zero_bit(void * addr,unsigned long size,unsigned long offset)346 find_next_zero_bit (void *addr, unsigned long size, unsigned long offset)
347 {
348 unsigned long *p = ((unsigned long *) addr) + (offset >> 6);
349 unsigned long result = offset & ~63UL;
350 unsigned long tmp;
351
352 if (offset >= size)
353 return size;
354 size -= result;
355 offset &= 63UL;
356 if (offset) {
357 tmp = *(p++);
358 tmp |= ~0UL >> (64-offset);
359 if (size < 64)
360 goto found_first;
361 if (~tmp)
362 goto found_middle;
363 size -= 64;
364 result += 64;
365 }
366 while (size & ~63UL) {
367 if (~(tmp = *(p++)))
368 goto found_middle;
369 result += 64;
370 size -= 64;
371 }
372 if (!size)
373 return result;
374 tmp = *p;
375 found_first:
376 tmp |= ~0UL << size;
377 if (tmp == ~0UL) /* any bits zero? */
378 return result + size; /* nope */
379 found_middle:
380 return result + ffz(tmp);
381 }
382
383 /*
384 * The optimizer actually does good code for this case..
385 */
386 #define find_first_zero_bit(addr, size) find_next_zero_bit((addr), (size), 0)
387
388 #ifdef __KERNEL__
389
390 #define ext2_set_bit test_and_set_bit
391 #define ext2_clear_bit test_and_clear_bit
392 #define ext2_test_bit test_bit
393 #define ext2_find_first_zero_bit find_first_zero_bit
394 #define ext2_find_next_zero_bit find_next_zero_bit
395
396 /* Bitmap functions for the minix filesystem. */
397 #define minix_test_and_set_bit(nr,addr) test_and_set_bit(nr,addr)
398 #define minix_set_bit(nr,addr) set_bit(nr,addr)
399 #define minix_test_and_clear_bit(nr,addr) test_and_clear_bit(nr,addr)
400 #define minix_test_bit(nr,addr) test_bit(nr,addr)
401 #define minix_find_first_zero_bit(addr,size) find_first_zero_bit(addr,size)
402
403 #endif /* __KERNEL__ */
404
405 #endif /* _ASM_IA64_BITOPS_H */
406