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Searched refs:TXS (Results 1 – 8 of 8) sorted by relevance

/linux-2.4.37.9/drivers/net/wan/
Dhd64570.h68 #define TXS 0x17 /* TX Clock Source */ macro
Dhd64572.h61 #define TXS 0x13d /* TX clock source */ macro
Dc101.c150 sca_out(txs, msci + TXS, port); in c101_set_iface()
Dhd6457x.c486 sca_out(port->txs, msci + TXS, card); in sca_set_port()
584 sca_out(port->txs, msci + TXS, card); in sca_open()
Dpci200syn.c170 sca_out(txs, msci + TXS, card); in pci200_set_iface()
Dn2.c208 sca_out(txs, msci + TXS, card); in n2_set_iface()
Dpc300_drv.c2285 cpc_readb(scabase + M_REG(TXS, ch)), in cpc_sca_status()
2751 cpc_writeb(scabase + M_REG(TXS, ch), in ch_config()
2770 cpc_writeb(scabase + M_REG(TXS, ch), in ch_config()
2773 cpc_writeb(scabase + M_REG(TXS, ch), in ch_config()
2790 cpc_writeb(scabase + M_REG(TXS, ch), 0); in ch_config()
/linux-2.4.37.9/drivers/char/
Dsynclinkmp.c355 #define TXS 0x37 macro
4063 write_reg(info, TXS, 0x40); in enable_loopback()
4077 write_reg(info, TXS, 0x00); in enable_loopback()
4123 write_reg(info, TXS, in set_rate()
4124 (unsigned char)((read_reg(info, TXS) & 0xf0) | BRValue)); in set_rate()
4130 write_reg(info, TXS,0); in set_rate()
4469 write_reg(info, TXS, RegValue); in async_mode()
4643 write_reg(info, TXS, RegValue); in hdlc_mode()