1 /*
2 * Goramo PCI200SYN synchronous serial card driver for Linux
3 *
4 * Copyright (C) 2002-2003 Krzysztof Halasa <khc@pm.waw.pl>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of version 2 of the GNU General Public License
8 * as published by the Free Software Foundation.
9 *
10 * For information see http://hq.pm.waw.pl/hdlc/
11 *
12 * Sources of information:
13 * Hitachi HD64572 SCA-II User's Manual
14 * PLX Technology Inc. PCI9052 Data Book
15 */
16
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/slab.h>
20 #include <linux/sched.h>
21 #include <linux/types.h>
22 #include <linux/fcntl.h>
23 #include <linux/in.h>
24 #include <linux/string.h>
25 #include <linux/errno.h>
26 #include <linux/init.h>
27 #include <linux/ioport.h>
28 #include <linux/netdevice.h>
29 #include <linux/hdlc.h>
30 #include <linux/pci.h>
31 #include <asm/delay.h>
32 #include <asm/io.h>
33
34 #include "hd64572.h"
35
36 static const char* version = "Goramo PCI200SYN driver version: 1.14c";
37 static const char* devname = "PCI200SYN";
38
39 #undef DEBUG_PKT
40 #define DEBUG_RINGS
41
42 #define PCI200SYN_PLX_SIZE 0x80 /* PLX control window size (128b) */
43 #define PCI200SYN_SCA_SIZE 0x400 /* SCA window size (1Kb) */
44 #define ALL_PAGES_ALWAYS_MAPPED
45 #define NEED_DETECT_RAM
46 #define MAX_TX_BUFFERS 10
47
48 static int pci_clock_freq = 33000000;
49 #define CLOCK_BASE pci_clock_freq
50
51 #define PCI_VENDOR_ID_GORAMO 0x10B5 /* uses PLX:9050 ID - this card */
52 #define PCI_DEVICE_ID_PCI200SYN 0x9050 /* doesn't have its own ID */
53
54
55 /*
56 * PLX PCI9052 local configuration and shared runtime registers.
57 * This structure can be used to access 9052 registers (memory mapped).
58 */
59 typedef struct {
60 u32 loc_addr_range[4]; /* 00-0Ch : Local Address Ranges */
61 u32 loc_rom_range; /* 10h : Local ROM Range */
62 u32 loc_addr_base[4]; /* 14-20h : Local Address Base Addrs */
63 u32 loc_rom_base; /* 24h : Local ROM Base */
64 u32 loc_bus_descr[4]; /* 28-34h : Local Bus Descriptors */
65 u32 rom_bus_descr; /* 38h : ROM Bus Descriptor */
66 u32 cs_base[4]; /* 3C-48h : Chip Select Base Addrs */
67 u32 intr_ctrl_stat; /* 4Ch : Interrupt Control/Status */
68 u32 init_ctrl; /* 50h : EEPROM ctrl, Init Ctrl, etc */
69 }plx9052;
70
71
72
73 typedef struct port_s {
74 hdlc_device hdlc; /* HDLC device struct - must be first */
75 struct card_s *card;
76 spinlock_t lock; /* TX lock */
77 sync_serial_settings settings;
78 int rxpart; /* partial frame received, next frame invalid*/
79 unsigned short encoding;
80 unsigned short parity;
81 u16 rxin; /* rx ring buffer 'in' pointer */
82 u16 txin; /* tx ring buffer 'in' and 'last' pointers */
83 u16 txlast;
84 u8 rxs, txs, tmc; /* SCA registers */
85 u8 phy_node; /* physical port # - 0 or 1 */
86 }port_t;
87
88
89
90 typedef struct card_s {
91 u8* rambase; /* buffer memory base (virtual) */
92 u8* scabase; /* SCA memory base (virtual) */
93 plx9052* plxbase; /* PLX registers memory base (virtual) */
94 u16 rx_ring_buffers; /* number of buffers in a ring */
95 u16 tx_ring_buffers;
96 u16 buff_offset; /* offset of first buffer of first channel */
97 u8 irq; /* interrupt request level */
98
99 port_t ports[2];
100 }card_t;
101
102
103 #define sca_in(reg, card) readb(card->scabase + (reg))
104 #define sca_out(value, reg, card) writeb(value, card->scabase + (reg))
105 #define sca_inw(reg, card) readw(card->scabase + (reg))
106 #define sca_outw(value, reg, card) writew(value, card->scabase + (reg))
107 #define sca_inl(reg, card) readl(card->scabase + (reg))
108 #define sca_outl(value, reg, card) writel(value, card->scabase + (reg))
109
110 #define port_to_card(port) (port->card)
111 #define log_node(port) (port->phy_node)
112 #define phy_node(port) (port->phy_node)
113 #define winbase(card) (card->rambase)
114 #define get_port(card, port) (&card->ports[port])
115 #define sca_flush(card) (sca_in(IER0, card));
116
new_memcpy_toio(char * dest,char * src,int length)117 static inline void new_memcpy_toio(char *dest, char *src, int length)
118 {
119 int len;
120 do {
121 len = length > 256 ? 256 : length;
122 memcpy_toio(dest, src, len);
123 dest += len;
124 src += len;
125 length -= len;
126 readb(dest);
127 } while (len);
128 }
129
130 #undef memcpy_toio
131 #define memcpy_toio new_memcpy_toio
132
133 #include "hd6457x.c"
134
135
pci200_set_iface(port_t * port)136 static void pci200_set_iface(port_t *port)
137 {
138 card_t *card = port->card;
139 u16 msci = get_msci(port);
140 u8 rxs = port->rxs & CLK_BRG_MASK;
141 u8 txs = port->txs & CLK_BRG_MASK;
142
143 sca_out(EXS_TES1, (phy_node(port) ? MSCI1_OFFSET : MSCI0_OFFSET) + EXS,
144 port_to_card(port));
145 switch(port->settings.clock_type) {
146 case CLOCK_INT:
147 rxs |= CLK_BRG; /* BRG output */
148 txs |= CLK_PIN_OUT | CLK_TX_RXCLK; /* RX clock */
149 break;
150
151 case CLOCK_TXINT:
152 rxs |= CLK_LINE; /* RXC input */
153 txs |= CLK_PIN_OUT | CLK_BRG; /* BRG output */
154 break;
155
156 case CLOCK_TXFROMRX:
157 rxs |= CLK_LINE; /* RXC input */
158 txs |= CLK_PIN_OUT | CLK_TX_RXCLK; /* RX clock */
159 break;
160
161 default: /* EXTernal clock */
162 rxs |= CLK_LINE; /* RXC input */
163 txs |= CLK_PIN_OUT | CLK_LINE; /* TXC input */
164 break;
165 }
166
167 port->rxs = rxs;
168 port->txs = txs;
169 sca_out(rxs, msci + RXS, card);
170 sca_out(txs, msci + TXS, card);
171 sca_set_port(port);
172 }
173
174
175
pci200_open(struct net_device * dev)176 static int pci200_open(struct net_device *dev)
177 {
178 hdlc_device *hdlc = dev_to_hdlc(dev);
179 port_t *port = hdlc_to_port(hdlc);
180
181 int result = hdlc_open(hdlc);
182 if (result)
183 return result;
184
185 MOD_INC_USE_COUNT;
186 sca_open(hdlc);
187 pci200_set_iface(port);
188 sca_flush(port_to_card(port));
189 return 0;
190 }
191
192
193
pci200_close(struct net_device * dev)194 static int pci200_close(struct net_device *dev)
195 {
196 hdlc_device *hdlc = dev_to_hdlc(dev);
197 sca_close(hdlc);
198 sca_flush(port_to_card(dev_to_port(dev)));
199 hdlc_close(hdlc);
200 MOD_DEC_USE_COUNT;
201 return 0;
202 }
203
204
205
pci200_ioctl(struct net_device * dev,struct ifreq * ifr,int cmd)206 static int pci200_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
207 {
208 const size_t size = sizeof(sync_serial_settings);
209 sync_serial_settings new_line, *line = ifr->ifr_settings.ifs_ifsu.sync;
210 hdlc_device *hdlc = dev_to_hdlc(dev);
211 port_t *port = hdlc_to_port(hdlc);
212
213 #ifdef DEBUG_RINGS
214 if (cmd == SIOCDEVPRIVATE) {
215 sca_dump_rings(hdlc);
216 return 0;
217 }
218 #endif
219 if (cmd != SIOCWANDEV)
220 return hdlc_ioctl(dev, ifr, cmd);
221
222 switch(ifr->ifr_settings.type) {
223 case IF_GET_IFACE:
224 ifr->ifr_settings.type = IF_IFACE_V35;
225 if (ifr->ifr_settings.size < size) {
226 ifr->ifr_settings.size = size; /* data size wanted */
227 return -ENOBUFS;
228 }
229 if (copy_to_user(line, &port->settings, size))
230 return -EFAULT;
231 return 0;
232
233 case IF_IFACE_V35:
234 case IF_IFACE_SYNC_SERIAL:
235 if (!capable(CAP_NET_ADMIN))
236 return -EPERM;
237
238 if (copy_from_user(&new_line, line, size))
239 return -EFAULT;
240
241 if (new_line.clock_type != CLOCK_EXT &&
242 new_line.clock_type != CLOCK_TXFROMRX &&
243 new_line.clock_type != CLOCK_INT &&
244 new_line.clock_type != CLOCK_TXINT)
245 return -EINVAL; /* No such clock setting */
246
247 if (new_line.loopback != 0 && new_line.loopback != 1)
248 return -EINVAL;
249
250 memcpy(&port->settings, &new_line, size); /* Update settings */
251 pci200_set_iface(port);
252 sca_flush(port_to_card(port));
253 return 0;
254
255 default:
256 return hdlc_ioctl(dev, ifr, cmd);
257 }
258 }
259
260
261
pci200_pci_remove_one(struct pci_dev * pdev)262 static void pci200_pci_remove_one(struct pci_dev *pdev)
263 {
264 int i;
265 card_t *card = pci_get_drvdata(pdev);
266
267 for(i = 0; i < 2; i++)
268 if (card->ports[i].card)
269 unregister_hdlc_device(&card->ports[i].hdlc);
270
271 if (card->irq)
272 free_irq(card->irq, card);
273
274 if (card->rambase)
275 iounmap(card->rambase);
276 if (card->scabase)
277 iounmap(card->scabase);
278 if (card->plxbase)
279 iounmap(card->plxbase);
280
281 pci_release_regions(pdev);
282 pci_disable_device(pdev);
283 pci_set_drvdata(pdev, NULL);
284 kfree(card);
285 }
286
287
288
pci200_pci_init_one(struct pci_dev * pdev,const struct pci_device_id * ent)289 static int __devinit pci200_pci_init_one(struct pci_dev *pdev,
290 const struct pci_device_id *ent)
291 {
292 card_t *card;
293 u8 rev_id;
294 u32 *p;
295 int i;
296 u32 ramsize;
297 u32 ramphys; /* buffer memory base */
298 u32 scaphys; /* SCA memory base */
299 u32 plxphys; /* PLX registers memory base */
300
301 #ifndef MODULE
302 static int printed_version;
303 if (!printed_version++)
304 printk(KERN_INFO "%s\n", version);
305 #endif
306
307 i = pci_enable_device(pdev);
308 if (i)
309 return i;
310
311 i = pci_request_regions(pdev, "PCI200SYN");
312 if (i) {
313 pci_disable_device(pdev);
314 return i;
315 }
316
317 card = kmalloc(sizeof(card_t), GFP_KERNEL);
318 if (card == NULL) {
319 printk(KERN_ERR "pci200syn: unable to allocate memory\n");
320 pci_release_regions(pdev);
321 pci_disable_device(pdev);
322 return -ENOBUFS;
323 }
324 memset(card, 0, sizeof(card_t));
325 pci_set_drvdata(pdev, card);
326
327 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
328 if (pci_resource_len(pdev, 0) != PCI200SYN_PLX_SIZE ||
329 pci_resource_len(pdev, 2) != PCI200SYN_SCA_SIZE ||
330 pci_resource_len(pdev, 3) < 16384) {
331 printk(KERN_ERR "pci200syn: invalid card EEPROM parameters\n");
332 pci200_pci_remove_one(pdev);
333 return -EFAULT;
334 }
335
336 plxphys = pci_resource_start(pdev,0) & PCI_BASE_ADDRESS_MEM_MASK;
337 card->plxbase = ioremap(plxphys, PCI200SYN_PLX_SIZE);
338
339 scaphys = pci_resource_start(pdev,2) & PCI_BASE_ADDRESS_MEM_MASK;
340 card->scabase = ioremap(scaphys, PCI200SYN_SCA_SIZE);
341
342 ramphys = pci_resource_start(pdev,3) & PCI_BASE_ADDRESS_MEM_MASK;
343 card->rambase = ioremap(ramphys, pci_resource_len(pdev,3));
344
345 if (card->plxbase == NULL ||
346 card->scabase == NULL ||
347 card->rambase == NULL) {
348 printk(KERN_ERR "pci200syn: ioremap() failed\n");
349 pci200_pci_remove_one(pdev);
350 }
351
352 /* Reset PLX */
353 p = &card->plxbase->init_ctrl;
354 writel(readl(p) | 0x40000000, p);
355 readl(p); /* Flush the write - do not use sca_flush */
356 udelay(1);
357
358 writel(readl(p) & ~0x40000000, p);
359 readl(p); /* Flush the write - do not use sca_flush */
360 udelay(1);
361
362 ramsize = sca_detect_ram(card, card->rambase,
363 pci_resource_len(pdev, 3));
364
365 /* number of TX + RX buffers for one port - this is dual port card */
366 i = ramsize / (2 * (sizeof(pkt_desc) + HDLC_MAX_MRU));
367 card->tx_ring_buffers = min(i / 2, MAX_TX_BUFFERS);
368 card->rx_ring_buffers = i - card->tx_ring_buffers;
369
370 card->buff_offset = 2 * sizeof(pkt_desc) * (card->tx_ring_buffers +
371 card->rx_ring_buffers);
372
373 printk(KERN_INFO "pci200syn: %u KB RAM at 0x%x, IRQ%u, using %u TX +"
374 " %u RX packets rings\n", ramsize / 1024, ramphys,
375 pdev->irq, card->tx_ring_buffers, card->rx_ring_buffers);
376
377 if (card->tx_ring_buffers < 1) {
378 printk(KERN_ERR "pci200syn: RAM test failed\n");
379 pci200_pci_remove_one(pdev);
380 return -EFAULT;
381 }
382
383 /* Enable interrupts on the PCI bridge */
384 p = &card->plxbase->intr_ctrl_stat;
385 writew(readw(p) | 0x0040, p);
386
387 /* Allocate IRQ */
388 if (request_irq(pdev->irq, sca_intr, SA_SHIRQ, devname, card)) {
389 printk(KERN_WARNING "pci200syn: could not allocate IRQ%d.\n",
390 pdev->irq);
391 pci200_pci_remove_one(pdev);
392 return -EBUSY;
393 }
394 card->irq = pdev->irq;
395
396 sca_init(card, 0);
397
398 for(i = 0; i < 2; i++) {
399 port_t *port = &card->ports[i];
400 struct net_device *dev = hdlc_to_dev(&port->hdlc);
401 port->phy_node = i;
402
403 spin_lock_init(&port->lock);
404 SET_MODULE_OWNER(dev);
405 dev->irq = card->irq;
406 dev->mem_start = ramphys;
407 dev->mem_end = ramphys + ramsize - 1;
408 dev->tx_queue_len = 50;
409 dev->do_ioctl = pci200_ioctl;
410 dev->open = pci200_open;
411 dev->stop = pci200_close;
412 port->hdlc.attach = sca_attach;
413 port->hdlc.xmit = sca_xmit;
414 port->settings.clock_type = CLOCK_EXT;
415 if (register_hdlc_device(&port->hdlc)) {
416 printk(KERN_ERR "pci200syn: unable to register hdlc "
417 "device\n");
418 pci200_pci_remove_one(pdev);
419 return -ENOBUFS;
420 }
421 port->card = card;
422 sca_init_sync_port(port); /* Set up SCA memory */
423
424 printk(KERN_INFO "%s: PCI200SYN node %d\n",
425 hdlc_to_name(&port->hdlc), port->phy_node);
426 }
427
428 sca_flush(card);
429 return 0;
430 }
431
432
433
434 static struct pci_device_id pci200_pci_tbl[] __devinitdata = {
435 { PCI_VENDOR_ID_GORAMO, PCI_DEVICE_ID_PCI200SYN, PCI_ANY_ID,
436 PCI_ANY_ID, 0, 0, 0 },
437 { 0, }
438 };
439
440
441 static struct pci_driver pci200_pci_driver = {
442 name: "PCI200SYN",
443 id_table: pci200_pci_tbl,
444 probe: pci200_pci_init_one,
445 remove: pci200_pci_remove_one,
446 };
447
448
pci200_init_module(void)449 static int __init pci200_init_module(void)
450 {
451 #ifdef MODULE
452 printk(KERN_INFO "%s\n", version);
453 #endif
454 if (pci_clock_freq < 1000000 || pci_clock_freq > 80000000) {
455 printk(KERN_ERR "pci200syn: Invalid PCI clock frequency\n");
456 return -EINVAL;
457 }
458 return pci_module_init(&pci200_pci_driver);
459 }
460
461
462
pci200_cleanup_module(void)463 static void __exit pci200_cleanup_module(void)
464 {
465 pci_unregister_driver(&pci200_pci_driver);
466 }
467
468 MODULE_AUTHOR("Krzysztof Halasa <khc@pm.waw.pl>");
469 MODULE_DESCRIPTION("Goramo PCI200SYN serial port driver");
470 MODULE_LICENSE("GPL v2");
471 MODULE_DEVICE_TABLE(pci, pci200_pci_tbl);
472 MODULE_PARM(pci_clock_freq, "i");
473 MODULE_PARM_DESC(pci_clock_freq, "System PCI clock frequency in Hz");
474 EXPORT_NO_SYMBOLS;
475 module_init(pci200_init_module);
476 module_exit(pci200_cleanup_module);
477