1 #define USE_PCI_CLOCK
2 static char rcsid[] =
3 // Important note:
4 // This string must have this exact format, including the space on its end
5 "Revision: 4.1.0 Date: 2003/11/19 ";
6
7 /*
8 * pc300.c Cyclades-PC300(tm) Driver.
9 *
10 * Author: Ivan Passos <ivan.passos@cyclades.com>
11 * Maintainer: PC300 Maintainer <pc300@cyclades.com>
12 *
13 * Copyright: (c) 1999-2003 Cyclades Corp.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
19 */
20
21 #include <linux/module.h>
22 #include <linux/kernel.h>
23 #include <linux/mm.h>
24 #include <linux/ioport.h>
25 #include <linux/pci.h>
26 #include <linux/errno.h>
27 #include <linux/string.h>
28 #include <linux/sched.h>
29 #include <linux/init.h>
30 #include <linux/delay.h>
31 #include <linux/net.h>
32 #include <linux/skbuff.h>
33 #include <linux/if_arp.h>
34 #include <linux/netdevice.h>
35 #include <linux/spinlock.h>
36 #include <linux/if.h>
37 #include <linux/version.h>
38 #include <net/arp.h>
39 #include <asm/io.h>
40 #include <asm/uaccess.h>
41 #include <net/syncppp.h>
42
43 #include "pc300.h"
44
45 #define CPC_LOCK(card,flags) \
46 do { \
47 spin_lock_irqsave(&card->card_lock, flags); \
48 } while (0)
49
50 #define CPC_UNLOCK(card,flags) \
51 do { \
52 spin_unlock_irqrestore(&card->card_lock, flags); \
53 } while (0)
54
55 #undef PC300_DEBUG_PCI
56 #undef PC300_DEBUG_INTR
57 #undef PC300_DEBUG_TX
58 #undef PC300_DEBUG_RX
59 #undef PC300_DEBUG_OTHER
60
61 static struct pci_device_id cpc_pci_dev_id[] __devinitdata = {
62 /* PC300/RSV or PC300/X21, 2 chan */
63 {0x120e, 0x300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x300},
64 /* PC300/RSV or PC300/X21, 1 chan */
65 {0x120e, 0x301, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x301},
66 /* PC300/TE, 2 chan */
67 {0x120e, 0x310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x310},
68 /* PC300/TE, 1 chan */
69 {0x120e, 0x311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x311},
70 /* PC300/TE-M, 2 chan */
71 {0x120e, 0x320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x320},
72 /* PC300/TE-M, 1 chan */
73 {0x120e, 0x321, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x321},
74 /* End of table */
75 {0,},
76 };
77 MODULE_DEVICE_TABLE(pci, cpc_pci_dev_id);
78
79 #ifndef cpc_min
80 #define cpc_min(a,b) (((a)<(b))?(a):(b))
81 #endif
82 #ifndef cpc_max
83 #define cpc_max(a,b) (((a)>(b))?(a):(b))
84 #endif
85
86 /* prototypes */
87 static void tx_dma_buf_pt_init(pc300_t *, int);
88 static void tx_dma_buf_init(pc300_t *, int);
89 static void rx_dma_buf_pt_init(pc300_t *, int);
90 static void rx_dma_buf_init(pc300_t *, int);
91 static void tx_dma_buf_check(pc300_t *, int);
92 static void rx_dma_buf_check(pc300_t *, int);
93 static void cpc_intr(int, void *, struct pt_regs *);
94 static struct net_device_stats *cpc_get_stats(struct net_device *);
95 static int clock_rate_calc(uclong, uclong, int *);
96 static uclong detect_ram(pc300_t *);
97 static void plx_init(pc300_t *);
98 static void cpc_trace(struct net_device *, struct sk_buff *, char);
99 static int cpc_attach(hdlc_device *, unsigned short, unsigned short);
100
101 #ifdef CONFIG_PC300_MLPPP
102 void cpc_tty_init(pc300dev_t * dev);
103 void cpc_tty_unregister_service(pc300dev_t * pc300dev);
104 void cpc_tty_receive(pc300dev_t * pc300dev);
105 void cpc_tty_trigger_poll(pc300dev_t * pc300dev);
106 void cpc_tty_reset_var(void);
107 #endif
108
109 /************************/
110 /*** DMA Routines ***/
111 /************************/
tx_dma_buf_pt_init(pc300_t * card,int ch)112 static void tx_dma_buf_pt_init(pc300_t * card, int ch)
113 {
114 int i;
115 int ch_factor = ch * N_DMA_TX_BUF;
116 volatile pcsca_bd_t *ptdescr = (pcsca_bd_t *) (card->hw.rambase
117 + DMA_TX_BD_BASE + ch_factor * sizeof(pcsca_bd_t));
118
119 for (i = 0; i < N_DMA_TX_BUF; i++, ptdescr++) {
120 cpc_writel(&ptdescr->next, (uclong) (DMA_TX_BD_BASE +
121 (ch_factor + ((i + 1) & (N_DMA_TX_BUF - 1))) * sizeof(pcsca_bd_t)));
122 cpc_writel(&ptdescr->ptbuf,
123 (uclong) (DMA_TX_BASE + (ch_factor + i) * BD_DEF_LEN));
124 }
125 }
126
tx_dma_buf_init(pc300_t * card,int ch)127 static void tx_dma_buf_init(pc300_t * card, int ch)
128 {
129 int i;
130 int ch_factor = ch * N_DMA_TX_BUF;
131 volatile pcsca_bd_t *ptdescr = (pcsca_bd_t *) (card->hw.rambase
132 + DMA_TX_BD_BASE + ch_factor * sizeof(pcsca_bd_t));
133
134 for (i = 0; i < N_DMA_TX_BUF; i++, ptdescr++) {
135 memset_io(ptdescr, 0, sizeof(pcsca_bd_t));
136 cpc_writew(&ptdescr->len, 0);
137 cpc_writeb(&ptdescr->status, DST_OSB);
138 }
139 tx_dma_buf_pt_init(card, ch);
140 }
141
rx_dma_buf_pt_init(pc300_t * card,int ch)142 static void rx_dma_buf_pt_init(pc300_t * card, int ch)
143 {
144 int i;
145 int ch_factor = ch * N_DMA_RX_BUF;
146 volatile pcsca_bd_t *ptdescr = (pcsca_bd_t *) (card->hw.rambase
147 + DMA_RX_BD_BASE + ch_factor * sizeof(pcsca_bd_t));
148
149 for (i = 0; i < N_DMA_RX_BUF; i++, ptdescr++) {
150 cpc_writel(&ptdescr->next, (uclong) (DMA_RX_BD_BASE +
151 (ch_factor + ((i + 1) & (N_DMA_RX_BUF - 1))) * sizeof(pcsca_bd_t)));
152 cpc_writel(&ptdescr->ptbuf,
153 (uclong) (DMA_RX_BASE + (ch_factor + i) * BD_DEF_LEN));
154 }
155 }
156
rx_dma_buf_init(pc300_t * card,int ch)157 static void rx_dma_buf_init(pc300_t * card, int ch)
158 {
159 int i;
160 int ch_factor = ch * N_DMA_RX_BUF;
161 volatile pcsca_bd_t *ptdescr = (pcsca_bd_t *) (card->hw.rambase
162 + DMA_RX_BD_BASE + ch_factor * sizeof(pcsca_bd_t));
163
164 for (i = 0; i < N_DMA_RX_BUF; i++, ptdescr++) {
165 memset_io(ptdescr, 0, sizeof(pcsca_bd_t));
166 cpc_writew(&ptdescr->len, 0);
167 cpc_writeb(&ptdescr->status, 0);
168 }
169 rx_dma_buf_pt_init(card, ch);
170 }
171
tx_dma_buf_check(pc300_t * card,int ch)172 static void tx_dma_buf_check(pc300_t * card, int ch)
173 {
174 volatile pcsca_bd_t *ptdescr;
175 int i;
176 ucshort first_bd = card->chan[ch].tx_first_bd;
177 ucshort next_bd = card->chan[ch].tx_next_bd;
178
179 printk("#CH%d: f_bd = %d(0x%08x), n_bd = %d(0x%08x)\n", ch,
180 first_bd, TX_BD_ADDR(ch, first_bd),
181 next_bd, TX_BD_ADDR(ch, next_bd));
182 for (i = first_bd,
183 ptdescr = (pcsca_bd_t *) (card->hw.rambase + TX_BD_ADDR(ch, first_bd));
184 i != ((next_bd + 1) & (N_DMA_TX_BUF - 1));
185 i = (i + 1) & (N_DMA_TX_BUF - 1),
186 ptdescr = (pcsca_bd_t *) (card->hw.rambase + TX_BD_ADDR(ch, i))) {
187 printk("\n CH%d TX%d: next=0x%lx, ptbuf=0x%lx, ST=0x%x, len=%d",
188 ch, i, (uclong) cpc_readl(&ptdescr->next),
189 (uclong) cpc_readl(&ptdescr->ptbuf),
190 cpc_readb(&ptdescr->status), cpc_readw(&ptdescr->len));
191 }
192 printk("\n");
193 }
194
195 #ifdef PC300_DEBUG_OTHER
196 /* Show all TX buffer descriptors */
tx1_dma_buf_check(pc300_t * card,int ch)197 static void tx1_dma_buf_check(pc300_t * card, int ch)
198 {
199 volatile pcsca_bd_t *ptdescr;
200 int i;
201 ucshort first_bd = card->chan[ch].tx_first_bd;
202 ucshort next_bd = card->chan[ch].tx_next_bd;
203 uclong scabase = card->hw.scabase;
204
205 printk ("\nnfree_tx_bd = %d \n", card->chan[ch].nfree_tx_bd);
206 printk("#CH%d: f_bd = %d(0x%08x), n_bd = %d(0x%08x)\n", ch,
207 first_bd, TX_BD_ADDR(ch, first_bd),
208 next_bd, TX_BD_ADDR(ch, next_bd));
209 printk("TX_CDA=0x%08lx, TX_EDA=0x%08lx\n",
210 (uclong) cpc_readl(scabase + DTX_REG(CDAL, ch)),
211 (uclong) cpc_readl(scabase + DTX_REG(EDAL, ch)));
212 for (i = 0; i < N_DMA_TX_BUF; i++) {
213 ptdescr = (pcsca_bd_t *) (card->hw.rambase + TX_BD_ADDR(ch, i));
214 printk("\n CH%d TX%d: next=0x%lx, ptbuf=0x%lx, ST=0x%x, len=%d",
215 ch, i, (uclong) cpc_readl(&ptdescr->next),
216 (uclong) cpc_readl(&ptdescr->ptbuf),
217 cpc_readb(&ptdescr->status), cpc_readw(&ptdescr->len));
218 }
219 printk("\n");
220 }
221 #endif
222
rx_dma_buf_check(pc300_t * card,int ch)223 static void rx_dma_buf_check(pc300_t * card, int ch)
224 {
225 volatile pcsca_bd_t *ptdescr;
226 int i;
227 ucshort first_bd = card->chan[ch].rx_first_bd;
228 ucshort last_bd = card->chan[ch].rx_last_bd;
229 int ch_factor;
230
231 ch_factor = ch * N_DMA_RX_BUF;
232 printk("#CH%d: f_bd = %d, l_bd = %d\n", ch, first_bd, last_bd);
233 for (i = 0, ptdescr = (pcsca_bd_t *) (card->hw.rambase +
234 DMA_RX_BD_BASE + ch_factor * sizeof(pcsca_bd_t));
235 i < N_DMA_RX_BUF; i++, ptdescr++) {
236 if (cpc_readb(&ptdescr->status) & DST_OSB)
237 printk ("\n CH%d RX%d: next=0x%lx, ptbuf=0x%lx, ST=0x%x, len=%d",
238 ch, i, (uclong) cpc_readl(&ptdescr->next),
239 (uclong) cpc_readl(&ptdescr->ptbuf),
240 cpc_readb(&ptdescr->status),
241 cpc_readw(&ptdescr->len));
242 }
243 printk("\n");
244 }
245
dma_get_rx_frame_size(pc300_t * card,int ch)246 int dma_get_rx_frame_size(pc300_t * card, int ch)
247 {
248 volatile pcsca_bd_t *ptdescr;
249 ucshort first_bd = card->chan[ch].rx_first_bd;
250 int rcvd = 0;
251 volatile ucchar status;
252
253 ptdescr = (pcsca_bd_t *)(card->hw.rambase + RX_BD_ADDR(ch, first_bd));
254 while ((status = cpc_readb(&ptdescr->status)) & DST_OSB) {
255 rcvd += cpc_readw(&ptdescr->len);
256 first_bd = (first_bd + 1) & (N_DMA_RX_BUF - 1);
257 if ((status & DST_EOM) || (first_bd == card->chan[ch].rx_last_bd)) {
258 /* Return the size of a good frame or incomplete bad frame
259 * (dma_buf_read will clean the buffer descriptors in this case). */
260 return (rcvd);
261 }
262 ptdescr = (pcsca_bd_t *)(card->hw.rambase + cpc_readl(&ptdescr->next));
263 }
264 return (-1);
265 }
266
267 /*
268 * dma_buf_write: writes a frame to the Tx DMA buffers
269 * NOTE: this function writes one frame at a time.
270 */
dma_buf_write(pc300_t * card,int ch,ucchar * ptdata,int len)271 int dma_buf_write(pc300_t * card, int ch, ucchar * ptdata, int len)
272 {
273 int i, nchar;
274 volatile pcsca_bd_t *ptdescr;
275 int tosend = len;
276 ucchar nbuf = ((len - 1) / BD_DEF_LEN) + 1;
277
278 if (nbuf >= card->chan[ch].nfree_tx_bd) {
279 return -ENOMEM;
280 }
281
282 for (i = 0; i < nbuf; i++) {
283 ptdescr = (pcsca_bd_t *) (card->hw.rambase +
284 TX_BD_ADDR(ch, card->chan[ch].tx_next_bd));
285 nchar = cpc_min(BD_DEF_LEN, tosend);
286 if (cpc_readb(&ptdescr->status) & DST_OSB) {
287 memcpy_toio((void *)(card->hw.rambase + cpc_readl(&ptdescr->ptbuf)),
288 &ptdata[len - tosend], nchar);
289 cpc_writew(&ptdescr->len, nchar);
290 card->chan[ch].nfree_tx_bd--;
291 if ((i + 1) == nbuf) {
292 /* This must be the last BD to be used */
293 cpc_writeb(&ptdescr->status, DST_EOM);
294 } else {
295 cpc_writeb(&ptdescr->status, 0);
296 }
297 } else {
298 return -ENOMEM;
299 }
300 tosend -= nchar;
301 card->chan[ch].tx_next_bd =
302 (card->chan[ch].tx_next_bd + 1) & (N_DMA_TX_BUF - 1);
303 }
304 /* If it gets to here, it means we have sent the whole frame */
305 return 0;
306 }
307
308 /*
309 * dma_buf_read: reads a frame from the Rx DMA buffers
310 * NOTE: this function reads one frame at a time.
311 */
dma_buf_read(pc300_t * card,int ch,struct sk_buff * skb)312 int dma_buf_read(pc300_t * card, int ch, struct sk_buff *skb)
313 {
314 int nchar;
315 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
316 volatile pcsca_bd_t *ptdescr;
317 int rcvd = 0;
318 volatile ucchar status;
319
320 ptdescr = (pcsca_bd_t *) (card->hw.rambase +
321 RX_BD_ADDR(ch, chan->rx_first_bd));
322 while ((status = cpc_readb(&ptdescr->status)) & DST_OSB) {
323 nchar = cpc_readw(&ptdescr->len);
324 if ((status & (DST_OVR | DST_CRC | DST_RBIT | DST_SHRT | DST_ABT))
325 || (nchar > BD_DEF_LEN)) {
326
327 if (nchar > BD_DEF_LEN)
328 status |= DST_RBIT;
329 rcvd = -status;
330 /* Discard remaining descriptors used by the bad frame */
331 while (chan->rx_first_bd != chan->rx_last_bd) {
332 cpc_writeb(&ptdescr->status, 0);
333 chan->rx_first_bd = (chan->rx_first_bd+1) & (N_DMA_RX_BUF-1);
334 if (status & DST_EOM)
335 break;
336 ptdescr = (pcsca_bd_t *) (card->hw.rambase +
337 cpc_readl(&ptdescr->next));
338 status = cpc_readb(&ptdescr->status);
339 }
340 break;
341 }
342 if (nchar != 0) {
343 if (skb) {
344 memcpy_fromio(skb_put(skb, nchar),
345 (void *)(card->hw.rambase+cpc_readl(&ptdescr->ptbuf)),nchar);
346 }
347 rcvd += nchar;
348 }
349 cpc_writeb(&ptdescr->status, 0);
350 cpc_writeb(&ptdescr->len, 0);
351 chan->rx_first_bd = (chan->rx_first_bd + 1) & (N_DMA_RX_BUF - 1);
352
353 if (status & DST_EOM)
354 break;
355
356 ptdescr = (pcsca_bd_t *) (card->hw.rambase + cpc_readl(&ptdescr->next));
357 }
358
359 if (rcvd != 0) {
360 /* Update pointer */
361 chan->rx_last_bd = (chan->rx_first_bd - 1) & (N_DMA_RX_BUF - 1);
362 /* Update EDA */
363 cpc_writel(card->hw.scabase + DRX_REG(EDAL, ch),
364 RX_BD_ADDR(ch, chan->rx_last_bd));
365 }
366 return (rcvd);
367 }
368
tx_dma_stop(pc300_t * card,int ch)369 void tx_dma_stop(pc300_t * card, int ch)
370 {
371 uclong scabase = card->hw.scabase;
372 ucchar drr_ena_bit = 1 << (5 + 2 * ch);
373 ucchar drr_rst_bit = 1 << (1 + 2 * ch);
374
375 /* Disable DMA */
376 cpc_writeb(scabase + DRR, drr_ena_bit);
377 cpc_writeb(scabase + DRR, drr_rst_bit & ~drr_ena_bit);
378 }
379
rx_dma_stop(pc300_t * card,int ch)380 void rx_dma_stop(pc300_t * card, int ch)
381 {
382 uclong scabase = card->hw.scabase;
383 ucchar drr_ena_bit = 1 << (4 + 2 * ch);
384 ucchar drr_rst_bit = 1 << (2 * ch);
385
386 /* Disable DMA */
387 cpc_writeb(scabase + DRR, drr_ena_bit);
388 cpc_writeb(scabase + DRR, drr_rst_bit & ~drr_ena_bit);
389 }
390
rx_dma_start(pc300_t * card,int ch)391 void rx_dma_start(pc300_t * card, int ch)
392 {
393 uclong scabase = card->hw.scabase;
394 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
395
396 /* Start DMA */
397 cpc_writel(scabase + DRX_REG(CDAL, ch),
398 RX_BD_ADDR(ch, chan->rx_first_bd));
399 if (cpc_readl(scabase + DRX_REG(CDAL,ch)) !=
400 RX_BD_ADDR(ch, chan->rx_first_bd)) {
401 cpc_writel(scabase + DRX_REG(CDAL, ch),
402 RX_BD_ADDR(ch, chan->rx_first_bd));
403 }
404 cpc_writel(scabase + DRX_REG(EDAL, ch),
405 RX_BD_ADDR(ch, chan->rx_last_bd));
406 cpc_writew(scabase + DRX_REG(BFLL, ch), BD_DEF_LEN);
407 cpc_writeb(scabase + DSR_RX(ch), DSR_DE);
408 if (!(cpc_readb(scabase + DSR_RX(ch)) & DSR_DE)) {
409 cpc_writeb(scabase + DSR_RX(ch), DSR_DE);
410 }
411 }
412
413 /*************************/
414 /*** FALC Routines ***/
415 /*************************/
falc_issue_cmd(pc300_t * card,int ch,ucchar cmd)416 void falc_issue_cmd(pc300_t * card, int ch, ucchar cmd)
417 {
418 uclong falcbase = card->hw.falcbase;
419 unsigned long i = 0;
420
421 while (cpc_readb(falcbase + F_REG(SIS, ch)) & SIS_CEC) {
422 if (i++ >= PC300_FALC_MAXLOOP) {
423 printk("%s: FALC command locked(cmd=0x%x).\n",
424 card->chan[ch].d.name, cmd);
425 break;
426 }
427 }
428 cpc_writeb(falcbase + F_REG(CMDR, ch), cmd);
429 }
430
falc_intr_enable(pc300_t * card,int ch)431 void falc_intr_enable(pc300_t * card, int ch)
432 {
433 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
434 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
435 falc_t *pfalc = (falc_t *) & chan->falc;
436 uclong falcbase = card->hw.falcbase;
437
438 /* Interrupt pins are open-drain */
439 cpc_writeb(falcbase + F_REG(IPC, ch),
440 cpc_readb(falcbase + F_REG(IPC, ch)) & ~IPC_IC0);
441 /* Conters updated each second */
442 cpc_writeb(falcbase + F_REG(FMR1, ch),
443 cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_ECM);
444 /* Enable SEC and ES interrupts */
445 cpc_writeb(falcbase + F_REG(IMR3, ch),
446 cpc_readb(falcbase + F_REG(IMR3, ch)) & ~(IMR3_SEC | IMR3_ES));
447 if (conf->fr_mode == PC300_FR_UNFRAMED) {
448 cpc_writeb(falcbase + F_REG(IMR4, ch),
449 cpc_readb(falcbase + F_REG(IMR4, ch)) & ~(IMR4_LOS));
450 } else {
451 cpc_writeb(falcbase + F_REG(IMR4, ch),
452 cpc_readb(falcbase + F_REG(IMR4, ch)) &
453 ~(IMR4_LFA | IMR4_AIS | IMR4_LOS | IMR4_SLIP));
454 }
455 if (conf->media == IF_IFACE_T1) {
456 cpc_writeb(falcbase + F_REG(IMR3, ch),
457 cpc_readb(falcbase + F_REG(IMR3, ch)) & ~IMR3_LLBSC);
458 } else {
459 cpc_writeb(falcbase + F_REG(IPC, ch),
460 cpc_readb(falcbase + F_REG(IPC, ch)) | IPC_SCI);
461 if (conf->fr_mode == PC300_FR_UNFRAMED) {
462 cpc_writeb(falcbase + F_REG(IMR2, ch),
463 cpc_readb(falcbase + F_REG(IMR2, ch)) & ~(IMR2_LOS));
464 } else {
465 cpc_writeb(falcbase + F_REG(IMR2, ch),
466 cpc_readb(falcbase + F_REG(IMR2, ch)) &
467 ~(IMR2_FAR | IMR2_LFA | IMR2_AIS | IMR2_LOS));
468 if (pfalc->multiframe_mode) {
469 cpc_writeb(falcbase + F_REG(IMR2, ch),
470 cpc_readb(falcbase + F_REG(IMR2, ch)) &
471 ~(IMR2_T400MS | IMR2_MFAR));
472 } else {
473 cpc_writeb(falcbase + F_REG(IMR2, ch),
474 cpc_readb(falcbase + F_REG(IMR2, ch)) |
475 IMR2_T400MS | IMR2_MFAR);
476 }
477 }
478 }
479 }
480
falc_open_timeslot(pc300_t * card,int ch,int timeslot)481 void falc_open_timeslot(pc300_t * card, int ch, int timeslot)
482 {
483 uclong falcbase = card->hw.falcbase;
484 ucchar tshf = card->chan[ch].falc.offset;
485
486 cpc_writeb(falcbase + F_REG((ICB1 + (timeslot - tshf) / 8), ch),
487 cpc_readb(falcbase + F_REG((ICB1 + (timeslot - tshf) / 8), ch)) &
488 ~(0x80 >> ((timeslot - tshf) & 0x07)));
489 cpc_writeb(falcbase + F_REG((TTR1 + timeslot / 8), ch),
490 cpc_readb(falcbase + F_REG((TTR1 + timeslot / 8), ch)) |
491 (0x80 >> (timeslot & 0x07)));
492 cpc_writeb(falcbase + F_REG((RTR1 + timeslot / 8), ch),
493 cpc_readb(falcbase + F_REG((RTR1 + timeslot / 8), ch)) |
494 (0x80 >> (timeslot & 0x07)));
495 }
496
falc_close_timeslot(pc300_t * card,int ch,int timeslot)497 void falc_close_timeslot(pc300_t * card, int ch, int timeslot)
498 {
499 uclong falcbase = card->hw.falcbase;
500 ucchar tshf = card->chan[ch].falc.offset;
501
502 cpc_writeb(falcbase + F_REG((ICB1 + (timeslot - tshf) / 8), ch),
503 cpc_readb(falcbase + F_REG((ICB1 + (timeslot - tshf) / 8), ch)) |
504 (0x80 >> ((timeslot - tshf) & 0x07)));
505 cpc_writeb(falcbase + F_REG((TTR1 + timeslot / 8), ch),
506 cpc_readb(falcbase + F_REG((TTR1 + timeslot / 8), ch)) &
507 ~(0x80 >> (timeslot & 0x07)));
508 cpc_writeb(falcbase + F_REG((RTR1 + timeslot / 8), ch),
509 cpc_readb(falcbase + F_REG((RTR1 + timeslot / 8), ch)) &
510 ~(0x80 >> (timeslot & 0x07)));
511 }
512
falc_close_all_timeslots(pc300_t * card,int ch)513 void falc_close_all_timeslots(pc300_t * card, int ch)
514 {
515 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
516 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
517 uclong falcbase = card->hw.falcbase;
518
519 cpc_writeb(falcbase + F_REG(ICB1, ch), 0xff);
520 cpc_writeb(falcbase + F_REG(TTR1, ch), 0);
521 cpc_writeb(falcbase + F_REG(RTR1, ch), 0);
522 cpc_writeb(falcbase + F_REG(ICB2, ch), 0xff);
523 cpc_writeb(falcbase + F_REG(TTR2, ch), 0);
524 cpc_writeb(falcbase + F_REG(RTR2, ch), 0);
525 cpc_writeb(falcbase + F_REG(ICB3, ch), 0xff);
526 cpc_writeb(falcbase + F_REG(TTR3, ch), 0);
527 cpc_writeb(falcbase + F_REG(RTR3, ch), 0);
528 if (conf->media == IF_IFACE_E1) {
529 cpc_writeb(falcbase + F_REG(ICB4, ch), 0xff);
530 cpc_writeb(falcbase + F_REG(TTR4, ch), 0);
531 cpc_writeb(falcbase + F_REG(RTR4, ch), 0);
532 }
533 }
534
falc_open_all_timeslots(pc300_t * card,int ch)535 void falc_open_all_timeslots(pc300_t * card, int ch)
536 {
537 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
538 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
539 uclong falcbase = card->hw.falcbase;
540
541 cpc_writeb(falcbase + F_REG(ICB1, ch), 0);
542 if (conf->fr_mode == PC300_FR_UNFRAMED) {
543 cpc_writeb(falcbase + F_REG(TTR1, ch), 0xff);
544 cpc_writeb(falcbase + F_REG(RTR1, ch), 0xff);
545 } else {
546 /* Timeslot 0 is never enabled */
547 cpc_writeb(falcbase + F_REG(TTR1, ch), 0x7f);
548 cpc_writeb(falcbase + F_REG(RTR1, ch), 0x7f);
549 }
550 cpc_writeb(falcbase + F_REG(ICB2, ch), 0);
551 cpc_writeb(falcbase + F_REG(TTR2, ch), 0xff);
552 cpc_writeb(falcbase + F_REG(RTR2, ch), 0xff);
553 cpc_writeb(falcbase + F_REG(ICB3, ch), 0);
554 cpc_writeb(falcbase + F_REG(TTR3, ch), 0xff);
555 cpc_writeb(falcbase + F_REG(RTR3, ch), 0xff);
556 if (conf->media == IF_IFACE_E1) {
557 cpc_writeb(falcbase + F_REG(ICB4, ch), 0);
558 cpc_writeb(falcbase + F_REG(TTR4, ch), 0xff);
559 cpc_writeb(falcbase + F_REG(RTR4, ch), 0xff);
560 } else {
561 cpc_writeb(falcbase + F_REG(ICB4, ch), 0xff);
562 cpc_writeb(falcbase + F_REG(TTR4, ch), 0x80);
563 cpc_writeb(falcbase + F_REG(RTR4, ch), 0x80);
564 }
565 }
566
falc_init_timeslot(pc300_t * card,int ch)567 void falc_init_timeslot(pc300_t * card, int ch)
568 {
569 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
570 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
571 falc_t *pfalc = (falc_t *) & chan->falc;
572 int tslot;
573
574 for (tslot = 0; tslot < pfalc->num_channels; tslot++) {
575 if (conf->tslot_bitmap & (1 << tslot)) {
576 // Channel enabled
577 falc_open_timeslot(card, ch, tslot + 1);
578 } else {
579 // Channel disabled
580 falc_close_timeslot(card, ch, tslot + 1);
581 }
582 }
583 }
584
falc_enable_comm(pc300_t * card,int ch)585 void falc_enable_comm(pc300_t * card, int ch)
586 {
587 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
588 falc_t *pfalc = (falc_t *) & chan->falc;
589
590 if (pfalc->full_bandwidth) {
591 falc_open_all_timeslots(card, ch);
592 } else {
593 falc_init_timeslot(card, ch);
594 }
595 // CTS/DCD ON
596 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
597 cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) &
598 ~((CPLD_REG1_FALC_DCD | CPLD_REG1_FALC_CTS) << (2 * ch)));
599 }
600
falc_disable_comm(pc300_t * card,int ch)601 void falc_disable_comm(pc300_t * card, int ch)
602 {
603 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
604 falc_t *pfalc = (falc_t *) & chan->falc;
605
606 if (pfalc->loop_active != 2) {
607 falc_close_all_timeslots(card, ch);
608 }
609 // CTS/DCD OFF
610 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
611 cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) |
612 ((CPLD_REG1_FALC_DCD | CPLD_REG1_FALC_CTS) << (2 * ch)));
613 }
614
falc_init_t1(pc300_t * card,int ch)615 void falc_init_t1(pc300_t * card, int ch)
616 {
617 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
618 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
619 falc_t *pfalc = (falc_t *) & chan->falc;
620 uclong falcbase = card->hw.falcbase;
621 ucchar dja = (ch ? (LIM2_DJA2 | LIM2_DJA1) : 0);
622
623 /* Switch to T1 mode (PCM 24) */
624 cpc_writeb(falcbase + F_REG(FMR1, ch), FMR1_PMOD);
625
626 /* Wait 20 us for setup */
627 udelay(20);
628
629 /* Transmit Buffer Size (1 frame) */
630 cpc_writeb(falcbase + F_REG(SIC1, ch), SIC1_XBS0);
631
632 /* Clock mode */
633 if (conf->phys_settings.clock_type == CLOCK_INT) { /* Master mode */
634 cpc_writeb(falcbase + F_REG(LIM0, ch),
635 cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_MAS);
636 } else { /* Slave mode */
637 cpc_writeb(falcbase + F_REG(LIM0, ch),
638 cpc_readb(falcbase + F_REG(LIM0, ch)) & ~LIM0_MAS);
639 cpc_writeb(falcbase + F_REG(LOOP, ch),
640 cpc_readb(falcbase + F_REG(LOOP, ch)) & ~LOOP_RTM);
641 }
642
643 cpc_writeb(falcbase + F_REG(IPC, ch), IPC_SCI);
644 cpc_writeb(falcbase + F_REG(FMR0, ch),
645 cpc_readb(falcbase + F_REG(FMR0, ch)) &
646 ~(FMR0_XC0 | FMR0_XC1 | FMR0_RC0 | FMR0_RC1));
647
648 switch (conf->lcode) {
649 case PC300_LC_AMI:
650 cpc_writeb(falcbase + F_REG(FMR0, ch),
651 cpc_readb(falcbase + F_REG(FMR0, ch)) |
652 FMR0_XC1 | FMR0_RC1);
653 /* Clear Channel register to ON for all channels */
654 cpc_writeb(falcbase + F_REG(CCB1, ch), 0xff);
655 cpc_writeb(falcbase + F_REG(CCB2, ch), 0xff);
656 cpc_writeb(falcbase + F_REG(CCB3, ch), 0xff);
657 break;
658
659 case PC300_LC_B8ZS:
660 cpc_writeb(falcbase + F_REG(FMR0, ch),
661 cpc_readb(falcbase + F_REG(FMR0, ch)) |
662 FMR0_XC0 | FMR0_XC1 | FMR0_RC0 | FMR0_RC1);
663 break;
664
665 case PC300_LC_NRZ:
666 cpc_writeb(falcbase + F_REG(FMR0, ch),
667 cpc_readb(falcbase + F_REG(FMR0, ch)) | 0x00);
668 break;
669 }
670
671 cpc_writeb(falcbase + F_REG(LIM0, ch),
672 cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_ELOS);
673 cpc_writeb(falcbase + F_REG(LIM0, ch),
674 cpc_readb(falcbase + F_REG(LIM0, ch)) & ~(LIM0_SCL1 | LIM0_SCL0));
675 /* Set interface mode to 2 MBPS */
676 cpc_writeb(falcbase + F_REG(FMR1, ch),
677 cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_IMOD);
678
679 switch (conf->fr_mode) {
680 case PC300_FR_ESF:
681 pfalc->multiframe_mode = 0;
682 cpc_writeb(falcbase + F_REG(FMR4, ch),
683 cpc_readb(falcbase + F_REG(FMR4, ch)) | FMR4_FM1);
684 cpc_writeb(falcbase + F_REG(FMR1, ch),
685 cpc_readb(falcbase + F_REG(FMR1, ch)) |
686 FMR1_CRC | FMR1_EDL);
687 cpc_writeb(falcbase + F_REG(XDL1, ch), 0);
688 cpc_writeb(falcbase + F_REG(XDL2, ch), 0);
689 cpc_writeb(falcbase + F_REG(XDL3, ch), 0);
690 cpc_writeb(falcbase + F_REG(FMR0, ch),
691 cpc_readb(falcbase + F_REG(FMR0, ch)) & ~FMR0_SRAF);
692 cpc_writeb(falcbase + F_REG(FMR2, ch),
693 cpc_readb(falcbase + F_REG(FMR2,ch)) | FMR2_MCSP | FMR2_SSP);
694 break;
695
696 case PC300_FR_D4:
697 pfalc->multiframe_mode = 1;
698 cpc_writeb(falcbase + F_REG(FMR4, ch),
699 cpc_readb(falcbase + F_REG(FMR4, ch)) &
700 ~(FMR4_FM1 | FMR4_FM0));
701 cpc_writeb(falcbase + F_REG(FMR0, ch),
702 cpc_readb(falcbase + F_REG(FMR0, ch)) | FMR0_SRAF);
703 cpc_writeb(falcbase + F_REG(FMR2, ch),
704 cpc_readb(falcbase + F_REG(FMR2, ch)) & ~FMR2_SSP);
705 break;
706 }
707
708 /* Enable Automatic Resynchronization */
709 cpc_writeb(falcbase + F_REG(FMR4, ch),
710 cpc_readb(falcbase + F_REG(FMR4, ch)) | FMR4_AUTO);
711
712 /* Transmit Automatic Remote Alarm */
713 cpc_writeb(falcbase + F_REG(FMR2, ch),
714 cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_AXRA);
715
716 /* Channel translation mode 1 : one to one */
717 cpc_writeb(falcbase + F_REG(FMR1, ch),
718 cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_CTM);
719
720 /* No signaling */
721 cpc_writeb(falcbase + F_REG(FMR1, ch),
722 cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_SIGM);
723 cpc_writeb(falcbase + F_REG(FMR5, ch),
724 cpc_readb(falcbase + F_REG(FMR5, ch)) &
725 ~(FMR5_EIBR | FMR5_SRS));
726 cpc_writeb(falcbase + F_REG(CCR1, ch), 0);
727
728 cpc_writeb(falcbase + F_REG(LIM1, ch),
729 cpc_readb(falcbase + F_REG(LIM1, ch)) | LIM1_RIL0 | LIM1_RIL1);
730
731 switch (conf->lbo) {
732 /* Provides proper Line Build Out */
733 case PC300_LBO_0_DB:
734 cpc_writeb(falcbase + F_REG(LIM2, ch), (LIM2_LOS1 | dja));
735 cpc_writeb(falcbase + F_REG(XPM0, ch), 0x5a);
736 cpc_writeb(falcbase + F_REG(XPM1, ch), 0x8f);
737 cpc_writeb(falcbase + F_REG(XPM2, ch), 0x20);
738 break;
739 case PC300_LBO_7_5_DB:
740 cpc_writeb(falcbase + F_REG(LIM2, ch), (0x40 | LIM2_LOS1 | dja));
741 cpc_writeb(falcbase + F_REG(XPM0, ch), 0x11);
742 cpc_writeb(falcbase + F_REG(XPM1, ch), 0x02);
743 cpc_writeb(falcbase + F_REG(XPM2, ch), 0x20);
744 break;
745 case PC300_LBO_15_DB:
746 cpc_writeb(falcbase + F_REG(LIM2, ch), (0x80 | LIM2_LOS1 | dja));
747 cpc_writeb(falcbase + F_REG(XPM0, ch), 0x8e);
748 cpc_writeb(falcbase + F_REG(XPM1, ch), 0x01);
749 cpc_writeb(falcbase + F_REG(XPM2, ch), 0x20);
750 break;
751 case PC300_LBO_22_5_DB:
752 cpc_writeb(falcbase + F_REG(LIM2, ch), (0xc0 | LIM2_LOS1 | dja));
753 cpc_writeb(falcbase + F_REG(XPM0, ch), 0x09);
754 cpc_writeb(falcbase + F_REG(XPM1, ch), 0x01);
755 cpc_writeb(falcbase + F_REG(XPM2, ch), 0x20);
756 break;
757 }
758
759 /* Transmit Clock-Slot Offset */
760 cpc_writeb(falcbase + F_REG(XC0, ch),
761 cpc_readb(falcbase + F_REG(XC0, ch)) | 0x01);
762 /* Transmit Time-slot Offset */
763 cpc_writeb(falcbase + F_REG(XC1, ch), 0x3e);
764 /* Receive Clock-Slot offset */
765 cpc_writeb(falcbase + F_REG(RC0, ch), 0x05);
766 /* Receive Time-slot offset */
767 cpc_writeb(falcbase + F_REG(RC1, ch), 0x00);
768
769 /* LOS Detection after 176 consecutive 0s */
770 cpc_writeb(falcbase + F_REG(PCDR, ch), 0x0a);
771 /* LOS Recovery after 22 ones in the time window of PCD */
772 cpc_writeb(falcbase + F_REG(PCRR, ch), 0x15);
773
774 cpc_writeb(falcbase + F_REG(IDLE, ch), 0x7f);
775
776 if (conf->fr_mode == PC300_FR_ESF_JAPAN) {
777 cpc_writeb(falcbase + F_REG(RC1, ch),
778 cpc_readb(falcbase + F_REG(RC1, ch)) | 0x80);
779 }
780
781 falc_close_all_timeslots(card, ch);
782 }
783
falc_init_e1(pc300_t * card,int ch)784 void falc_init_e1(pc300_t * card, int ch)
785 {
786 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
787 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
788 falc_t *pfalc = (falc_t *) & chan->falc;
789 uclong falcbase = card->hw.falcbase;
790 ucchar dja = (ch ? (LIM2_DJA2 | LIM2_DJA1) : 0);
791
792 /* Switch to E1 mode (PCM 30) */
793 cpc_writeb(falcbase + F_REG(FMR1, ch),
794 cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_PMOD);
795
796 /* Clock mode */
797 if (conf->phys_settings.clock_type == CLOCK_INT) { /* Master mode */
798 cpc_writeb(falcbase + F_REG(LIM0, ch),
799 cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_MAS);
800 } else { /* Slave mode */
801 cpc_writeb(falcbase + F_REG(LIM0, ch),
802 cpc_readb(falcbase + F_REG(LIM0, ch)) & ~LIM0_MAS);
803 }
804 cpc_writeb(falcbase + F_REG(LOOP, ch),
805 cpc_readb(falcbase + F_REG(LOOP, ch)) & ~LOOP_SFM);
806
807 cpc_writeb(falcbase + F_REG(IPC, ch), IPC_SCI);
808 cpc_writeb(falcbase + F_REG(FMR0, ch),
809 cpc_readb(falcbase + F_REG(FMR0, ch)) &
810 ~(FMR0_XC0 | FMR0_XC1 | FMR0_RC0 | FMR0_RC1));
811
812 switch (conf->lcode) {
813 case PC300_LC_AMI:
814 cpc_writeb(falcbase + F_REG(FMR0, ch),
815 cpc_readb(falcbase + F_REG(FMR0, ch)) |
816 FMR0_XC1 | FMR0_RC1);
817 break;
818
819 case PC300_LC_HDB3:
820 cpc_writeb(falcbase + F_REG(FMR0, ch),
821 cpc_readb(falcbase + F_REG(FMR0, ch)) |
822 FMR0_XC0 | FMR0_XC1 | FMR0_RC0 | FMR0_RC1);
823 break;
824
825 case PC300_LC_NRZ:
826 break;
827 }
828
829 cpc_writeb(falcbase + F_REG(LIM0, ch),
830 cpc_readb(falcbase + F_REG(LIM0, ch)) & ~(LIM0_SCL1 | LIM0_SCL0));
831 /* Set interface mode to 2 MBPS */
832 cpc_writeb(falcbase + F_REG(FMR1, ch),
833 cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_IMOD);
834
835 cpc_writeb(falcbase + F_REG(XPM0, ch), 0x18);
836 cpc_writeb(falcbase + F_REG(XPM1, ch), 0x03);
837 cpc_writeb(falcbase + F_REG(XPM2, ch), 0x00);
838
839 switch (conf->fr_mode) {
840 case PC300_FR_MF_CRC4:
841 pfalc->multiframe_mode = 1;
842 cpc_writeb(falcbase + F_REG(FMR1, ch),
843 cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_XFS);
844 cpc_writeb(falcbase + F_REG(FMR2, ch),
845 cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_RFS1);
846 cpc_writeb(falcbase + F_REG(FMR2, ch),
847 cpc_readb(falcbase + F_REG(FMR2, ch)) & ~FMR2_RFS0);
848 cpc_writeb(falcbase + F_REG(FMR3, ch),
849 cpc_readb(falcbase + F_REG(FMR3, ch)) & ~FMR3_EXTIW);
850
851 /* MultiFrame Resynchronization */
852 cpc_writeb(falcbase + F_REG(FMR1, ch),
853 cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_MFCS);
854
855 /* Automatic Loss of Multiframe > 914 CRC errors */
856 cpc_writeb(falcbase + F_REG(FMR2, ch),
857 cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_ALMF);
858
859 /* S1 and SI1/SI2 spare Bits set to 1 */
860 cpc_writeb(falcbase + F_REG(XSP, ch),
861 cpc_readb(falcbase + F_REG(XSP, ch)) & ~XSP_AXS);
862 cpc_writeb(falcbase + F_REG(XSP, ch),
863 cpc_readb(falcbase + F_REG(XSP, ch)) | XSP_EBP);
864 cpc_writeb(falcbase + F_REG(XSP, ch),
865 cpc_readb(falcbase + F_REG(XSP, ch)) | XSP_XS13 | XSP_XS15);
866
867 /* Automatic Force Resynchronization */
868 cpc_writeb(falcbase + F_REG(FMR1, ch),
869 cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_AFR);
870
871 /* Transmit Automatic Remote Alarm */
872 cpc_writeb(falcbase + F_REG(FMR2, ch),
873 cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_AXRA);
874
875 /* Transmit Spare Bits for National Use (Y, Sn, Sa) */
876 cpc_writeb(falcbase + F_REG(XSW, ch),
877 cpc_readb(falcbase + F_REG(XSW, ch)) |
878 XSW_XY0 | XSW_XY1 | XSW_XY2 | XSW_XY3 | XSW_XY4);
879 break;
880
881 case PC300_FR_MF_NON_CRC4:
882 case PC300_FR_D4:
883 pfalc->multiframe_mode = 0;
884 cpc_writeb(falcbase + F_REG(FMR1, ch),
885 cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_XFS);
886 cpc_writeb(falcbase + F_REG(FMR2, ch),
887 cpc_readb(falcbase + F_REG(FMR2, ch)) &
888 ~(FMR2_RFS1 | FMR2_RFS0));
889 cpc_writeb(falcbase + F_REG(XSW, ch),
890 cpc_readb(falcbase + F_REG(XSW, ch)) | XSW_XSIS);
891 cpc_writeb(falcbase + F_REG(XSP, ch),
892 cpc_readb(falcbase + F_REG(XSP, ch)) | XSP_XSIF);
893
894 /* Automatic Force Resynchronization */
895 cpc_writeb(falcbase + F_REG(FMR1, ch),
896 cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_AFR);
897
898 /* Transmit Automatic Remote Alarm */
899 cpc_writeb(falcbase + F_REG(FMR2, ch),
900 cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_AXRA);
901
902 /* Transmit Spare Bits for National Use (Y, Sn, Sa) */
903 cpc_writeb(falcbase + F_REG(XSW, ch),
904 cpc_readb(falcbase + F_REG(XSW, ch)) |
905 XSW_XY0 | XSW_XY1 | XSW_XY2 | XSW_XY3 | XSW_XY4);
906 break;
907
908 case PC300_FR_UNFRAMED:
909 pfalc->multiframe_mode = 0;
910 cpc_writeb(falcbase + F_REG(FMR1, ch),
911 cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_XFS);
912 cpc_writeb(falcbase + F_REG(FMR2, ch),
913 cpc_readb(falcbase + F_REG(FMR2, ch)) &
914 ~(FMR2_RFS1 | FMR2_RFS0));
915 cpc_writeb(falcbase + F_REG(XSP, ch),
916 cpc_readb(falcbase + F_REG(XSP, ch)) | XSP_TT0);
917 cpc_writeb(falcbase + F_REG(XSW, ch),
918 cpc_readb(falcbase + F_REG(XSW, ch)) &
919 ~(XSW_XTM|XSW_XY0|XSW_XY1|XSW_XY2|XSW_XY3|XSW_XY4));
920 cpc_writeb(falcbase + F_REG(TSWM, ch), 0xff);
921 cpc_writeb(falcbase + F_REG(FMR2, ch),
922 cpc_readb(falcbase + F_REG(FMR2, ch)) |
923 (FMR2_RTM | FMR2_DAIS));
924 cpc_writeb(falcbase + F_REG(FMR2, ch),
925 cpc_readb(falcbase + F_REG(FMR2, ch)) & ~FMR2_AXRA);
926 cpc_writeb(falcbase + F_REG(FMR1, ch),
927 cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_AFR);
928 pfalc->sync = 1;
929 cpc_writeb(falcbase + card->hw.cpld_reg2,
930 cpc_readb(falcbase + card->hw.cpld_reg2) |
931 (CPLD_REG2_FALC_LED2 << (2 * ch)));
932 break;
933 }
934
935 /* No signaling */
936 cpc_writeb(falcbase + F_REG(XSP, ch),
937 cpc_readb(falcbase + F_REG(XSP, ch)) & ~XSP_CASEN);
938 cpc_writeb(falcbase + F_REG(CCR1, ch), 0);
939
940 cpc_writeb(falcbase + F_REG(LIM1, ch),
941 cpc_readb(falcbase + F_REG(LIM1, ch)) | LIM1_RIL0 | LIM1_RIL1);
942 cpc_writeb(falcbase + F_REG(LIM2, ch), (LIM2_LOS1 | dja));
943
944 /* Transmit Clock-Slot Offset */
945 cpc_writeb(falcbase + F_REG(XC0, ch),
946 cpc_readb(falcbase + F_REG(XC0, ch)) | 0x01);
947 /* Transmit Time-slot Offset */
948 cpc_writeb(falcbase + F_REG(XC1, ch), 0x3e);
949 /* Receive Clock-Slot offset */
950 cpc_writeb(falcbase + F_REG(RC0, ch), 0x05);
951 /* Receive Time-slot offset */
952 cpc_writeb(falcbase + F_REG(RC1, ch), 0x00);
953
954 /* LOS Detection after 176 consecutive 0s */
955 cpc_writeb(falcbase + F_REG(PCDR, ch), 0x0a);
956 /* LOS Recovery after 22 ones in the time window of PCD */
957 cpc_writeb(falcbase + F_REG(PCRR, ch), 0x15);
958
959 cpc_writeb(falcbase + F_REG(IDLE, ch), 0x7f);
960
961 falc_close_all_timeslots(card, ch);
962 }
963
falc_init_hdlc(pc300_t * card,int ch)964 void falc_init_hdlc(pc300_t * card, int ch)
965 {
966 uclong falcbase = card->hw.falcbase;
967 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
968 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
969
970 /* Enable transparent data transfer */
971 if (conf->fr_mode == PC300_FR_UNFRAMED) {
972 cpc_writeb(falcbase + F_REG(MODE, ch), 0);
973 } else {
974 cpc_writeb(falcbase + F_REG(MODE, ch),
975 cpc_readb(falcbase + F_REG(MODE, ch)) |
976 (MODE_HRAC | MODE_MDS2));
977 cpc_writeb(falcbase + F_REG(RAH2, ch), 0xff);
978 cpc_writeb(falcbase + F_REG(RAH1, ch), 0xff);
979 cpc_writeb(falcbase + F_REG(RAL2, ch), 0xff);
980 cpc_writeb(falcbase + F_REG(RAL1, ch), 0xff);
981 }
982
983 /* Tx/Rx reset */
984 falc_issue_cmd(card, ch, CMDR_RRES | CMDR_XRES | CMDR_SRES);
985
986 /* Enable interrupt sources */
987 falc_intr_enable(card, ch);
988 }
989
te_config(pc300_t * card,int ch)990 void te_config(pc300_t * card, int ch)
991 {
992 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
993 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
994 falc_t *pfalc = (falc_t *) & chan->falc;
995 uclong falcbase = card->hw.falcbase;
996 ucchar dummy;
997 unsigned long flags;
998
999 memset(pfalc, 0, sizeof(falc_t));
1000 switch (conf->media) {
1001 case IF_IFACE_T1:
1002 pfalc->num_channels = NUM_OF_T1_CHANNELS;
1003 pfalc->offset = 1;
1004 break;
1005 case IF_IFACE_E1:
1006 pfalc->num_channels = NUM_OF_E1_CHANNELS;
1007 pfalc->offset = 0;
1008 break;
1009 }
1010 if (conf->tslot_bitmap == 0xffffffffUL)
1011 pfalc->full_bandwidth = 1;
1012 else
1013 pfalc->full_bandwidth = 0;
1014
1015 CPC_LOCK(card, flags);
1016 /* Reset the FALC chip */
1017 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
1018 cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) |
1019 (CPLD_REG1_FALC_RESET << (2 * ch)));
1020 udelay(10000);
1021 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
1022 cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) &
1023 ~(CPLD_REG1_FALC_RESET << (2 * ch)));
1024
1025 if (conf->media == IF_IFACE_T1) {
1026 falc_init_t1(card, ch);
1027 } else {
1028 falc_init_e1(card, ch);
1029 }
1030 falc_init_hdlc(card, ch);
1031 if (conf->rx_sens == PC300_RX_SENS_SH) {
1032 cpc_writeb(falcbase + F_REG(LIM0, ch),
1033 cpc_readb(falcbase + F_REG(LIM0, ch)) & ~LIM0_EQON);
1034 } else {
1035 cpc_writeb(falcbase + F_REG(LIM0, ch),
1036 cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_EQON);
1037 }
1038 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
1039 cpc_readb(card->hw.falcbase + card->hw.cpld_reg2) |
1040 ((CPLD_REG2_FALC_TX_CLK | CPLD_REG2_FALC_RX_CLK) << (2 * ch)));
1041
1042 /* Clear all interrupt registers */
1043 dummy = cpc_readb(falcbase + F_REG(FISR0, ch)) +
1044 cpc_readb(falcbase + F_REG(FISR1, ch)) +
1045 cpc_readb(falcbase + F_REG(FISR2, ch)) +
1046 cpc_readb(falcbase + F_REG(FISR3, ch));
1047 CPC_UNLOCK(card, flags);
1048 }
1049
falc_check_status(pc300_t * card,int ch,unsigned char frs0)1050 void falc_check_status(pc300_t * card, int ch, unsigned char frs0)
1051 {
1052 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1053 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1054 falc_t *pfalc = (falc_t *) & chan->falc;
1055 uclong falcbase = card->hw.falcbase;
1056
1057 /* Verify LOS */
1058 if (frs0 & FRS0_LOS) {
1059 if (!pfalc->red_alarm) {
1060 pfalc->red_alarm = 1;
1061 pfalc->los++;
1062 if (!pfalc->blue_alarm) {
1063 // EVENT_FALC_ABNORMAL
1064 if (conf->media == IF_IFACE_T1) {
1065 /* Disable this interrupt as it may otherwise interfere
1066 * with other working boards. */
1067 cpc_writeb(falcbase + F_REG(IMR0, ch),
1068 cpc_readb(falcbase + F_REG(IMR0, ch))
1069 | IMR0_PDEN);
1070 }
1071 falc_disable_comm(card, ch);
1072 // EVENT_FALC_ABNORMAL
1073 }
1074 }
1075 } else {
1076 if (pfalc->red_alarm) {
1077 pfalc->red_alarm = 0;
1078 pfalc->losr++;
1079 }
1080 }
1081
1082 if (conf->fr_mode != PC300_FR_UNFRAMED) {
1083 /* Verify AIS alarm */
1084 if (frs0 & FRS0_AIS) {
1085 if (!pfalc->blue_alarm) {
1086 pfalc->blue_alarm = 1;
1087 pfalc->ais++;
1088 // EVENT_AIS
1089 if (conf->media == IF_IFACE_T1) {
1090 /* Disable this interrupt as it may otherwise interfere with other working boards. */
1091 cpc_writeb(falcbase + F_REG(IMR0, ch),
1092 cpc_readb(falcbase + F_REG(IMR0, ch)) | IMR0_PDEN);
1093 }
1094 falc_disable_comm(card, ch);
1095 // EVENT_AIS
1096 }
1097 } else {
1098 pfalc->blue_alarm = 0;
1099 }
1100
1101 /* Verify LFA */
1102 if (frs0 & FRS0_LFA) {
1103 if (!pfalc->loss_fa) {
1104 pfalc->loss_fa = 1;
1105 pfalc->lfa++;
1106 if (!pfalc->blue_alarm && !pfalc->red_alarm) {
1107 // EVENT_FALC_ABNORMAL
1108 if (conf->media == IF_IFACE_T1) {
1109 /* Disable this interrupt as it may otherwise
1110 * interfere with other working boards. */
1111 cpc_writeb(falcbase + F_REG(IMR0, ch),
1112 cpc_readb(falcbase + F_REG(IMR0, ch))
1113 | IMR0_PDEN);
1114 }
1115 falc_disable_comm(card, ch);
1116 // EVENT_FALC_ABNORMAL
1117 }
1118 }
1119 } else {
1120 if (pfalc->loss_fa) {
1121 pfalc->loss_fa = 0;
1122 pfalc->farec++;
1123 }
1124 }
1125
1126 /* Verify LMFA */
1127 if (pfalc->multiframe_mode && (frs0 & FRS0_LMFA)) {
1128 /* D4 or CRC4 frame mode */
1129 if (!pfalc->loss_mfa) {
1130 pfalc->loss_mfa = 1;
1131 pfalc->lmfa++;
1132 if (!pfalc->blue_alarm && !pfalc->red_alarm &&
1133 !pfalc->loss_fa) {
1134 // EVENT_FALC_ABNORMAL
1135 if (conf->media == IF_IFACE_T1) {
1136 /* Disable this interrupt as it may otherwise
1137 * interfere with other working boards. */
1138 cpc_writeb(falcbase + F_REG(IMR0, ch),
1139 cpc_readb(falcbase + F_REG(IMR0, ch))
1140 | IMR0_PDEN);
1141 }
1142 falc_disable_comm(card, ch);
1143 // EVENT_FALC_ABNORMAL
1144 }
1145 }
1146 } else {
1147 pfalc->loss_mfa = 0;
1148 }
1149
1150 /* Verify Remote Alarm */
1151 if (frs0 & FRS0_RRA) {
1152 if (!pfalc->yellow_alarm) {
1153 pfalc->yellow_alarm = 1;
1154 pfalc->rai++;
1155 if (pfalc->sync) {
1156 // EVENT_RAI
1157 falc_disable_comm(card, ch);
1158 // EVENT_RAI
1159 }
1160 }
1161 } else {
1162 pfalc->yellow_alarm = 0;
1163 }
1164 } /* if !PC300_UNFRAMED */
1165
1166 if (pfalc->red_alarm || pfalc->loss_fa ||
1167 pfalc->loss_mfa || pfalc->blue_alarm) {
1168 if (pfalc->sync) {
1169 pfalc->sync = 0;
1170 chan->d.line_off++;
1171 cpc_writeb(falcbase + card->hw.cpld_reg2,
1172 cpc_readb(falcbase + card->hw.cpld_reg2) &
1173 ~(CPLD_REG2_FALC_LED2 << (2 * ch)));
1174 }
1175 } else {
1176 if (!pfalc->sync) {
1177 pfalc->sync = 1;
1178 chan->d.line_on++;
1179 cpc_writeb(falcbase + card->hw.cpld_reg2,
1180 cpc_readb(falcbase + card->hw.cpld_reg2) |
1181 (CPLD_REG2_FALC_LED2 << (2 * ch)));
1182 }
1183 }
1184
1185 if (pfalc->sync && !pfalc->yellow_alarm) {
1186 if (!pfalc->active) {
1187 // EVENT_FALC_NORMAL
1188 if (pfalc->loop_active) {
1189 return;
1190 }
1191 if (conf->media == IF_IFACE_T1) {
1192 cpc_writeb(falcbase + F_REG(IMR0, ch),
1193 cpc_readb(falcbase + F_REG(IMR0, ch)) & ~IMR0_PDEN);
1194 }
1195 falc_enable_comm(card, ch);
1196 // EVENT_FALC_NORMAL
1197 pfalc->active = 1;
1198 }
1199 } else {
1200 if (pfalc->active) {
1201 pfalc->active = 0;
1202 }
1203 }
1204 }
1205
falc_update_stats(pc300_t * card,int ch)1206 void falc_update_stats(pc300_t * card, int ch)
1207 {
1208 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1209 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1210 falc_t *pfalc = (falc_t *) & chan->falc;
1211 uclong falcbase = card->hw.falcbase;
1212 ucshort counter;
1213
1214 counter = cpc_readb(falcbase + F_REG(FECL, ch));
1215 counter |= cpc_readb(falcbase + F_REG(FECH, ch)) << 8;
1216 pfalc->fec += counter;
1217
1218 counter = cpc_readb(falcbase + F_REG(CVCL, ch));
1219 counter |= cpc_readb(falcbase + F_REG(CVCH, ch)) << 8;
1220 pfalc->cvc += counter;
1221
1222 counter = cpc_readb(falcbase + F_REG(CECL, ch));
1223 counter |= cpc_readb(falcbase + F_REG(CECH, ch)) << 8;
1224 pfalc->cec += counter;
1225
1226 counter = cpc_readb(falcbase + F_REG(EBCL, ch));
1227 counter |= cpc_readb(falcbase + F_REG(EBCH, ch)) << 8;
1228 pfalc->ebc += counter;
1229
1230 if (cpc_readb(falcbase + F_REG(LCR1, ch)) & LCR1_EPRM) {
1231 mdelay(10);
1232 counter = cpc_readb(falcbase + F_REG(BECL, ch));
1233 counter |= cpc_readb(falcbase + F_REG(BECH, ch)) << 8;
1234 pfalc->bec += counter;
1235
1236 if (((conf->media == IF_IFACE_T1) &&
1237 (cpc_readb(falcbase + F_REG(FRS1, ch)) & FRS1_LLBAD) &&
1238 (!(cpc_readb(falcbase + F_REG(FRS1, ch)) & FRS1_PDEN)))
1239 ||
1240 ((conf->media == IF_IFACE_E1) &&
1241 (cpc_readb(falcbase + F_REG(RSP, ch)) & RSP_LLBAD))) {
1242 pfalc->prbs = 2;
1243 } else {
1244 pfalc->prbs = 1;
1245 }
1246 }
1247 }
1248
1249 /*----------------------------------------------------------------------------
1250 * falc_remote_loop
1251 *----------------------------------------------------------------------------
1252 * Description: In the remote loopback mode the clock and data recovered
1253 * from the line inputs RL1/2 or RDIP/RDIN are routed back
1254 * to the line outputs XL1/2 or XDOP/XDON via the analog
1255 * transmitter. As in normal mode they are processsed by
1256 * the synchronizer and then sent to the system interface.
1257 *----------------------------------------------------------------------------
1258 */
falc_remote_loop(pc300_t * card,int ch,int loop_on)1259 void falc_remote_loop(pc300_t * card, int ch, int loop_on)
1260 {
1261 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1262 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1263 falc_t *pfalc = (falc_t *) & chan->falc;
1264 uclong falcbase = card->hw.falcbase;
1265
1266 if (loop_on) {
1267 // EVENT_FALC_ABNORMAL
1268 if (conf->media == IF_IFACE_T1) {
1269 /* Disable this interrupt as it may otherwise interfere with
1270 * other working boards. */
1271 cpc_writeb(falcbase + F_REG(IMR0, ch),
1272 cpc_readb(falcbase + F_REG(IMR0, ch)) | IMR0_PDEN);
1273 }
1274 falc_disable_comm(card, ch);
1275 // EVENT_FALC_ABNORMAL
1276 cpc_writeb(falcbase + F_REG(LIM1, ch),
1277 cpc_readb(falcbase + F_REG(LIM1, ch)) | LIM1_RL);
1278 pfalc->loop_active = 1;
1279 } else {
1280 cpc_writeb(falcbase + F_REG(LIM1, ch),
1281 cpc_readb(falcbase + F_REG(LIM1, ch)) & ~LIM1_RL);
1282 pfalc->sync = 0;
1283 cpc_writeb(falcbase + card->hw.cpld_reg2,
1284 cpc_readb(falcbase + card->hw.cpld_reg2) &
1285 ~(CPLD_REG2_FALC_LED2 << (2 * ch)));
1286 pfalc->active = 0;
1287 falc_issue_cmd(card, ch, CMDR_XRES);
1288 pfalc->loop_active = 0;
1289 }
1290 }
1291
1292 /*----------------------------------------------------------------------------
1293 * falc_local_loop
1294 *----------------------------------------------------------------------------
1295 * Description: The local loopback mode disconnects the receive lines
1296 * RL1/RL2 resp. RDIP/RDIN from the receiver. Instead of the
1297 * signals coming from the line the data provided by system
1298 * interface are routed through the analog receiver back to
1299 * the system interface. The unipolar bit stream will be
1300 * undisturbed transmitted on the line. Receiver and transmitter
1301 * coding must be identical.
1302 *----------------------------------------------------------------------------
1303 */
falc_local_loop(pc300_t * card,int ch,int loop_on)1304 void falc_local_loop(pc300_t * card, int ch, int loop_on)
1305 {
1306 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1307 falc_t *pfalc = (falc_t *) & chan->falc;
1308 uclong falcbase = card->hw.falcbase;
1309
1310 if (loop_on) {
1311 cpc_writeb(falcbase + F_REG(LIM0, ch),
1312 cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_LL);
1313 pfalc->loop_active = 1;
1314 } else {
1315 cpc_writeb(falcbase + F_REG(LIM0, ch),
1316 cpc_readb(falcbase + F_REG(LIM0, ch)) & ~LIM0_LL);
1317 pfalc->loop_active = 0;
1318 }
1319 }
1320
1321 /*----------------------------------------------------------------------------
1322 * falc_payload_loop
1323 *----------------------------------------------------------------------------
1324 * Description: This routine allows to enable/disable payload loopback.
1325 * When the payload loop is activated, the received 192 bits
1326 * of payload data will be looped back to the transmit
1327 * direction. The framing bits, CRC6 and DL bits are not
1328 * looped. They are originated by the FALC-LH transmitter.
1329 *----------------------------------------------------------------------------
1330 */
falc_payload_loop(pc300_t * card,int ch,int loop_on)1331 void falc_payload_loop(pc300_t * card, int ch, int loop_on)
1332 {
1333 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1334 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1335 falc_t *pfalc = (falc_t *) & chan->falc;
1336 uclong falcbase = card->hw.falcbase;
1337
1338 if (loop_on) {
1339 // EVENT_FALC_ABNORMAL
1340 if (conf->media == IF_IFACE_T1) {
1341 /* Disable this interrupt as it may otherwise interfere with
1342 * other working boards. */
1343 cpc_writeb(falcbase + F_REG(IMR0, ch),
1344 cpc_readb(falcbase + F_REG(IMR0, ch)) | IMR0_PDEN);
1345 }
1346 falc_disable_comm(card, ch);
1347 // EVENT_FALC_ABNORMAL
1348 cpc_writeb(falcbase + F_REG(FMR2, ch),
1349 cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_PLB);
1350 if (conf->media == IF_IFACE_T1) {
1351 cpc_writeb(falcbase + F_REG(FMR4, ch),
1352 cpc_readb(falcbase + F_REG(FMR4, ch)) | FMR4_TM);
1353 } else {
1354 cpc_writeb(falcbase + F_REG(FMR5, ch),
1355 cpc_readb(falcbase + F_REG(FMR5, ch)) | XSP_TT0);
1356 }
1357 falc_open_all_timeslots(card, ch);
1358 pfalc->loop_active = 2;
1359 } else {
1360 cpc_writeb(falcbase + F_REG(FMR2, ch),
1361 cpc_readb(falcbase + F_REG(FMR2, ch)) & ~FMR2_PLB);
1362 if (conf->media == IF_IFACE_T1) {
1363 cpc_writeb(falcbase + F_REG(FMR4, ch),
1364 cpc_readb(falcbase + F_REG(FMR4, ch)) & ~FMR4_TM);
1365 } else {
1366 cpc_writeb(falcbase + F_REG(FMR5, ch),
1367 cpc_readb(falcbase + F_REG(FMR5, ch)) & ~XSP_TT0);
1368 }
1369 pfalc->sync = 0;
1370 cpc_writeb(falcbase + card->hw.cpld_reg2,
1371 cpc_readb(falcbase + card->hw.cpld_reg2) &
1372 ~(CPLD_REG2_FALC_LED2 << (2 * ch)));
1373 pfalc->active = 0;
1374 falc_issue_cmd(card, ch, CMDR_XRES);
1375 pfalc->loop_active = 0;
1376 }
1377 }
1378
1379 /*----------------------------------------------------------------------------
1380 * turn_off_xlu
1381 *----------------------------------------------------------------------------
1382 * Description: Turns XLU bit off in the proper register
1383 *----------------------------------------------------------------------------
1384 */
turn_off_xlu(pc300_t * card,int ch)1385 void turn_off_xlu(pc300_t * card, int ch)
1386 {
1387 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1388 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1389 uclong falcbase = card->hw.falcbase;
1390
1391 if (conf->media == IF_IFACE_T1) {
1392 cpc_writeb(falcbase + F_REG(FMR5, ch),
1393 cpc_readb(falcbase + F_REG(FMR5, ch)) & ~FMR5_XLU);
1394 } else {
1395 cpc_writeb(falcbase + F_REG(FMR3, ch),
1396 cpc_readb(falcbase + F_REG(FMR3, ch)) & ~FMR3_XLU);
1397 }
1398 }
1399
1400 /*----------------------------------------------------------------------------
1401 * turn_off_xld
1402 *----------------------------------------------------------------------------
1403 * Description: Turns XLD bit off in the proper register
1404 *----------------------------------------------------------------------------
1405 */
turn_off_xld(pc300_t * card,int ch)1406 void turn_off_xld(pc300_t * card, int ch)
1407 {
1408 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1409 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1410 uclong falcbase = card->hw.falcbase;
1411
1412 if (conf->media == IF_IFACE_T1) {
1413 cpc_writeb(falcbase + F_REG(FMR5, ch),
1414 cpc_readb(falcbase + F_REG(FMR5, ch)) & ~FMR5_XLD);
1415 } else {
1416 cpc_writeb(falcbase + F_REG(FMR3, ch),
1417 cpc_readb(falcbase + F_REG(FMR3, ch)) & ~FMR3_XLD);
1418 }
1419 }
1420
1421 /*----------------------------------------------------------------------------
1422 * falc_generate_loop_up_code
1423 *----------------------------------------------------------------------------
1424 * Description: This routine writes the proper FALC chip register in order
1425 * to generate a LOOP activation code over a T1/E1 line.
1426 *----------------------------------------------------------------------------
1427 */
falc_generate_loop_up_code(pc300_t * card,int ch)1428 void falc_generate_loop_up_code(pc300_t * card, int ch)
1429 {
1430 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1431 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1432 falc_t *pfalc = (falc_t *) & chan->falc;
1433 uclong falcbase = card->hw.falcbase;
1434
1435 if (conf->media == IF_IFACE_T1) {
1436 cpc_writeb(falcbase + F_REG(FMR5, ch),
1437 cpc_readb(falcbase + F_REG(FMR5, ch)) | FMR5_XLU);
1438 } else {
1439 cpc_writeb(falcbase + F_REG(FMR3, ch),
1440 cpc_readb(falcbase + F_REG(FMR3, ch)) | FMR3_XLU);
1441 }
1442 // EVENT_FALC_ABNORMAL
1443 if (conf->media == IF_IFACE_T1) {
1444 /* Disable this interrupt as it may otherwise interfere with
1445 * other working boards. */
1446 cpc_writeb(falcbase + F_REG(IMR0, ch),
1447 cpc_readb(falcbase + F_REG(IMR0, ch)) | IMR0_PDEN);
1448 }
1449 falc_disable_comm(card, ch);
1450 // EVENT_FALC_ABNORMAL
1451 pfalc->loop_gen = 1;
1452 }
1453
1454 /*----------------------------------------------------------------------------
1455 * falc_generate_loop_down_code
1456 *----------------------------------------------------------------------------
1457 * Description: This routine writes the proper FALC chip register in order
1458 * to generate a LOOP deactivation code over a T1/E1 line.
1459 *----------------------------------------------------------------------------
1460 */
falc_generate_loop_down_code(pc300_t * card,int ch)1461 void falc_generate_loop_down_code(pc300_t * card, int ch)
1462 {
1463 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1464 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1465 falc_t *pfalc = (falc_t *) & chan->falc;
1466 uclong falcbase = card->hw.falcbase;
1467
1468 if (conf->media == IF_IFACE_T1) {
1469 cpc_writeb(falcbase + F_REG(FMR5, ch),
1470 cpc_readb(falcbase + F_REG(FMR5, ch)) | FMR5_XLD);
1471 } else {
1472 cpc_writeb(falcbase + F_REG(FMR3, ch),
1473 cpc_readb(falcbase + F_REG(FMR3, ch)) | FMR3_XLD);
1474 }
1475 pfalc->sync = 0;
1476 cpc_writeb(falcbase + card->hw.cpld_reg2,
1477 cpc_readb(falcbase + card->hw.cpld_reg2) &
1478 ~(CPLD_REG2_FALC_LED2 << (2 * ch)));
1479 pfalc->active = 0;
1480 // falc_issue_cmd(card, ch, CMDR_XRES);
1481 pfalc->loop_gen = 0;
1482 }
1483
1484 /*----------------------------------------------------------------------------
1485 * falc_pattern_test
1486 *----------------------------------------------------------------------------
1487 * Description: This routine generates a pattern code and checks
1488 * it on the reception side.
1489 *----------------------------------------------------------------------------
1490 */
falc_pattern_test(pc300_t * card,int ch,unsigned int activate)1491 void falc_pattern_test(pc300_t * card, int ch, unsigned int activate)
1492 {
1493 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1494 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1495 falc_t *pfalc = (falc_t *) & chan->falc;
1496 uclong falcbase = card->hw.falcbase;
1497
1498 if (activate) {
1499 pfalc->prbs = 1;
1500 pfalc->bec = 0;
1501 if (conf->media == IF_IFACE_T1) {
1502 /* Disable local loop activation/deactivation detect */
1503 cpc_writeb(falcbase + F_REG(IMR3, ch),
1504 cpc_readb(falcbase + F_REG(IMR3, ch)) | IMR3_LLBSC);
1505 } else {
1506 /* Disable local loop activation/deactivation detect */
1507 cpc_writeb(falcbase + F_REG(IMR1, ch),
1508 cpc_readb(falcbase + F_REG(IMR1, ch)) | IMR1_LLBSC);
1509 }
1510 /* Activates generation and monitoring of PRBS
1511 * (Pseudo Random Bit Sequence) */
1512 cpc_writeb(falcbase + F_REG(LCR1, ch),
1513 cpc_readb(falcbase + F_REG(LCR1, ch)) | LCR1_EPRM | LCR1_XPRBS);
1514 } else {
1515 pfalc->prbs = 0;
1516 /* Deactivates generation and monitoring of PRBS
1517 * (Pseudo Random Bit Sequence) */
1518 cpc_writeb(falcbase + F_REG(LCR1, ch),
1519 cpc_readb(falcbase+F_REG(LCR1,ch)) & ~(LCR1_EPRM | LCR1_XPRBS));
1520 if (conf->media == IF_IFACE_T1) {
1521 /* Enable local loop activation/deactivation detect */
1522 cpc_writeb(falcbase + F_REG(IMR3, ch),
1523 cpc_readb(falcbase + F_REG(IMR3, ch)) & ~IMR3_LLBSC);
1524 } else {
1525 /* Enable local loop activation/deactivation detect */
1526 cpc_writeb(falcbase + F_REG(IMR1, ch),
1527 cpc_readb(falcbase + F_REG(IMR1, ch)) & ~IMR1_LLBSC);
1528 }
1529 }
1530 }
1531
1532 /*----------------------------------------------------------------------------
1533 * falc_pattern_test_error
1534 *----------------------------------------------------------------------------
1535 * Description: This routine returns the bit error counter value
1536 *----------------------------------------------------------------------------
1537 */
falc_pattern_test_error(pc300_t * card,int ch)1538 ucshort falc_pattern_test_error(pc300_t * card, int ch)
1539 {
1540 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1541 falc_t *pfalc = (falc_t *) & chan->falc;
1542
1543 return (pfalc->bec);
1544 }
1545
1546 /**********************************/
1547 /*** Net Interface Routines ***/
1548 /**********************************/
1549
1550 static void
cpc_trace(struct net_device * dev,struct sk_buff * skb_main,char rx_tx)1551 cpc_trace(struct net_device *dev, struct sk_buff *skb_main, char rx_tx)
1552 {
1553 struct sk_buff *skb;
1554
1555 if ((skb = dev_alloc_skb(10 + skb_main->len)) == NULL) {
1556 printk("%s: out of memory\n", dev->name);
1557 return;
1558 }
1559 skb_put(skb, 10 + skb_main->len);
1560
1561 skb->dev = dev;
1562 skb->protocol = htons(ETH_P_CUST);
1563 skb->mac.raw = skb->data;
1564 skb->pkt_type = PACKET_HOST;
1565 skb->len = 10 + skb_main->len;
1566
1567 memcpy(skb->data, dev->name, 5);
1568 skb->data[5] = '[';
1569 skb->data[6] = rx_tx;
1570 skb->data[7] = ']';
1571 skb->data[8] = ':';
1572 skb->data[9] = ' ';
1573 memcpy(&skb->data[10], skb_main->data, skb_main->len);
1574
1575 netif_rx(skb);
1576 }
1577
cpc_tx_timeout(struct net_device * dev)1578 void cpc_tx_timeout(struct net_device *dev)
1579 {
1580 pc300dev_t *d = (pc300dev_t *) dev->priv;
1581 pc300ch_t *chan = (pc300ch_t *) d->chan;
1582 pc300_t *card = (pc300_t *) chan->card;
1583 struct net_device_stats *stats = &d->hdlc->stats;
1584 int ch = chan->channel;
1585 uclong flags;
1586 ucchar ilar;
1587
1588 stats->tx_errors++;
1589 stats->tx_aborted_errors++;
1590 CPC_LOCK(card, flags);
1591 if ((ilar = cpc_readb(card->hw.scabase + ILAR)) != 0) {
1592 printk("%s: ILAR=0x%x\n", dev->name, ilar);
1593 cpc_writeb(card->hw.scabase + ILAR, ilar);
1594 cpc_writeb(card->hw.scabase + DMER, 0x80);
1595 }
1596 if (card->hw.type == PC300_TE) {
1597 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
1598 cpc_readb(card->hw.falcbase + card->hw.cpld_reg2) &
1599 ~(CPLD_REG2_FALC_LED1 << (2 * ch)));
1600 }
1601 dev->trans_start = jiffies;
1602 CPC_UNLOCK(card, flags);
1603 netif_wake_queue(dev);
1604 }
1605
cpc_queue_xmit(struct sk_buff * skb,struct net_device * dev)1606 int cpc_queue_xmit(struct sk_buff *skb, struct net_device *dev)
1607 {
1608 pc300dev_t *d = (pc300dev_t *) dev->priv;
1609 pc300ch_t *chan = (pc300ch_t *) d->chan;
1610 pc300_t *card = (pc300_t *) chan->card;
1611 struct net_device_stats *stats = &d->hdlc->stats;
1612 int ch = chan->channel;
1613 uclong flags;
1614 #ifdef PC300_DEBUG_TX
1615 int i;
1616 #endif
1617
1618 if (chan->conf.monitor) {
1619 /* In monitor mode no Tx is done: ignore packet */
1620 dev_kfree_skb(skb);
1621 return 0;
1622 } else if (!netif_carrier_ok(dev)) {
1623 /* DCD must be OFF: drop packet */
1624 dev_kfree_skb(skb);
1625 stats->tx_errors++;
1626 stats->tx_carrier_errors++;
1627 return 0;
1628 } else if (cpc_readb(card->hw.scabase + M_REG(ST3, ch)) & ST3_DCD) {
1629 printk("%s: DCD is OFF. Going administrative down.\n", dev->name);
1630 stats->tx_errors++;
1631 stats->tx_carrier_errors++;
1632 dev_kfree_skb(skb);
1633 netif_carrier_off(dev);
1634 CPC_LOCK(card, flags);
1635 cpc_writeb(card->hw.scabase + M_REG(CMD, ch), CMD_TX_BUF_CLR);
1636 if (card->hw.type == PC300_TE) {
1637 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
1638 cpc_readb(card->hw.falcbase + card->hw.cpld_reg2) &
1639 ~(CPLD_REG2_FALC_LED1 << (2 * ch)));
1640 }
1641 CPC_UNLOCK(card, flags);
1642 netif_wake_queue(dev);
1643 return 0;
1644 }
1645
1646 /* Write buffer to DMA buffers */
1647 if (dma_buf_write(card, ch, (ucchar *) skb->data, skb->len) != 0) {
1648 // printk("%s: write error. Dropping TX packet.\n", dev->name);
1649 netif_stop_queue(dev);
1650 dev_kfree_skb(skb);
1651 stats->tx_errors++;
1652 stats->tx_dropped++;
1653 return 0;
1654 }
1655 #ifdef PC300_DEBUG_TX
1656 printk("%s T:", dev->name);
1657 for (i = 0; i < skb->len; i++)
1658 printk(" %02x", *(skb->data + i));
1659 printk("\n");
1660 #endif
1661
1662 if (d->trace_on) {
1663 cpc_trace(dev, skb, 'T');
1664 }
1665 dev->trans_start = jiffies;
1666
1667 /* Start transmission */
1668 CPC_LOCK(card, flags);
1669 /* verify if it has more than one free descriptor */
1670 if (card->chan[ch].nfree_tx_bd <= 1) {
1671 /* don't have so stop the queue */
1672 netif_stop_queue(dev);
1673 }
1674 cpc_writel(card->hw.scabase + DTX_REG(EDAL, ch),
1675 TX_BD_ADDR(ch, chan->tx_next_bd));
1676 cpc_writeb(card->hw.scabase + M_REG(CMD, ch), CMD_TX_ENA);
1677 cpc_writeb(card->hw.scabase + DSR_TX(ch), DSR_DE);
1678 if (card->hw.type == PC300_TE) {
1679 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
1680 cpc_readb(card->hw.falcbase + card->hw.cpld_reg2) |
1681 (CPLD_REG2_FALC_LED1 << (2 * ch)));
1682 }
1683 CPC_UNLOCK(card, flags);
1684 dev_kfree_skb(skb);
1685
1686 return 0;
1687 }
1688
cpc_net_rx(hdlc_device * hdlc)1689 void cpc_net_rx(hdlc_device * hdlc)
1690 {
1691 struct net_device *dev = hdlc_to_dev(hdlc);
1692 pc300dev_t *d = (pc300dev_t *) dev->priv;
1693 pc300ch_t *chan = (pc300ch_t *) d->chan;
1694 pc300_t *card = (pc300_t *) chan->card;
1695 struct net_device_stats *stats = &d->hdlc->stats;
1696 int ch = chan->channel;
1697 #ifdef PC300_DEBUG_RX
1698 int i;
1699 #endif
1700 int rxb;
1701 struct sk_buff *skb;
1702
1703 while (1) {
1704 if ((rxb = dma_get_rx_frame_size(card, ch)) == -1)
1705 return;
1706
1707 if (!netif_carrier_ok(dev)) {
1708 /* DCD must be OFF: drop packet */
1709 printk("%s : DCD is OFF - drop %d rx bytes\n", dev->name, rxb);
1710 skb = NULL;
1711 } else {
1712 if (rxb > (dev->mtu + 40)) { /* add headers */
1713 printk("%s : MTU exceeded %d\n", dev->name, rxb);
1714 skb = NULL;
1715 } else {
1716 skb = dev_alloc_skb(rxb);
1717 if (skb == NULL) {
1718 printk("%s: Memory squeeze!!\n", dev->name);
1719 return;
1720 }
1721 skb->dev = dev;
1722 }
1723 }
1724
1725 if (((rxb = dma_buf_read(card, ch, skb)) <= 0) || (skb == NULL)) {
1726 #ifdef PC300_DEBUG_RX
1727 printk("%s: rxb = %x\n", dev->name, rxb);
1728 #endif
1729 if ((skb == NULL) && (rxb > 0)) {
1730 /* rxb > dev->mtu */
1731 stats->rx_errors++;
1732 stats->rx_length_errors++;
1733 continue;
1734 }
1735
1736 if (rxb < 0) { /* Invalid frame */
1737 rxb = -rxb;
1738 if (rxb & DST_OVR) {
1739 stats->rx_errors++;
1740 stats->rx_fifo_errors++;
1741 }
1742 if (rxb & DST_CRC) {
1743 stats->rx_errors++;
1744 stats->rx_crc_errors++;
1745 }
1746 if (rxb & (DST_RBIT | DST_SHRT | DST_ABT)) {
1747 stats->rx_errors++;
1748 stats->rx_frame_errors++;
1749 }
1750 }
1751 if (skb) {
1752 dev_kfree_skb_irq(skb);
1753 }
1754 continue;
1755 }
1756
1757 stats->rx_bytes += rxb;
1758
1759 #ifdef PC300_DEBUG_RX
1760 printk("%s R:", dev->name);
1761 for (i = 0; i < skb->len; i++)
1762 printk(" %02x", *(skb->data + i));
1763 printk("\n");
1764 #endif
1765 if (d->trace_on) {
1766 cpc_trace(dev, skb, 'R');
1767 }
1768 stats->rx_packets++;
1769 skb->mac.raw = skb->data;
1770 skb->protocol = hdlc_type_trans(skb, dev);
1771 netif_rx(skb);
1772 }
1773 }
1774
1775 /************************************/
1776 /*** PC300 Interrupt Routines ***/
1777 /************************************/
sca_tx_intr(pc300dev_t * dev)1778 static void sca_tx_intr(pc300dev_t *dev)
1779 {
1780 pc300ch_t *chan = (pc300ch_t *)dev->chan;
1781 pc300_t *card = (pc300_t *)chan->card;
1782 int ch = chan->channel;
1783 volatile pcsca_bd_t * ptdescr;
1784 struct net_device_stats *stats = &dev->hdlc->stats;
1785
1786 /* Clean up descriptors from previous transmission */
1787 ptdescr = (pcsca_bd_t *)(card->hw.rambase +
1788 TX_BD_ADDR(ch,chan->tx_first_bd));
1789 while ((cpc_readl(card->hw.scabase + DTX_REG(CDAL,ch)) !=
1790 TX_BD_ADDR(ch,chan->tx_first_bd)) &&
1791 (cpc_readb(&ptdescr->status) & DST_OSB)) {
1792 stats->tx_packets++;
1793 stats->tx_bytes += cpc_readw(&ptdescr->len);
1794 cpc_writeb(&ptdescr->status, DST_OSB);
1795 cpc_writew(&ptdescr->len, 0);
1796 chan->nfree_tx_bd++;
1797 chan->tx_first_bd = (chan->tx_first_bd + 1) & (N_DMA_TX_BUF - 1);
1798 ptdescr = (pcsca_bd_t *)(card->hw.rambase +
1799 TX_BD_ADDR(ch,chan->tx_first_bd));
1800 }
1801
1802 #ifdef CONFIG_PC300_MLPPP
1803 if (chan->conf.proto == PC300_PROTO_MLPPP) {
1804 cpc_tty_trigger_poll(dev);
1805 } else {
1806 #endif
1807 /* Tell the upper layer we are ready to transmit more packets */
1808 netif_wake_queue((struct net_device*)dev->hdlc);
1809 #ifdef CONFIG_PC300_MLPPP
1810 }
1811 #endif
1812 }
1813
sca_intr(pc300_t * card)1814 static void sca_intr(pc300_t * card)
1815 {
1816 uclong scabase = card->hw.scabase;
1817 volatile uclong status;
1818 int ch;
1819 int intr_count = 0;
1820 unsigned char dsr_rx;
1821
1822 while ((status = cpc_readl(scabase + ISR0)) != 0) {
1823 for (ch = 0; ch < card->hw.nchan; ch++) {
1824 pc300ch_t *chan = &card->chan[ch];
1825 pc300dev_t *d = &chan->d;
1826 hdlc_device *hdlc = d->hdlc;
1827 struct net_device *dev = hdlc_to_dev(hdlc);
1828
1829 spin_lock(&card->card_lock);
1830
1831 /**** Reception ****/
1832 if (status & IR0_DRX((IR0_DMIA | IR0_DMIB), ch)) {
1833 ucchar drx_stat = cpc_readb(scabase + DSR_RX(ch));
1834
1835 /* Clear RX interrupts */
1836 cpc_writeb(scabase + DSR_RX(ch), drx_stat | DSR_DWE);
1837
1838 #ifdef PC300_DEBUG_INTR
1839 printk ("sca_intr: RX intr chan[%d] (st=0x%08lx, dsr=0x%02x)\n",
1840 ch, status, drx_stat);
1841 #endif
1842 if (status & IR0_DRX(IR0_DMIA, ch)) {
1843 if (drx_stat & DSR_BOF) {
1844 #ifdef CONFIG_PC300_MLPPP
1845 if (chan->conf.proto == PC300_PROTO_MLPPP) {
1846 /* verify if driver is TTY */
1847 if ((cpc_readb(scabase + DSR_RX(ch)) & DSR_DE)) {
1848 rx_dma_stop(card, ch);
1849 }
1850 cpc_tty_receive(d);
1851 rx_dma_start(card, ch);
1852 } else
1853 #endif
1854 {
1855 if ((cpc_readb(scabase + DSR_RX(ch)) & DSR_DE)) {
1856 rx_dma_stop(card, ch);
1857 }
1858 cpc_net_rx(hdlc);
1859 /* Discard invalid frames */
1860 hdlc->stats.rx_errors++;
1861 hdlc->stats.rx_over_errors++;
1862 chan->rx_first_bd = 0;
1863 chan->rx_last_bd = N_DMA_RX_BUF - 1;
1864 rx_dma_start(card, ch);
1865 }
1866 }
1867 }
1868 if (status & IR0_DRX(IR0_DMIB, ch)) {
1869 if (drx_stat & DSR_EOM) {
1870 if (card->hw.type == PC300_TE) {
1871 cpc_writeb(card->hw.falcbase +
1872 card->hw.cpld_reg2,
1873 cpc_readb (card->hw.falcbase +
1874 card->hw.cpld_reg2) |
1875 (CPLD_REG2_FALC_LED1 << (2 * ch)));
1876 }
1877 #ifdef CONFIG_PC300_MLPPP
1878 if (chan->conf.proto == PC300_PROTO_MLPPP) {
1879 /* verify if driver is TTY */
1880 cpc_tty_receive(d);
1881 } else {
1882 cpc_net_rx(hdlc);
1883 }
1884 #else
1885 cpc_net_rx(hdlc);
1886 #endif
1887 if (card->hw.type == PC300_TE) {
1888 cpc_writeb(card->hw.falcbase +
1889 card->hw.cpld_reg2,
1890 cpc_readb (card->hw.falcbase +
1891 card->hw.cpld_reg2) &
1892 ~ (CPLD_REG2_FALC_LED1 << (2 * ch)));
1893 }
1894 }
1895 }
1896 if (!(dsr_rx = cpc_readb(scabase + DSR_RX(ch)) & DSR_DE)) {
1897 #ifdef PC300_DEBUG_INTR
1898 printk("%s: RX intr chan[%d] (st=0x%08lx, dsr=0x%02x, dsr2=0x%02x)\n",
1899 dev->name, ch, status, drx_stat, dsr_rx);
1900 #endif
1901 cpc_writeb(scabase + DSR_RX(ch), (dsr_rx | DSR_DE) & 0xfe);
1902 }
1903 }
1904
1905 /**** Transmission ****/
1906 if (status & IR0_DTX((IR0_EFT | IR0_DMIA | IR0_DMIB), ch)) {
1907 ucchar dtx_stat = cpc_readb(scabase + DSR_TX(ch));
1908
1909 /* Clear TX interrupts */
1910 cpc_writeb(scabase + DSR_TX(ch), dtx_stat | DSR_DWE);
1911
1912 #ifdef PC300_DEBUG_INTR
1913 printk ("sca_intr: TX intr chan[%d] (st=0x%08lx, dsr=0x%02x)\n",
1914 ch, status, dtx_stat);
1915 #endif
1916 if (status & IR0_DTX(IR0_EFT, ch)) {
1917 if (dtx_stat & DSR_UDRF) {
1918 if (cpc_readb (scabase + M_REG(TBN, ch)) != 0) {
1919 cpc_writeb(scabase + M_REG(CMD,ch), CMD_TX_BUF_CLR);
1920 }
1921 if (card->hw.type == PC300_TE) {
1922 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
1923 cpc_readb (card->hw.falcbase +
1924 card->hw.cpld_reg2) &
1925 ~ (CPLD_REG2_FALC_LED1 << (2 * ch)));
1926 }
1927 hdlc->stats.tx_errors++;
1928 hdlc->stats.tx_fifo_errors++;
1929 sca_tx_intr(d);
1930 }
1931 }
1932 if (status & IR0_DTX(IR0_DMIA, ch)) {
1933 if (dtx_stat & DSR_BOF) {
1934 }
1935 }
1936 if (status & IR0_DTX(IR0_DMIB, ch)) {
1937 if (dtx_stat & DSR_EOM) {
1938 if (card->hw.type == PC300_TE) {
1939 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
1940 cpc_readb (card->hw.falcbase +
1941 card->hw.cpld_reg2) &
1942 ~ (CPLD_REG2_FALC_LED1 << (2 * ch)));
1943 }
1944 sca_tx_intr(d);
1945 }
1946 }
1947 }
1948
1949 /**** MSCI ****/
1950 if (status & IR0_M(IR0_RXINTA, ch)) {
1951 ucchar st1 = cpc_readb(scabase + M_REG(ST1, ch));
1952
1953 /* Clear MSCI interrupts */
1954 cpc_writeb(scabase + M_REG(ST1, ch), st1);
1955
1956 #ifdef PC300_DEBUG_INTR
1957 printk("sca_intr: MSCI intr chan[%d] (st=0x%08lx, st1=0x%02x)\n",
1958 ch, status, st1);
1959 #endif
1960 if (st1 & ST1_CDCD) { /* DCD changed */
1961 if (cpc_readb(scabase + M_REG(ST3, ch)) & ST3_DCD) {
1962 printk ("%s: DCD is OFF. Going administrative down.\n",
1963 dev->name);
1964 #ifdef CONFIG_PC300_MLPPP
1965 if (chan->conf.proto != PC300_PROTO_MLPPP) {
1966 netif_carrier_off(dev);
1967 }
1968 #else
1969 netif_carrier_off(dev);
1970
1971 #endif
1972 card->chan[ch].d.line_off++;
1973 } else { /* DCD = 1 */
1974 printk ("%s: DCD is ON. Going administrative up.\n",
1975 dev->name);
1976 #ifdef CONFIG_PC300_MLPPP
1977 if (chan->conf.proto != PC300_PROTO_MLPPP)
1978 /* verify if driver is not TTY */
1979 #endif
1980 netif_carrier_on(dev);
1981 card->chan[ch].d.line_on++;
1982 }
1983 }
1984 }
1985 spin_unlock(&card->card_lock);
1986 }
1987 if (++intr_count == 10)
1988 /* Too much work at this board. Force exit */
1989 break;
1990 }
1991 }
1992
falc_t1_loop_detection(pc300_t * card,int ch,ucchar frs1)1993 static void falc_t1_loop_detection(pc300_t * card, int ch, ucchar frs1)
1994 {
1995 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1996 falc_t *pfalc = (falc_t *) & chan->falc;
1997 uclong falcbase = card->hw.falcbase;
1998
1999 if (((cpc_readb(falcbase + F_REG(LCR1, ch)) & LCR1_XPRBS) == 0) &&
2000 !pfalc->loop_gen) {
2001 if (frs1 & FRS1_LLBDD) {
2002 // A Line Loop Back Deactivation signal detected
2003 if (pfalc->loop_active) {
2004 falc_remote_loop(card, ch, 0);
2005 }
2006 } else {
2007 if ((frs1 & FRS1_LLBAD) &&
2008 ((cpc_readb(falcbase + F_REG(LCR1, ch)) & LCR1_EPRM) == 0)) {
2009 // A Line Loop Back Activation signal detected
2010 if (!pfalc->loop_active) {
2011 falc_remote_loop(card, ch, 1);
2012 }
2013 }
2014 }
2015 }
2016 }
2017
falc_e1_loop_detection(pc300_t * card,int ch,ucchar rsp)2018 static void falc_e1_loop_detection(pc300_t * card, int ch, ucchar rsp)
2019 {
2020 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
2021 falc_t *pfalc = (falc_t *) & chan->falc;
2022 uclong falcbase = card->hw.falcbase;
2023
2024 if (((cpc_readb(falcbase + F_REG(LCR1, ch)) & LCR1_XPRBS) == 0) &&
2025 !pfalc->loop_gen) {
2026 if (rsp & RSP_LLBDD) {
2027 // A Line Loop Back Deactivation signal detected
2028 if (pfalc->loop_active) {
2029 falc_remote_loop(card, ch, 0);
2030 }
2031 } else {
2032 if ((rsp & RSP_LLBAD) &&
2033 ((cpc_readb(falcbase + F_REG(LCR1, ch)) & LCR1_EPRM) == 0)) {
2034 // A Line Loop Back Activation signal detected
2035 if (!pfalc->loop_active) {
2036 falc_remote_loop(card, ch, 1);
2037 }
2038 }
2039 }
2040 }
2041 }
2042
falc_t1_intr(pc300_t * card,int ch)2043 static void falc_t1_intr(pc300_t * card, int ch)
2044 {
2045 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
2046 falc_t *pfalc = (falc_t *) & chan->falc;
2047 uclong falcbase = card->hw.falcbase;
2048 ucchar isr0, isr3, gis;
2049 ucchar dummy;
2050
2051 while ((gis = cpc_readb(falcbase + F_REG(GIS, ch))) != 0) {
2052 if (gis & GIS_ISR0) {
2053 isr0 = cpc_readb(falcbase + F_REG(FISR0, ch));
2054 if (isr0 & FISR0_PDEN) {
2055 /* Read the bit to clear the situation */
2056 if (cpc_readb(falcbase + F_REG(FRS1, ch)) &
2057 FRS1_PDEN) {
2058 pfalc->pden++;
2059 }
2060 }
2061 }
2062
2063 if (gis & GIS_ISR1) {
2064 dummy = cpc_readb(falcbase + F_REG(FISR1, ch));
2065 }
2066
2067 if (gis & GIS_ISR2) {
2068 dummy = cpc_readb(falcbase + F_REG(FISR2, ch));
2069 }
2070
2071 if (gis & GIS_ISR3) {
2072 isr3 = cpc_readb(falcbase + F_REG(FISR3, ch));
2073 if (isr3 & FISR3_SEC) {
2074 pfalc->sec++;
2075 falc_update_stats(card, ch);
2076 falc_check_status(card, ch,
2077 cpc_readb(falcbase + F_REG(FRS0, ch)));
2078 }
2079 if (isr3 & FISR3_ES) {
2080 pfalc->es++;
2081 }
2082 if (isr3 & FISR3_LLBSC) {
2083 falc_t1_loop_detection(card, ch,
2084 cpc_readb(falcbase + F_REG(FRS1, ch)));
2085 }
2086 }
2087 }
2088 }
2089
falc_e1_intr(pc300_t * card,int ch)2090 static void falc_e1_intr(pc300_t * card, int ch)
2091 {
2092 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
2093 falc_t *pfalc = (falc_t *) & chan->falc;
2094 uclong falcbase = card->hw.falcbase;
2095 ucchar isr1, isr2, isr3, gis, rsp;
2096 ucchar dummy;
2097
2098 while ((gis = cpc_readb(falcbase + F_REG(GIS, ch))) != 0) {
2099 rsp = cpc_readb(falcbase + F_REG(RSP, ch));
2100
2101 if (gis & GIS_ISR0) {
2102 dummy = cpc_readb(falcbase + F_REG(FISR0, ch));
2103 }
2104 if (gis & GIS_ISR1) {
2105 isr1 = cpc_readb(falcbase + F_REG(FISR1, ch));
2106 if (isr1 & FISR1_XMB) {
2107 if ((pfalc->xmb_cause & 2)
2108 && pfalc->multiframe_mode) {
2109 if (cpc_readb (falcbase + F_REG(FRS0, ch)) &
2110 (FRS0_LOS | FRS0_AIS | FRS0_LFA)) {
2111 cpc_writeb(falcbase + F_REG(XSP, ch),
2112 cpc_readb(falcbase + F_REG(XSP, ch))
2113 & ~XSP_AXS);
2114 } else {
2115 cpc_writeb(falcbase + F_REG(XSP, ch),
2116 cpc_readb(falcbase + F_REG(XSP, ch))
2117 | XSP_AXS);
2118 }
2119 }
2120 pfalc->xmb_cause = 0;
2121 cpc_writeb(falcbase + F_REG(IMR1, ch),
2122 cpc_readb(falcbase + F_REG(IMR1, ch)) | IMR1_XMB);
2123 }
2124 if (isr1 & FISR1_LLBSC) {
2125 falc_e1_loop_detection(card, ch, rsp);
2126 }
2127 }
2128 if (gis & GIS_ISR2) {
2129 isr2 = cpc_readb(falcbase + F_REG(FISR2, ch));
2130 if (isr2 & FISR2_T400MS) {
2131 cpc_writeb(falcbase + F_REG(XSW, ch),
2132 cpc_readb(falcbase + F_REG(XSW, ch)) | XSW_XRA);
2133 }
2134 if (isr2 & FISR2_MFAR) {
2135 cpc_writeb(falcbase + F_REG(XSW, ch),
2136 cpc_readb(falcbase + F_REG(XSW, ch)) & ~XSW_XRA);
2137 }
2138 if (isr2 & (FISR2_FAR | FISR2_LFA | FISR2_AIS | FISR2_LOS)) {
2139 pfalc->xmb_cause |= 2;
2140 cpc_writeb(falcbase + F_REG(IMR1, ch),
2141 cpc_readb(falcbase + F_REG(IMR1, ch)) & ~IMR1_XMB);
2142 }
2143 }
2144 if (gis & GIS_ISR3) {
2145 isr3 = cpc_readb(falcbase + F_REG(FISR3, ch));
2146 if (isr3 & FISR3_SEC) {
2147 pfalc->sec++;
2148 falc_update_stats(card, ch);
2149 falc_check_status(card, ch,
2150 cpc_readb(falcbase + F_REG(FRS0, ch)));
2151 }
2152 if (isr3 & FISR3_ES) {
2153 pfalc->es++;
2154 }
2155 }
2156 }
2157 }
2158
falc_intr(pc300_t * card)2159 static void falc_intr(pc300_t * card)
2160 {
2161 int ch;
2162
2163 for (ch = 0; ch < card->hw.nchan; ch++) {
2164 pc300ch_t *chan = &card->chan[ch];
2165 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
2166
2167 if (conf->media == IF_IFACE_T1) {
2168 falc_t1_intr(card, ch);
2169 } else {
2170 falc_e1_intr(card, ch);
2171 }
2172 }
2173 }
2174
cpc_intr(int irq,void * dev_id,struct pt_regs * regs)2175 static void cpc_intr(int irq, void *dev_id, struct pt_regs *regs)
2176 {
2177 pc300_t *card;
2178 volatile ucchar plx_status;
2179
2180 if ((card = (pc300_t *) dev_id) == 0) {
2181 #ifdef PC300_DEBUG_INTR
2182 printk("cpc_intr: spurious intr %d\n", irq);
2183 #endif
2184 return; /* spurious intr */
2185 }
2186
2187 if (card->hw.rambase == 0) {
2188 #ifdef PC300_DEBUG_INTR
2189 printk("cpc_intr: spurious intr2 %d\n", irq);
2190 #endif
2191 return; /* spurious intr */
2192 }
2193
2194 switch (card->hw.type) {
2195 case PC300_RSV:
2196 case PC300_X21:
2197 sca_intr(card);
2198 break;
2199
2200 case PC300_TE:
2201 while ( (plx_status = (cpc_readb(card->hw.plxbase + card->hw.intctl_reg) &
2202 (PLX_9050_LINT1_STATUS | PLX_9050_LINT2_STATUS))) != 0) {
2203 if (plx_status & PLX_9050_LINT1_STATUS) { /* SCA Interrupt */
2204 sca_intr(card);
2205 }
2206 if (plx_status & PLX_9050_LINT2_STATUS) { /* FALC Interrupt */
2207 falc_intr(card);
2208 }
2209 }
2210 break;
2211 }
2212 }
2213
cpc_sca_status(pc300_t * card,int ch)2214 void cpc_sca_status(pc300_t * card, int ch)
2215 {
2216 ucchar ilar;
2217 uclong scabase = card->hw.scabase;
2218 uclong flags;
2219
2220 tx_dma_buf_check(card, ch);
2221 rx_dma_buf_check(card, ch);
2222 ilar = cpc_readb(scabase + ILAR);
2223 printk ("ILAR=0x%02x, WCRL=0x%02x, PCR=0x%02x, BTCR=0x%02x, BOLR=0x%02x\n",
2224 ilar, cpc_readb(scabase + WCRL), cpc_readb(scabase + PCR),
2225 cpc_readb(scabase + BTCR), cpc_readb(scabase + BOLR));
2226 printk("TX_CDA=0x%08lx, TX_EDA=0x%08lx\n",
2227 (uclong) cpc_readl(scabase + DTX_REG(CDAL, ch)),
2228 (uclong) cpc_readl(scabase + DTX_REG(EDAL, ch)));
2229 printk("RX_CDA=0x%08lx, RX_EDA=0x%08lx, BFL=0x%04x\n",
2230 (uclong) cpc_readl(scabase + DRX_REG(CDAL, ch)),
2231 (uclong) cpc_readl(scabase + DRX_REG(EDAL, ch)),
2232 cpc_readw(scabase + DRX_REG(BFLL, ch)));
2233 printk("DMER=0x%02x, DSR_TX=0x%02x, DSR_RX=0x%02x\n",
2234 cpc_readb(scabase + DMER), cpc_readb(scabase + DSR_TX(ch)),
2235 cpc_readb(scabase + DSR_RX(ch)));
2236 printk("DMR_TX=0x%02x, DMR_RX=0x%02x, DIR_TX=0x%02x, DIR_RX=0x%02x\n",
2237 cpc_readb(scabase + DMR_TX(ch)), cpc_readb(scabase + DMR_RX(ch)),
2238 cpc_readb(scabase + DIR_TX(ch)),
2239 cpc_readb(scabase + DIR_RX(ch)));
2240 printk("DCR_TX=0x%02x, DCR_RX=0x%02x, FCT_TX=0x%02x, FCT_RX=0x%02x\n",
2241 cpc_readb(scabase + DCR_TX(ch)), cpc_readb(scabase + DCR_RX(ch)),
2242 cpc_readb(scabase + FCT_TX(ch)),
2243 cpc_readb(scabase + FCT_RX(ch)));
2244 printk("MD0=0x%02x, MD1=0x%02x, MD2=0x%02x, MD3=0x%02x, IDL=0x%02x\n",
2245 cpc_readb(scabase + M_REG(MD0, ch)),
2246 cpc_readb(scabase + M_REG(MD1, ch)),
2247 cpc_readb(scabase + M_REG(MD2, ch)),
2248 cpc_readb(scabase + M_REG(MD3, ch)),
2249 cpc_readb(scabase + M_REG(IDL, ch)));
2250 printk("CMD=0x%02x, SA0=0x%02x, SA1=0x%02x, TFN=0x%02x, CTL=0x%02x\n",
2251 cpc_readb(scabase + M_REG(CMD, ch)),
2252 cpc_readb(scabase + M_REG(SA0, ch)),
2253 cpc_readb(scabase + M_REG(SA1, ch)),
2254 cpc_readb(scabase + M_REG(TFN, ch)),
2255 cpc_readb(scabase + M_REG(CTL, ch)));
2256 printk("ST0=0x%02x, ST1=0x%02x, ST2=0x%02x, ST3=0x%02x, ST4=0x%02x\n",
2257 cpc_readb(scabase + M_REG(ST0, ch)),
2258 cpc_readb(scabase + M_REG(ST1, ch)),
2259 cpc_readb(scabase + M_REG(ST2, ch)),
2260 cpc_readb(scabase + M_REG(ST3, ch)),
2261 cpc_readb(scabase + M_REG(ST4, ch)));
2262 printk ("CST0=0x%02x, CST1=0x%02x, CST2=0x%02x, CST3=0x%02x, FST=0x%02x\n",
2263 cpc_readb(scabase + M_REG(CST0, ch)),
2264 cpc_readb(scabase + M_REG(CST1, ch)),
2265 cpc_readb(scabase + M_REG(CST2, ch)),
2266 cpc_readb(scabase + M_REG(CST3, ch)),
2267 cpc_readb(scabase + M_REG(FST, ch)));
2268 printk("TRC0=0x%02x, TRC1=0x%02x, RRC=0x%02x, TBN=0x%02x, RBN=0x%02x\n",
2269 cpc_readb(scabase + M_REG(TRC0, ch)),
2270 cpc_readb(scabase + M_REG(TRC1, ch)),
2271 cpc_readb(scabase + M_REG(RRC, ch)),
2272 cpc_readb(scabase + M_REG(TBN, ch)),
2273 cpc_readb(scabase + M_REG(RBN, ch)));
2274 printk("TFS=0x%02x, TNR0=0x%02x, TNR1=0x%02x, RNR=0x%02x\n",
2275 cpc_readb(scabase + M_REG(TFS, ch)),
2276 cpc_readb(scabase + M_REG(TNR0, ch)),
2277 cpc_readb(scabase + M_REG(TNR1, ch)),
2278 cpc_readb(scabase + M_REG(RNR, ch)));
2279 printk("TCR=0x%02x, RCR=0x%02x, TNR1=0x%02x, RNR=0x%02x\n",
2280 cpc_readb(scabase + M_REG(TCR, ch)),
2281 cpc_readb(scabase + M_REG(RCR, ch)),
2282 cpc_readb(scabase + M_REG(TNR1, ch)),
2283 cpc_readb(scabase + M_REG(RNR, ch)));
2284 printk("TXS=0x%02x, RXS=0x%02x, EXS=0x%02x, TMCT=0x%02x, TMCR=0x%02x\n",
2285 cpc_readb(scabase + M_REG(TXS, ch)),
2286 cpc_readb(scabase + M_REG(RXS, ch)),
2287 cpc_readb(scabase + M_REG(EXS, ch)),
2288 cpc_readb(scabase + M_REG(TMCT, ch)),
2289 cpc_readb(scabase + M_REG(TMCR, ch)));
2290 printk("IE0=0x%02x, IE1=0x%02x, IE2=0x%02x, IE4=0x%02x, FIE=0x%02x\n",
2291 cpc_readb(scabase + M_REG(IE0, ch)),
2292 cpc_readb(scabase + M_REG(IE1, ch)),
2293 cpc_readb(scabase + M_REG(IE2, ch)),
2294 cpc_readb(scabase + M_REG(IE4, ch)),
2295 cpc_readb(scabase + M_REG(FIE, ch)));
2296 printk("IER0=0x%08lx\n", (uclong) cpc_readl(scabase + IER0));
2297
2298 if (ilar != 0) {
2299 CPC_LOCK(card, flags);
2300 cpc_writeb(scabase + ILAR, ilar);
2301 cpc_writeb(scabase + DMER, 0x80);
2302 CPC_UNLOCK(card, flags);
2303 }
2304 }
2305
cpc_falc_status(pc300_t * card,int ch)2306 void cpc_falc_status(pc300_t * card, int ch)
2307 {
2308 pc300ch_t *chan = &card->chan[ch];
2309 falc_t *pfalc = (falc_t *) & chan->falc;
2310 uclong flags;
2311
2312 CPC_LOCK(card, flags);
2313 printk("CH%d: %s %s %d channels\n",
2314 ch, (pfalc->sync ? "SYNC" : ""), (pfalc->active ? "ACTIVE" : ""),
2315 pfalc->num_channels);
2316
2317 printk(" pden=%d, los=%d, losr=%d, lfa=%d, farec=%d\n",
2318 pfalc->pden, pfalc->los, pfalc->losr, pfalc->lfa, pfalc->farec);
2319 printk(" lmfa=%d, ais=%d, sec=%d, es=%d, rai=%d\n",
2320 pfalc->lmfa, pfalc->ais, pfalc->sec, pfalc->es, pfalc->rai);
2321 printk(" bec=%d, fec=%d, cvc=%d, cec=%d, ebc=%d\n",
2322 pfalc->bec, pfalc->fec, pfalc->cvc, pfalc->cec, pfalc->ebc);
2323
2324 printk("\n");
2325 printk(" STATUS: %s %s %s %s %s %s\n",
2326 (pfalc->red_alarm ? "RED" : ""),
2327 (pfalc->blue_alarm ? "BLU" : ""),
2328 (pfalc->yellow_alarm ? "YEL" : ""),
2329 (pfalc->loss_fa ? "LFA" : ""),
2330 (pfalc->loss_mfa ? "LMF" : ""), (pfalc->prbs ? "PRB" : ""));
2331 CPC_UNLOCK(card, flags);
2332 }
2333
cpc_change_mtu(struct net_device * dev,int new_mtu)2334 int cpc_change_mtu(struct net_device *dev, int new_mtu)
2335 {
2336 if ((new_mtu < 128) || (new_mtu > PC300_DEF_MTU))
2337 return -EINVAL;
2338 dev->mtu = new_mtu;
2339 return 0;
2340 }
2341
cpc_ioctl(struct net_device * dev,struct ifreq * ifr,int cmd)2342 int cpc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2343 {
2344 hdlc_device *hdlc = dev_to_hdlc(dev);
2345 pc300dev_t *d = (pc300dev_t *) dev->priv;
2346 pc300ch_t *chan = (pc300ch_t *) d->chan;
2347 pc300_t *card = (pc300_t *) chan->card;
2348 pc300conf_t conf_aux;
2349 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
2350 int ch = chan->channel;
2351 void *arg = (void *) ifr->ifr_data;
2352 uclong scabase = card->hw.scabase;
2353
2354 if (!capable(CAP_NET_ADMIN))
2355 return -EPERM;
2356
2357 switch (cmd) {
2358 case SIOCGPC300CONF:
2359 #ifdef CONFIG_PC300_MLPPP
2360 if (conf->proto != PC300_PROTO_MLPPP) {
2361 conf->proto = hdlc->proto;
2362 }
2363 #else
2364 conf->proto = hdlc->proto;
2365 #endif
2366 memcpy(&conf_aux.conf, conf, sizeof(pc300chconf_t));
2367 memcpy(&conf_aux.hw, &card->hw, sizeof(pc300hw_t));
2368 if (!arg ||
2369 copy_to_user(arg, &conf_aux, sizeof(pc300conf_t)))
2370 return -EINVAL;
2371 return 0;
2372 case SIOCSPC300CONF:
2373 if (!suser())
2374 return -EPERM;
2375 if (!arg ||
2376 copy_from_user(&conf_aux.conf, arg, sizeof(pc300chconf_t)))
2377 return -EINVAL;
2378 if (card->hw.cpld_id < 0x02 &&
2379 conf_aux.conf.fr_mode == PC300_FR_UNFRAMED) {
2380 /* CPLD_ID < 0x02 doesn't support Unframed E1 */
2381 return -EINVAL;
2382 }
2383 #ifdef CONFIG_PC300_MLPPP
2384 if (conf_aux.conf.proto == PC300_PROTO_MLPPP) {
2385 if (conf->proto != PC300_PROTO_MLPPP) {
2386 memcpy(conf, &conf_aux.conf, sizeof(pc300chconf_t));
2387 cpc_tty_init(d); /* init TTY driver */
2388 }
2389 } else {
2390 if (conf_aux.conf.proto == 0xffff) {
2391 if (conf->proto == PC300_PROTO_MLPPP){
2392 /* ifdown interface */
2393 cpc_close(dev);
2394 }
2395 } else {
2396 memcpy(conf, &conf_aux.conf, sizeof(pc300chconf_t));
2397 hdlc->proto = conf->proto;
2398 }
2399 }
2400 #else
2401 memcpy(conf, &conf_aux.conf, sizeof(pc300chconf_t));
2402 hdlc->proto = conf->proto;
2403 #endif
2404 return 0;
2405 case SIOCGPC300STATUS:
2406 cpc_sca_status(card, ch);
2407 return 0;
2408 case SIOCGPC300FALCSTATUS:
2409 cpc_falc_status(card, ch);
2410 return 0;
2411
2412 case SIOCGPC300UTILSTATS:
2413 {
2414 if (!arg) { /* clear statistics */
2415 memset(&hdlc->stats, 0, sizeof(struct net_device_stats));
2416 if (card->hw.type == PC300_TE) {
2417 memset(&chan->falc, 0, sizeof(falc_t));
2418 }
2419 } else {
2420 pc300stats_t pc300stats;
2421
2422 memset(&pc300stats, 0, sizeof(pc300stats_t));
2423 pc300stats.hw_type = card->hw.type;
2424 pc300stats.line_on = card->chan[ch].d.line_on;
2425 pc300stats.line_off = card->chan[ch].d.line_off;
2426 memcpy(&pc300stats.gen_stats, &hdlc->stats,
2427 sizeof(struct net_device_stats));
2428 if (card->hw.type == PC300_TE)
2429 memcpy(&pc300stats.te_stats,&chan->falc,sizeof(falc_t));
2430 if (copy_to_user(arg, &pc300stats, sizeof(pc300stats_t)))
2431 return -EFAULT;
2432 }
2433 return 0;
2434 }
2435
2436 case SIOCGPC300UTILSTATUS:
2437 {
2438 struct pc300status pc300status;
2439
2440 pc300status.hw_type = card->hw.type;
2441 if (card->hw.type == PC300_TE) {
2442 pc300status.te_status.sync = chan->falc.sync;
2443 pc300status.te_status.red_alarm = chan->falc.red_alarm;
2444 pc300status.te_status.blue_alarm = chan->falc.blue_alarm;
2445 pc300status.te_status.loss_fa = chan->falc.loss_fa;
2446 pc300status.te_status.yellow_alarm =chan->falc.yellow_alarm;
2447 pc300status.te_status.loss_mfa = chan->falc.loss_mfa;
2448 pc300status.te_status.prbs = chan->falc.prbs;
2449 } else {
2450 pc300status.gen_status.dcd =
2451 !(cpc_readb (scabase + M_REG(ST3, ch)) & ST3_DCD);
2452 pc300status.gen_status.cts =
2453 !(cpc_readb (scabase + M_REG(ST3, ch)) & ST3_CTS);
2454 pc300status.gen_status.rts =
2455 !(cpc_readb (scabase + M_REG(CTL, ch)) & CTL_RTS);
2456 pc300status.gen_status.dtr =
2457 !(cpc_readb (scabase + M_REG(CTL, ch)) & CTL_DTR);
2458 /* There is no DSR in HD64572 */
2459 }
2460 if (!arg
2461 || copy_to_user(arg, &pc300status, sizeof(pc300status_t)))
2462 return -EINVAL;
2463 return 0;
2464 }
2465
2466 case SIOCSPC300TRACE:
2467 /* Sets/resets a trace_flag for the respective device */
2468 if (!arg || copy_from_user(&d->trace_on, arg,sizeof(unsigned char)))
2469 return -EINVAL;
2470 return 0;
2471
2472 case SIOCSPC300LOOPBACK:
2473 {
2474 struct pc300loopback pc300loop;
2475
2476 /* TE boards only */
2477 if (card->hw.type != PC300_TE)
2478 return -EINVAL;
2479
2480 if (!arg ||
2481 copy_from_user(&pc300loop, arg, sizeof(pc300loopback_t)))
2482 return -EINVAL;
2483 switch (pc300loop.loop_type) {
2484 case PC300LOCLOOP: /* Turn the local loop on/off */
2485 falc_local_loop(card, ch, pc300loop.loop_on);
2486 return 0;
2487
2488 case PC300REMLOOP: /* Turn the remote loop on/off */
2489 falc_remote_loop(card, ch, pc300loop.loop_on);
2490 return 0;
2491
2492 case PC300PAYLOADLOOP: /* Turn the payload loop on/off */
2493 falc_payload_loop(card, ch, pc300loop.loop_on);
2494 return 0;
2495
2496 case PC300GENLOOPUP: /* Generate loop UP */
2497 if (pc300loop.loop_on) {
2498 falc_generate_loop_up_code (card, ch);
2499 } else {
2500 turn_off_xlu(card, ch);
2501 }
2502 return 0;
2503
2504 case PC300GENLOOPDOWN: /* Generate loop DOWN */
2505 if (pc300loop.loop_on) {
2506 falc_generate_loop_down_code (card, ch);
2507 } else {
2508 turn_off_xld(card, ch);
2509 }
2510 return 0;
2511
2512 default:
2513 return -EINVAL;
2514 }
2515 }
2516
2517 case SIOCSPC300PATTERNTEST:
2518 /* Turn the pattern test on/off and show the errors counter */
2519 {
2520 struct pc300patterntst pc300patrntst;
2521
2522 /* TE boards only */
2523 if (card->hw.type != PC300_TE)
2524 return -EINVAL;
2525
2526 if (card->hw.cpld_id < 0x02) {
2527 /* CPLD_ID < 0x02 doesn't support pattern test */
2528 return -EINVAL;
2529 }
2530
2531 if (!arg ||
2532 copy_from_user(&pc300patrntst,arg,sizeof(pc300patterntst_t)))
2533 return -EINVAL;
2534 if (pc300patrntst.patrntst_on == 2) {
2535 if (chan->falc.prbs == 0) {
2536 falc_pattern_test(card, ch, 1);
2537 }
2538 pc300patrntst.num_errors =
2539 falc_pattern_test_error(card, ch);
2540 if (!arg
2541 || copy_to_user(arg, &pc300patrntst,
2542 sizeof (pc300patterntst_t)))
2543 return -EINVAL;
2544 } else {
2545 falc_pattern_test(card, ch, pc300patrntst.patrntst_on);
2546 }
2547 return 0;
2548 }
2549
2550 case SIOCWANDEV:
2551 switch (ifr->ifr_settings.type) {
2552 case IF_GET_IFACE:
2553 {
2554 const size_t size = sizeof(sync_serial_settings);
2555 sync_serial_settings *line = ifr->ifr_settings.ifs_ifsu.sync;
2556
2557 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
2558 if (ifr->ifr_settings.size < size) {
2559 ifr->ifr_settings.size = size; /* data size wanted */
2560 return -ENOBUFS;
2561 }
2562 if (copy_to_user(line, &conf->phys_settings, size))
2563 return -EFAULT;
2564 return 0;
2565 }
2566
2567 case IF_IFACE_V35:
2568 case IF_IFACE_V24:
2569 case IF_IFACE_X21:
2570 {
2571 const size_t size = sizeof(sync_serial_settings);
2572 sync_serial_settings *line = ifr->ifr_settings.ifs_ifsu.sync;
2573
2574 if (!capable(CAP_NET_ADMIN)) {
2575 return -EPERM;
2576 }
2577 if (ifr->ifr_settings.size != size) {
2578 return -ENOMEM; //incorrect data len
2579 }
2580 if (copy_from_user(&conf->phys_settings, line, size)) {
2581 return -EFAULT;
2582 }
2583 if (conf->phys_settings.loopback) {
2584 cpc_writeb(card->hw.scabase + M_REG(MD2, ch),
2585 cpc_readb(card->hw.scabase + M_REG(MD2, ch)) |
2586 MD2_LOOP_MIR);
2587 }
2588 conf->media = ifr->ifr_settings.type;
2589 return 0;
2590 }
2591
2592 case IF_IFACE_T1:
2593 case IF_IFACE_E1:
2594 {
2595 const size_t te_size = sizeof(te1_settings);
2596 const size_t size = sizeof(sync_serial_settings);
2597 sync_serial_settings *line = ifr->ifr_settings.ifs_ifsu.sync;
2598
2599 if (!capable(CAP_NET_ADMIN)) {
2600 return -EPERM;
2601 }
2602 if (ifr->ifr_settings.size != te_size) {
2603 return -ENOMEM; //incorrect data len
2604 }
2605 if (copy_from_user(&conf->phys_settings, line, size)) {
2606 return -EFAULT;
2607 }/* Ignoring HDLC slot_map for a while */
2608 if (conf->phys_settings.loopback) {
2609 cpc_writeb(card->hw.scabase + M_REG(MD2, ch),
2610 cpc_readb(card->hw.scabase + M_REG(MD2, ch)) |
2611 MD2_LOOP_MIR);
2612 }
2613 conf->media = ifr->ifr_settings.type;
2614 return 0;
2615 }
2616
2617 default:
2618 return hdlc_ioctl(dev, ifr, cmd);
2619 }
2620
2621 default:
2622 return hdlc_ioctl(dev, ifr, cmd);
2623 }
2624 }
2625
cpc_get_stats(struct net_device * dev)2626 static struct net_device_stats *cpc_get_stats(struct net_device *dev)
2627 {
2628 pc300dev_t *d = (pc300dev_t *) dev->priv;
2629
2630 if (d)
2631 return &d->hdlc->stats;
2632 else
2633 return NULL;
2634 }
2635
clock_rate_calc(uclong rate,uclong clock,int * br_io)2636 static int clock_rate_calc(uclong rate, uclong clock, int *br_io)
2637 {
2638 int br, tc;
2639 int br_pwr, error;
2640
2641 if (rate == 0)
2642 return (0);
2643
2644 for (br = 0, br_pwr = 1; br <= 9; br++, br_pwr <<= 1) {
2645 if ((tc = clock / br_pwr / rate) <= 0xff) {
2646 *br_io = br;
2647 break;
2648 }
2649 }
2650
2651 if (tc <= 0xff) {
2652 error = ((rate - (clock / br_pwr / rate)) / rate) * 1000;
2653 /* Errors bigger than +/- 1% won't be tolerated */
2654 if (error < -10 || error > 10)
2655 return (-1);
2656 else
2657 return (tc);
2658 } else {
2659 return (-1);
2660 }
2661 }
2662
ch_config(pc300dev_t * d)2663 int ch_config(pc300dev_t * d)
2664 {
2665 pc300ch_t *chan = (pc300ch_t *) d->chan;
2666 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
2667 pc300_t *card = (pc300_t *) chan->card;
2668 uclong scabase = card->hw.scabase;
2669 uclong plxbase = card->hw.plxbase;
2670 int ch = chan->channel;
2671 uclong clkrate = chan->conf.phys_settings.clock_rate;
2672 uclong clktype = chan->conf.phys_settings.clock_type;
2673 ucshort encoding = chan->conf.proto_settings.encoding;
2674 ucshort parity = chan->conf.proto_settings.parity;
2675 int tmc, br;
2676 ucchar md0, md2;
2677
2678 /* Reset the channel */
2679 cpc_writeb(scabase + M_REG(CMD, ch), CMD_CH_RST);
2680
2681 /* Configure the SCA registers */
2682 switch (parity) {
2683 case PARITY_NONE:
2684 md0 = MD0_BIT_SYNC;
2685 break;
2686 case PARITY_CRC16_PR0:
2687 md0 = MD0_CRC16_0|MD0_CRCC0|MD0_BIT_SYNC;
2688 break;
2689 case PARITY_CRC16_PR1:
2690 md0 = MD0_CRC16_1|MD0_CRCC0|MD0_BIT_SYNC;
2691 break;
2692 case PARITY_CRC32_PR1_CCITT:
2693 md0 = MD0_CRC32|MD0_CRCC0|MD0_BIT_SYNC;
2694 break;
2695 case PARITY_CRC16_PR1_CCITT:
2696 default:
2697 md0 = MD0_CRC_CCITT|MD0_CRCC0|MD0_BIT_SYNC;
2698 break;
2699 }
2700 switch (encoding) {
2701 case ENCODING_NRZI:
2702 md2 = MD2_F_DUPLEX|MD2_ADPLL_X8|MD2_NRZI;
2703 break;
2704 case ENCODING_FM_MARK: /* FM1 */
2705 md2 = MD2_F_DUPLEX|MD2_ADPLL_X8|MD2_FM|MD2_FM1;
2706 break;
2707 case ENCODING_FM_SPACE: /* FM0 */
2708 md2 = MD2_F_DUPLEX|MD2_ADPLL_X8|MD2_FM|MD2_FM0;
2709 break;
2710 case ENCODING_MANCHESTER: /* It's not working... */
2711 md2 = MD2_F_DUPLEX|MD2_ADPLL_X8|MD2_FM|MD2_MANCH;
2712 break;
2713 case ENCODING_NRZ:
2714 default:
2715 md2 = MD2_F_DUPLEX|MD2_ADPLL_X8|MD2_NRZ;
2716 break;
2717 }
2718 cpc_writeb(scabase + M_REG(MD0, ch), md0);
2719 cpc_writeb(scabase + M_REG(MD1, ch), 0);
2720 cpc_writeb(scabase + M_REG(MD2, ch), md2);
2721 cpc_writeb(scabase + M_REG(IDL, ch), 0x7e);
2722 cpc_writeb(scabase + M_REG(CTL, ch), CTL_URSKP | CTL_IDLC);
2723
2724 /* Configure HW media */
2725 switch (card->hw.type) {
2726 case PC300_RSV:
2727 if (conf->media == IF_IFACE_V35) {
2728 cpc_writel((plxbase + card->hw.gpioc_reg),
2729 cpc_readl(plxbase + card->hw.gpioc_reg) | PC300_CHMEDIA_MASK(ch));
2730 } else {
2731 cpc_writel((plxbase + card->hw.gpioc_reg),
2732 cpc_readl(plxbase + card->hw.gpioc_reg) & ~PC300_CHMEDIA_MASK(ch));
2733 }
2734 break;
2735
2736 case PC300_X21:
2737 break;
2738
2739 case PC300_TE:
2740 te_config(card, ch);
2741 break;
2742 }
2743
2744 switch (card->hw.type) {
2745 case PC300_RSV:
2746 case PC300_X21:
2747 if (clktype == CLOCK_INT || clktype == CLOCK_TXINT) {
2748 /* Calculate the clkrate parameters */
2749 tmc = clock_rate_calc(clkrate, card->hw.clock, &br);
2750 cpc_writeb(scabase + M_REG(TMCT, ch), tmc);
2751 cpc_writeb(scabase + M_REG(TXS, ch),
2752 (TXS_DTRXC | TXS_IBRG | br));
2753 if (clktype == CLOCK_INT) {
2754 cpc_writeb(scabase + M_REG(TMCR, ch), tmc);
2755 cpc_writeb(scabase + M_REG(RXS, ch),
2756 (RXS_IBRG | br));
2757 } else {
2758 cpc_writeb(scabase + M_REG(TMCR, ch), 1);
2759 cpc_writeb(scabase + M_REG(RXS, ch), 0);
2760 }
2761 if (card->hw.type == PC300_X21) {
2762 cpc_writeb(scabase + M_REG(GPO, ch), 1);
2763 cpc_writeb(scabase + M_REG(EXS, ch), EXS_TES1 | EXS_RES1);
2764 } else {
2765 cpc_writeb(scabase + M_REG(EXS, ch), EXS_TES1);
2766 }
2767 } else {
2768 cpc_writeb(scabase + M_REG(TMCT, ch), 1);
2769 if (clktype == CLOCK_EXT) {
2770 cpc_writeb(scabase + M_REG(TXS, ch),
2771 TXS_DTRXC);
2772 } else {
2773 cpc_writeb(scabase + M_REG(TXS, ch),
2774 TXS_DTRXC|TXS_RCLK);
2775 }
2776 cpc_writeb(scabase + M_REG(TMCR, ch), 1);
2777 cpc_writeb(scabase + M_REG(RXS, ch), 0);
2778 if (card->hw.type == PC300_X21) {
2779 cpc_writeb(scabase + M_REG(GPO, ch), 0);
2780 cpc_writeb(scabase + M_REG(EXS, ch), EXS_TES1 | EXS_RES1);
2781 } else {
2782 cpc_writeb(scabase + M_REG(EXS, ch), EXS_TES1);
2783 }
2784 }
2785 break;
2786
2787 case PC300_TE:
2788 /* SCA always receives clock from the FALC chip */
2789 cpc_writeb(scabase + M_REG(TMCT, ch), 1);
2790 cpc_writeb(scabase + M_REG(TXS, ch), 0);
2791 cpc_writeb(scabase + M_REG(TMCR, ch), 1);
2792 cpc_writeb(scabase + M_REG(RXS, ch), 0);
2793 cpc_writeb(scabase + M_REG(EXS, ch), 0);
2794 break;
2795 }
2796
2797 /* Enable Interrupts */
2798 cpc_writel(scabase + IER0,
2799 cpc_readl(scabase + IER0) |
2800 IR0_M(IR0_RXINTA, ch) |
2801 IR0_DRX(IR0_EFT | IR0_DMIA | IR0_DMIB, ch) |
2802 IR0_DTX(IR0_EFT | IR0_DMIA | IR0_DMIB, ch));
2803 cpc_writeb(scabase + M_REG(IE0, ch),
2804 cpc_readl(scabase + M_REG(IE0, ch)) | IE0_RXINTA);
2805 cpc_writeb(scabase + M_REG(IE1, ch),
2806 cpc_readl(scabase + M_REG(IE1, ch)) | IE1_CDCD);
2807
2808 return 0;
2809 }
2810
rx_config(pc300dev_t * d)2811 int rx_config(pc300dev_t * d)
2812 {
2813 pc300ch_t *chan = (pc300ch_t *) d->chan;
2814 pc300_t *card = (pc300_t *) chan->card;
2815 uclong scabase = card->hw.scabase;
2816 int ch = chan->channel;
2817
2818 cpc_writeb(scabase + DSR_RX(ch), 0);
2819
2820 /* General RX settings */
2821 cpc_writeb(scabase + M_REG(RRC, ch), 0);
2822 cpc_writeb(scabase + M_REG(RNR, ch), 16);
2823
2824 /* Enable reception */
2825 cpc_writeb(scabase + M_REG(CMD, ch), CMD_RX_CRC_INIT);
2826 cpc_writeb(scabase + M_REG(CMD, ch), CMD_RX_ENA);
2827
2828 /* Initialize DMA stuff */
2829 chan->rx_first_bd = 0;
2830 chan->rx_last_bd = N_DMA_RX_BUF - 1;
2831 rx_dma_buf_init(card, ch);
2832 cpc_writeb(scabase + DCR_RX(ch), DCR_FCT_CLR);
2833 cpc_writeb(scabase + DMR_RX(ch), (DMR_TMOD | DMR_NF));
2834 cpc_writeb(scabase + DIR_RX(ch), (DIR_EOM | DIR_BOF));
2835
2836 /* Start DMA */
2837 rx_dma_start(card, ch);
2838
2839 return 0;
2840 }
2841
tx_config(pc300dev_t * d)2842 int tx_config(pc300dev_t * d)
2843 {
2844 pc300ch_t *chan = (pc300ch_t *) d->chan;
2845 pc300_t *card = (pc300_t *) chan->card;
2846 uclong scabase = card->hw.scabase;
2847 int ch = chan->channel;
2848
2849 cpc_writeb(scabase + DSR_TX(ch), 0);
2850
2851 /* General TX settings */
2852 cpc_writeb(scabase + M_REG(TRC0, ch), 0);
2853 cpc_writeb(scabase + M_REG(TFS, ch), 32);
2854 cpc_writeb(scabase + M_REG(TNR0, ch), 20);
2855 cpc_writeb(scabase + M_REG(TNR1, ch), 48);
2856 cpc_writeb(scabase + M_REG(TCR, ch), 8);
2857
2858 /* Enable transmission */
2859 cpc_writeb(scabase + M_REG(CMD, ch), CMD_TX_CRC_INIT);
2860
2861 /* Initialize DMA stuff */
2862 chan->tx_first_bd = 0;
2863 chan->tx_next_bd = 0;
2864 tx_dma_buf_init(card, ch);
2865 cpc_writeb(scabase + DCR_TX(ch), DCR_FCT_CLR);
2866 cpc_writeb(scabase + DMR_TX(ch), (DMR_TMOD | DMR_NF));
2867 cpc_writeb(scabase + DIR_TX(ch), (DIR_EOM | DIR_BOF | DIR_UDRF));
2868 cpc_writel(scabase + DTX_REG(CDAL, ch), TX_BD_ADDR(ch, chan->tx_first_bd));
2869 cpc_writel(scabase + DTX_REG(EDAL, ch), TX_BD_ADDR(ch, chan->tx_next_bd));
2870
2871 return 0;
2872 }
2873
cpc_attach(hdlc_device * hdlc,unsigned short encoding,unsigned short parity)2874 static int cpc_attach(hdlc_device * hdlc, unsigned short encoding,
2875 unsigned short parity)
2876 {
2877 struct net_device * dev = hdlc_to_dev(hdlc);
2878 pc300dev_t *d = (pc300dev_t *)dev->priv;
2879 pc300ch_t *chan = (pc300ch_t *)d->chan;
2880 pc300_t *card = (pc300_t *)chan->card;
2881 pc300chconf_t *conf = (pc300chconf_t *)&chan->conf;
2882
2883 if (card->hw.type == PC300_TE) {
2884 if (encoding != ENCODING_NRZ && encoding != ENCODING_NRZI) {
2885 return -EINVAL;
2886 }
2887 } else {
2888 if (encoding != ENCODING_NRZ && encoding != ENCODING_NRZI &&
2889 encoding != ENCODING_FM_MARK && encoding != ENCODING_FM_SPACE) {
2890 /* Driver doesn't support ENCODING_MANCHESTER yet */
2891 return -EINVAL;
2892 }
2893 }
2894
2895 if (parity != PARITY_NONE && parity != PARITY_CRC16_PR0 &&
2896 parity != PARITY_CRC16_PR1 && parity != PARITY_CRC32_PR1_CCITT &&
2897 parity != PARITY_CRC16_PR1_CCITT) {
2898 return -EINVAL;
2899 }
2900
2901 conf->proto_settings.encoding = encoding;
2902 conf->proto_settings.parity = parity;
2903 return 0;
2904 }
2905
cpc_opench(pc300dev_t * d)2906 void cpc_opench(pc300dev_t * d)
2907 {
2908 pc300ch_t *chan = (pc300ch_t *) d->chan;
2909 pc300_t *card = (pc300_t *) chan->card;
2910 int ch = chan->channel;
2911 uclong scabase = card->hw.scabase;
2912
2913 ch_config(d);
2914
2915 rx_config(d);
2916
2917 tx_config(d);
2918
2919 /* Assert RTS and DTR */
2920 cpc_writeb(scabase + M_REG(CTL, ch),
2921 cpc_readb(scabase + M_REG(CTL, ch)) & ~(CTL_RTS | CTL_DTR));
2922 }
2923
cpc_closech(pc300dev_t * d)2924 void cpc_closech(pc300dev_t * d)
2925 {
2926 pc300ch_t *chan = (pc300ch_t *) d->chan;
2927 pc300_t *card = (pc300_t *) chan->card;
2928 falc_t *pfalc = (falc_t *) & chan->falc;
2929 int ch = chan->channel;
2930
2931 cpc_writeb(card->hw.scabase + M_REG(CMD, ch), CMD_CH_RST);
2932 rx_dma_stop(card, ch);
2933 tx_dma_stop(card, ch);
2934
2935 if (card->hw.type == PC300_TE) {
2936 memset(pfalc, 0, sizeof(falc_t));
2937 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
2938 cpc_readb(card->hw.falcbase + card->hw.cpld_reg2) &
2939 ~((CPLD_REG2_FALC_TX_CLK | CPLD_REG2_FALC_RX_CLK |
2940 CPLD_REG2_FALC_LED2) << (2 * ch)));
2941 /* Reset the FALC chip */
2942 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
2943 cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) |
2944 (CPLD_REG1_FALC_RESET << (2 * ch)));
2945 udelay(10000);
2946 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
2947 cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) &
2948 ~(CPLD_REG1_FALC_RESET << (2 * ch)));
2949 }
2950 }
2951
cpc_open(struct net_device * dev)2952 int cpc_open(struct net_device *dev)
2953 {
2954 hdlc_device *hdlc = dev_to_hdlc(dev);
2955 pc300dev_t *d = (pc300dev_t *) dev->priv;
2956 struct ifreq ifr;
2957 int result;
2958
2959 #ifdef PC300_DEBUG_OTHER
2960 printk("pc300: cpc_open");
2961 #endif
2962
2963 if (hdlc->proto == IF_PROTO_PPP) {
2964 d->if_ptr = &hdlc->state.ppp.pppdev;
2965 }
2966
2967 result = hdlc_open(hdlc);
2968 if (hdlc->proto == IF_PROTO_PPP) {
2969 dev->priv = d;
2970 }
2971 if (result) {
2972 return result;
2973 }
2974
2975 MOD_INC_USE_COUNT;
2976 sprintf(ifr.ifr_name, "%s", dev->name);
2977 cpc_opench(d);
2978 netif_start_queue(dev);
2979 return 0;
2980 }
2981
cpc_close(struct net_device * dev)2982 int cpc_close(struct net_device *dev)
2983 {
2984 hdlc_device *hdlc = dev_to_hdlc(dev);
2985 pc300dev_t *d = (pc300dev_t *) dev->priv;
2986 pc300ch_t *chan = (pc300ch_t *) d->chan;
2987 pc300_t *card = (pc300_t *) chan->card;
2988 uclong flags;
2989
2990 #ifdef PC300_DEBUG_OTHER
2991 printk("pc300: cpc_close");
2992 #endif
2993
2994 netif_stop_queue(dev);
2995
2996 CPC_LOCK(card, flags);
2997 cpc_closech(d);
2998 CPC_UNLOCK(card, flags);
2999
3000 hdlc_close(hdlc);
3001 if (hdlc->proto == IF_PROTO_PPP) {
3002 d->if_ptr = NULL;
3003 }
3004 #ifdef CONFIG_PC300_MLPPP
3005 if (chan->conf.proto == PC300_PROTO_MLPPP) {
3006 cpc_tty_unregister_service(d);
3007 chan->conf.proto = 0xffff;
3008 }
3009 #endif
3010
3011 MOD_DEC_USE_COUNT;
3012 return 0;
3013 }
3014
detect_ram(pc300_t * card)3015 static uclong detect_ram(pc300_t * card)
3016 {
3017 uclong i;
3018 ucchar data;
3019 uclong rambase = card->hw.rambase;
3020
3021 card->hw.ramsize = PC300_RAMSIZE;
3022 /* Let's find out how much RAM is present on this board */
3023 for (i = 0; i < card->hw.ramsize; i++) {
3024 data = (ucchar) (i & 0xff);
3025 cpc_writeb(rambase + i, data);
3026 if (cpc_readb(rambase + i) != data) {
3027 break;
3028 }
3029 }
3030 return (i);
3031 }
3032
plx_init(pc300_t * card)3033 static void plx_init(pc300_t * card)
3034 {
3035 struct RUNTIME_9050 *plx_ctl = (struct RUNTIME_9050 *) card->hw.plxbase;
3036
3037 /* Reset PLX */
3038 cpc_writel(&plx_ctl->init_ctrl,
3039 cpc_readl(&plx_ctl->init_ctrl) | 0x40000000);
3040 udelay(10000L);
3041 cpc_writel(&plx_ctl->init_ctrl,
3042 cpc_readl(&plx_ctl->init_ctrl) & ~0x40000000);
3043
3044 /* Reload Config. Registers from EEPROM */
3045 cpc_writel(&plx_ctl->init_ctrl,
3046 cpc_readl(&plx_ctl->init_ctrl) | 0x20000000);
3047 udelay(10000L);
3048 cpc_writel(&plx_ctl->init_ctrl,
3049 cpc_readl(&plx_ctl->init_ctrl) & ~0x20000000);
3050
3051 }
3052
show_version(void)3053 static inline void show_version(void)
3054 {
3055 char *rcsvers, *rcsdate, *tmp;
3056
3057 rcsvers = strchr(rcsid, ' ');
3058 rcsvers++;
3059 tmp = strchr(rcsvers, ' ');
3060 *tmp++ = '\0';
3061 rcsdate = strchr(tmp, ' ');
3062 rcsdate++;
3063 tmp = strrchr(rcsdate, ' ');
3064 *tmp = '\0';
3065 printk(KERN_INFO "Cyclades-PC300 driver %s %s (built %s %s)\n",
3066 rcsvers, rcsdate, __DATE__, __TIME__);
3067 } /* show_version */
3068
cpc_init_card(pc300_t * card)3069 static void cpc_init_card(pc300_t * card)
3070 {
3071 int i, devcount = 0;
3072 static int board_nbr = 1;
3073
3074 /* Enable interrupts on the PCI bridge */
3075 plx_init(card);
3076 cpc_writew(card->hw.plxbase + card->hw.intctl_reg,
3077 cpc_readw(card->hw.plxbase + card->hw.intctl_reg) | 0x0040);
3078
3079 #ifdef USE_PCI_CLOCK
3080 /* Set board clock to PCI clock */
3081 cpc_writel(card->hw.plxbase + card->hw.gpioc_reg,
3082 cpc_readl(card->hw.plxbase + card->hw.gpioc_reg) | 0x00000004UL);
3083 card->hw.clock = PC300_PCI_CLOCK;
3084 #else
3085 /* Set board clock to internal oscillator clock */
3086 cpc_writel(card->hw.plxbase + card->hw.gpioc_reg,
3087 cpc_readl(card->hw.plxbase + card->hw.gpioc_reg) & ~0x00000004UL);
3088 card->hw.clock = PC300_OSC_CLOCK;
3089 #endif
3090
3091 /* Detect actual on-board RAM size */
3092 card->hw.ramsize = detect_ram(card);
3093
3094 /* Set Global SCA-II registers */
3095 cpc_writeb(card->hw.scabase + PCR, PCR_PR2);
3096 cpc_writeb(card->hw.scabase + BTCR, 0x10);
3097 cpc_writeb(card->hw.scabase + WCRL, 0);
3098 cpc_writeb(card->hw.scabase + DMER, 0x80);
3099
3100 if (card->hw.type == PC300_TE) {
3101 ucchar reg1;
3102
3103 /* Check CPLD version */
3104 reg1 = cpc_readb(card->hw.falcbase + CPLD_REG1);
3105 cpc_writeb(card->hw.falcbase + CPLD_REG1, (reg1 + 0x5a));
3106 if (cpc_readb(card->hw.falcbase + CPLD_REG1) == reg1) {
3107 /* New CPLD */
3108 card->hw.cpld_id = cpc_readb(card->hw.falcbase + CPLD_ID_REG);
3109 card->hw.cpld_reg1 = CPLD_V2_REG1;
3110 card->hw.cpld_reg2 = CPLD_V2_REG2;
3111 } else {
3112 /* old CPLD */
3113 card->hw.cpld_id = 0;
3114 card->hw.cpld_reg1 = CPLD_REG1;
3115 card->hw.cpld_reg2 = CPLD_REG2;
3116 cpc_writeb(card->hw.falcbase + CPLD_REG1, reg1);
3117 }
3118
3119 /* Enable the board's global clock */
3120 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
3121 cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) |
3122 CPLD_REG1_GLOBAL_CLK);
3123
3124 }
3125
3126 for (i = 0; i < card->hw.nchan; i++) {
3127 pc300ch_t *chan = &card->chan[i];
3128 pc300dev_t *d = &chan->d;
3129 hdlc_device *hdlc;
3130 struct net_device *dev;
3131
3132 chan->card = card;
3133 chan->channel = i;
3134 chan->conf.phys_settings.clock_rate = 0;
3135 chan->conf.phys_settings.clock_type = CLOCK_EXT;
3136 chan->conf.proto_settings.encoding = ENCODING_NRZ;
3137 chan->conf.proto_settings.parity = PARITY_CRC16_PR1_CCITT;
3138 switch (card->hw.type) {
3139 case PC300_TE:
3140 chan->conf.media = IF_IFACE_T1;
3141 chan->conf.lcode = PC300_LC_B8ZS;
3142 chan->conf.fr_mode = PC300_FR_ESF;
3143 chan->conf.lbo = PC300_LBO_0_DB;
3144 chan->conf.rx_sens = PC300_RX_SENS_SH;
3145 chan->conf.tslot_bitmap = 0xffffffffUL;
3146 break;
3147
3148 case PC300_X21:
3149 chan->conf.media = IF_IFACE_X21;
3150 break;
3151
3152 case PC300_RSV:
3153 default:
3154 chan->conf.media = IF_IFACE_V35;
3155 break;
3156 }
3157 chan->conf.proto = IF_PROTO_PPP;
3158 chan->tx_first_bd = 0;
3159 chan->tx_next_bd = 0;
3160 chan->rx_first_bd = 0;
3161 chan->rx_last_bd = N_DMA_RX_BUF - 1;
3162 chan->nfree_tx_bd = N_DMA_TX_BUF;
3163
3164 d->chan = chan;
3165 d->tx_skb = NULL;
3166 d->trace_on = 0;
3167 d->line_on = 0;
3168 d->line_off = 0;
3169
3170 d->hdlc = (hdlc_device *) kmalloc(sizeof(hdlc_device), GFP_KERNEL);
3171 if (d->hdlc == NULL)
3172 continue;
3173 memset(d->hdlc, 0, sizeof(hdlc_device));
3174
3175 hdlc = d->hdlc;
3176 hdlc->xmit = cpc_queue_xmit;
3177 hdlc->attach = cpc_attach;
3178
3179 dev = hdlc_to_dev(hdlc);
3180
3181 dev->mem_start = card->hw.ramphys;
3182 dev->mem_end = card->hw.ramphys + card->hw.ramsize - 1;
3183 dev->irq = card->hw.irq;
3184 dev->init = NULL;
3185 dev->tx_queue_len = PC300_TX_QUEUE_LEN;
3186 dev->mtu = PC300_DEF_MTU;
3187
3188 dev->open = cpc_open;
3189 dev->stop = cpc_close;
3190 dev->tx_timeout = cpc_tx_timeout;
3191 dev->watchdog_timeo = PC300_TX_TIMEOUT;
3192 dev->get_stats = cpc_get_stats;
3193 dev->set_multicast_list = NULL;
3194 dev->set_mac_address = NULL;
3195 dev->change_mtu = cpc_change_mtu;
3196 dev->do_ioctl = cpc_ioctl;
3197
3198 if (register_hdlc_device(hdlc) == 0) {
3199 dev->priv = d; /* We need 'priv', hdlc doesn't */
3200 printk("%s: Cyclades-PC300/", dev->name);
3201 switch (card->hw.type) {
3202 case PC300_TE:
3203 if (card->hw.bus == PC300_PMC) {
3204 printk("TE-M");
3205 } else {
3206 printk("TE ");
3207 }
3208 break;
3209
3210 case PC300_X21:
3211 printk("X21 ");
3212 break;
3213
3214 case PC300_RSV:
3215 default:
3216 printk("RSV ");
3217 break;
3218 }
3219 printk (" #%d, %ldKB of RAM at 0x%08lx, IRQ%d, channel %d.\n",
3220 board_nbr, card->hw.ramsize / 1024,
3221 card->hw.ramphys, card->hw.irq, i + 1);
3222 devcount++;
3223 } else {
3224 printk ("Dev%d on card(0x%08lx): unable to allocate i/f name.\n",
3225 i + 1, card->hw.ramphys);
3226 *(dev->name) = 0;
3227 kfree(d->hdlc);
3228 continue;
3229 }
3230 }
3231 spin_lock_init(&card->card_lock);
3232
3233 board_nbr++;
3234 }
3235
3236 static int __devinit
cpc_init_one(struct pci_dev * pdev,const struct pci_device_id * ent)3237 cpc_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3238 {
3239 static int first_time = 1;
3240 ucchar cpc_rev_id;
3241 int err = 0, eeprom_outdated = 0;
3242 ucshort device_id;
3243 pc300_t *card;
3244
3245 if (first_time) {
3246 first_time = 0;
3247 show_version();
3248 #ifdef CONFIG_PC300_MLPPP
3249 cpc_tty_reset_var();
3250 #endif
3251 }
3252
3253 card = (pc300_t *) kmalloc(sizeof(pc300_t), GFP_KERNEL);
3254 if (card == NULL) {
3255 printk("PC300 found at RAM 0x%08lx, "
3256 "but could not allocate card structure.\n",
3257 pci_resource_start(pdev, 3));
3258 return -ENOMEM;
3259 }
3260 memset(card, 0, sizeof(pc300_t));
3261
3262 /* read PCI configuration area */
3263 device_id = ent->device;
3264 card->hw.irq = pdev->irq;
3265 card->hw.iophys = pci_resource_start(pdev, 1);
3266 card->hw.iosize = pci_resource_len(pdev, 1);
3267 card->hw.scaphys = pci_resource_start(pdev, 2);
3268 card->hw.scasize = pci_resource_len(pdev, 2);
3269 card->hw.ramphys = pci_resource_start(pdev, 3);
3270 card->hw.alloc_ramsize = pci_resource_len(pdev, 3);
3271 card->hw.falcphys = pci_resource_start(pdev, 4);
3272 card->hw.falcsize = pci_resource_len(pdev, 4);
3273 card->hw.plxphys = pci_resource_start(pdev, 5);
3274 card->hw.plxsize = pci_resource_len(pdev, 5);
3275 pci_read_config_byte(pdev, PCI_REVISION_ID, &cpc_rev_id);
3276
3277 switch (device_id) {
3278 case PCI_DEVICE_ID_PC300_RX_1:
3279 case PCI_DEVICE_ID_PC300_TE_1:
3280 card->hw.nchan = 1;
3281 break;
3282
3283 case PCI_DEVICE_ID_PC300_RX_2:
3284 case PCI_DEVICE_ID_PC300_TE_2:
3285 default:
3286 card->hw.nchan = PC300_MAXCHAN;
3287 break;
3288 }
3289 #ifdef PC300_DEBUG_PCI
3290 printk("cpc (bus=0x0%x,pci_id=0x%x,", pdev->bus->number, pdev->devfn);
3291 printk("rev_id=%d) IRQ%d\n", cpc_rev_id, card->hw.irq);
3292 printk("cpc:found ramaddr=0x%08lx plxaddr=0x%08lx "
3293 "ctladdr=0x%08lx falcaddr=0x%08lx\n",
3294 card->hw.ramphys, card->hw.plxphys, card->hw.scaphys,
3295 card->hw.falcphys);
3296 #endif
3297 /* Although we don't use this I/O region, we should
3298 * request it from the kernel anyway, to avoid problems
3299 * with other drivers accessing it. */
3300 if (!request_region(card->hw.iophys, card->hw.iosize, "PLX Registers")) {
3301 /* In case we can't allocate it, warn user */
3302 printk("WARNING: couldn't allocate I/O region for PC300 board "
3303 "at 0x%08lx!\n", card->hw.ramphys);
3304 }
3305
3306 if (card->hw.plxphys) {
3307 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, card->hw.plxphys);
3308 } else {
3309 eeprom_outdated = 1;
3310 card->hw.plxphys = pci_resource_start(pdev, 0);
3311 card->hw.plxsize = pci_resource_len(pdev, 0);
3312 }
3313
3314 if (!request_mem_region(card->hw.plxphys, card->hw.plxsize,
3315 "PLX Registers")) {
3316 printk("PC300 found at RAM 0x%08lx, "
3317 "but could not allocate PLX mem region.\n",
3318 card->hw.ramphys);
3319 err = -ENODEV;
3320 goto err_release_io;
3321 }
3322 if (!request_mem_region(card->hw.ramphys, card->hw.alloc_ramsize,
3323 "On-board RAM")) {
3324 printk("PC300 found at RAM 0x%08lx, "
3325 "but could not allocate RAM mem region.\n",
3326 card->hw.ramphys);
3327 err = -ENODEV;
3328 goto err_release_plx;
3329 }
3330 if (!request_mem_region(card->hw.scaphys, card->hw.scasize,
3331 "SCA-II Registers")) {
3332 printk("PC300 found at RAM 0x%08lx, "
3333 "but could not allocate SCA mem region.\n",
3334 card->hw.ramphys);
3335 err = -ENODEV;
3336 goto err_release_ram;
3337 }
3338
3339 if ((err = pci_enable_device(pdev)) != 0)
3340 goto err_release_sca;
3341
3342 card->hw.plxbase = (uclong) ioremap(card->hw.plxphys, card->hw.plxsize);
3343 card->hw.rambase = (uclong) ioremap(card->hw.ramphys,
3344 card->hw.alloc_ramsize);
3345 card->hw.scabase = (uclong) ioremap(card->hw.scaphys, card->hw.scasize);
3346 switch (device_id) {
3347 case PCI_DEVICE_ID_PC300_TE_1:
3348 case PCI_DEVICE_ID_PC300_TE_2:
3349 request_mem_region(card->hw.falcphys, card->hw.falcsize,
3350 "FALC Registers");
3351 card->hw.falcbase = (uclong) ioremap(card->hw.falcphys,
3352 card->hw.falcsize);
3353 break;
3354
3355 case PCI_DEVICE_ID_PC300_RX_1:
3356 case PCI_DEVICE_ID_PC300_RX_2:
3357 default:
3358 card->hw.falcbase = 0;
3359 break;
3360 }
3361
3362 #ifdef PC300_DEBUG_PCI
3363 printk("cpc: relocate ramaddr=0x%08lx plxaddr=0x%08lx "
3364 "ctladdr=0x%08lx falcaddr=0x%08lx\n",
3365 card->hw.rambase, card->hw.plxbase, card->hw.scabase,
3366 card->hw.falcbase);
3367 #endif
3368
3369 /* Set PCI drv pointer to the card structure */
3370 pdev->driver_data = card;
3371
3372 /* Set board type */
3373 switch (device_id) {
3374 case PCI_DEVICE_ID_PC300_TE_1:
3375 case PCI_DEVICE_ID_PC300_TE_2:
3376 card->hw.type = PC300_TE;
3377 card->hw.bus = PC300_PCI;
3378 /* Set PLX register offsets */
3379 card->hw.gpioc_reg = 0x50;
3380 card->hw.intctl_reg = 0x4c;
3381 break;
3382 case PCI_DEVICE_ID_PC300_RX_1:
3383 case PCI_DEVICE_ID_PC300_RX_2:
3384 default:
3385 card->hw.bus = PC300_PCI;
3386 /* Set PLX register offsets */
3387 card->hw.gpioc_reg = 0x50;
3388 card->hw.intctl_reg = 0x4c;
3389
3390 if ((cpc_readl(card->hw.plxbase + card->hw.gpioc_reg) & PC300_CTYPE_MASK)) {
3391 card->hw.type = PC300_X21;
3392 } else {
3393 card->hw.type = PC300_RSV;
3394 }
3395 break;
3396 }
3397
3398 /* Allocate IRQ */
3399 if (request_irq(card->hw.irq, cpc_intr, SA_SHIRQ, "Cyclades-PC300", card)) {
3400 printk ("PC300 found at RAM 0x%08lx, but could not allocate IRQ%d.\n",
3401 card->hw.ramphys, card->hw.irq);
3402 goto err_io_unmap;
3403 }
3404
3405 cpc_init_card(card);
3406
3407 if (eeprom_outdated)
3408 printk("WARNING: PC300 with outdated EEPROM.\n");
3409 return 0;
3410
3411 err_io_unmap:
3412 iounmap((void *) card->hw.plxbase);
3413 iounmap((void *) card->hw.scabase);
3414 iounmap((void *) card->hw.rambase);
3415 if (card->hw.type == PC300_TE) {
3416 iounmap((void *) card->hw.falcbase);
3417 release_mem_region(card->hw.falcphys, card->hw.falcsize);
3418 }
3419 err_release_sca:
3420 release_mem_region(card->hw.scaphys, card->hw.scasize);
3421 err_release_ram:
3422 release_mem_region(card->hw.ramphys, card->hw.alloc_ramsize);
3423 err_release_plx:
3424 release_mem_region(card->hw.plxphys, card->hw.plxsize);
3425 err_release_io:
3426 release_region(card->hw.iophys, card->hw.iosize);
3427 kfree(card);
3428 return -ENODEV;
3429 }
3430
cpc_remove_one(struct pci_dev * pdev)3431 static void __devexit cpc_remove_one(struct pci_dev *pdev)
3432 {
3433 pc300_t *card = (pc300_t *) pdev->driver_data;
3434
3435 if (card->hw.rambase != 0) {
3436 int i;
3437
3438 /* Disable interrupts on the PCI bridge */
3439 cpc_writew(card->hw.plxbase + card->hw.intctl_reg,
3440 cpc_readw(card->hw.plxbase + card->hw.intctl_reg) & ~(0x0040));
3441
3442 for (i = 0; i < card->hw.nchan; i++) {
3443 unregister_hdlc_device(card->chan[i].d.hdlc);
3444 }
3445 iounmap((void *) card->hw.plxbase);
3446 iounmap((void *) card->hw.scabase);
3447 iounmap((void *) card->hw.rambase);
3448 release_mem_region(card->hw.plxphys, card->hw.plxsize);
3449 release_mem_region(card->hw.ramphys, card->hw.alloc_ramsize);
3450 release_mem_region(card->hw.scaphys, card->hw.scasize);
3451 release_region(card->hw.iophys, card->hw.iosize);
3452 if (card->hw.type == PC300_TE) {
3453 iounmap((void *) card->hw.falcbase);
3454 release_mem_region(card->hw.falcphys, card->hw.falcsize);
3455 }
3456 if (card->hw.irq)
3457 free_irq(card->hw.irq, card);
3458 kfree(card);
3459 }
3460 }
3461
3462 static struct pci_driver cpc_driver = {
3463 .name = "pc300",
3464 .id_table = cpc_pci_dev_id,
3465 .probe = cpc_init_one,
3466 .remove = __devexit_p(cpc_remove_one),
3467 };
3468
cpc_init(void)3469 static int __init cpc_init(void)
3470 {
3471 return pci_module_init(&cpc_driver);
3472 }
3473
cpc_cleanup_module(void)3474 static void __exit cpc_cleanup_module(void)
3475 {
3476 pci_unregister_driver(&cpc_driver);
3477 }
3478
3479 module_init(cpc_init);
3480 module_exit(cpc_cleanup_module);
3481
3482 MODULE_DESCRIPTION("Cyclades-PC300 cards driver");
3483 MODULE_AUTHOR( "Author: Ivan Passos <ivan.passos@cyclades.com>\r\n"
3484 "Maintainer: PC300 Maintainer <pc300@cyclades.com");
3485 MODULE_LICENSE("GPL");
3486
3487