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Searched refs:KSEG1 (Results 1 – 25 of 48) sorted by relevance

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/linux-2.4.37.9/include/asm-mips/vr4181/
Dvr4181.h33 #define VR4181_BCUCNTREG1 __preg16(KSEG1 + 0x0A000000) /* BCU control register 1 (R/W) */
34 #define VR4181_CMUCLKMSK __preg16(KSEG1 + 0x0A000004) /* Clock mask register (R/W) */
43 #define VR4181_BCUSPEEDREG __preg16(KSEG1 + 0x0A00000C) /* BCU access time parameter (R/W) */
44 #define VR4181_BCURFCNTREG __preg16(KSEG1 + 0x0A000010) /* BCU refresh control register (R/W) */
45 #define VR4181_REVIDREG __preg16(KSEG1 + 0x0A000014) /* Revision ID register (R) */
46 #define VR4181_CLKSPEEDREG __preg16(KSEG1 + 0x0A000018) /* Clock speed register (R) */
47 #define VR4181_EDOMCYTREG __preg16(KSEG1 + 0x0A000300) /* Memory cycle timing register (R/W) */
48 #define VR4181_MEMCFG_REG __preg16(KSEG1 + 0x0A000304) /* Memory configuration register (R/W) */
49 #define VR4181_MODE_REG __preg16(KSEG1 + 0x0A000308) /* SDRAM mode register (R/W) */
50 #define VR4181_SDTIMINGREG __preg16(KSEG1 + 0x0A00030C) /* SDRAM timing register (R/W) */
[all …]
/linux-2.4.37.9/arch/mips/sibyte/sb1250/
Dbcm1250_tbprof.c67 out64(0, KSEG1 + A_SCD_PERF_CNT_1); in arm_tb()
68 scdperfcnt = in64(KSEG1 + A_SCD_PERF_CNT_CFG); in arm_tb()
76 KSEG1 + A_SCD_PERF_CNT_CFG); in arm_tb()
77 out64(next, KSEG1 + A_SCD_PERF_CNT_1); in arm_tb()
79 out64(M_SCD_TRACE_CFG_RESET, KSEG1 + A_SCD_TRACE_CFG); in arm_tb()
85 , KSEG1 + A_SCD_TRACE_CFG); in arm_tb()
97 out64(M_SCD_TRACE_CFG_START_READ, KSEG1 + A_SCD_TRACE_CFG); in sbprof_tb_intr()
103 p[i-1] = in64(KSEG1 + A_SCD_TRACE_READ); // read t2 hi in sbprof_tb_intr()
104 p[i-2] = in64(KSEG1 + A_SCD_TRACE_READ); // read t2 lo in sbprof_tb_intr()
105 p[i-3] = in64(KSEG1 + A_SCD_TRACE_READ); // read t1 hi in sbprof_tb_intr()
[all …]
Dirq.c112 cur_ints = __in64(KSEG1 + A_IMR_MAPPER(cpu) + R_IMR_INTERRUPT_MASK); in sb1250_mask_irq()
114 __out64(cur_ints, KSEG1 + A_IMR_MAPPER(cpu) + R_IMR_INTERRUPT_MASK); in sb1250_mask_irq()
124 cur_ints = __in64(KSEG1 + A_IMR_MAPPER(cpu) + R_IMR_INTERRUPT_MASK); in sb1250_unmask_irq()
126 __out64(cur_ints, KSEG1 + A_IMR_MAPPER(cpu) + R_IMR_INTERRUPT_MASK); in sb1250_unmask_irq()
161 cur_ints = __in64(KSEG1 + A_IMR_MAPPER(old_cpu) + R_IMR_INTERRUPT_MASK); in sb1250_set_affinity()
166 __out64(cur_ints, KSEG1 + A_IMR_MAPPER(old_cpu) + R_IMR_INTERRUPT_MASK); in sb1250_set_affinity()
171 cur_ints = __in64(KSEG1 + A_IMR_MAPPER(cpu) + R_IMR_INTERRUPT_MASK); in sb1250_set_affinity()
173 __out64(cur_ints, KSEG1 + A_IMR_MAPPER(cpu) + R_IMR_INTERRUPT_MASK); in sb1250_set_affinity()
216 pending = in64(KSEG1 + A_IMR_REGISTER(sb1250_irq_owner[irq], in ack_sb1250_irq()
227 KSEG1+A_IMR_REGISTER(cpu_logical_map(i), in ack_sb1250_irq()
[all …]
Dtime.c70 out64(IMR_IP4_VAL, KSEG1 + A_IMR_REGISTER(cpu, R_IMR_INTERRUPT_MAP_BASE) in sb1250_time_init()
75 out64(0, KSEG1 + A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); in sb1250_time_init()
82 , KSEG1 + A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)); in sb1250_time_init()
86 KSEG1 + A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); in sb1250_time_init()
107 KSEG1 + A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); in sb1250_timer_interrupt()
131 in64(KSEG1 + A_SCD_TIMER_REGISTER(0, R_SCD_TIMER_CNT)); in sb1250_gettimeoffset()
Dsmp.c39 KSEG1 + A_IMR_CPU0_BASE + R_IMR_MAILBOX_SET_CPU,
40 KSEG1 + A_IMR_CPU1_BASE + R_IMR_MAILBOX_SET_CPU
44 KSEG1 + A_IMR_CPU0_BASE + R_IMR_MAILBOX_CLR_CPU,
45 KSEG1 + A_IMR_CPU1_BASE + R_IMR_MAILBOX_CLR_CPU
49 KSEG1 + A_IMR_CPU0_BASE + R_IMR_MAILBOX_CPU,
50 KSEG1 + A_IMR_CPU1_BASE + R_IMR_MAILBOX_CPU
Dsetup.c169 out64(0, KSEG1 + A_SCD_ZBBUS_CYCLE_COUNT); in sb1250_setup()
Dirq_handler.S128 PTR_LA v0, KSEG1 + A_IMR_CPU0_BASE
/linux-2.4.37.9/drivers/char/
Dite_gpio.c47 #define ITE_GPADR (*(volatile __u8 *)(0x14013800 + KSEG1))
48 #define ITE_GPBDR (*(volatile __u8 *)(0x14013808 + KSEG1))
49 #define ITE_GPCDR (*(volatile __u8 *)(0x14013810 + KSEG1))
50 #define ITE_GPACR (*(volatile __u16 *)(0x14013802 + KSEG1))
51 #define ITE_GPBCR (*(volatile __u16 *)(0x1401380a + KSEG1))
52 #define ITE_GPCCR (*(volatile __u16 *)(0x14013812 + KSEG1))
53 #define ITE_GPAICR (*(volatile __u16 *)(0x14013804 + KSEG1))
54 #define ITE_GPBICR (*(volatile __u16 *)(0x1401380c + KSEG1))
55 #define ITE_GPCICR (*(volatile __u16 *)(0x14013814 + KSEG1))
56 #define ITE_GPAISR (*(volatile __u8 *)(0x14013806 + KSEG1))
[all …]
/linux-2.4.37.9/arch/mips/baget/
Dbalo.c25 static volatile int *mem_limit = (volatile int*)KSEG1;
26 static volatile int *mem_limit_dbe = (volatile int*)KSEG1;
29 return p < (int*)(KSEG1+BALO_OFFSET) || in can_write()
30 p >= (int*)(KSEG1+BALO_OFFSET+BALO_SIZE); in can_write()
96 reset_and_jump(START, (int)mem_limit-KSEG1+KSEG0); in start_kernel()
Dbalo_supp.S57 or v0, KSEG1 # Run uncached.
66 li t0, KSEG1
68 li t1, KSEG1
93 or v0, KSEG1
102 li t0, KSEG1
/linux-2.4.37.9/include/asm-mips/jmr3927/
Djmr3927.h36 #define JMR3927_PORT_BASE KSEG1
49 #define JMR3927_ROM0_BASE (KSEG1 + JMR3927_ROMCE0)
50 #define JMR3927_ROM1_BASE (KSEG1 + JMR3927_ROMCE1)
51 #define JMR3927_IOC_BASE (KSEG1 + JMR3927_ROMCE2)
52 #define JMR3927_IOB_BASE (KSEG1 + JMR3927_ROMCE3)
58 #define JMR3927_JMY1394_BASE (KSEG1 + JMR3927_ROMCE5)
60 #define JMR3927_PCIMEM_BASE (KSEG1 + JMR3927_PCIMEM)
61 #define JMR3927_PCIIO_BASE (KSEG1 + JMR3927_PCIIO)
/linux-2.4.37.9/arch/mips/dec/prom/
Dmemory.c45 for (memory_page = (unsigned char *) KSEG1 + CHUNK_SIZE; in pmax_setup_memory_region()
46 (mem_err== 0) && (memory_page < ((unsigned char *) KSEG1+0x1E000000)); in pmax_setup_memory_region()
52 add_memory_region(0, (unsigned long)memory_page - KSEG1 - CHUNK_SIZE, in pmax_setup_memory_region()
/linux-2.4.37.9/arch/mips/mips-boards/generic/
Dinit.c136 set_io_port_base(KSEG1); in prom_init()
157 set_io_port_base(KSEG1); in prom_init()
187 set_io_port_base(KSEG1); in prom_init()
/linux-2.4.37.9/arch/mips/pmc-sierra/stretch/
Dsetup.h20 #define PMC_STRETCH_BASE (0x1A000000 + KSEG1) /* FIXME */
25 #define PMC_STRETCH_PCI_BASE (0x1A000000 + KSEG1) /* FIXME */
/linux-2.4.37.9/arch/mips/sibyte/swarm/
Ddbg_io.c40 #define duart_out(reg, val) csr_out32(val, KSEG1 + A_DUART_CHANREG(kgdb_port,reg))
41 #define duart_in(reg) csr_in32(KSEG1 + A_DUART_CHANREG(kgdb_port,reg))
/linux-2.4.37.9/drivers/i2c/
Di2c-sibyte.c56 { NULL, 0, (void *)(KSEG1+A_SMB_BASE(0)) },
57 { NULL, 1, (void *)(KSEG1+A_SMB_BASE(1)) }
/linux-2.4.37.9/include/asm-mips/
Daddrspace.h43 #define KSEG1 0xa0000000 macro
67 #define KSEG1ADDR(a) (CPHYSADDR(a) | KSEG1)
/linux-2.4.37.9/include/asm-mips64/
Daddrspace.h44 #define KSEG1 0xffffffffa0000000 macro
69 #define KSEG1ADDR(a) (CPHYSADDR(a) | KSEG1)
/linux-2.4.37.9/include/asm-mips/tx4927/
Dtx4927_pci.h25 #define TX4927_PCI_CLK_ADDR (KSEG1 + TX4927_CE3 + 0x00040020)
27 #define TX4927_IMSTAT_ADDR(n) (KSEG1 + TX4927_CE3 + 0x0004001a + (n))
/linux-2.4.37.9/include/asm-mips/sibyte/
Dsb1250.h61 #define IO_SPACE_BASE KSEG1
/linux-2.4.37.9/arch/mips/gt64120/ev64120/
Dsetup.c112 set_io_port_base(KSEG1); in ev64120_setup()
/linux-2.4.37.9/arch/mips/galileo-boards/ev96100/
Dsetup.c135 set_io_port_base(KSEG1); in ev96100_setup()
/linux-2.4.37.9/arch/mips/lasat/
Dprom.c124 set_io_port_base(KSEG1); in prom_init()
/linux-2.4.37.9/arch/mips/ddb5xxx/common/
Drtc_ds1386.c152 db_assert((rtc_base & 0xe0000000) == KSEG1); in rtc_ds1386_init()
/linux-2.4.37.9/arch/mips/lib/
Dr3k_dump_tlb.c160 paddr = (KSEG1 | (unsigned int) pte_val(*pte)) & PAGE_MASK; in vtop()

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