Searched refs:INREG (Results 1 – 3 of 3) sorted by relevance
191 if (INREG(LVDS) & PORT_ENABLE) in intelfbhw_check_non_crt()193 else if (INREG(DVOA) & PORT_ENABLE) in intelfbhw_check_non_crt()195 else if (INREG(DVOB) & PORT_ENABLE) in intelfbhw_check_non_crt()197 else if (INREG(DVOC) & PORT_ENABLE) in intelfbhw_check_non_crt()307 tmp = INREG(DSPACNTR); in intelfbhw_do_blank()314 tmp = INREG(DSPABASE); in intelfbhw_do_blank()332 tmp = INREG(ADPA) & ~ADPA_DPMS_CONTROL_MASK; in intelfbhw_do_blank()386 hw->vga0_divisor = INREG(VGA0_DIVISOR); in intelfbhw_read_hw_state()387 hw->vga1_divisor = INREG(VGA1_DIVISOR); in intelfbhw_read_hw_state()388 hw->vga_pd = INREG(VGAPD); in intelfbhw_read_hw_state()[all …]
473 #define INREG(addr) readl(dinfo->mmio_base + (addr)) macro507 head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK; \508 tail = INREG(PRI_RING_TAIL) & RING_TAIL_MASK; \
575 #define INREG(addr) readl((rinfo->mmio_base)+addr) macro594 unsigned int _tmp = INREG(addr); \604 return (INREG(CLOCK_CNTL_DATA)); in _INPLL()656 if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY)) in radeon_engine_flush()667 if ((INREG(RBBM_STATUS) & 0x7f) >= entries) in _radeon_fifo_wait()680 if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) { in _radeon_engine_idle()755 clock_cntl_index = INREG(CLOCK_CNTL_INDEX); in _radeon_engine_reset()766 host_path_cntl = INREG(HOST_PATH_CNTL); in _radeon_engine_reset()767 rbbm_soft_reset = INREG(RBBM_SOFT_RESET); in _radeon_engine_reset()776 INREG(RBBM_SOFT_RESET); in _radeon_engine_reset()[all …]