Lines Matching refs:INREG
575 #define INREG(addr) readl((rinfo->mmio_base)+addr) macro
594 unsigned int _tmp = INREG(addr); \
604 return (INREG(CLOCK_CNTL_DATA)); in _INPLL()
656 if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY)) in radeon_engine_flush()
667 if ((INREG(RBBM_STATUS) & 0x7f) >= entries) in _radeon_fifo_wait()
680 if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) { in _radeon_engine_idle()
755 clock_cntl_index = INREG(CLOCK_CNTL_INDEX); in _radeon_engine_reset()
766 host_path_cntl = INREG(HOST_PATH_CNTL); in _radeon_engine_reset()
767 rbbm_soft_reset = INREG(RBBM_SOFT_RESET); in _radeon_engine_reset()
776 INREG(RBBM_SOFT_RESET); in _radeon_engine_reset()
778 tmp = INREG(RB2D_DSTCACHE_MODE); in _radeon_engine_reset()
789 INREG(RBBM_SOFT_RESET); in _radeon_engine_reset()
798 INREG(RBBM_SOFT_RESET); in _radeon_engine_reset()
802 INREG(HOST_PATH_CNTL); in _radeon_engine_reset()
1189 u32 tmp = INREG(RADEON_BIOS_4_SCRATCH); in radeon_get_moninfo()
1230 tmp = INREG(FP_GEN_CNTL); in radeon_get_moninfo()
1285 save_crtc2_gen_cntl = INREG(CRTC2_GEN_CNTL); in radeon_fixup_apertures()
1288 save_crtc_gen_cntl = INREG(CRTC_GEN_CNTL); in radeon_fixup_apertures()
1289 save_crtc_ext_cntl = INREG(CRTC_EXT_CNTL); in radeon_fixup_apertures()
1295 aper_base = INREG(CONFIG_APER_0_BASE); in radeon_fixup_apertures()
1296 aper_size = INREG(CONFIG_APER_SIZE); in radeon_fixup_apertures()
1564 tmp = INREG(FP_VERT_STRETCH); in radeon_get_dfpinfo()
1596 tmp = INREG(FP_CRTC_H_TOTAL_DISP); in radeon_get_dfpinfo()
1601 tmp = INREG(FP_H_SYNC_STRT_WID); in radeon_get_dfpinfo()
1608 tmp = INREG(FP_CRTC_V_TOTAL_DISP); in radeon_get_dfpinfo()
1613 tmp = INREG(FP_V_SYNC_STRT_WID); in radeon_get_dfpinfo()
1714 tmp = INREG(CONFIG_MEMSIZE); in radeonfb_pci_register()
1720 tmp = INREG(MEM_SDRAM_MODE_REG); in radeonfb_pci_register()
1786 RTRACE("BIOS 4 scratch = %x\n", INREG(RADEON_BIOS_4_SCRATCH)); in radeonfb_pci_register()
1788 INREG(FP_GEN_CNTL), INREG(FP2_GEN_CNTL)); in radeonfb_pci_register()
1790 INREG(TMDS_TRANSMITTER_CNTL), INREG(TMDS_CNTL), INREG(LVDS_GEN_CNTL)); in radeonfb_pci_register()
1792 INREG(DAC_CNTL), INREG(DAC_CNTL2), INREG(CRTC_GEN_CNTL)); in radeonfb_pci_register()
1865 rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16; in radeonfb_pci_register()
1995 rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16; in radeon_engine_init()
2618 tmp = INREG(LVDS_GEN_CNTL); in radeonfb_ioctl()
2622 tmp = INREG(LVDS_GEN_CNTL); in radeonfb_ioctl()
2630 tmp = INREG(CRTC_EXT_CNTL); in radeonfb_ioctl()
2635 tmp = INREG(CRTC_EXT_CNTL); in radeonfb_ioctl()
2655 tmp = INREG(LVDS_GEN_CNTL); in radeonfb_ioctl()
2659 tmp = INREG(CRTC_EXT_CNTL); in radeonfb_ioctl()
2735 u32 val = INREG(CRTC_EXT_CNTL); in radeonfb_blank()
2736 u32 val_lvds = INREG(LVDS_GEN_CNTL); in radeonfb_blank()
2737 u32 val_dfp = INREG(FP_GEN_CNTL); in radeonfb_blank()
2850 dac_cntl2 = INREG(DAC_CNTL2); in radeon_setcolreg()
2916 save->crtc_gen_cntl = INREG(CRTC_GEN_CNTL); in radeon_save_state()
2917 save->crtc_ext_cntl = INREG(CRTC_EXT_CNTL); in radeon_save_state()
2918 save->crtc_more_cntl = INREG(CRTC_MORE_CNTL); in radeon_save_state()
2919 save->dac_cntl = INREG(DAC_CNTL); in radeon_save_state()
2920 save->crtc_h_total_disp = INREG(CRTC_H_TOTAL_DISP); in radeon_save_state()
2921 save->crtc_h_sync_strt_wid = INREG(CRTC_H_SYNC_STRT_WID); in radeon_save_state()
2922 save->crtc_v_total_disp = INREG(CRTC_V_TOTAL_DISP); in radeon_save_state()
2923 save->crtc_v_sync_strt_wid = INREG(CRTC_V_SYNC_STRT_WID); in radeon_save_state()
2924 save->crtc_pitch = INREG(CRTC_PITCH); in radeon_save_state()
2926 save->surface_cntl = INREG(SURFACE_CNTL); in radeon_save_state()
2930 save->fp_crtc_h_total_disp = INREG(FP_CRTC_H_TOTAL_DISP); in radeon_save_state()
2931 save->fp_crtc_v_total_disp = INREG(FP_CRTC_V_TOTAL_DISP); in radeon_save_state()
2932 save->fp_gen_cntl = INREG(FP_GEN_CNTL); in radeon_save_state()
2933 save->fp_h_sync_strt_wid = INREG(FP_H_SYNC_STRT_WID); in radeon_save_state()
2934 save->fp_horz_stretch = INREG(FP_HORZ_STRETCH); in radeon_save_state()
2935 save->fp_v_sync_strt_wid = INREG(FP_V_SYNC_STRT_WID); in radeon_save_state()
2936 save->fp_vert_stretch = INREG(FP_VERT_STRETCH); in radeon_save_state()
2937 save->lvds_gen_cntl = INREG(LVDS_GEN_CNTL); in radeon_save_state()
2938 save->lvds_pll_cntl = INREG(LVDS_PLL_CNTL); in radeon_save_state()
2939 save->tmds_crc = INREG(TMDS_CRC); in radeon_save_state()
2940 save->tmds_transmitter_cntl = INREG(TMDS_TRANSMITTER_CNTL); in radeon_save_state()
3340 while ((INREG(CLOCK_CNTL_INDEX) & PPLL_DIV_SEL_MASK) != in radeon_write_pll_regs()
3420 unsigned int tmp = INREG(LVDS_GEN_CNTL); in radeon_write_mode()
3474 unsigned int lvds_gen_cntl = INREG(LVDS_GEN_CNTL); in radeon_set_backlight_enable()
3493 (void)INREG(LVDS_GEN_CNTL); in radeon_set_backlight_enable()
3548 return INREG( MC_IND_DATA); in INMC()
3563 rinfo->save_regs[9] = INREG(DISP_MISC_CNTL); in radeon_pm_save_regs()
3564 rinfo->save_regs[10] = INREG(DISP_PWR_MAN); in radeon_pm_save_regs()
3565 rinfo->save_regs[11] = INREG(LVDS_GEN_CNTL); in radeon_pm_save_regs()
3566 rinfo->save_regs[12] = INREG(LVDS_PLL_CNTL); in radeon_pm_save_regs()
3567 rinfo->save_regs[13] = INREG(TV_DAC_CNTL); in radeon_pm_save_regs()
3568 rinfo->save_regs[14] = INREG(BUS_CNTL1); in radeon_pm_save_regs()
3569 rinfo->save_regs[15] = INREG(CRTC_OFFSET_CNTL); in radeon_pm_save_regs()
3570 rinfo->save_regs[16] = INREG(AGP_CNTL); in radeon_pm_save_regs()
3571 rinfo->save_regs[17] = (INREG(CRTC_GEN_CNTL) & 0xfdffffff) | 0x04000000; in radeon_pm_save_regs()
3572 rinfo->save_regs[18] = (INREG(CRTC2_GEN_CNTL) & 0xfdffffff) | 0x04000000; in radeon_pm_save_regs()
3573 rinfo->save_regs[19] = INREG(GPIOPAD_A); in radeon_pm_save_regs()
3574 rinfo->save_regs[20] = INREG(GPIOPAD_EN); in radeon_pm_save_regs()
3575 rinfo->save_regs[21] = INREG(GPIOPAD_MASK); in radeon_pm_save_regs()
3576 rinfo->save_regs[22] = INREG(ZV_LCDPAD_A); in radeon_pm_save_regs()
3577 rinfo->save_regs[23] = INREG(ZV_LCDPAD_EN); in radeon_pm_save_regs()
3578 rinfo->save_regs[24] = INREG(ZV_LCDPAD_MASK); in radeon_pm_save_regs()
3579 rinfo->save_regs[25] = INREG(GPIO_VGA_DDC); in radeon_pm_save_regs()
3580 rinfo->save_regs[26] = INREG(GPIO_DVI_DDC); in radeon_pm_save_regs()
3581 rinfo->save_regs[27] = INREG(GPIO_MONID); in radeon_pm_save_regs()
3582 rinfo->save_regs[28] = INREG(GPIO_CRT2_DDC); in radeon_pm_save_regs()
3584 rinfo->save_regs[29] = INREG(SURFACE_CNTL); in radeon_pm_save_regs()
3585 rinfo->save_regs[30] = INREG(MC_FB_LOCATION); in radeon_pm_save_regs()
3586 rinfo->save_regs[31] = INREG(DISPLAY_BASE_ADDR); in radeon_pm_save_regs()
3587 rinfo->save_regs[32] = INREG(MC_AGP_LOCATION); in radeon_pm_save_regs()
3588 rinfo->save_regs[33] = INREG(CRTC2_DISPLAY_BASE_ADDR); in radeon_pm_save_regs()
3676 reg = INREG(BUS_CNTL1); in radeon_pm_low_current()
3688 reg = INREG(TV_DAC_CNTL); in radeon_pm_low_current()
3695 reg = INREG(TMDS_TRANSMITTER_CNTL); in radeon_pm_low_current()
3699 reg = INREG(DAC_CNTL); in radeon_pm_low_current()
3703 reg = INREG(DAC_CNTL2); in radeon_pm_low_current()
3707 reg = INREG(TV_DAC_CNTL); in radeon_pm_low_current()
3832 OUTREG(BUS_CNTL1, INREG(BUS_CNTL1) | BUS_CNTL1__AGPCLK_VALID); in radeon_pm_setup_for_suspend()
3835 (INREG(BUS_CNTL1) & ~BUS_CNTL1__MOBILE_PLATFORM_SEL_MASK) in radeon_pm_setup_for_suspend()
3837 OUTREG(CRTC_OFFSET_CNTL, (INREG(CRTC_OFFSET_CNTL) & ~CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN)); in radeon_pm_setup_for_suspend()
3845 (INREG(AGP_CNTL) & ~(AGP_CNTL__MAX_IDLE_CLK_MASK)) in radeon_pm_setup_for_suspend()
3852 disp_mis_cntl = INREG(DISP_MISC_CNTL); in radeon_pm_setup_for_suspend()
3869 disp_pwr_man = INREG(DISP_PWR_MAN); in radeon_pm_setup_for_suspend()
3894 disp_pwr_man = INREG(DISP_PWR_MAN); in radeon_pm_setup_for_suspend()
3910 …OUTREG( CRTC_GEN_CNTL, (INREG( CRTC_GEN_CNTL) & ~CRTC_GEN_CNTL__CRTC_EN) | CRTC_GEN_CNTL__CRTC_DIS… in radeon_pm_setup_for_suspend()
3911 …OUTREG( CRTC2_GEN_CNTL, (INREG( CRTC2_GEN_CNTL) & ~CRTC2_GEN_CNTL__CRTC2_EN) | CRTC2_GEN_CNTL__CRT… in radeon_pm_setup_for_suspend()
4107 mem_sdram_mode = INREG( MEM_SDRAM_MODE_REG); in radeon_pm_program_mode_reg()
4120 while( (INREG( MC_STATUS) & (MC_STATUS__MEM_PWRUP_COMPL_A | MC_STATUS__MEM_PWRUP_COMPL_B) ) == 0 ) in radeon_pm_program_mode_reg()
4208 crtcGenCntl = INREG( CRTC_GEN_CNTL); in radeon_pm_full_reset_sdram()
4209 crtcGenCntl2 = INREG( CRTC2_GEN_CNTL); in radeon_pm_full_reset_sdram()
4211 memRefreshCntl = INREG( MEM_REFRESH_CNTL); in radeon_pm_full_reset_sdram()
4212 crtc_more_cntl = INREG( CRTC_MORE_CNTL); in radeon_pm_full_reset_sdram()
4213 fp_gen_cntl = INREG( FP_GEN_CNTL); in radeon_pm_full_reset_sdram()
4214 fp2_gen_cntl = INREG( FP2_GEN_CNTL); in radeon_pm_full_reset_sdram()
4229 INREG( MEM_SDRAM_MODE_REG) & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE); // Init Not Complete in radeon_pm_full_reset_sdram()
4246 INREG( MEM_SDRAM_MODE_REG) | MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE); // Init Complete in radeon_pm_full_reset_sdram()
4436 dp_cntl_save = INREG(DP_CNTL); in fbcon_radeon_bmove()