191 	if (INREG(LVDS) & PORT_ENABLE)  in intelfbhw_check_non_crt()
193 	else if (INREG(DVOA) & PORT_ENABLE)  in intelfbhw_check_non_crt()
195 	else if (INREG(DVOB) & PORT_ENABLE)  in intelfbhw_check_non_crt()
197 	else if (INREG(DVOC) & PORT_ENABLE)  in intelfbhw_check_non_crt()
307 	tmp = INREG(DSPACNTR);  in intelfbhw_do_blank()
314 	tmp = INREG(DSPABASE);  in intelfbhw_do_blank()
332 	tmp = INREG(ADPA) & ~ADPA_DPMS_CONTROL_MASK;  in intelfbhw_do_blank()
386 	hw->vga0_divisor = INREG(VGA0_DIVISOR);  in intelfbhw_read_hw_state()
387 	hw->vga1_divisor = INREG(VGA1_DIVISOR);  in intelfbhw_read_hw_state()
388 	hw->vga_pd = INREG(VGAPD);  in intelfbhw_read_hw_state()
389 	hw->dpll_a = INREG(DPLL_A);  in intelfbhw_read_hw_state()
390 	hw->dpll_b = INREG(DPLL_B);  in intelfbhw_read_hw_state()
391 	hw->fpa0 = INREG(FPA0);  in intelfbhw_read_hw_state()
392 	hw->fpa1 = INREG(FPA1);  in intelfbhw_read_hw_state()
393 	hw->fpb0 = INREG(FPB0);  in intelfbhw_read_hw_state()
394 	hw->fpb1 = INREG(FPB1);  in intelfbhw_read_hw_state()
402 		hw->palette_a[i] = INREG(PALETTE_A + (i << 2));  in intelfbhw_read_hw_state()
403 		hw->palette_b[i] = INREG(PALETTE_B + (i << 2));  in intelfbhw_read_hw_state()
410 	hw->htotal_a = INREG(HTOTAL_A);  in intelfbhw_read_hw_state()
411 	hw->hblank_a = INREG(HBLANK_A);  in intelfbhw_read_hw_state()
412 	hw->hsync_a = INREG(HSYNC_A);  in intelfbhw_read_hw_state()
413 	hw->vtotal_a = INREG(VTOTAL_A);  in intelfbhw_read_hw_state()
414 	hw->vblank_a = INREG(VBLANK_A);  in intelfbhw_read_hw_state()
415 	hw->vsync_a = INREG(VSYNC_A);  in intelfbhw_read_hw_state()
416 	hw->src_size_a = INREG(SRC_SIZE_A);  in intelfbhw_read_hw_state()
417 	hw->bclrpat_a = INREG(BCLRPAT_A);  in intelfbhw_read_hw_state()
418 	hw->htotal_b = INREG(HTOTAL_B);  in intelfbhw_read_hw_state()
419 	hw->hblank_b = INREG(HBLANK_B);  in intelfbhw_read_hw_state()
420 	hw->hsync_b = INREG(HSYNC_B);  in intelfbhw_read_hw_state()
421 	hw->vtotal_b = INREG(VTOTAL_B);  in intelfbhw_read_hw_state()
422 	hw->vblank_b = INREG(VBLANK_B);  in intelfbhw_read_hw_state()
423 	hw->vsync_b = INREG(VSYNC_B);  in intelfbhw_read_hw_state()
424 	hw->src_size_b = INREG(SRC_SIZE_B);  in intelfbhw_read_hw_state()
425 	hw->bclrpat_b = INREG(BCLRPAT_B);  in intelfbhw_read_hw_state()
430 	hw->adpa = INREG(ADPA);  in intelfbhw_read_hw_state()
431 	hw->dvoa = INREG(DVOA);  in intelfbhw_read_hw_state()
432 	hw->dvob = INREG(DVOB);  in intelfbhw_read_hw_state()
433 	hw->dvoc = INREG(DVOC);  in intelfbhw_read_hw_state()
434 	hw->dvoa_srcdim = INREG(DVOA_SRCDIM);  in intelfbhw_read_hw_state()
435 	hw->dvob_srcdim = INREG(DVOB_SRCDIM);  in intelfbhw_read_hw_state()
436 	hw->dvoc_srcdim = INREG(DVOC_SRCDIM);  in intelfbhw_read_hw_state()
437 	hw->lvds = INREG(LVDS);  in intelfbhw_read_hw_state()
442 	hw->pipe_a_conf = INREG(PIPEACONF);  in intelfbhw_read_hw_state()
443 	hw->pipe_b_conf = INREG(PIPEBCONF);  in intelfbhw_read_hw_state()
444 	hw->disp_arb = INREG(DISPARB);  in intelfbhw_read_hw_state()
449 	hw->cursor_a_control = INREG(CURSOR_A_CONTROL);  in intelfbhw_read_hw_state()
450 	hw->cursor_b_control = INREG(CURSOR_B_CONTROL);  in intelfbhw_read_hw_state()
451 	hw->cursor_a_base = INREG(CURSOR_A_BASEADDR);  in intelfbhw_read_hw_state()
452 	hw->cursor_b_base = INREG(CURSOR_B_BASEADDR);  in intelfbhw_read_hw_state()
458 		hw->cursor_a_palette[i] = INREG(CURSOR_A_PALETTE0 + (i << 2));  in intelfbhw_read_hw_state()
459 		hw->cursor_b_palette[i] = INREG(CURSOR_B_PALETTE0 + (i << 2));  in intelfbhw_read_hw_state()
465 	hw->cursor_size = INREG(CURSOR_SIZE);  in intelfbhw_read_hw_state()
470 	hw->disp_a_ctrl = INREG(DSPACNTR);  in intelfbhw_read_hw_state()
471 	hw->disp_b_ctrl = INREG(DSPBCNTR);  in intelfbhw_read_hw_state()
472 	hw->disp_a_base = INREG(DSPABASE);  in intelfbhw_read_hw_state()
473 	hw->disp_b_base = INREG(DSPBBASE);  in intelfbhw_read_hw_state()
474 	hw->disp_a_stride = INREG(DSPASTRIDE);  in intelfbhw_read_hw_state()
475 	hw->disp_b_stride = INREG(DSPBSTRIDE);  in intelfbhw_read_hw_state()
480 	hw->vgacntrl = INREG(VGACNTRL);  in intelfbhw_read_hw_state()
485 	hw->add_id = INREG(ADD_ID);  in intelfbhw_read_hw_state()
491 		hw->swf0x[i] = INREG(SWF00 + (i << 2));  in intelfbhw_read_hw_state()
492 		hw->swf1x[i] = INREG(SWF10 + (i << 2));  in intelfbhw_read_hw_state()
494 			hw->swf3x[i] = INREG(SWF30 + (i << 2));  in intelfbhw_read_hw_state()
498 		hw->fence[i] = INREG(FENCE + (i << 2));  in intelfbhw_read_hw_state()
500 	hw->instpm = INREG(INSTPM);  in intelfbhw_read_hw_state()
501 	hw->mem_mode = INREG(MEM_MODE);  in intelfbhw_read_hw_state()
502 	hw->fw_blc_0 = INREG(FW_BLC_0);  in intelfbhw_read_hw_state()
503 	hw->fw_blc_1 = INREG(FW_BLC_1);  in intelfbhw_read_hw_state()
1076 	tmp = INREG(VGACNTRL);  in intelfbhw_program_mode()
1137 	tmp = INREG(DSPACNTR);  in intelfbhw_program_mode()
1140 	tmp = INREG(DSPBCNTR);  in intelfbhw_program_mode()
1148 	tmp = INREG(ADPA);  in intelfbhw_program_mode()
1154 	tmp = INREG(pipe_conf_reg);  in intelfbhw_program_mode()
1159 	tmp = INREG(dpll_reg);  in intelfbhw_program_mode()
1181 	tmp = INREG(dpll_reg);  in intelfbhw_program_mode()
1189 	tmp = INREG(ADPA);  in intelfbhw_program_mode()
1201 		tmp = INREG(DSPACNTR);  in intelfbhw_program_mode()
1215 	u32 last_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;  in wait_ring()
1223 		dinfo->ring_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;  in wait_ring()
1308 	dinfo->ring_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;  in refresh_ring()
1309 	dinfo->ring_tail = INREG(PRI_RING_TAIL) & RING_TAIL_MASK;  in refresh_ring()
1328 	tmp = INREG(PRI_RING_LENGTH);  in reset_state()
1382 	DBG_MSG("INSTPM was 0x%08x, setting to 0x%08x\n", INREG(INSTPM),  in intelfbhw_2d_start()
1619 		tmp = INREG(CURSOR_A_CONTROL);  in intelfbhw_cursor_init()
1628 		tmp = INREG(CURSOR_CONTROL);  in intelfbhw_cursor_init()
1658 		tmp = INREG(CURSOR_A_CONTROL);  in intelfbhw_cursor_hide()
1665 		tmp = INREG(CURSOR_CONTROL);  in intelfbhw_cursor_hide()
1692 		tmp = INREG(CURSOR_A_CONTROL);  in intelfbhw_cursor_show()
1699 		tmp = INREG(CURSOR_CONTROL);  in intelfbhw_cursor_show()