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Searched refs:BIT_0 (Results 1 – 8 of 8) sorted by relevance

/linux-2.4.37.9/drivers/net/e100/
De100_config.h49 #define CB_CFIG_MWI_EN BIT_0 /* Enable MWI on PCI bus */
63 #define CB_CFIG_LATE_SCB BIT_0 /* Update SCB After New Tx Start */
73 #define CB_CFIG_DISC_SHORT_FRAMES BIT_0 /* Discard Short Frames */
79 #define CB_CFIG_503_MII BIT_0 /* 503 vs. MII mode */
96 #define CB_CFIG_LINEAR_PRI_MODE BIT_0 /* Linear Priority mode */
104 #define CB_CFIG_PROMISCUOUS BIT_0 /* Promiscuous Mode Enable */
117 #define CB_CFIG_STRIPPING BIT_0 /* Padding Disabled */
122 #define CB_CFIG_TX_ADDR_WAKE BIT_0 /* Address Wakeup */
143 #define CB_CFIG_RECEIVE_GAMLA_MODE BIT_0 /* D102 receive mode */
De100.h174 #define BIT_0 0x0001 macro
288 #define SCB_RUC_START BIT_0 /* RU Start */
291 #define SCB_RUC_LOAD_HDS (BIT_0 | BIT_2) /* Load RFD Header Data Size */
296 #define SCB_INT_MASK BIT_0 /* Mask interrupts */
386 #define RFD_RECEIVE_COLLISION BIT_0 /* Collision detected on Receive */
447 #define PHY_82555_LED_ON_559 (BIT_0 | BIT_2) // activity LED is on for 559 and later
448 #define PHY_82555_LED_ON_PRE_559 (BIT_0 | BIT_1 | BIT_2) // activity LED is on for 558 and be…
718 #define IPCB_HARDWAREPARSING_ENABLE BIT_0
De100_config.c337 if (bdp->config[7] & (u8) BIT_0) { in e100_config_promisc()
338 bdp->config[7] &= (u8) (~BIT_0); in e100_config_promisc()
354 if (!(bdp->config[7] & (u8) BIT_0)) { in e100_config_promisc()
355 bdp->config[7] |= (u8) (BIT_0); in e100_config_promisc()
De100_phy.h136 #define PHY_100_ER0_FDX_INDIC BIT_0 /* 1 = FDX, 0 = half duplex */
De100_phy.c962 if (readb(&bdp->scb->scb_ext.d101m_scb.scb_gen_stat) & BIT_0) { in e100_get_link_state()
/linux-2.4.37.9/drivers/net/sk98lin/h/
Dskgehw.h63 #define BIT_0 1L macro
235 #define PCI_MEMSPACE BIT_0 /* Memory Space Indicator */
241 #define PCI_IOSPACE BIT_0 /* I/O Space Indicator */
248 #define PCI_ROMEN BIT_0 /* Address Decode enable */
299 #define PCI_USEDATA64 BIT_0 /* Use 64Bit Data bus ext */
833 #define PC_VCC_OFF BIT_0 /* Switch VCC Off */
878 #define IS_XA2_C BIT_0 /* Q_XA2 Encoding Error */
899 #define IS_R2_PAR_ERR BIT_0 /* Queue R2 Parity Error */
1004 #define GP_IO_0 BIT_0 /* IO_0 pin */
1021 #define I2C_STOP BIT_0 /* Interrupt I2C transfer */
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/linux-2.4.37.9/drivers/scsi/
Dqla1280.c1669 mr = BIT_3 | BIT_2 | BIT_1 | BIT_0; in qla12160_set_target_parameters()
1730 (ha->bus_settings[bus].qtag_enables & (BIT_0 << target))) { in qla1280_slave_configure()
2260 qla1280_mailbox_command(ha, BIT_1 | BIT_0, &mb[0]))) { in qla1280_isp_firmware()
2268 qla1280_mailbox_command(ha, BIT_1 | BIT_0, &mb[0]); in qla1280_isp_firmware()
2557 BIT_2 | BIT_1 | BIT_0, in qla1280_setup_chip()
2575 BIT_1 | BIT_0, in qla1280_setup_chip()
2608 qla1280_mailbox_command(ha, BIT_1 | BIT_0, &mb[0]))) { in qla1280_setup_chip()
2614 qla1280_mailbox_command(ha, BIT_1 | BIT_0, &mb[0]); in qla1280_setup_chip()
2670 BIT_3 | BIT_2 | BIT_1 | BIT_0, in qla1280_init_rings()
2684 BIT_3 | BIT_2 | BIT_1 | BIT_0, in qla1280_init_rings()
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Dqla1280.h28 #define BIT_0 0x1 macro
122 #define SRB_TIMEOUT BIT_0 /* Command timed out */
146 #define QLA1280_QBUSY BIT_0
164 #define ISP_RESET BIT_0 /* ISP soft reset */
176 #define NV_CLOCK BIT_0
198 #define BIOS_ENABLE BIT_0
566 #define RF_CONT BIT_0 /* Continuation. */