Lines Matching refs:BIT_0
63 #define BIT_0 1L macro
235 #define PCI_MEMSPACE BIT_0 /* Memory Space Indicator */
241 #define PCI_IOSPACE BIT_0 /* I/O Space Indicator */
248 #define PCI_ROMEN BIT_0 /* Address Decode enable */
299 #define PCI_USEDATA64 BIT_0 /* Use 64Bit Data bus ext */
833 #define PC_VCC_OFF BIT_0 /* Switch VCC Off */
878 #define IS_XA2_C BIT_0 /* Q_XA2 Encoding Error */
899 #define IS_R2_PAR_ERR BIT_0 /* Queue R2 Parity Error */
1004 #define GP_IO_0 BIT_0 /* IO_0 pin */
1021 #define I2C_STOP BIT_0 /* Interrupt I2C transfer */
1025 #define I2C_CLR_IRQ BIT_0 /* Clear I2C IRQ */
1204 #define CSR_IRQ_CL_C BIT_0 /* Clear ERR IRQ */
1253 #define T2_STEP01 BIT_0 /* Inc AC/Dec BC by 1 */
1449 #define GMF_RST_SET BIT_0 /* Set GMAC FIFO Reset */
1482 #define GMC_RST_SET BIT_0 /* Set GMAC Reset */
1509 #define GPC_RST_SET BIT_0 /* Set GPHY Reset */
1546 #define GM_IS_RX_COMPL BIT_0 /* Frame Reception Complete */
1587 #define WOL_CTL_PATT_ENA(x) (BIT_0 << (x))