1669 	mr = BIT_3 | BIT_2 | BIT_1 | BIT_0;  in qla12160_set_target_parameters()
1730 	    (ha->bus_settings[bus].qtag_enables & (BIT_0 << target))) {  in qla1280_slave_configure()
2260 		      qla1280_mailbox_command(ha, BIT_1 | BIT_0, &mb[0]))) {  in qla1280_isp_firmware()
2268 			qla1280_mailbox_command(ha, BIT_1 | BIT_0, &mb[0]);  in qla1280_isp_firmware()
2557 						      BIT_2 | BIT_1 | BIT_0,  in qla1280_setup_chip()
2575 						      BIT_1 | BIT_0,  in qla1280_setup_chip()
2608 		      qla1280_mailbox_command(ha, BIT_1 | BIT_0, &mb[0]))) {  in qla1280_setup_chip()
2614 			qla1280_mailbox_command(ha, BIT_1 | BIT_0, &mb[0]);  in qla1280_setup_chip()
2670 					       BIT_3 | BIT_2 | BIT_1 | BIT_0,  in qla1280_init_rings()
2684 						 BIT_3 | BIT_2 | BIT_1 | BIT_0,  in qla1280_init_rings()
2888 	WRT_REG_WORD(&reg->gpio_enable, (BIT_3 + BIT_2 + BIT_1 + BIT_0));  in qla1280_nvram_config()
2889 	mb[0] = nv->termination.c & (BIT_3 + BIT_2 + BIT_1 + BIT_0);  in qla1280_nvram_config()
2896 	status |= qla1280_mailbox_command(ha, BIT_1 | BIT_0, &mb[0]);  in qla1280_nvram_config()
2902  	status |= qla1280_mailbox_command(ha, BIT_1 | BIT_0, &mb[0]);  in qla1280_nvram_config()
2906 	mask = BIT_5 | BIT_1 | BIT_0;  in qla1280_nvram_config()
2924 					  BIT_1 | BIT_0, &mb[0]);  in qla1280_nvram_config()
2930 	status |= qla1280_mailbox_command(ha, BIT_2 | BIT_1 | BIT_0, &mb[0]);  in qla1280_nvram_config()
2944 	status |= qla1280_mailbox_command(ha, BIT_2 | BIT_1 | BIT_0, &mb[0]);  in qla1280_nvram_config()
2948 	status |= qla1280_mailbox_command(ha, BIT_1 | BIT_0, &mb[0]);  in qla1280_nvram_config()
2954 	status |= qla1280_mailbox_command(ha, BIT_2 | BIT_1 | BIT_0, &mb[0]);  in qla1280_nvram_config()
2960 	status |= qla1280_mailbox_command(ha, BIT_2 | BIT_1 | BIT_0, &mb[0]);  in qla1280_nvram_config()
2972 		status |= qla1280_mailbox_command(ha, BIT_1 | BIT_0, &mb[0]);  in qla1280_nvram_config()
2983 			uint8_t mr = BIT_2 | BIT_1 | BIT_0;  in qla1280_nvram_config()
3032 			mb[0] = BIT_0 << target;  in qla1280_nvram_config()
3141 			data |= BIT_0;  in qla1280_nvram_request()
3219 		if (mr & BIT_0) {  in qla1280_mailbox_command()
3352 	status = qla1280_mailbox_command(ha, BIT_2 | BIT_1 | BIT_0, &mb[0]);  in qla1280_bus_reset()
3406 	status = qla1280_mailbox_command(ha, BIT_2 | BIT_1 | BIT_0, &mb[0]);  in qla1280_device_reset()
3441 	status = qla1280_mailbox_command(ha, BIT_1 | BIT_0, &mb[0]);  in qla1280_abort_device()
4283 	if (mailbox[0] & BIT_0) {  in qla1280_isr()
4351 			index = mailbox[6] & BIT_0;  in qla1280_isr()
4389 			index = mailbox[6] & BIT_0;  in qla1280_isr()
4903 	qla1280_mailbox_command(ha, BIT_6 | BIT_3 | BIT_2 | BIT_1 | BIT_0,  in qla12160_get_target_parameters()