1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * tegra30_i2s.c - Tegra30 I2S driver
4  *
5  * Author: Stephen Warren <swarren@nvidia.com>
6  * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
7  *
8  * Based on code copyright/by:
9  *
10  * Copyright (c) 2009-2010, NVIDIA Corporation.
11  * Scott Peterson <speterson@nvidia.com>
12  *
13  * Copyright (C) 2010 Google, Inc.
14  * Iliyan Malchev <malchev@google.com>
15  */
16 
17 #include <linux/clk.h>
18 #include <linux/device.h>
19 #include <linux/io.h>
20 #include <linux/module.h>
21 #include <linux/of.h>
22 #include <linux/of_device.h>
23 #include <linux/platform_device.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/regmap.h>
26 #include <linux/reset.h>
27 #include <linux/slab.h>
28 #include <sound/core.h>
29 #include <sound/pcm.h>
30 #include <sound/pcm_params.h>
31 #include <sound/soc.h>
32 #include <sound/dmaengine_pcm.h>
33 
34 #include "tegra30_ahub.h"
35 #include "tegra30_i2s.h"
36 
37 #define DRV_NAME "tegra30-i2s"
38 
tegra30_i2s_runtime_suspend(struct device * dev)39 static __maybe_unused int tegra30_i2s_runtime_suspend(struct device *dev)
40 {
41 	struct tegra30_i2s *i2s = dev_get_drvdata(dev);
42 
43 	regcache_cache_only(i2s->regmap, true);
44 
45 	clk_disable_unprepare(i2s->clk_i2s);
46 
47 	return 0;
48 }
49 
tegra30_i2s_runtime_resume(struct device * dev)50 static __maybe_unused int tegra30_i2s_runtime_resume(struct device *dev)
51 {
52 	struct tegra30_i2s *i2s = dev_get_drvdata(dev);
53 	int ret;
54 
55 	ret = clk_prepare_enable(i2s->clk_i2s);
56 	if (ret) {
57 		dev_err(dev, "clk_enable failed: %d\n", ret);
58 		return ret;
59 	}
60 
61 	regcache_cache_only(i2s->regmap, false);
62 	regcache_mark_dirty(i2s->regmap);
63 
64 	ret = regcache_sync(i2s->regmap);
65 	if (ret)
66 		goto disable_clocks;
67 
68 	return 0;
69 
70 disable_clocks:
71 	clk_disable_unprepare(i2s->clk_i2s);
72 
73 	return ret;
74 }
75 
tegra30_i2s_set_fmt(struct snd_soc_dai * dai,unsigned int fmt)76 static int tegra30_i2s_set_fmt(struct snd_soc_dai *dai,
77 				unsigned int fmt)
78 {
79 	struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
80 	unsigned int mask = 0, val = 0;
81 
82 	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
83 	case SND_SOC_DAIFMT_NB_NF:
84 		break;
85 	default:
86 		return -EINVAL;
87 	}
88 
89 	mask |= TEGRA30_I2S_CTRL_MASTER_ENABLE;
90 	switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
91 	case SND_SOC_DAIFMT_BP_FP:
92 		val |= TEGRA30_I2S_CTRL_MASTER_ENABLE;
93 		break;
94 	case SND_SOC_DAIFMT_BC_FC:
95 		break;
96 	default:
97 		return -EINVAL;
98 	}
99 
100 	mask |= TEGRA30_I2S_CTRL_FRAME_FORMAT_MASK |
101 		TEGRA30_I2S_CTRL_LRCK_MASK;
102 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
103 	case SND_SOC_DAIFMT_DSP_A:
104 		val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC;
105 		val |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
106 		break;
107 	case SND_SOC_DAIFMT_DSP_B:
108 		val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC;
109 		val |= TEGRA30_I2S_CTRL_LRCK_R_LOW;
110 		break;
111 	case SND_SOC_DAIFMT_I2S:
112 		val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
113 		val |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
114 		break;
115 	case SND_SOC_DAIFMT_RIGHT_J:
116 		val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
117 		val |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
118 		break;
119 	case SND_SOC_DAIFMT_LEFT_J:
120 		val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
121 		val |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
122 		break;
123 	default:
124 		return -EINVAL;
125 	}
126 
127 	pm_runtime_get_sync(dai->dev);
128 	regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL, mask, val);
129 	pm_runtime_put(dai->dev);
130 
131 	return 0;
132 }
133 
tegra30_i2s_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)134 static int tegra30_i2s_hw_params(struct snd_pcm_substream *substream,
135 				 struct snd_pcm_hw_params *params,
136 				 struct snd_soc_dai *dai)
137 {
138 	struct device *dev = dai->dev;
139 	struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
140 	unsigned int mask, val, reg;
141 	int ret, sample_size, srate, i2sclock, bitcnt;
142 	struct tegra30_ahub_cif_conf cif_conf;
143 
144 	if (params_channels(params) != 2)
145 		return -EINVAL;
146 
147 	mask = TEGRA30_I2S_CTRL_BIT_SIZE_MASK;
148 	switch (params_format(params)) {
149 	case SNDRV_PCM_FORMAT_S16_LE:
150 		val = TEGRA30_I2S_CTRL_BIT_SIZE_16;
151 		sample_size = 16;
152 		break;
153 	default:
154 		return -EINVAL;
155 	}
156 
157 	regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL, mask, val);
158 
159 	srate = params_rate(params);
160 
161 	/* Final "* 2" required by Tegra hardware */
162 	i2sclock = srate * params_channels(params) * sample_size * 2;
163 
164 	bitcnt = (i2sclock / (2 * srate)) - 1;
165 	if (bitcnt < 0 || bitcnt > TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US)
166 		return -EINVAL;
167 
168 	ret = clk_set_rate(i2s->clk_i2s, i2sclock);
169 	if (ret) {
170 		dev_err(dev, "Can't set I2S clock rate: %d\n", ret);
171 		return ret;
172 	}
173 
174 	val = bitcnt << TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT;
175 
176 	if (i2sclock % (2 * srate))
177 		val |= TEGRA30_I2S_TIMING_NON_SYM_ENABLE;
178 
179 	regmap_write(i2s->regmap, TEGRA30_I2S_TIMING, val);
180 
181 	cif_conf.threshold = 0;
182 	cif_conf.audio_channels = 2;
183 	cif_conf.client_channels = 2;
184 	cif_conf.audio_bits = TEGRA30_AUDIOCIF_BITS_16;
185 	cif_conf.client_bits = TEGRA30_AUDIOCIF_BITS_16;
186 	cif_conf.expand = 0;
187 	cif_conf.stereo_conv = 0;
188 	cif_conf.replicate = 0;
189 	cif_conf.truncate = 0;
190 	cif_conf.mono_conv = 0;
191 
192 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
193 		cif_conf.direction = TEGRA30_AUDIOCIF_DIRECTION_RX;
194 		reg = TEGRA30_I2S_CIF_RX_CTRL;
195 	} else {
196 		cif_conf.direction = TEGRA30_AUDIOCIF_DIRECTION_TX;
197 		reg = TEGRA30_I2S_CIF_TX_CTRL;
198 	}
199 
200 	i2s->soc_data->set_audio_cif(i2s->regmap, reg, &cif_conf);
201 
202 	val = (1 << TEGRA30_I2S_OFFSET_RX_DATA_OFFSET_SHIFT) |
203 	      (1 << TEGRA30_I2S_OFFSET_TX_DATA_OFFSET_SHIFT);
204 	regmap_write(i2s->regmap, TEGRA30_I2S_OFFSET, val);
205 
206 	return 0;
207 }
208 
tegra30_i2s_start_playback(struct tegra30_i2s * i2s)209 static void tegra30_i2s_start_playback(struct tegra30_i2s *i2s)
210 {
211 	tegra30_ahub_enable_tx_fifo(i2s->playback_fifo_cif);
212 	regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL,
213 			   TEGRA30_I2S_CTRL_XFER_EN_TX,
214 			   TEGRA30_I2S_CTRL_XFER_EN_TX);
215 }
216 
tegra30_i2s_stop_playback(struct tegra30_i2s * i2s)217 static void tegra30_i2s_stop_playback(struct tegra30_i2s *i2s)
218 {
219 	tegra30_ahub_disable_tx_fifo(i2s->playback_fifo_cif);
220 	regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL,
221 			   TEGRA30_I2S_CTRL_XFER_EN_TX, 0);
222 }
223 
tegra30_i2s_start_capture(struct tegra30_i2s * i2s)224 static void tegra30_i2s_start_capture(struct tegra30_i2s *i2s)
225 {
226 	tegra30_ahub_enable_rx_fifo(i2s->capture_fifo_cif);
227 	regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL,
228 			   TEGRA30_I2S_CTRL_XFER_EN_RX,
229 			   TEGRA30_I2S_CTRL_XFER_EN_RX);
230 }
231 
tegra30_i2s_stop_capture(struct tegra30_i2s * i2s)232 static void tegra30_i2s_stop_capture(struct tegra30_i2s *i2s)
233 {
234 	regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL,
235 			   TEGRA30_I2S_CTRL_XFER_EN_RX, 0);
236 	tegra30_ahub_disable_rx_fifo(i2s->capture_fifo_cif);
237 }
238 
tegra30_i2s_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)239 static int tegra30_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
240 				struct snd_soc_dai *dai)
241 {
242 	struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
243 
244 	switch (cmd) {
245 	case SNDRV_PCM_TRIGGER_START:
246 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
247 	case SNDRV_PCM_TRIGGER_RESUME:
248 		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
249 			tegra30_i2s_start_playback(i2s);
250 		else
251 			tegra30_i2s_start_capture(i2s);
252 		break;
253 	case SNDRV_PCM_TRIGGER_STOP:
254 	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
255 	case SNDRV_PCM_TRIGGER_SUSPEND:
256 		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
257 			tegra30_i2s_stop_playback(i2s);
258 		else
259 			tegra30_i2s_stop_capture(i2s);
260 		break;
261 	default:
262 		return -EINVAL;
263 	}
264 
265 	return 0;
266 }
267 
tegra30_i2s_set_tdm(struct snd_soc_dai * dai,unsigned int tx_mask,unsigned int rx_mask,int slots,int slot_width)268 static int tegra30_i2s_set_tdm(struct snd_soc_dai *dai,
269 			       unsigned int tx_mask, unsigned int rx_mask,
270 			       int slots, int slot_width)
271 {
272 	struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
273 	unsigned int mask, val;
274 
275 	dev_dbg(dai->dev, "%s: txmask=0x%08x rxmask=0x%08x slots=%d width=%d\n",
276 		 __func__, tx_mask, rx_mask, slots, slot_width);
277 
278 	mask = TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_MASK |
279 	       TEGRA30_I2S_SLOT_CTRL_RX_SLOT_ENABLES_MASK |
280 	       TEGRA30_I2S_SLOT_CTRL_TX_SLOT_ENABLES_MASK;
281 
282 	val = (tx_mask << TEGRA30_I2S_SLOT_CTRL_TX_SLOT_ENABLES_SHIFT) |
283 	      (rx_mask << TEGRA30_I2S_SLOT_CTRL_RX_SLOT_ENABLES_SHIFT) |
284 	      ((slots - 1) << TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_SHIFT);
285 
286 	pm_runtime_get_sync(dai->dev);
287 	regmap_update_bits(i2s->regmap, TEGRA30_I2S_SLOT_CTRL, mask, val);
288 	/* set the fsync width to minimum of 1 clock width */
289 	regmap_update_bits(i2s->regmap, TEGRA30_I2S_CH_CTRL,
290 			   TEGRA30_I2S_CH_CTRL_FSYNC_WIDTH_MASK, 0x0);
291 	pm_runtime_put(dai->dev);
292 
293 	return 0;
294 }
295 
tegra30_i2s_probe(struct snd_soc_dai * dai)296 static int tegra30_i2s_probe(struct snd_soc_dai *dai)
297 {
298 	struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
299 
300 	snd_soc_dai_init_dma_data(dai,	&i2s->playback_dma_data,
301 					&i2s->capture_dma_data);
302 
303 	return 0;
304 }
305 
306 static const struct snd_soc_dai_ops tegra30_i2s_dai_ops = {
307 	.probe		= tegra30_i2s_probe,
308 	.set_fmt	= tegra30_i2s_set_fmt,
309 	.hw_params	= tegra30_i2s_hw_params,
310 	.trigger	= tegra30_i2s_trigger,
311 	.set_tdm_slot	= tegra30_i2s_set_tdm,
312 };
313 
314 static const struct snd_soc_dai_driver tegra30_i2s_dai_template = {
315 	.playback = {
316 		.stream_name = "Playback",
317 		.channels_min = 2,
318 		.channels_max = 2,
319 		.rates = SNDRV_PCM_RATE_8000_96000,
320 		.formats = SNDRV_PCM_FMTBIT_S16_LE,
321 	},
322 	.capture = {
323 		.stream_name = "Capture",
324 		.channels_min = 2,
325 		.channels_max = 2,
326 		.rates = SNDRV_PCM_RATE_8000_96000,
327 		.formats = SNDRV_PCM_FMTBIT_S16_LE,
328 	},
329 	.ops = &tegra30_i2s_dai_ops,
330 	.symmetric_rate = 1,
331 };
332 
333 static const struct snd_soc_component_driver tegra30_i2s_component = {
334 	.name			= DRV_NAME,
335 	.legacy_dai_naming	= 1,
336 };
337 
tegra30_i2s_wr_rd_reg(struct device * dev,unsigned int reg)338 static bool tegra30_i2s_wr_rd_reg(struct device *dev, unsigned int reg)
339 {
340 	switch (reg) {
341 	case TEGRA30_I2S_CTRL:
342 	case TEGRA30_I2S_TIMING:
343 	case TEGRA30_I2S_OFFSET:
344 	case TEGRA30_I2S_CH_CTRL:
345 	case TEGRA30_I2S_SLOT_CTRL:
346 	case TEGRA30_I2S_CIF_RX_CTRL:
347 	case TEGRA30_I2S_CIF_TX_CTRL:
348 	case TEGRA30_I2S_FLOWCTL:
349 	case TEGRA30_I2S_TX_STEP:
350 	case TEGRA30_I2S_FLOW_STATUS:
351 	case TEGRA30_I2S_FLOW_TOTAL:
352 	case TEGRA30_I2S_FLOW_OVER:
353 	case TEGRA30_I2S_FLOW_UNDER:
354 	case TEGRA30_I2S_LCOEF_1_4_0:
355 	case TEGRA30_I2S_LCOEF_1_4_1:
356 	case TEGRA30_I2S_LCOEF_1_4_2:
357 	case TEGRA30_I2S_LCOEF_1_4_3:
358 	case TEGRA30_I2S_LCOEF_1_4_4:
359 	case TEGRA30_I2S_LCOEF_1_4_5:
360 	case TEGRA30_I2S_LCOEF_2_4_0:
361 	case TEGRA30_I2S_LCOEF_2_4_1:
362 	case TEGRA30_I2S_LCOEF_2_4_2:
363 		return true;
364 	default:
365 		return false;
366 	}
367 }
368 
tegra30_i2s_volatile_reg(struct device * dev,unsigned int reg)369 static bool tegra30_i2s_volatile_reg(struct device *dev, unsigned int reg)
370 {
371 	switch (reg) {
372 	case TEGRA30_I2S_FLOW_STATUS:
373 	case TEGRA30_I2S_FLOW_TOTAL:
374 	case TEGRA30_I2S_FLOW_OVER:
375 	case TEGRA30_I2S_FLOW_UNDER:
376 		return true;
377 	default:
378 		return false;
379 	}
380 }
381 
382 static const struct regmap_config tegra30_i2s_regmap_config = {
383 	.reg_bits = 32,
384 	.reg_stride = 4,
385 	.val_bits = 32,
386 	.max_register = TEGRA30_I2S_LCOEF_2_4_2,
387 	.writeable_reg = tegra30_i2s_wr_rd_reg,
388 	.readable_reg = tegra30_i2s_wr_rd_reg,
389 	.volatile_reg = tegra30_i2s_volatile_reg,
390 	.cache_type = REGCACHE_FLAT,
391 };
392 
393 static const struct tegra30_i2s_soc_data tegra30_i2s_config = {
394 	.set_audio_cif = tegra30_ahub_set_cif,
395 };
396 
397 static const struct tegra30_i2s_soc_data tegra124_i2s_config = {
398 	.set_audio_cif = tegra124_ahub_set_cif,
399 };
400 
401 static const struct of_device_id tegra30_i2s_of_match[] = {
402 	{ .compatible = "nvidia,tegra124-i2s", .data = &tegra124_i2s_config },
403 	{ .compatible = "nvidia,tegra30-i2s", .data = &tegra30_i2s_config },
404 	{},
405 };
406 
tegra30_i2s_platform_probe(struct platform_device * pdev)407 static int tegra30_i2s_platform_probe(struct platform_device *pdev)
408 {
409 	struct tegra30_i2s *i2s;
410 	const struct tegra30_i2s_soc_data *soc_data;
411 	u32 cif_ids[2];
412 	void __iomem *regs;
413 	int ret;
414 
415 	i2s = devm_kzalloc(&pdev->dev, sizeof(struct tegra30_i2s), GFP_KERNEL);
416 	if (!i2s) {
417 		ret = -ENOMEM;
418 		goto err;
419 	}
420 	dev_set_drvdata(&pdev->dev, i2s);
421 
422 	soc_data = of_device_get_match_data(&pdev->dev);
423 	if (!soc_data) {
424 		dev_err(&pdev->dev, "Error: No device match found\n");
425 		ret = -ENODEV;
426 		goto err;
427 	}
428 	i2s->soc_data = soc_data;
429 
430 	i2s->dai = tegra30_i2s_dai_template;
431 	i2s->dai.name = dev_name(&pdev->dev);
432 
433 	ret = of_property_read_u32_array(pdev->dev.of_node,
434 					 "nvidia,ahub-cif-ids", cif_ids,
435 					 ARRAY_SIZE(cif_ids));
436 	if (ret < 0)
437 		goto err;
438 
439 	i2s->playback_i2s_cif = cif_ids[0];
440 	i2s->capture_i2s_cif = cif_ids[1];
441 
442 	i2s->clk_i2s = devm_clk_get(&pdev->dev, NULL);
443 	if (IS_ERR(i2s->clk_i2s)) {
444 		dev_err(&pdev->dev, "Can't retrieve i2s clock\n");
445 		ret = PTR_ERR(i2s->clk_i2s);
446 		goto err;
447 	}
448 
449 	regs = devm_platform_ioremap_resource(pdev, 0);
450 	if (IS_ERR(regs)) {
451 		ret = PTR_ERR(regs);
452 		goto err;
453 	}
454 
455 	i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
456 					    &tegra30_i2s_regmap_config);
457 	if (IS_ERR(i2s->regmap)) {
458 		dev_err(&pdev->dev, "regmap init failed\n");
459 		ret = PTR_ERR(i2s->regmap);
460 		goto err;
461 	}
462 	regcache_cache_only(i2s->regmap, true);
463 
464 	pm_runtime_enable(&pdev->dev);
465 
466 	i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
467 	i2s->playback_dma_data.maxburst = 4;
468 	ret = tegra30_ahub_allocate_tx_fifo(&i2s->playback_fifo_cif,
469 					    i2s->playback_dma_chan,
470 					    sizeof(i2s->playback_dma_chan),
471 					    &i2s->playback_dma_data.addr);
472 	if (ret) {
473 		dev_err(&pdev->dev, "Could not alloc TX FIFO: %d\n", ret);
474 		goto err_pm_disable;
475 	}
476 	ret = tegra30_ahub_set_rx_cif_source(i2s->playback_i2s_cif,
477 					     i2s->playback_fifo_cif);
478 	if (ret) {
479 		dev_err(&pdev->dev, "Could not route TX FIFO: %d\n", ret);
480 		goto err_free_tx_fifo;
481 	}
482 
483 	i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
484 	i2s->capture_dma_data.maxburst = 4;
485 	ret = tegra30_ahub_allocate_rx_fifo(&i2s->capture_fifo_cif,
486 					    i2s->capture_dma_chan,
487 					    sizeof(i2s->capture_dma_chan),
488 					    &i2s->capture_dma_data.addr);
489 	if (ret) {
490 		dev_err(&pdev->dev, "Could not alloc RX FIFO: %d\n", ret);
491 		goto err_unroute_tx_fifo;
492 	}
493 	ret = tegra30_ahub_set_rx_cif_source(i2s->capture_fifo_cif,
494 					     i2s->capture_i2s_cif);
495 	if (ret) {
496 		dev_err(&pdev->dev, "Could not route TX FIFO: %d\n", ret);
497 		goto err_free_rx_fifo;
498 	}
499 
500 	ret = snd_soc_register_component(&pdev->dev, &tegra30_i2s_component,
501 				   &i2s->dai, 1);
502 	if (ret) {
503 		dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
504 		ret = -ENOMEM;
505 		goto err_unroute_rx_fifo;
506 	}
507 
508 	ret = tegra_pcm_platform_register_with_chan_names(&pdev->dev,
509 				&i2s->dma_config, i2s->playback_dma_chan,
510 				i2s->capture_dma_chan);
511 	if (ret) {
512 		dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
513 		goto err_unregister_component;
514 	}
515 
516 	return 0;
517 
518 err_unregister_component:
519 	snd_soc_unregister_component(&pdev->dev);
520 err_unroute_rx_fifo:
521 	tegra30_ahub_unset_rx_cif_source(i2s->capture_fifo_cif);
522 err_free_rx_fifo:
523 	tegra30_ahub_free_rx_fifo(i2s->capture_fifo_cif);
524 err_unroute_tx_fifo:
525 	tegra30_ahub_unset_rx_cif_source(i2s->playback_i2s_cif);
526 err_free_tx_fifo:
527 	tegra30_ahub_free_tx_fifo(i2s->playback_fifo_cif);
528 err_pm_disable:
529 	pm_runtime_disable(&pdev->dev);
530 err:
531 	return ret;
532 }
533 
tegra30_i2s_platform_remove(struct platform_device * pdev)534 static void tegra30_i2s_platform_remove(struct platform_device *pdev)
535 {
536 	struct tegra30_i2s *i2s = dev_get_drvdata(&pdev->dev);
537 
538 	tegra_pcm_platform_unregister(&pdev->dev);
539 	snd_soc_unregister_component(&pdev->dev);
540 
541 	tegra30_ahub_unset_rx_cif_source(i2s->capture_fifo_cif);
542 	tegra30_ahub_free_rx_fifo(i2s->capture_fifo_cif);
543 
544 	tegra30_ahub_unset_rx_cif_source(i2s->playback_i2s_cif);
545 	tegra30_ahub_free_tx_fifo(i2s->playback_fifo_cif);
546 
547 	pm_runtime_disable(&pdev->dev);
548 }
549 
550 static const struct dev_pm_ops tegra30_i2s_pm_ops = {
551 	SET_RUNTIME_PM_OPS(tegra30_i2s_runtime_suspend,
552 			   tegra30_i2s_runtime_resume, NULL)
553 	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
554 				pm_runtime_force_resume)
555 };
556 
557 static struct platform_driver tegra30_i2s_driver = {
558 	.driver = {
559 		.name = DRV_NAME,
560 		.of_match_table = tegra30_i2s_of_match,
561 		.pm = &tegra30_i2s_pm_ops,
562 	},
563 	.probe = tegra30_i2s_platform_probe,
564 	.remove_new = tegra30_i2s_platform_remove,
565 };
566 module_platform_driver(tegra30_i2s_driver);
567 
568 MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
569 MODULE_DESCRIPTION("Tegra30 I2S ASoC driver");
570 MODULE_LICENSE("GPL");
571 MODULE_ALIAS("platform:" DRV_NAME);
572 MODULE_DEVICE_TABLE(of, tegra30_i2s_of_match);
573