1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * tegra186_dspk.h - Definitions for Tegra186 DSPK driver
4  *
5  * Copyright (c) 2020 NVIDIA CORPORATION. All rights reserved.
6  *
7  */
8 
9 #ifndef __TEGRA186_DSPK_H__
10 #define __TEGRA186_DSPK_H__
11 
12 /* Register offsets from DSPK BASE */
13 #define TEGRA186_DSPK_RX_STATUS			0x0c
14 #define TEGRA186_DSPK_RX_INT_STATUS		0x10
15 #define TEGRA186_DSPK_RX_INT_MASK		0x14
16 #define TEGRA186_DSPK_RX_INT_SET		0x18
17 #define TEGRA186_DSPK_RX_INT_CLEAR		0x1c
18 #define TEGRA186_DSPK_RX_CIF_CTRL		0x20
19 #define TEGRA186_DSPK_ENABLE			0x40
20 #define TEGRA186_DSPK_SOFT_RESET		0x44
21 #define TEGRA186_DSPK_CG			0x48
22 #define TEGRA186_DSPK_STATUS			0x4c
23 #define TEGRA186_DSPK_INT_STATUS		0x50
24 #define TEGRA186_DSPK_CORE_CTRL			0x60
25 #define TEGRA186_DSPK_CODEC_CTRL		0x64
26 
27 /* DSPK CORE CONTROL fields */
28 #define CH_SEL_SHIFT				8
29 #define TEGRA186_DSPK_CHANNEL_SELECT_MASK	(0x3 << CH_SEL_SHIFT)
30 #define DSPK_OSR_SHIFT				4
31 #define TEGRA186_DSPK_OSR_MASK			(0x3 << DSPK_OSR_SHIFT)
32 #define LRSEL_POL_SHIFT				0
33 #define TEGRA186_DSPK_CTRL_LRSEL_POLARITY_MASK	(0x1 << LRSEL_POL_SHIFT)
34 #define TEGRA186_DSPK_RX_FIFO_DEPTH		64
35 
36 #define DSPK_OSR_FACTOR				32
37 
38 /* DSPK interface clock ratio */
39 #define DSPK_CLK_RATIO				4
40 
41 enum tegra_dspk_osr {
42 	DSPK_OSR_32,
43 	DSPK_OSR_64,
44 	DSPK_OSR_128,
45 	DSPK_OSR_256,
46 };
47 
48 enum tegra_dspk_ch_sel {
49 	DSPK_CH_SELECT_LEFT,
50 	DSPK_CH_SELECT_RIGHT,
51 	DSPK_CH_SELECT_STEREO,
52 };
53 
54 enum tegra_dspk_lrsel {
55 	DSPK_LRSEL_LEFT,
56 	DSPK_LRSEL_RIGHT,
57 };
58 
59 struct tegra186_dspk {
60 	unsigned int rx_fifo_th;
61 	unsigned int osr_val;
62 	unsigned int lrsel;
63 	unsigned int ch_sel;
64 	unsigned int mono_to_stereo;
65 	unsigned int stereo_to_mono;
66 	struct clk *clk_dspk;
67 	struct regmap *regmap;
68 };
69 
70 #endif
71