1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * File:         sound/soc/codecs/ssm2602.h
4  * Author:       Cliff Cai <Cliff.Cai@analog.com>
5  *
6  * Created:      Tue June 06 2008
7  *
8  * Modified:
9  *               Copyright 2008 Analog Devices Inc.
10  *
11  * Bugs:         Enter bugs at http://blackfin.uclinux.org/
12  */
13 
14 #ifndef _SSM2602_H
15 #define _SSM2602_H
16 
17 #include <linux/regmap.h>
18 
19 struct device;
20 
21 enum ssm2602_type {
22 	SSM2602,
23 	SSM2604,
24 };
25 
26 extern const struct regmap_config ssm2602_regmap_config;
27 
28 int ssm2602_probe(struct device *dev, enum ssm2602_type type,
29 	struct regmap *regmap);
30 
31 /* SSM2602 Codec Register definitions */
32 
33 #define SSM2602_LINVOL   0x00
34 #define SSM2602_RINVOL   0x01
35 #define SSM2602_LOUT1V   0x02
36 #define SSM2602_ROUT1V   0x03
37 #define SSM2602_APANA    0x04
38 #define SSM2602_APDIGI   0x05
39 #define SSM2602_PWR      0x06
40 #define SSM2602_IFACE    0x07
41 #define SSM2602_SRATE    0x08
42 #define SSM2602_ACTIVE   0x09
43 #define SSM2602_RESET	 0x0f
44 
45 /*SSM2602 Codec Register Field definitions
46  *(Mask value to extract the corresponding Register field)
47  */
48 
49 /*Left ADC Volume Control (SSM2602_REG_LEFT_ADC_VOL)*/
50 #define     LINVOL_LIN_VOL                0x01F   /* Left Channel PGA Volume control                      */
51 #define     LINVOL_LIN_ENABLE_MUTE        0x080   /* Left Channel Input Mute                              */
52 #define     LINVOL_LRIN_BOTH              0x100   /* Left Channel Line Input Volume update                */
53 
54 /*Right ADC Volume Control (SSM2602_REG_RIGHT_ADC_VOL)*/
55 #define     RINVOL_RIN_VOL                0x01F   /* Right Channel PGA Volume control                     */
56 #define     RINVOL_RIN_ENABLE_MUTE        0x080   /* Right Channel Input Mute                             */
57 #define     RINVOL_RLIN_BOTH              0x100   /* Right Channel Line Input Volume update               */
58 
59 /*Left DAC Volume Control (SSM2602_REG_LEFT_DAC_VOL)*/
60 #define     LOUT1V_LHP_VOL                0x07F   /* Left Channel Headphone volume control                */
61 #define     LOUT1V_ENABLE_LZC             0x080   /* Left Channel Zero cross detect enable                */
62 #define     LOUT1V_LRHP_BOTH              0x100   /* Left Channel Headphone volume update                 */
63 
64 /*Right DAC Volume Control (SSM2602_REG_RIGHT_DAC_VOL)*/
65 #define     ROUT1V_RHP_VOL                0x07F   /* Right Channel Headphone volume control               */
66 #define     ROUT1V_ENABLE_RZC             0x080   /* Right Channel Zero cross detect enable               */
67 #define     ROUT1V_RLHP_BOTH              0x100   /* Right Channel Headphone volume update                */
68 
69 /*Analogue Audio Path Control (SSM2602_REG_ANALOGUE_PATH)*/
70 #define     APANA_ENABLE_MIC_BOOST       0x001   /* Primary Microphone Amplifier gain booster control    */
71 #define     APANA_ENABLE_MIC_MUTE        0x002   /* Microphone Mute Control                              */
72 #define     APANA_ADC_IN_SELECT          0x004   /* Microphone/Line IN select to ADC (1=MIC, 0=Line In)  */
73 #define     APANA_ENABLE_BYPASS          0x008   /* Line input bypass to line output                     */
74 #define     APANA_SELECT_DAC             0x010   /* Select DAC (1=Select DAC, 0=Don't Select DAC)        */
75 #define     APANA_ENABLE_SIDETONE        0x020   /* Enable/Disable Side Tone                             */
76 #define     APANA_SIDETONE_ATTN          0x0C0   /* Side Tone Attenuation                                */
77 #define     APANA_ENABLE_MIC_BOOST2      0x100   /* Secondary Microphone Amplifier gain booster control  */
78 
79 /*Digital Audio Path Control (SSM2602_REG_DIGITAL_PATH)*/
80 #define     APDIGI_ENABLE_ADC_HPF         0x001   /* Enable/Disable ADC Highpass Filter                   */
81 #define     APDIGI_DE_EMPHASIS            0x006   /* De-Emphasis Control                                  */
82 #define     APDIGI_ENABLE_DAC_MUTE        0x008   /* DAC Mute Control                                     */
83 #define     APDIGI_STORE_OFFSET           0x010   /* Store/Clear DC offset when HPF is disabled           */
84 
85 /*Power Down Control (SSM2602_REG_POWER)
86  *(1=Enable PowerDown, 0=Disable PowerDown)
87  */
88 #define     PWR_LINE_IN_PDN            0x001   /* Line Input Power Down                                */
89 #define     PWR_MIC_PDN                0x002   /* Microphone Input & Bias Power Down                   */
90 #define     PWR_ADC_PDN                0x004   /* ADC Power Down                                       */
91 #define     PWR_DAC_PDN                0x008   /* DAC Power Down                                       */
92 #define     PWR_OUT_PDN                0x010   /* Outputs Power Down                                   */
93 #define     PWR_OSC_PDN                0x020   /* Oscillator Power Down                                */
94 #define     PWR_CLK_OUT_PDN            0x040   /* CLKOUT Power Down                                    */
95 #define     PWR_POWER_OFF              0x080   /* POWEROFF Mode                                        */
96 
97 /*Digital Audio Interface Format (SSM2602_REG_DIGITAL_IFACE)*/
98 #define     IFACE_IFACE_FORMAT           0x003   /* Digital Audio input format control                   */
99 #define     IFACE_AUDIO_DATA_LEN         0x00C   /* Audio Data word length control                       */
100 #define     IFACE_DAC_LR_POLARITY        0x010   /* Polarity Control for clocks in RJ,LJ and I2S modes   */
101 #define     IFACE_DAC_LR_SWAP            0x020   /* Swap DAC data control                                */
102 #define     IFACE_ENABLE_MASTER          0x040   /* Enable/Disable Master Mode                           */
103 #define     IFACE_BCLK_INVERT            0x080   /* Bit Clock Inversion control                          */
104 
105 /*Sampling Control (SSM2602_REG_SAMPLING_CTRL)*/
106 #define     SRATE_ENABLE_USB_MODE        0x001   /* Enable/Disable USB Mode                              */
107 #define     SRATE_BOS_RATE               0x002   /* Base Over-Sampling rate                              */
108 #define     SRATE_SAMPLE_RATE            0x03C   /* Clock setting condition (Sampling rate control)      */
109 #define     SRATE_CORECLK_DIV2           0x040   /* Core Clock divider select                            */
110 #define     SRATE_CLKOUT_DIV2            0x080   /* Clock Out divider select                             */
111 
112 /*Active Control (SSM2602_REG_ACTIVE_CTRL)*/
113 #define     ACTIVE_ACTIVATE_CODEC         0x001   /* Activate Codec Digital Audio Interface               */
114 
115 /*********************************************************************/
116 
117 #define SSM2602_CACHEREGNUM 	10
118 
119 enum ssm2602_clk {
120 	SSM2602_SYSCLK,
121 	SSM2602_CLK_CLKOUT,
122 	SSM2602_CLK_XTO
123 };
124 
125 #endif
126