1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * HD-audio stream operations
4  */
5 
6 #include <linux/kernel.h>
7 #include <linux/delay.h>
8 #include <linux/export.h>
9 #include <linux/clocksource.h>
10 #include <sound/compress_driver.h>
11 #include <sound/core.h>
12 #include <sound/pcm.h>
13 #include <sound/hdaudio.h>
14 #include <sound/hda_register.h>
15 #include "trace.h"
16 
17 /*
18  * the hdac_stream library is intended to be used with the following
19  * transitions. The states are not formally defined in the code but loosely
20  * inspired by boolean variables. Note that the 'prepared' field is not used
21  * in this library but by the callers during the hw_params/prepare transitions
22  *
23  *			   |
24  *	stream_init()	   |
25  *			   v
26  *			+--+-------+
27  *			|  unused  |
28  *			+--+----+--+
29  *			   |    ^
30  *	stream_assign()	   | 	|    stream_release()
31  *			   v	|
32  *			+--+----+--+
33  *			|  opened  |
34  *			+--+----+--+
35  *			   |    ^
36  *	stream_reset()	   |    |
37  *	stream_setup()	   |	|    stream_cleanup()
38  *			   v	|
39  *			+--+----+--+
40  *			| prepared |
41  *			+--+----+--+
42  *			   |    ^
43  *	stream_start()	   | 	|    stream_stop()
44  *			   v	|
45  *			+--+----+--+
46  *			|  running |
47  *			+----------+
48  */
49 
50 /**
51  * snd_hdac_get_stream_stripe_ctl - get stripe control value
52  * @bus: HD-audio core bus
53  * @substream: PCM substream
54  */
snd_hdac_get_stream_stripe_ctl(struct hdac_bus * bus,struct snd_pcm_substream * substream)55 int snd_hdac_get_stream_stripe_ctl(struct hdac_bus *bus,
56 				   struct snd_pcm_substream *substream)
57 {
58 	struct snd_pcm_runtime *runtime = substream->runtime;
59 	unsigned int channels = runtime->channels,
60 		     rate = runtime->rate,
61 		     bits_per_sample = runtime->sample_bits,
62 		     max_sdo_lines, value, sdo_line;
63 
64 	/* T_AZA_GCAP_NSDO is 1:2 bitfields in GCAP */
65 	max_sdo_lines = snd_hdac_chip_readl(bus, GCAP) & AZX_GCAP_NSDO;
66 
67 	/* following is from HD audio spec */
68 	for (sdo_line = max_sdo_lines; sdo_line > 0; sdo_line >>= 1) {
69 		if (rate > 48000)
70 			value = (channels * bits_per_sample *
71 					(rate / 48000)) / sdo_line;
72 		else
73 			value = (channels * bits_per_sample) / sdo_line;
74 
75 		if (value >= bus->sdo_limit)
76 			break;
77 	}
78 
79 	/* stripe value: 0 for 1SDO, 1 for 2SDO, 2 for 4SDO lines */
80 	return sdo_line >> 1;
81 }
82 EXPORT_SYMBOL_GPL(snd_hdac_get_stream_stripe_ctl);
83 
84 /**
85  * snd_hdac_stream_init - initialize each stream (aka device)
86  * @bus: HD-audio core bus
87  * @azx_dev: HD-audio core stream object to initialize
88  * @idx: stream index number
89  * @direction: stream direction (SNDRV_PCM_STREAM_PLAYBACK or SNDRV_PCM_STREAM_CAPTURE)
90  * @tag: the tag id to assign
91  *
92  * Assign the starting bdl address to each stream (device) and initialize.
93  */
snd_hdac_stream_init(struct hdac_bus * bus,struct hdac_stream * azx_dev,int idx,int direction,int tag)94 void snd_hdac_stream_init(struct hdac_bus *bus, struct hdac_stream *azx_dev,
95 			  int idx, int direction, int tag)
96 {
97 	azx_dev->bus = bus;
98 	/* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
99 	azx_dev->sd_addr = bus->remap_addr + (0x20 * idx + 0x80);
100 	/* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
101 	azx_dev->sd_int_sta_mask = 1 << idx;
102 	azx_dev->index = idx;
103 	azx_dev->direction = direction;
104 	azx_dev->stream_tag = tag;
105 	snd_hdac_dsp_lock_init(azx_dev);
106 	list_add_tail(&azx_dev->list, &bus->stream_list);
107 
108 	if (bus->spbcap) {
109 		azx_dev->spib_addr = bus->spbcap + AZX_SPB_BASE +
110 					AZX_SPB_INTERVAL * idx +
111 					AZX_SPB_SPIB;
112 
113 		azx_dev->fifo_addr = bus->spbcap + AZX_SPB_BASE +
114 					AZX_SPB_INTERVAL * idx +
115 					AZX_SPB_MAXFIFO;
116 	}
117 
118 	if (bus->drsmcap)
119 		azx_dev->dpibr_addr = bus->drsmcap + AZX_DRSM_BASE +
120 					AZX_DRSM_INTERVAL * idx;
121 }
122 EXPORT_SYMBOL_GPL(snd_hdac_stream_init);
123 
124 /**
125  * snd_hdac_stream_start - start a stream
126  * @azx_dev: HD-audio core stream to start
127  *
128  * Start a stream, set start_wallclk and set the running flag.
129  */
snd_hdac_stream_start(struct hdac_stream * azx_dev)130 void snd_hdac_stream_start(struct hdac_stream *azx_dev)
131 {
132 	struct hdac_bus *bus = azx_dev->bus;
133 	int stripe_ctl;
134 
135 	trace_snd_hdac_stream_start(bus, azx_dev);
136 
137 	azx_dev->start_wallclk = snd_hdac_chip_readl(bus, WALLCLK);
138 
139 	/* enable SIE */
140 	snd_hdac_chip_updatel(bus, INTCTL,
141 			      1 << azx_dev->index,
142 			      1 << azx_dev->index);
143 	/* set stripe control */
144 	if (azx_dev->stripe) {
145 		if (azx_dev->substream)
146 			stripe_ctl = snd_hdac_get_stream_stripe_ctl(bus, azx_dev->substream);
147 		else
148 			stripe_ctl = 0;
149 		snd_hdac_stream_updateb(azx_dev, SD_CTL_3B, SD_CTL_STRIPE_MASK,
150 					stripe_ctl);
151 	}
152 	/* set DMA start and interrupt mask */
153 	if (bus->access_sdnctl_in_dword)
154 		snd_hdac_stream_updatel(azx_dev, SD_CTL,
155 				0, SD_CTL_DMA_START | SD_INT_MASK);
156 	else
157 		snd_hdac_stream_updateb(azx_dev, SD_CTL,
158 				0, SD_CTL_DMA_START | SD_INT_MASK);
159 	azx_dev->running = true;
160 }
161 EXPORT_SYMBOL_GPL(snd_hdac_stream_start);
162 
163 /**
164  * snd_hdac_stream_clear - helper to clear stream registers and stop DMA transfers
165  * @azx_dev: HD-audio core stream to stop
166  */
snd_hdac_stream_clear(struct hdac_stream * azx_dev)167 static void snd_hdac_stream_clear(struct hdac_stream *azx_dev)
168 {
169 	snd_hdac_stream_updateb(azx_dev, SD_CTL,
170 				SD_CTL_DMA_START | SD_INT_MASK, 0);
171 	snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
172 	if (azx_dev->stripe)
173 		snd_hdac_stream_updateb(azx_dev, SD_CTL_3B, SD_CTL_STRIPE_MASK, 0);
174 	azx_dev->running = false;
175 }
176 
177 /**
178  * snd_hdac_stream_stop - stop a stream
179  * @azx_dev: HD-audio core stream to stop
180  *
181  * Stop a stream DMA and disable stream interrupt
182  */
snd_hdac_stream_stop(struct hdac_stream * azx_dev)183 void snd_hdac_stream_stop(struct hdac_stream *azx_dev)
184 {
185 	trace_snd_hdac_stream_stop(azx_dev->bus, azx_dev);
186 
187 	snd_hdac_stream_clear(azx_dev);
188 	/* disable SIE */
189 	snd_hdac_chip_updatel(azx_dev->bus, INTCTL, 1 << azx_dev->index, 0);
190 }
191 EXPORT_SYMBOL_GPL(snd_hdac_stream_stop);
192 
193 /**
194  * snd_hdac_stop_streams - stop all streams
195  * @bus: HD-audio core bus
196  */
snd_hdac_stop_streams(struct hdac_bus * bus)197 void snd_hdac_stop_streams(struct hdac_bus *bus)
198 {
199 	struct hdac_stream *stream;
200 
201 	list_for_each_entry(stream, &bus->stream_list, list)
202 		snd_hdac_stream_stop(stream);
203 }
204 EXPORT_SYMBOL_GPL(snd_hdac_stop_streams);
205 
206 /**
207  * snd_hdac_stop_streams_and_chip - stop all streams and chip if running
208  * @bus: HD-audio core bus
209  */
snd_hdac_stop_streams_and_chip(struct hdac_bus * bus)210 void snd_hdac_stop_streams_and_chip(struct hdac_bus *bus)
211 {
212 
213 	if (bus->chip_init) {
214 		snd_hdac_stop_streams(bus);
215 		snd_hdac_bus_stop_chip(bus);
216 	}
217 }
218 EXPORT_SYMBOL_GPL(snd_hdac_stop_streams_and_chip);
219 
220 /**
221  * snd_hdac_stream_reset - reset a stream
222  * @azx_dev: HD-audio core stream to reset
223  */
snd_hdac_stream_reset(struct hdac_stream * azx_dev)224 void snd_hdac_stream_reset(struct hdac_stream *azx_dev)
225 {
226 	unsigned char val;
227 	int dma_run_state;
228 
229 	snd_hdac_stream_clear(azx_dev);
230 
231 	dma_run_state = snd_hdac_stream_readb(azx_dev, SD_CTL) & SD_CTL_DMA_START;
232 
233 	snd_hdac_stream_updateb(azx_dev, SD_CTL, 0, SD_CTL_STREAM_RESET);
234 
235 	/* wait for hardware to report that the stream entered reset */
236 	snd_hdac_stream_readb_poll(azx_dev, SD_CTL, val, (val & SD_CTL_STREAM_RESET), 3, 300);
237 
238 	if (azx_dev->bus->dma_stop_delay && dma_run_state)
239 		udelay(azx_dev->bus->dma_stop_delay);
240 
241 	snd_hdac_stream_updateb(azx_dev, SD_CTL, SD_CTL_STREAM_RESET, 0);
242 
243 	/* wait for hardware to report that the stream is out of reset */
244 	snd_hdac_stream_readb_poll(azx_dev, SD_CTL, val, !(val & SD_CTL_STREAM_RESET), 3, 300);
245 
246 	/* reset first position - may not be synced with hw at this time */
247 	if (azx_dev->posbuf)
248 		*azx_dev->posbuf = 0;
249 }
250 EXPORT_SYMBOL_GPL(snd_hdac_stream_reset);
251 
252 /**
253  * snd_hdac_stream_setup -  set up the SD for streaming
254  * @azx_dev: HD-audio core stream to set up
255  */
snd_hdac_stream_setup(struct hdac_stream * azx_dev)256 int snd_hdac_stream_setup(struct hdac_stream *azx_dev)
257 {
258 	struct hdac_bus *bus = azx_dev->bus;
259 	struct snd_pcm_runtime *runtime;
260 	unsigned int val;
261 
262 	if (azx_dev->substream)
263 		runtime = azx_dev->substream->runtime;
264 	else
265 		runtime = NULL;
266 	/* make sure the run bit is zero for SD */
267 	snd_hdac_stream_clear(azx_dev);
268 	/* program the stream_tag */
269 	val = snd_hdac_stream_readl(azx_dev, SD_CTL);
270 	val = (val & ~SD_CTL_STREAM_TAG_MASK) |
271 		(azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
272 	if (!bus->snoop)
273 		val |= SD_CTL_TRAFFIC_PRIO;
274 	snd_hdac_stream_writel(azx_dev, SD_CTL, val);
275 
276 	/* program the length of samples in cyclic buffer */
277 	snd_hdac_stream_writel(azx_dev, SD_CBL, azx_dev->bufsize);
278 
279 	/* program the stream format */
280 	/* this value needs to be the same as the one programmed */
281 	snd_hdac_stream_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
282 
283 	/* program the stream LVI (last valid index) of the BDL */
284 	snd_hdac_stream_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
285 
286 	/* program the BDL address */
287 	/* lower BDL address */
288 	snd_hdac_stream_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
289 	/* upper BDL address */
290 	snd_hdac_stream_writel(azx_dev, SD_BDLPU,
291 			       upper_32_bits(azx_dev->bdl.addr));
292 
293 	/* enable the position buffer */
294 	if (bus->use_posbuf && bus->posbuf.addr) {
295 		if (!(snd_hdac_chip_readl(bus, DPLBASE) & AZX_DPLBASE_ENABLE))
296 			snd_hdac_chip_writel(bus, DPLBASE,
297 				(u32)bus->posbuf.addr | AZX_DPLBASE_ENABLE);
298 	}
299 
300 	/* set the interrupt enable bits in the descriptor control register */
301 	snd_hdac_stream_updatel(azx_dev, SD_CTL, 0, SD_INT_MASK);
302 
303 	azx_dev->fifo_size = snd_hdac_stream_readw(azx_dev, SD_FIFOSIZE) + 1;
304 
305 	/* when LPIB delay correction gives a small negative value,
306 	 * we ignore it; currently set the threshold statically to
307 	 * 64 frames
308 	 */
309 	if (runtime && runtime->period_size > 64)
310 		azx_dev->delay_negative_threshold =
311 			-frames_to_bytes(runtime, 64);
312 	else
313 		azx_dev->delay_negative_threshold = 0;
314 
315 	/* wallclk has 24Mhz clock source */
316 	if (runtime)
317 		azx_dev->period_wallclk = (((runtime->period_size * 24000) /
318 				    runtime->rate) * 1000);
319 
320 	return 0;
321 }
322 EXPORT_SYMBOL_GPL(snd_hdac_stream_setup);
323 
324 /**
325  * snd_hdac_stream_cleanup - cleanup a stream
326  * @azx_dev: HD-audio core stream to clean up
327  */
snd_hdac_stream_cleanup(struct hdac_stream * azx_dev)328 void snd_hdac_stream_cleanup(struct hdac_stream *azx_dev)
329 {
330 	snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
331 	snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
332 	snd_hdac_stream_writel(azx_dev, SD_CTL, 0);
333 	azx_dev->bufsize = 0;
334 	azx_dev->period_bytes = 0;
335 	azx_dev->format_val = 0;
336 }
337 EXPORT_SYMBOL_GPL(snd_hdac_stream_cleanup);
338 
339 /**
340  * snd_hdac_stream_assign - assign a stream for the PCM
341  * @bus: HD-audio core bus
342  * @substream: PCM substream to assign
343  *
344  * Look for an unused stream for the given PCM substream, assign it
345  * and return the stream object.  If no stream is free, returns NULL.
346  * The function tries to keep using the same stream object when it's used
347  * beforehand.  Also, when bus->reverse_assign flag is set, the last free
348  * or matching entry is returned.  This is needed for some strange codecs.
349  */
snd_hdac_stream_assign(struct hdac_bus * bus,struct snd_pcm_substream * substream)350 struct hdac_stream *snd_hdac_stream_assign(struct hdac_bus *bus,
351 					   struct snd_pcm_substream *substream)
352 {
353 	struct hdac_stream *azx_dev;
354 	struct hdac_stream *res = NULL;
355 
356 	/* make a non-zero unique key for the substream */
357 	int key = (substream->number << 2) | (substream->stream + 1);
358 
359 	if (substream->pcm)
360 		key |= (substream->pcm->device << 16);
361 
362 	spin_lock_irq(&bus->reg_lock);
363 	list_for_each_entry(azx_dev, &bus->stream_list, list) {
364 		if (azx_dev->direction != substream->stream)
365 			continue;
366 		if (azx_dev->opened)
367 			continue;
368 		if (azx_dev->assigned_key == key) {
369 			res = azx_dev;
370 			break;
371 		}
372 		if (!res || bus->reverse_assign)
373 			res = azx_dev;
374 	}
375 	if (res) {
376 		res->opened = 1;
377 		res->running = 0;
378 		res->assigned_key = key;
379 		res->substream = substream;
380 	}
381 	spin_unlock_irq(&bus->reg_lock);
382 	return res;
383 }
384 EXPORT_SYMBOL_GPL(snd_hdac_stream_assign);
385 
386 /**
387  * snd_hdac_stream_release_locked - release the assigned stream
388  * @azx_dev: HD-audio core stream to release
389  *
390  * Release the stream that has been assigned by snd_hdac_stream_assign().
391  * The bus->reg_lock needs to be taken at a higher level
392  */
snd_hdac_stream_release_locked(struct hdac_stream * azx_dev)393 void snd_hdac_stream_release_locked(struct hdac_stream *azx_dev)
394 {
395 	azx_dev->opened = 0;
396 	azx_dev->running = 0;
397 	azx_dev->substream = NULL;
398 }
399 EXPORT_SYMBOL_GPL(snd_hdac_stream_release_locked);
400 
401 /**
402  * snd_hdac_stream_release - release the assigned stream
403  * @azx_dev: HD-audio core stream to release
404  *
405  * Release the stream that has been assigned by snd_hdac_stream_assign().
406  */
snd_hdac_stream_release(struct hdac_stream * azx_dev)407 void snd_hdac_stream_release(struct hdac_stream *azx_dev)
408 {
409 	struct hdac_bus *bus = azx_dev->bus;
410 
411 	spin_lock_irq(&bus->reg_lock);
412 	snd_hdac_stream_release_locked(azx_dev);
413 	spin_unlock_irq(&bus->reg_lock);
414 }
415 EXPORT_SYMBOL_GPL(snd_hdac_stream_release);
416 
417 /**
418  * snd_hdac_get_stream - return hdac_stream based on stream_tag and
419  * direction
420  *
421  * @bus: HD-audio core bus
422  * @dir: direction for the stream to be found
423  * @stream_tag: stream tag for stream to be found
424  */
snd_hdac_get_stream(struct hdac_bus * bus,int dir,int stream_tag)425 struct hdac_stream *snd_hdac_get_stream(struct hdac_bus *bus,
426 					int dir, int stream_tag)
427 {
428 	struct hdac_stream *s;
429 
430 	list_for_each_entry(s, &bus->stream_list, list) {
431 		if (s->direction == dir && s->stream_tag == stream_tag)
432 			return s;
433 	}
434 
435 	return NULL;
436 }
437 EXPORT_SYMBOL_GPL(snd_hdac_get_stream);
438 
439 /*
440  * set up a BDL entry
441  */
setup_bdle(struct hdac_bus * bus,struct snd_dma_buffer * dmab,struct hdac_stream * azx_dev,__le32 ** bdlp,int ofs,int size,int with_ioc)442 static int setup_bdle(struct hdac_bus *bus,
443 		      struct snd_dma_buffer *dmab,
444 		      struct hdac_stream *azx_dev, __le32 **bdlp,
445 		      int ofs, int size, int with_ioc)
446 {
447 	__le32 *bdl = *bdlp;
448 
449 	while (size > 0) {
450 		dma_addr_t addr;
451 		int chunk;
452 
453 		if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
454 			return -EINVAL;
455 
456 		addr = snd_sgbuf_get_addr(dmab, ofs);
457 		/* program the address field of the BDL entry */
458 		bdl[0] = cpu_to_le32((u32)addr);
459 		bdl[1] = cpu_to_le32(upper_32_bits(addr));
460 		/* program the size field of the BDL entry */
461 		chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size);
462 		/* one BDLE cannot cross 4K boundary on CTHDA chips */
463 		if (bus->align_bdle_4k) {
464 			u32 remain = 0x1000 - (ofs & 0xfff);
465 
466 			if (chunk > remain)
467 				chunk = remain;
468 		}
469 		bdl[2] = cpu_to_le32(chunk);
470 		/* program the IOC to enable interrupt
471 		 * only when the whole fragment is processed
472 		 */
473 		size -= chunk;
474 		bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
475 		bdl += 4;
476 		azx_dev->frags++;
477 		ofs += chunk;
478 	}
479 	*bdlp = bdl;
480 	return ofs;
481 }
482 
483 /**
484  * snd_hdac_stream_setup_periods - set up BDL entries
485  * @azx_dev: HD-audio core stream to set up
486  *
487  * Set up the buffer descriptor table of the given stream based on the
488  * period and buffer sizes of the assigned PCM substream.
489  */
snd_hdac_stream_setup_periods(struct hdac_stream * azx_dev)490 int snd_hdac_stream_setup_periods(struct hdac_stream *azx_dev)
491 {
492 	struct hdac_bus *bus = azx_dev->bus;
493 	struct snd_pcm_substream *substream = azx_dev->substream;
494 	struct snd_compr_stream *cstream = azx_dev->cstream;
495 	struct snd_pcm_runtime *runtime = NULL;
496 	struct snd_dma_buffer *dmab;
497 	__le32 *bdl;
498 	int i, ofs, periods, period_bytes;
499 	int pos_adj, pos_align;
500 
501 	if (substream) {
502 		runtime = substream->runtime;
503 		dmab = snd_pcm_get_dma_buf(substream);
504 	} else if (cstream) {
505 		dmab = snd_pcm_get_dma_buf(cstream);
506 	} else {
507 		WARN(1, "No substream or cstream assigned\n");
508 		return -EINVAL;
509 	}
510 
511 	/* reset BDL address */
512 	snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
513 	snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
514 
515 	period_bytes = azx_dev->period_bytes;
516 	periods = azx_dev->bufsize / period_bytes;
517 
518 	/* program the initial BDL entries */
519 	bdl = (__le32 *)azx_dev->bdl.area;
520 	ofs = 0;
521 	azx_dev->frags = 0;
522 
523 	pos_adj = bus->bdl_pos_adj;
524 	if (runtime && !azx_dev->no_period_wakeup && pos_adj > 0) {
525 		pos_align = pos_adj;
526 		pos_adj = DIV_ROUND_UP(pos_adj * runtime->rate, 48000);
527 		if (!pos_adj)
528 			pos_adj = pos_align;
529 		else
530 			pos_adj = roundup(pos_adj, pos_align);
531 		pos_adj = frames_to_bytes(runtime, pos_adj);
532 		if (pos_adj >= period_bytes) {
533 			dev_warn(bus->dev, "Too big adjustment %d\n",
534 				 pos_adj);
535 			pos_adj = 0;
536 		} else {
537 			ofs = setup_bdle(bus, dmab, azx_dev,
538 					 &bdl, ofs, pos_adj, true);
539 			if (ofs < 0)
540 				goto error;
541 		}
542 	} else
543 		pos_adj = 0;
544 
545 	for (i = 0; i < periods; i++) {
546 		if (i == periods - 1 && pos_adj)
547 			ofs = setup_bdle(bus, dmab, azx_dev,
548 					 &bdl, ofs, period_bytes - pos_adj, 0);
549 		else
550 			ofs = setup_bdle(bus, dmab, azx_dev,
551 					 &bdl, ofs, period_bytes,
552 					 !azx_dev->no_period_wakeup);
553 		if (ofs < 0)
554 			goto error;
555 	}
556 	return 0;
557 
558  error:
559 	dev_err(bus->dev, "Too many BDL entries: buffer=%d, period=%d\n",
560 		azx_dev->bufsize, period_bytes);
561 	return -EINVAL;
562 }
563 EXPORT_SYMBOL_GPL(snd_hdac_stream_setup_periods);
564 
565 /**
566  * snd_hdac_stream_set_params - set stream parameters
567  * @azx_dev: HD-audio core stream for which parameters are to be set
568  * @format_val: format value parameter
569  *
570  * Setup the HD-audio core stream parameters from substream of the stream
571  * and passed format value
572  */
snd_hdac_stream_set_params(struct hdac_stream * azx_dev,unsigned int format_val)573 int snd_hdac_stream_set_params(struct hdac_stream *azx_dev,
574 				 unsigned int format_val)
575 {
576 	struct snd_pcm_substream *substream = azx_dev->substream;
577 	struct snd_compr_stream *cstream = azx_dev->cstream;
578 	unsigned int bufsize, period_bytes;
579 	unsigned int no_period_wakeup;
580 	int err;
581 
582 	if (substream) {
583 		bufsize = snd_pcm_lib_buffer_bytes(substream);
584 		period_bytes = snd_pcm_lib_period_bytes(substream);
585 		no_period_wakeup = substream->runtime->no_period_wakeup;
586 	} else if (cstream) {
587 		bufsize = cstream->runtime->buffer_size;
588 		period_bytes = cstream->runtime->fragment_size;
589 		no_period_wakeup = 0;
590 	} else {
591 		return -EINVAL;
592 	}
593 
594 	if (bufsize != azx_dev->bufsize ||
595 	    period_bytes != azx_dev->period_bytes ||
596 	    format_val != azx_dev->format_val ||
597 	    no_period_wakeup != azx_dev->no_period_wakeup) {
598 		azx_dev->bufsize = bufsize;
599 		azx_dev->period_bytes = period_bytes;
600 		azx_dev->format_val = format_val;
601 		azx_dev->no_period_wakeup = no_period_wakeup;
602 		err = snd_hdac_stream_setup_periods(azx_dev);
603 		if (err < 0)
604 			return err;
605 	}
606 	return 0;
607 }
608 EXPORT_SYMBOL_GPL(snd_hdac_stream_set_params);
609 
azx_cc_read(const struct cyclecounter * cc)610 static u64 azx_cc_read(const struct cyclecounter *cc)
611 {
612 	struct hdac_stream *azx_dev = container_of(cc, struct hdac_stream, cc);
613 
614 	return snd_hdac_chip_readl(azx_dev->bus, WALLCLK);
615 }
616 
azx_timecounter_init(struct hdac_stream * azx_dev,bool force,u64 last)617 static void azx_timecounter_init(struct hdac_stream *azx_dev,
618 				 bool force, u64 last)
619 {
620 	struct timecounter *tc = &azx_dev->tc;
621 	struct cyclecounter *cc = &azx_dev->cc;
622 	u64 nsec;
623 
624 	cc->read = azx_cc_read;
625 	cc->mask = CLOCKSOURCE_MASK(32);
626 
627 	/*
628 	 * Calculate the optimal mult/shift values. The counter wraps
629 	 * around after ~178.9 seconds.
630 	 */
631 	clocks_calc_mult_shift(&cc->mult, &cc->shift, 24000000,
632 			       NSEC_PER_SEC, 178);
633 
634 	nsec = 0; /* audio time is elapsed time since trigger */
635 	timecounter_init(tc, cc, nsec);
636 	if (force) {
637 		/*
638 		 * force timecounter to use predefined value,
639 		 * used for synchronized starts
640 		 */
641 		tc->cycle_last = last;
642 	}
643 }
644 
645 /**
646  * snd_hdac_stream_timecounter_init - initialize time counter
647  * @azx_dev: HD-audio core stream (master stream)
648  * @streams: bit flags of streams to set up
649  *
650  * Initializes the time counter of streams marked by the bit flags (each
651  * bit corresponds to the stream index).
652  * The trigger timestamp of PCM substream assigned to the given stream is
653  * updated accordingly, too.
654  */
snd_hdac_stream_timecounter_init(struct hdac_stream * azx_dev,unsigned int streams)655 void snd_hdac_stream_timecounter_init(struct hdac_stream *azx_dev,
656 				      unsigned int streams)
657 {
658 	struct hdac_bus *bus = azx_dev->bus;
659 	struct snd_pcm_runtime *runtime = azx_dev->substream->runtime;
660 	struct hdac_stream *s;
661 	bool inited = false;
662 	u64 cycle_last = 0;
663 
664 	list_for_each_entry(s, &bus->stream_list, list) {
665 		if ((streams & (1 << s->index))) {
666 			azx_timecounter_init(s, inited, cycle_last);
667 			if (!inited) {
668 				inited = true;
669 				cycle_last = s->tc.cycle_last;
670 			}
671 		}
672 	}
673 
674 	snd_pcm_gettime(runtime, &runtime->trigger_tstamp);
675 	runtime->trigger_tstamp_latched = true;
676 }
677 EXPORT_SYMBOL_GPL(snd_hdac_stream_timecounter_init);
678 
679 /**
680  * snd_hdac_stream_sync_trigger - turn on/off stream sync register
681  * @azx_dev: HD-audio core stream (master stream)
682  * @set: true = set, false = clear
683  * @streams: bit flags of streams to sync
684  * @reg: the stream sync register address
685  */
snd_hdac_stream_sync_trigger(struct hdac_stream * azx_dev,bool set,unsigned int streams,unsigned int reg)686 void snd_hdac_stream_sync_trigger(struct hdac_stream *azx_dev, bool set,
687 				  unsigned int streams, unsigned int reg)
688 {
689 	struct hdac_bus *bus = azx_dev->bus;
690 	unsigned int val;
691 
692 	if (!reg)
693 		reg = AZX_REG_SSYNC;
694 	val = _snd_hdac_chip_readl(bus, reg);
695 	if (set)
696 		val |= streams;
697 	else
698 		val &= ~streams;
699 	_snd_hdac_chip_writel(bus, reg, val);
700 }
701 EXPORT_SYMBOL_GPL(snd_hdac_stream_sync_trigger);
702 
703 /**
704  * snd_hdac_stream_sync - sync with start/stop trigger operation
705  * @azx_dev: HD-audio core stream (master stream)
706  * @start: true = start, false = stop
707  * @streams: bit flags of streams to sync
708  *
709  * For @start = true, wait until all FIFOs get ready.
710  * For @start = false, wait until all RUN bits are cleared.
711  */
snd_hdac_stream_sync(struct hdac_stream * azx_dev,bool start,unsigned int streams)712 void snd_hdac_stream_sync(struct hdac_stream *azx_dev, bool start,
713 			  unsigned int streams)
714 {
715 	struct hdac_bus *bus = azx_dev->bus;
716 	int nwait, timeout;
717 	struct hdac_stream *s;
718 
719 	for (timeout = 5000; timeout; timeout--) {
720 		nwait = 0;
721 		list_for_each_entry(s, &bus->stream_list, list) {
722 			if (!(streams & (1 << s->index)))
723 				continue;
724 
725 			if (start) {
726 				/* check FIFO gets ready */
727 				if (!(snd_hdac_stream_readb(s, SD_STS) &
728 				      SD_STS_FIFO_READY))
729 					nwait++;
730 			} else {
731 				/* check RUN bit is cleared */
732 				if (snd_hdac_stream_readb(s, SD_CTL) &
733 				    SD_CTL_DMA_START) {
734 					nwait++;
735 					/*
736 					 * Perform stream reset if DMA RUN
737 					 * bit not cleared within given timeout
738 					 */
739 					if (timeout == 1)
740 						snd_hdac_stream_reset(s);
741 				}
742 			}
743 		}
744 		if (!nwait)
745 			break;
746 		cpu_relax();
747 	}
748 }
749 EXPORT_SYMBOL_GPL(snd_hdac_stream_sync);
750 
751 /**
752  * snd_hdac_stream_spbcap_enable - enable SPIB for a stream
753  * @bus: HD-audio core bus
754  * @enable: flag to enable/disable SPIB
755  * @index: stream index for which SPIB need to be enabled
756  */
snd_hdac_stream_spbcap_enable(struct hdac_bus * bus,bool enable,int index)757 void snd_hdac_stream_spbcap_enable(struct hdac_bus *bus,
758 				   bool enable, int index)
759 {
760 	u32 mask = 0;
761 
762 	if (!bus->spbcap) {
763 		dev_err(bus->dev, "Address of SPB capability is NULL\n");
764 		return;
765 	}
766 
767 	mask |= (1 << index);
768 
769 	if (enable)
770 		snd_hdac_updatel(bus->spbcap, AZX_REG_SPB_SPBFCCTL, mask, mask);
771 	else
772 		snd_hdac_updatel(bus->spbcap, AZX_REG_SPB_SPBFCCTL, mask, 0);
773 }
774 EXPORT_SYMBOL_GPL(snd_hdac_stream_spbcap_enable);
775 
776 /**
777  * snd_hdac_stream_set_spib - sets the spib value of a stream
778  * @bus: HD-audio core bus
779  * @azx_dev: hdac_stream
780  * @value: spib value to set
781  */
snd_hdac_stream_set_spib(struct hdac_bus * bus,struct hdac_stream * azx_dev,u32 value)782 int snd_hdac_stream_set_spib(struct hdac_bus *bus,
783 			     struct hdac_stream *azx_dev, u32 value)
784 {
785 	if (!bus->spbcap) {
786 		dev_err(bus->dev, "Address of SPB capability is NULL\n");
787 		return -EINVAL;
788 	}
789 
790 	writel(value, azx_dev->spib_addr);
791 
792 	return 0;
793 }
794 EXPORT_SYMBOL_GPL(snd_hdac_stream_set_spib);
795 
796 /**
797  * snd_hdac_stream_get_spbmaxfifo - gets the spib value of a stream
798  * @bus: HD-audio core bus
799  * @azx_dev: hdac_stream
800  *
801  * Return maxfifo for the stream
802  */
snd_hdac_stream_get_spbmaxfifo(struct hdac_bus * bus,struct hdac_stream * azx_dev)803 int snd_hdac_stream_get_spbmaxfifo(struct hdac_bus *bus,
804 				   struct hdac_stream *azx_dev)
805 {
806 	if (!bus->spbcap) {
807 		dev_err(bus->dev, "Address of SPB capability is NULL\n");
808 		return -EINVAL;
809 	}
810 
811 	return readl(azx_dev->fifo_addr);
812 }
813 EXPORT_SYMBOL_GPL(snd_hdac_stream_get_spbmaxfifo);
814 
815 /**
816  * snd_hdac_stream_drsm_enable - enable DMA resume for a stream
817  * @bus: HD-audio core bus
818  * @enable: flag to enable/disable DRSM
819  * @index: stream index for which DRSM need to be enabled
820  */
snd_hdac_stream_drsm_enable(struct hdac_bus * bus,bool enable,int index)821 void snd_hdac_stream_drsm_enable(struct hdac_bus *bus,
822 				 bool enable, int index)
823 {
824 	u32 mask = 0;
825 
826 	if (!bus->drsmcap) {
827 		dev_err(bus->dev, "Address of DRSM capability is NULL\n");
828 		return;
829 	}
830 
831 	mask |= (1 << index);
832 
833 	if (enable)
834 		snd_hdac_updatel(bus->drsmcap, AZX_REG_DRSM_CTL, mask, mask);
835 	else
836 		snd_hdac_updatel(bus->drsmcap, AZX_REG_DRSM_CTL, mask, 0);
837 }
838 EXPORT_SYMBOL_GPL(snd_hdac_stream_drsm_enable);
839 
840 /*
841  * snd_hdac_stream_wait_drsm - wait for HW to clear RSM for a stream
842  * @azx_dev: HD-audio core stream to await RSM for
843  *
844  * Returns 0 on success and -ETIMEDOUT upon a timeout.
845  */
snd_hdac_stream_wait_drsm(struct hdac_stream * azx_dev)846 int snd_hdac_stream_wait_drsm(struct hdac_stream *azx_dev)
847 {
848 	struct hdac_bus *bus = azx_dev->bus;
849 	u32 mask, reg;
850 	int ret;
851 
852 	mask = 1 << azx_dev->index;
853 
854 	ret = read_poll_timeout(snd_hdac_reg_readl, reg, !(reg & mask), 250, 2000, false, bus,
855 				bus->drsmcap + AZX_REG_DRSM_CTL);
856 	if (ret)
857 		dev_dbg(bus->dev, "polling RSM 0x%08x failed: %d\n", mask, ret);
858 	return ret;
859 }
860 EXPORT_SYMBOL_GPL(snd_hdac_stream_wait_drsm);
861 
862 /**
863  * snd_hdac_stream_set_dpibr - sets the dpibr value of a stream
864  * @bus: HD-audio core bus
865  * @azx_dev: hdac_stream
866  * @value: dpib value to set
867  */
snd_hdac_stream_set_dpibr(struct hdac_bus * bus,struct hdac_stream * azx_dev,u32 value)868 int snd_hdac_stream_set_dpibr(struct hdac_bus *bus,
869 			      struct hdac_stream *azx_dev, u32 value)
870 {
871 	if (!bus->drsmcap) {
872 		dev_err(bus->dev, "Address of DRSM capability is NULL\n");
873 		return -EINVAL;
874 	}
875 
876 	writel(value, azx_dev->dpibr_addr);
877 
878 	return 0;
879 }
880 EXPORT_SYMBOL_GPL(snd_hdac_stream_set_dpibr);
881 
882 /**
883  * snd_hdac_stream_set_lpib - sets the lpib value of a stream
884  * @azx_dev: hdac_stream
885  * @value: lpib value to set
886  */
snd_hdac_stream_set_lpib(struct hdac_stream * azx_dev,u32 value)887 int snd_hdac_stream_set_lpib(struct hdac_stream *azx_dev, u32 value)
888 {
889 	snd_hdac_stream_writel(azx_dev, SD_LPIB, value);
890 
891 	return 0;
892 }
893 EXPORT_SYMBOL_GPL(snd_hdac_stream_set_lpib);
894 
895 #ifdef CONFIG_SND_HDA_DSP_LOADER
896 /**
897  * snd_hdac_dsp_prepare - prepare for DSP loading
898  * @azx_dev: HD-audio core stream used for DSP loading
899  * @format: HD-audio stream format
900  * @byte_size: data chunk byte size
901  * @bufp: allocated buffer
902  *
903  * Allocate the buffer for the given size and set up the given stream for
904  * DSP loading.  Returns the stream tag (>= 0), or a negative error code.
905  */
snd_hdac_dsp_prepare(struct hdac_stream * azx_dev,unsigned int format,unsigned int byte_size,struct snd_dma_buffer * bufp)906 int snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format,
907 			 unsigned int byte_size, struct snd_dma_buffer *bufp)
908 {
909 	struct hdac_bus *bus = azx_dev->bus;
910 	__le32 *bdl;
911 	int err;
912 
913 	snd_hdac_dsp_lock(azx_dev);
914 	spin_lock_irq(&bus->reg_lock);
915 	if (azx_dev->running || azx_dev->locked) {
916 		spin_unlock_irq(&bus->reg_lock);
917 		err = -EBUSY;
918 		goto unlock;
919 	}
920 	azx_dev->locked = true;
921 	spin_unlock_irq(&bus->reg_lock);
922 
923 	err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG, bus->dev,
924 				  byte_size, bufp);
925 	if (err < 0)
926 		goto err_alloc;
927 
928 	azx_dev->substream = NULL;
929 	azx_dev->bufsize = byte_size;
930 	azx_dev->period_bytes = byte_size;
931 	azx_dev->format_val = format;
932 
933 	snd_hdac_stream_reset(azx_dev);
934 
935 	/* reset BDL address */
936 	snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
937 	snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
938 
939 	azx_dev->frags = 0;
940 	bdl = (__le32 *)azx_dev->bdl.area;
941 	err = setup_bdle(bus, bufp, azx_dev, &bdl, 0, byte_size, 0);
942 	if (err < 0)
943 		goto error;
944 
945 	snd_hdac_stream_setup(azx_dev);
946 	snd_hdac_dsp_unlock(azx_dev);
947 	return azx_dev->stream_tag;
948 
949  error:
950 	snd_dma_free_pages(bufp);
951  err_alloc:
952 	spin_lock_irq(&bus->reg_lock);
953 	azx_dev->locked = false;
954 	spin_unlock_irq(&bus->reg_lock);
955  unlock:
956 	snd_hdac_dsp_unlock(azx_dev);
957 	return err;
958 }
959 EXPORT_SYMBOL_GPL(snd_hdac_dsp_prepare);
960 
961 /**
962  * snd_hdac_dsp_trigger - start / stop DSP loading
963  * @azx_dev: HD-audio core stream used for DSP loading
964  * @start: trigger start or stop
965  */
snd_hdac_dsp_trigger(struct hdac_stream * azx_dev,bool start)966 void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start)
967 {
968 	if (start)
969 		snd_hdac_stream_start(azx_dev);
970 	else
971 		snd_hdac_stream_stop(azx_dev);
972 }
973 EXPORT_SYMBOL_GPL(snd_hdac_dsp_trigger);
974 
975 /**
976  * snd_hdac_dsp_cleanup - clean up the stream from DSP loading to normal
977  * @azx_dev: HD-audio core stream used for DSP loading
978  * @dmab: buffer used by DSP loading
979  */
snd_hdac_dsp_cleanup(struct hdac_stream * azx_dev,struct snd_dma_buffer * dmab)980 void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev,
981 			  struct snd_dma_buffer *dmab)
982 {
983 	struct hdac_bus *bus = azx_dev->bus;
984 
985 	if (!dmab->area || !azx_dev->locked)
986 		return;
987 
988 	snd_hdac_dsp_lock(azx_dev);
989 	/* reset BDL address */
990 	snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
991 	snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
992 	snd_hdac_stream_writel(azx_dev, SD_CTL, 0);
993 	azx_dev->bufsize = 0;
994 	azx_dev->period_bytes = 0;
995 	azx_dev->format_val = 0;
996 
997 	snd_dma_free_pages(dmab);
998 	dmab->area = NULL;
999 
1000 	spin_lock_irq(&bus->reg_lock);
1001 	azx_dev->locked = false;
1002 	spin_unlock_irq(&bus->reg_lock);
1003 	snd_hdac_dsp_unlock(azx_dev);
1004 }
1005 EXPORT_SYMBOL_GPL(snd_hdac_dsp_cleanup);
1006 #endif /* CONFIG_SND_HDA_DSP_LOADER */
1007