1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Based on 5.2.0, Family Programming Guide (Sept 30, 2020) 4 * 5 * Copyright (C) 2021 Integrated Device Technology, Inc., a Renesas Company. 6 */ 7 #ifndef HAVE_IDT8A340_REG 8 #define HAVE_IDT8A340_REG 9 10 #define PAGE_ADDR_BASE 0x0000 11 #define PAGE_ADDR 0x00fc 12 13 #define HW_REVISION 0x8180 14 #define REV_ID 0x007a 15 16 #define HW_DPLL_0 (0x8a00) 17 #define HW_DPLL_1 (0x8b00) 18 #define HW_DPLL_2 (0x8c00) 19 #define HW_DPLL_3 (0x8d00) 20 #define HW_DPLL_4 (0x8e00) 21 #define HW_DPLL_5 (0x8f00) 22 #define HW_DPLL_6 (0x9000) 23 #define HW_DPLL_7 (0x9100) 24 25 #define HW_DPLL_TOD_SW_TRIG_ADDR__0 (0x080) 26 #define HW_DPLL_TOD_CTRL_1 (0x089) 27 #define HW_DPLL_TOD_CTRL_2 (0x08A) 28 #define HW_DPLL_TOD_OVR__0 (0x098) 29 #define HW_DPLL_TOD_OUT_0__0 (0x0B0) 30 31 #define HW_Q0_Q1_CH_SYNC_CTRL_0 (0xa740) 32 #define HW_Q0_Q1_CH_SYNC_CTRL_1 (0xa741) 33 #define HW_Q2_Q3_CH_SYNC_CTRL_0 (0xa742) 34 #define HW_Q2_Q3_CH_SYNC_CTRL_1 (0xa743) 35 #define HW_Q4_Q5_CH_SYNC_CTRL_0 (0xa744) 36 #define HW_Q4_Q5_CH_SYNC_CTRL_1 (0xa745) 37 #define HW_Q6_Q7_CH_SYNC_CTRL_0 (0xa746) 38 #define HW_Q6_Q7_CH_SYNC_CTRL_1 (0xa747) 39 #define HW_Q8_CH_SYNC_CTRL_0 (0xa748) 40 #define HW_Q8_CH_SYNC_CTRL_1 (0xa749) 41 #define HW_Q9_CH_SYNC_CTRL_0 (0xa74a) 42 #define HW_Q9_CH_SYNC_CTRL_1 (0xa74b) 43 #define HW_Q10_CH_SYNC_CTRL_0 (0xa74c) 44 #define HW_Q10_CH_SYNC_CTRL_1 (0xa74d) 45 #define HW_Q11_CH_SYNC_CTRL_0 (0xa74e) 46 #define HW_Q11_CH_SYNC_CTRL_1 (0xa74f) 47 48 #define SYNC_SOURCE_DPLL0_TOD_PPS 0x14 49 #define SYNC_SOURCE_DPLL1_TOD_PPS 0x15 50 #define SYNC_SOURCE_DPLL2_TOD_PPS 0x16 51 #define SYNC_SOURCE_DPLL3_TOD_PPS 0x17 52 53 #define SYNCTRL1_MASTER_SYNC_RST BIT(7) 54 #define SYNCTRL1_MASTER_SYNC_TRIG BIT(5) 55 #define SYNCTRL1_TOD_SYNC_TRIG BIT(4) 56 #define SYNCTRL1_FBDIV_FRAME_SYNC_TRIG BIT(3) 57 #define SYNCTRL1_FBDIV_SYNC_TRIG BIT(2) 58 #define SYNCTRL1_Q1_DIV_SYNC_TRIG BIT(1) 59 #define SYNCTRL1_Q0_DIV_SYNC_TRIG BIT(0) 60 61 #define HW_Q8_CTRL_SPARE (0xa7d4) 62 #define HW_Q11_CTRL_SPARE (0xa7ec) 63 64 /** 65 * Select FOD5 as sync_trigger for Q8 divider. 66 * Transition from logic zero to one 67 * sets trigger to sync Q8 divider. 68 * 69 * Unused when FOD4 is driving Q8 divider (normal operation). 70 */ 71 #define Q9_TO_Q8_SYNC_TRIG BIT(1) 72 73 /** 74 * Enable FOD5 as driver for clock and sync for Q8 divider. 75 * Enable fanout buffer for FOD5. 76 * 77 * Unused when FOD4 is driving Q8 divider (normal operation). 78 */ 79 #define Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK (BIT(0) | BIT(2)) 80 81 /** 82 * Select FOD6 as sync_trigger for Q11 divider. 83 * Transition from logic zero to one 84 * sets trigger to sync Q11 divider. 85 * 86 * Unused when FOD7 is driving Q11 divider (normal operation). 87 */ 88 #define Q10_TO_Q11_SYNC_TRIG BIT(1) 89 90 /** 91 * Enable FOD6 as driver for clock and sync for Q11 divider. 92 * Enable fanout buffer for FOD6. 93 * 94 * Unused when FOD7 is driving Q11 divider (normal operation). 95 */ 96 #define Q10_TO_Q11_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK (BIT(0) | BIT(2)) 97 98 #define RESET_CTRL 0xc000 99 #define SM_RESET 0x0012 100 #define SM_RESET_V520 0x0013 101 #define SM_RESET_CMD 0x5A 102 103 #define GENERAL_STATUS 0xc014 104 #define BOOT_STATUS 0x0000 105 #define HW_REV_ID 0x000A 106 #define BOND_ID 0x000B 107 #define HW_CSR_ID 0x000C 108 #define HW_IRQ_ID 0x000E 109 #define MAJ_REL 0x0010 110 #define MIN_REL 0x0011 111 #define HOTFIX_REL 0x0012 112 #define PIPELINE_ID 0x0014 113 #define BUILD_ID 0x0018 114 #define JTAG_DEVICE_ID 0x001c 115 #define PRODUCT_ID 0x001e 116 #define OTP_SCSR_CONFIG_SELECT 0x0022 117 118 #define STATUS 0xc03c 119 #define DPLL0_STATUS 0x0018 120 #define DPLL1_STATUS 0x0019 121 #define DPLL2_STATUS 0x001a 122 #define DPLL3_STATUS 0x001b 123 #define DPLL4_STATUS 0x001c 124 #define DPLL5_STATUS 0x001d 125 #define DPLL6_STATUS 0x001e 126 #define DPLL7_STATUS 0x001f 127 #define DPLL_SYS_STATUS 0x0020 128 #define DPLL_SYS_APLL_STATUS 0x0021 129 #define DPLL0_FILTER_STATUS 0x0044 130 #define DPLL1_FILTER_STATUS 0x004c 131 #define DPLL2_FILTER_STATUS 0x0054 132 #define DPLL3_FILTER_STATUS 0x005c 133 #define DPLL4_FILTER_STATUS 0x0064 134 #define DPLL5_FILTER_STATUS 0x006c 135 #define DPLL6_FILTER_STATUS 0x0074 136 #define DPLL7_FILTER_STATUS 0x007c 137 #define DPLLSYS_FILTER_STATUS 0x0084 138 #define USER_GPIO0_TO_7_STATUS 0x008a 139 #define USER_GPIO8_TO_15_STATUS 0x008b 140 141 #define GPIO_USER_CONTROL 0xc160 142 #define GPIO0_TO_7_OUT 0x0000 143 #define GPIO8_TO_15_OUT 0x0001 144 #define GPIO0_TO_7_OUT_V520 0x0002 145 #define GPIO8_TO_15_OUT_V520 0x0003 146 147 #define STICKY_STATUS_CLEAR 0xc164 148 149 #define GPIO_TOD_NOTIFICATION_CLEAR 0xc16c 150 151 #define ALERT_CFG 0xc188 152 153 #define SYS_DPLL_XO 0xc194 154 155 #define SYS_APLL 0xc19c 156 157 #define INPUT_0 0xc1b0 158 #define INPUT_1 0xc1c0 159 #define INPUT_2 0xc1d0 160 #define INPUT_3 0xc200 161 #define INPUT_4 0xc210 162 #define INPUT_5 0xc220 163 #define INPUT_6 0xc230 164 #define INPUT_7 0xc240 165 #define INPUT_8 0xc250 166 #define INPUT_9 0xc260 167 #define INPUT_10 0xc280 168 #define INPUT_11 0xc290 169 #define INPUT_12 0xc2a0 170 #define INPUT_13 0xc2b0 171 #define INPUT_14 0xc2c0 172 #define INPUT_15 0xc2d0 173 174 #define REF_MON_0 0xc2e0 175 #define REF_MON_1 0xc2ec 176 #define REF_MON_2 0xc300 177 #define REF_MON_3 0xc30c 178 #define REF_MON_4 0xc318 179 #define REF_MON_5 0xc324 180 #define REF_MON_6 0xc330 181 #define REF_MON_7 0xc33c 182 #define REF_MON_8 0xc348 183 #define REF_MON_9 0xc354 184 #define REF_MON_10 0xc360 185 #define REF_MON_11 0xc36c 186 #define REF_MON_12 0xc380 187 #define REF_MON_13 0xc38c 188 #define REF_MON_14 0xc398 189 #define REF_MON_15 0xc3a4 190 191 #define DPLL_0 0xc3b0 192 #define DPLL_CTRL_REG_0 0x0002 193 #define DPLL_CTRL_REG_1 0x0003 194 #define DPLL_CTRL_REG_2 0x0004 195 #define DPLL_TOD_SYNC_CFG 0x0031 196 #define DPLL_COMBO_SLAVE_CFG_0 0x0032 197 #define DPLL_COMBO_SLAVE_CFG_1 0x0033 198 #define DPLL_SLAVE_REF_CFG 0x0034 199 #define DPLL_REF_MODE 0x0035 200 #define DPLL_PHASE_MEASUREMENT_CFG 0x0036 201 #define DPLL_MODE 0x0037 202 #define DPLL_MODE_V520 0x003B 203 #define DPLL_1 0xc400 204 #define DPLL_2 0xc438 205 #define DPLL_2_V520 0xc43c 206 #define DPLL_3 0xc480 207 #define DPLL_4 0xc4b8 208 #define DPLL_4_V520 0xc4bc 209 #define DPLL_5 0xc500 210 #define DPLL_6 0xc538 211 #define DPLL_6_V520 0xc53c 212 #define DPLL_7 0xc580 213 #define SYS_DPLL 0xc5b8 214 #define SYS_DPLL_V520 0xc5bc 215 216 #define DPLL_CTRL_0 0xc600 217 #define DPLL_CTRL_DPLL_MANU_REF_CFG 0x0001 218 #define DPLL_CTRL_DPLL_FOD_FREQ 0x001c 219 #define DPLL_CTRL_COMBO_MASTER_CFG 0x003a 220 #define DPLL_CTRL_1 0xc63c 221 #define DPLL_CTRL_2 0xc680 222 #define DPLL_CTRL_3 0xc6bc 223 #define DPLL_CTRL_4 0xc700 224 #define DPLL_CTRL_5 0xc73c 225 #define DPLL_CTRL_6 0xc780 226 #define DPLL_CTRL_7 0xc7bc 227 #define SYS_DPLL_CTRL 0xc800 228 229 #define DPLL_PHASE_0 0xc818 230 /* Signed 42-bit FFO in units of 2^(-53) */ 231 #define DPLL_WR_PHASE 0x0000 232 #define DPLL_PHASE_1 0xc81c 233 #define DPLL_PHASE_2 0xc820 234 #define DPLL_PHASE_3 0xc824 235 #define DPLL_PHASE_4 0xc828 236 #define DPLL_PHASE_5 0xc82c 237 #define DPLL_PHASE_6 0xc830 238 #define DPLL_PHASE_7 0xc834 239 240 #define DPLL_FREQ_0 0xc838 241 /* Signed 42-bit FFO in units of 2^(-53) */ 242 #define DPLL_WR_FREQ 0x0000 243 #define DPLL_FREQ_1 0xc840 244 #define DPLL_FREQ_2 0xc848 245 #define DPLL_FREQ_3 0xc850 246 #define DPLL_FREQ_4 0xc858 247 #define DPLL_FREQ_5 0xc860 248 #define DPLL_FREQ_6 0xc868 249 #define DPLL_FREQ_7 0xc870 250 251 #define DPLL_PHASE_PULL_IN_0 0xc880 252 #define PULL_IN_OFFSET 0x0000 /* Signed 32 bit */ 253 #define PULL_IN_SLOPE_LIMIT 0x0004 /* Unsigned 24 bit */ 254 #define PULL_IN_CTRL 0x0007 255 #define DPLL_PHASE_PULL_IN_1 0xc888 256 #define DPLL_PHASE_PULL_IN_2 0xc890 257 #define DPLL_PHASE_PULL_IN_3 0xc898 258 #define DPLL_PHASE_PULL_IN_4 0xc8a0 259 #define DPLL_PHASE_PULL_IN_5 0xc8a8 260 #define DPLL_PHASE_PULL_IN_6 0xc8b0 261 #define DPLL_PHASE_PULL_IN_7 0xc8b8 262 263 #define GPIO_CFG 0xc8c0 264 #define GPIO_CFG_GBL 0x0000 265 #define GPIO_0 0xc8c2 266 #define GPIO_DCO_INC_DEC 0x0000 267 #define GPIO_OUT_CTRL_0 0x0001 268 #define GPIO_OUT_CTRL_1 0x0002 269 #define GPIO_TOD_TRIG 0x0003 270 #define GPIO_DPLL_INDICATOR 0x0004 271 #define GPIO_LOS_INDICATOR 0x0005 272 #define GPIO_REF_INPUT_DSQ_0 0x0006 273 #define GPIO_REF_INPUT_DSQ_1 0x0007 274 #define GPIO_REF_INPUT_DSQ_2 0x0008 275 #define GPIO_REF_INPUT_DSQ_3 0x0009 276 #define GPIO_MAN_CLK_SEL_0 0x000a 277 #define GPIO_MAN_CLK_SEL_1 0x000b 278 #define GPIO_MAN_CLK_SEL_2 0x000c 279 #define GPIO_SLAVE 0x000d 280 #define GPIO_ALERT_OUT_CFG 0x000e 281 #define GPIO_TOD_NOTIFICATION_CFG 0x000f 282 #define GPIO_CTRL 0x0010 283 #define GPIO_CTRL_V520 0x0011 284 #define GPIO_1 0xc8d4 285 #define GPIO_2 0xc8e6 286 #define GPIO_3 0xc900 287 #define GPIO_4 0xc912 288 #define GPIO_5 0xc924 289 #define GPIO_6 0xc936 290 #define GPIO_7 0xc948 291 #define GPIO_8 0xc95a 292 #define GPIO_9 0xc980 293 #define GPIO_10 0xc992 294 #define GPIO_11 0xc9a4 295 #define GPIO_12 0xc9b6 296 #define GPIO_13 0xc9c8 297 #define GPIO_14 0xc9da 298 #define GPIO_15 0xca00 299 300 #define OUT_DIV_MUX 0xca12 301 #define OUTPUT_0 0xca14 302 #define OUTPUT_0_V520 0xca20 303 /* FOD frequency output divider value */ 304 #define OUT_DIV 0x0000 305 #define OUT_DUTY_CYCLE_HIGH 0x0004 306 #define OUT_CTRL_0 0x0008 307 #define OUT_CTRL_1 0x0009 308 /* Phase adjustment in FOD cycles */ 309 #define OUT_PHASE_ADJ 0x000c 310 #define OUTPUT_1 0xca24 311 #define OUTPUT_1_V520 0xca30 312 #define OUTPUT_2 0xca34 313 #define OUTPUT_2_V520 0xca40 314 #define OUTPUT_3 0xca44 315 #define OUTPUT_3_V520 0xca50 316 #define OUTPUT_4 0xca54 317 #define OUTPUT_4_V520 0xca60 318 #define OUTPUT_5 0xca64 319 #define OUTPUT_5_V520 0xca80 320 #define OUTPUT_6 0xca80 321 #define OUTPUT_6_V520 0xca90 322 #define OUTPUT_7 0xca90 323 #define OUTPUT_7_V520 0xcaa0 324 #define OUTPUT_8 0xcaa0 325 #define OUTPUT_8_V520 0xcab0 326 #define OUTPUT_9 0xcab0 327 #define OUTPUT_9_V520 0xcac0 328 #define OUTPUT_10 0xcac0 329 #define OUTPUT_10_V520 0xcad0 330 #define OUTPUT_11 0xcad0 331 #define OUTPUT_11_V520 0xcae0 332 333 #define SERIAL 0xcae0 334 #define SERIAL_V520 0xcaf0 335 336 #define PWM_ENCODER_0 0xcb00 337 #define PWM_ENCODER_1 0xcb08 338 #define PWM_ENCODER_2 0xcb10 339 #define PWM_ENCODER_3 0xcb18 340 #define PWM_ENCODER_4 0xcb20 341 #define PWM_ENCODER_5 0xcb28 342 #define PWM_ENCODER_6 0xcb30 343 #define PWM_ENCODER_7 0xcb38 344 #define PWM_DECODER_0 0xcb40 345 #define PWM_DECODER_1 0xcb48 346 #define PWM_DECODER_1_V520 0xcb4a 347 #define PWM_DECODER_2 0xcb50 348 #define PWM_DECODER_2_V520 0xcb54 349 #define PWM_DECODER_3 0xcb58 350 #define PWM_DECODER_3_V520 0xcb5e 351 #define PWM_DECODER_4 0xcb60 352 #define PWM_DECODER_4_V520 0xcb68 353 #define PWM_DECODER_5 0xcb68 354 #define PWM_DECODER_5_V520 0xcb80 355 #define PWM_DECODER_6 0xcb70 356 #define PWM_DECODER_6_V520 0xcb8a 357 #define PWM_DECODER_7 0xcb80 358 #define PWM_DECODER_7_V520 0xcb94 359 #define PWM_DECODER_8 0xcb88 360 #define PWM_DECODER_8_V520 0xcb9e 361 #define PWM_DECODER_9 0xcb90 362 #define PWM_DECODER_9_V520 0xcba8 363 #define PWM_DECODER_10 0xcb98 364 #define PWM_DECODER_10_V520 0xcbb2 365 #define PWM_DECODER_11 0xcba0 366 #define PWM_DECODER_11_V520 0xcbbc 367 #define PWM_DECODER_12 0xcba8 368 #define PWM_DECODER_12_V520 0xcbc6 369 #define PWM_DECODER_13 0xcbb0 370 #define PWM_DECODER_13_V520 0xcbd0 371 #define PWM_DECODER_14 0xcbb8 372 #define PWM_DECODER_14_V520 0xcbda 373 #define PWM_DECODER_15 0xcbc0 374 #define PWM_DECODER_15_V520 0xcbe4 375 #define PWM_USER_DATA 0xcbc8 376 #define PWM_USER_DATA_V520 0xcbf0 377 378 #define TOD_0 0xcbcc 379 #define TOD_0_V520 0xcc00 380 /* Enable TOD counter, output channel sync and even-PPS mode */ 381 #define TOD_CFG 0x0000 382 #define TOD_CFG_V520 0x0001 383 #define TOD_1 0xcbce 384 #define TOD_1_V520 0xcc02 385 #define TOD_2 0xcbd0 386 #define TOD_2_V520 0xcc04 387 #define TOD_3 0xcbd2 388 #define TOD_3_V520 0xcc06 389 390 #define TOD_WRITE_0 0xcc00 391 #define TOD_WRITE_0_V520 0xcc10 392 /* 8-bit subns, 32-bit ns, 48-bit seconds */ 393 #define TOD_WRITE 0x0000 394 /* Counter increments after TOD write is completed */ 395 #define TOD_WRITE_COUNTER 0x000c 396 /* TOD write trigger configuration */ 397 #define TOD_WRITE_SELECT_CFG_0 0x000d 398 /* TOD write trigger selection */ 399 #define TOD_WRITE_CMD 0x000f 400 #define TOD_WRITE_1 0xcc10 401 #define TOD_WRITE_1_V520 0xcc20 402 #define TOD_WRITE_2 0xcc20 403 #define TOD_WRITE_2_V520 0xcc30 404 #define TOD_WRITE_3 0xcc30 405 #define TOD_WRITE_3_V520 0xcc40 406 407 #define TOD_READ_PRIMARY_0 0xcc40 408 #define TOD_READ_PRIMARY_0_V520 0xcc50 409 /* 8-bit subns, 32-bit ns, 48-bit seconds */ 410 #define TOD_READ_PRIMARY_BASE 0x0000 411 /* Counter increments after TOD write is completed */ 412 #define TOD_READ_PRIMARY_COUNTER 0x000b 413 /* Read trigger configuration */ 414 #define TOD_READ_PRIMARY_SEL_CFG_0 0x000c 415 /* Read trigger selection */ 416 #define TOD_READ_PRIMARY_CMD 0x000e 417 #define TOD_READ_PRIMARY_CMD_V520 0x000f 418 #define TOD_READ_PRIMARY_1 0xcc50 419 #define TOD_READ_PRIMARY_1_V520 0xcc60 420 #define TOD_READ_PRIMARY_2 0xcc60 421 #define TOD_READ_PRIMARY_2_V520 0xcc80 422 #define TOD_READ_PRIMARY_3 0xcc80 423 #define TOD_READ_PRIMARY_3_V520 0xcc90 424 425 #define TOD_READ_SECONDARY_0 0xcc90 426 #define TOD_READ_SECONDARY_0_V520 0xcca0 427 /* 8-bit subns, 32-bit ns, 48-bit seconds */ 428 #define TOD_READ_SECONDARY_BASE 0x0000 429 /* Counter increments after TOD write is completed */ 430 #define TOD_READ_SECONDARY_COUNTER 0x000b 431 /* Read trigger configuration */ 432 #define TOD_READ_SECONDARY_SEL_CFG_0 0x000c 433 /* Read trigger selection */ 434 #define TOD_READ_SECONDARY_CMD 0x000e 435 #define TOD_READ_SECONDARY_CMD_V520 0x000f 436 437 #define TOD_READ_SECONDARY_1 0xcca0 438 #define TOD_READ_SECONDARY_1_V520 0xccb0 439 #define TOD_READ_SECONDARY_2 0xccb0 440 #define TOD_READ_SECONDARY_2_V520 0xccc0 441 #define TOD_READ_SECONDARY_3 0xccc0 442 #define TOD_READ_SECONDARY_3_V520 0xccd0 443 444 #define OUTPUT_TDC_CFG 0xccd0 445 #define OUTPUT_TDC_CFG_V520 0xcce0 446 #define OUTPUT_TDC_0 0xcd00 447 #define OUTPUT_TDC_1 0xcd08 448 #define OUTPUT_TDC_2 0xcd10 449 #define OUTPUT_TDC_3 0xcd18 450 #define INPUT_TDC 0xcd20 451 452 #define SCRATCH 0xcf50 453 #define SCRATCH_V520 0xcf4c 454 455 #define EEPROM 0xcf68 456 #define EEPROM_V520 0xcf64 457 458 #define OTP 0xcf70 459 460 #define BYTE 0xcf80 461 462 /* Bit definitions for the MAJ_REL register */ 463 #define MAJOR_SHIFT (1) 464 #define MAJOR_MASK (0x7f) 465 #define PR_BUILD BIT(0) 466 467 /* Bit definitions for the USER_GPIO0_TO_7_STATUS register */ 468 #define GPIO0_LEVEL BIT(0) 469 #define GPIO1_LEVEL BIT(1) 470 #define GPIO2_LEVEL BIT(2) 471 #define GPIO3_LEVEL BIT(3) 472 #define GPIO4_LEVEL BIT(4) 473 #define GPIO5_LEVEL BIT(5) 474 #define GPIO6_LEVEL BIT(6) 475 #define GPIO7_LEVEL BIT(7) 476 477 /* Bit definitions for the USER_GPIO8_TO_15_STATUS register */ 478 #define GPIO8_LEVEL BIT(0) 479 #define GPIO9_LEVEL BIT(1) 480 #define GPIO10_LEVEL BIT(2) 481 #define GPIO11_LEVEL BIT(3) 482 #define GPIO12_LEVEL BIT(4) 483 #define GPIO13_LEVEL BIT(5) 484 #define GPIO14_LEVEL BIT(6) 485 #define GPIO15_LEVEL BIT(7) 486 487 /* Bit definitions for the GPIO0_TO_7_OUT register */ 488 #define GPIO0_DRIVE_LEVEL BIT(0) 489 #define GPIO1_DRIVE_LEVEL BIT(1) 490 #define GPIO2_DRIVE_LEVEL BIT(2) 491 #define GPIO3_DRIVE_LEVEL BIT(3) 492 #define GPIO4_DRIVE_LEVEL BIT(4) 493 #define GPIO5_DRIVE_LEVEL BIT(5) 494 #define GPIO6_DRIVE_LEVEL BIT(6) 495 #define GPIO7_DRIVE_LEVEL BIT(7) 496 497 /* Bit definitions for the GPIO8_TO_15_OUT register */ 498 #define GPIO8_DRIVE_LEVEL BIT(0) 499 #define GPIO9_DRIVE_LEVEL BIT(1) 500 #define GPIO10_DRIVE_LEVEL BIT(2) 501 #define GPIO11_DRIVE_LEVEL BIT(3) 502 #define GPIO12_DRIVE_LEVEL BIT(4) 503 #define GPIO13_DRIVE_LEVEL BIT(5) 504 #define GPIO14_DRIVE_LEVEL BIT(6) 505 #define GPIO15_DRIVE_LEVEL BIT(7) 506 507 /* Bit definitions for the DPLL_TOD_SYNC_CFG register */ 508 #define TOD_SYNC_SOURCE_SHIFT (1) 509 #define TOD_SYNC_SOURCE_MASK (0x3) 510 #define TOD_SYNC_EN BIT(0) 511 512 /* Bit definitions for the DPLL_MODE register */ 513 #define WRITE_TIMER_MODE BIT(6) 514 #define PLL_MODE_SHIFT (3) 515 #define PLL_MODE_MASK (0x7) 516 #define STATE_MODE_SHIFT (0) 517 #define STATE_MODE_MASK (0x7) 518 519 /* Bit definitions for the DPLL_MANU_REF_CFG register */ 520 #define MANUAL_REFERENCE_SHIFT (0) 521 #define MANUAL_REFERENCE_MASK (0x1f) 522 523 /* Bit definitions for the GPIO_CFG_GBL register */ 524 #define SUPPLY_MODE_SHIFT (0) 525 #define SUPPLY_MODE_MASK (0x3) 526 527 /* Bit definitions for the GPIO_DCO_INC_DEC register */ 528 #define INCDEC_DPLL_INDEX_SHIFT (0) 529 #define INCDEC_DPLL_INDEX_MASK (0x7) 530 531 /* Bit definitions for the GPIO_OUT_CTRL_0 register */ 532 #define CTRL_OUT_0 BIT(0) 533 #define CTRL_OUT_1 BIT(1) 534 #define CTRL_OUT_2 BIT(2) 535 #define CTRL_OUT_3 BIT(3) 536 #define CTRL_OUT_4 BIT(4) 537 #define CTRL_OUT_5 BIT(5) 538 #define CTRL_OUT_6 BIT(6) 539 #define CTRL_OUT_7 BIT(7) 540 541 /* Bit definitions for the GPIO_OUT_CTRL_1 register */ 542 #define CTRL_OUT_8 BIT(0) 543 #define CTRL_OUT_9 BIT(1) 544 #define CTRL_OUT_10 BIT(2) 545 #define CTRL_OUT_11 BIT(3) 546 #define CTRL_OUT_12 BIT(4) 547 #define CTRL_OUT_13 BIT(5) 548 #define CTRL_OUT_14 BIT(6) 549 #define CTRL_OUT_15 BIT(7) 550 551 /* Bit definitions for the GPIO_TOD_TRIG register */ 552 #define TOD_TRIG_0 BIT(0) 553 #define TOD_TRIG_1 BIT(1) 554 #define TOD_TRIG_2 BIT(2) 555 #define TOD_TRIG_3 BIT(3) 556 557 /* Bit definitions for the GPIO_DPLL_INDICATOR register */ 558 #define IND_DPLL_INDEX_SHIFT (0) 559 #define IND_DPLL_INDEX_MASK (0x7) 560 561 /* Bit definitions for the GPIO_LOS_INDICATOR register */ 562 #define REFMON_INDEX_SHIFT (0) 563 #define REFMON_INDEX_MASK (0xf) 564 /* Active level of LOS indicator, 0=low 1=high */ 565 #define ACTIVE_LEVEL BIT(4) 566 567 /* Bit definitions for the GPIO_REF_INPUT_DSQ_0 register */ 568 #define DSQ_INP_0 BIT(0) 569 #define DSQ_INP_1 BIT(1) 570 #define DSQ_INP_2 BIT(2) 571 #define DSQ_INP_3 BIT(3) 572 #define DSQ_INP_4 BIT(4) 573 #define DSQ_INP_5 BIT(5) 574 #define DSQ_INP_6 BIT(6) 575 #define DSQ_INP_7 BIT(7) 576 577 /* Bit definitions for the GPIO_REF_INPUT_DSQ_1 register */ 578 #define DSQ_INP_8 BIT(0) 579 #define DSQ_INP_9 BIT(1) 580 #define DSQ_INP_10 BIT(2) 581 #define DSQ_INP_11 BIT(3) 582 #define DSQ_INP_12 BIT(4) 583 #define DSQ_INP_13 BIT(5) 584 #define DSQ_INP_14 BIT(6) 585 #define DSQ_INP_15 BIT(7) 586 587 /* Bit definitions for the GPIO_REF_INPUT_DSQ_2 register */ 588 #define DSQ_DPLL_0 BIT(0) 589 #define DSQ_DPLL_1 BIT(1) 590 #define DSQ_DPLL_2 BIT(2) 591 #define DSQ_DPLL_3 BIT(3) 592 #define DSQ_DPLL_4 BIT(4) 593 #define DSQ_DPLL_5 BIT(5) 594 #define DSQ_DPLL_6 BIT(6) 595 #define DSQ_DPLL_7 BIT(7) 596 597 /* Bit definitions for the GPIO_REF_INPUT_DSQ_3 register */ 598 #define DSQ_DPLL_SYS BIT(0) 599 #define GPIO_DSQ_LEVEL BIT(1) 600 601 /* Bit definitions for the GPIO_TOD_NOTIFICATION_CFG register */ 602 #define DPLL_TOD_SHIFT (0) 603 #define DPLL_TOD_MASK (0x3) 604 #define TOD_READ_SECONDARY BIT(2) 605 #define GPIO_ASSERT_LEVEL BIT(3) 606 607 /* Bit definitions for the GPIO_CTRL register */ 608 #define GPIO_FUNCTION_EN BIT(0) 609 #define GPIO_CMOS_OD_MODE BIT(1) 610 #define GPIO_CONTROL_DIR BIT(2) 611 #define GPIO_PU_PD_MODE BIT(3) 612 #define GPIO_FUNCTION_SHIFT (4) 613 #define GPIO_FUNCTION_MASK (0xf) 614 615 /* Bit definitions for the OUT_CTRL_1 register */ 616 #define OUT_SYNC_DISABLE BIT(7) 617 #define SQUELCH_VALUE BIT(6) 618 #define SQUELCH_DISABLE BIT(5) 619 #define PAD_VDDO_SHIFT (2) 620 #define PAD_VDDO_MASK (0x7) 621 #define PAD_CMOSDRV_SHIFT (0) 622 #define PAD_CMOSDRV_MASK (0x3) 623 624 /* Bit definitions for the TOD_CFG register */ 625 #define TOD_EVEN_PPS_MODE BIT(2) 626 #define TOD_OUT_SYNC_ENABLE BIT(1) 627 #define TOD_ENABLE BIT(0) 628 629 /* Bit definitions for the TOD_WRITE_SELECT_CFG_0 register */ 630 #define WR_PWM_DECODER_INDEX_SHIFT (4) 631 #define WR_PWM_DECODER_INDEX_MASK (0xf) 632 #define WR_REF_INDEX_SHIFT (0) 633 #define WR_REF_INDEX_MASK (0xf) 634 635 /* Bit definitions for the TOD_WRITE_CMD register */ 636 #define TOD_WRITE_SELECTION_SHIFT (0) 637 #define TOD_WRITE_SELECTION_MASK (0xf) 638 /* 4.8.7 */ 639 #define TOD_WRITE_TYPE_SHIFT (4) 640 #define TOD_WRITE_TYPE_MASK (0x3) 641 642 /* Bit definitions for the TOD_READ_PRIMARY_SEL_CFG_0 register */ 643 #define RD_PWM_DECODER_INDEX_SHIFT (4) 644 #define RD_PWM_DECODER_INDEX_MASK (0xf) 645 #define RD_REF_INDEX_SHIFT (0) 646 #define RD_REF_INDEX_MASK (0xf) 647 648 /* Bit definitions for the TOD_READ_PRIMARY_CMD register */ 649 #define TOD_READ_TRIGGER_MODE BIT(4) 650 #define TOD_READ_TRIGGER_SHIFT (0) 651 #define TOD_READ_TRIGGER_MASK (0xf) 652 653 /* Bit definitions for the DPLL_CTRL_COMBO_MASTER_CFG register */ 654 #define COMBO_MASTER_HOLD BIT(0) 655 656 /* Bit definitions for DPLL_SYS_STATUS register */ 657 #define DPLL_SYS_STATE_MASK (0xf) 658 659 /* Bit definitions for SYS_APLL_STATUS register */ 660 #define SYS_APLL_LOSS_LOCK_LIVE_MASK BIT(0) 661 #define SYS_APLL_LOSS_LOCK_LIVE_LOCKED 0 662 #define SYS_APLL_LOSS_LOCK_LIVE_UNLOCKED 1 663 664 /* Bit definitions for the DPLL0_STATUS register */ 665 #define DPLL_STATE_MASK (0xf) 666 #define DPLL_STATE_SHIFT (0x0) 667 668 /* Values of DPLL_N.DPLL_MODE.PLL_MODE */ 669 enum pll_mode { 670 PLL_MODE_MIN = 0, 671 PLL_MODE_PLL = PLL_MODE_MIN, 672 PLL_MODE_WRITE_PHASE = 1, 673 PLL_MODE_WRITE_FREQUENCY = 2, 674 PLL_MODE_GPIO_INC_DEC = 3, 675 PLL_MODE_SYNTHESIS = 4, 676 PLL_MODE_PHASE_MEASUREMENT = 5, 677 PLL_MODE_DISABLED = 6, 678 PLL_MODE_MAX = PLL_MODE_DISABLED, 679 }; 680 681 /* Values of DPLL_CTRL_n.DPLL_MANU_REF_CFG.MANUAL_REFERENCE */ 682 enum manual_reference { 683 MANU_REF_MIN = 0, 684 MANU_REF_CLK0 = MANU_REF_MIN, 685 MANU_REF_CLK1, 686 MANU_REF_CLK2, 687 MANU_REF_CLK3, 688 MANU_REF_CLK4, 689 MANU_REF_CLK5, 690 MANU_REF_CLK6, 691 MANU_REF_CLK7, 692 MANU_REF_CLK8, 693 MANU_REF_CLK9, 694 MANU_REF_CLK10, 695 MANU_REF_CLK11, 696 MANU_REF_CLK12, 697 MANU_REF_CLK13, 698 MANU_REF_CLK14, 699 MANU_REF_CLK15, 700 MANU_REF_WRITE_PHASE, 701 MANU_REF_WRITE_FREQUENCY, 702 MANU_REF_XO_DPLL, 703 MANU_REF_MAX = MANU_REF_XO_DPLL, 704 }; 705 706 enum hw_tod_write_trig_sel { 707 HW_TOD_WR_TRIG_SEL_MIN = 0, 708 HW_TOD_WR_TRIG_SEL_MSB = HW_TOD_WR_TRIG_SEL_MIN, 709 HW_TOD_WR_TRIG_SEL_RESERVED = 1, 710 HW_TOD_WR_TRIG_SEL_TOD_PPS = 2, 711 HW_TOD_WR_TRIG_SEL_IRIGB_PPS = 3, 712 HW_TOD_WR_TRIG_SEL_PWM_PPS = 4, 713 HW_TOD_WR_TRIG_SEL_GPIO = 5, 714 HW_TOD_WR_TRIG_SEL_FOD_SYNC = 6, 715 WR_TRIG_SEL_MAX = HW_TOD_WR_TRIG_SEL_FOD_SYNC, 716 }; 717 718 enum scsr_read_trig_sel { 719 /* CANCEL CURRENT TOD READ; MODULE BECOMES IDLE - NO TRIGGER OCCURS */ 720 SCSR_TOD_READ_TRIG_SEL_DISABLE = 0, 721 /* TRIGGER IMMEDIATELY */ 722 SCSR_TOD_READ_TRIG_SEL_IMMEDIATE = 1, 723 /* TRIGGER ON RISING EDGE OF INTERNAL TOD PPS SIGNAL */ 724 SCSR_TOD_READ_TRIG_SEL_TODPPS = 2, 725 /* TRGGER ON RISING EDGE OF SELECTED REFERENCE INPUT */ 726 SCSR_TOD_READ_TRIG_SEL_REFCLK = 3, 727 /* TRIGGER ON RISING EDGE OF SELECTED PWM DECODER 1PPS OUTPUT */ 728 SCSR_TOD_READ_TRIG_SEL_PWMPPS = 4, 729 SCSR_TOD_READ_TRIG_SEL_RESERVED = 5, 730 /* TRIGGER WHEN WRITE FREQUENCY EVENT OCCURS */ 731 SCSR_TOD_READ_TRIG_SEL_WRITEFREQUENCYEVENT = 6, 732 /* TRIGGER ON SELECTED GPIO */ 733 SCSR_TOD_READ_TRIG_SEL_GPIO = 7, 734 SCSR_TOD_READ_TRIG_SEL_MAX = SCSR_TOD_READ_TRIG_SEL_GPIO, 735 }; 736 737 /* Values STATUS.DPLL_SYS_STATUS.DPLL_SYS_STATE */ 738 enum dpll_state { 739 DPLL_STATE_MIN = 0, 740 DPLL_STATE_FREERUN = DPLL_STATE_MIN, 741 DPLL_STATE_LOCKACQ = 1, 742 DPLL_STATE_LOCKREC = 2, 743 DPLL_STATE_LOCKED = 3, 744 DPLL_STATE_HOLDOVER = 4, 745 DPLL_STATE_OPEN_LOOP = 5, 746 DPLL_STATE_MAX = DPLL_STATE_OPEN_LOOP, 747 }; 748 749 /* 4.8.7 only */ 750 enum scsr_tod_write_trig_sel { 751 SCSR_TOD_WR_TRIG_SEL_DISABLE = 0, 752 SCSR_TOD_WR_TRIG_SEL_IMMEDIATE = 1, 753 SCSR_TOD_WR_TRIG_SEL_REFCLK = 2, 754 SCSR_TOD_WR_TRIG_SEL_PWMPPS = 3, 755 SCSR_TOD_WR_TRIG_SEL_TODPPS = 4, 756 SCSR_TOD_WR_TRIG_SEL_SYNCFOD = 5, 757 SCSR_TOD_WR_TRIG_SEL_GPIO = 6, 758 SCSR_TOD_WR_TRIG_SEL_MAX = SCSR_TOD_WR_TRIG_SEL_GPIO, 759 }; 760 761 /* 4.8.7 only */ 762 enum scsr_tod_write_type_sel { 763 SCSR_TOD_WR_TYPE_SEL_ABSOLUTE = 0, 764 SCSR_TOD_WR_TYPE_SEL_DELTA_PLUS = 1, 765 SCSR_TOD_WR_TYPE_SEL_DELTA_MINUS = 2, 766 SCSR_TOD_WR_TYPE_SEL_MAX = SCSR_TOD_WR_TYPE_SEL_DELTA_MINUS, 767 }; 768 #endif 769