1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __LINUX_GPIO_DRIVER_H
3 #define __LINUX_GPIO_DRIVER_H
4 
5 #include <linux/bits.h>
6 #include <linux/irqchip/chained_irq.h>
7 #include <linux/irqdomain.h>
8 #include <linux/irqhandler.h>
9 #include <linux/lockdep.h>
10 #include <linux/pinctrl/pinconf-generic.h>
11 #include <linux/pinctrl/pinctrl.h>
12 #include <linux/property.h>
13 #include <linux/spinlock_types.h>
14 #include <linux/types.h>
15 
16 #ifdef CONFIG_GENERIC_MSI_IRQ
17 #include <asm/msi.h>
18 #endif
19 
20 struct device;
21 struct irq_chip;
22 struct irq_data;
23 struct module;
24 struct of_phandle_args;
25 struct pinctrl_dev;
26 struct seq_file;
27 
28 struct gpio_chip;
29 struct gpio_desc;
30 struct gpio_device;
31 
32 enum gpio_lookup_flags;
33 enum gpiod_flags;
34 
35 union gpio_irq_fwspec {
36 	struct irq_fwspec	fwspec;
37 #ifdef CONFIG_GENERIC_MSI_IRQ
38 	msi_alloc_info_t	msiinfo;
39 #endif
40 };
41 
42 #define GPIO_LINE_DIRECTION_IN	1
43 #define GPIO_LINE_DIRECTION_OUT	0
44 
45 /**
46  * struct gpio_irq_chip - GPIO interrupt controller
47  */
48 struct gpio_irq_chip {
49 	/**
50 	 * @chip:
51 	 *
52 	 * GPIO IRQ chip implementation, provided by GPIO driver.
53 	 */
54 	struct irq_chip *chip;
55 
56 	/**
57 	 * @domain:
58 	 *
59 	 * Interrupt translation domain; responsible for mapping between GPIO
60 	 * hwirq number and Linux IRQ number.
61 	 */
62 	struct irq_domain *domain;
63 
64 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
65 	/**
66 	 * @fwnode:
67 	 *
68 	 * Firmware node corresponding to this gpiochip/irqchip, necessary
69 	 * for hierarchical irqdomain support.
70 	 */
71 	struct fwnode_handle *fwnode;
72 
73 	/**
74 	 * @parent_domain:
75 	 *
76 	 * If non-NULL, will be set as the parent of this GPIO interrupt
77 	 * controller's IRQ domain to establish a hierarchical interrupt
78 	 * domain. The presence of this will activate the hierarchical
79 	 * interrupt support.
80 	 */
81 	struct irq_domain *parent_domain;
82 
83 	/**
84 	 * @child_to_parent_hwirq:
85 	 *
86 	 * This callback translates a child hardware IRQ offset to a parent
87 	 * hardware IRQ offset on a hierarchical interrupt chip. The child
88 	 * hardware IRQs correspond to the GPIO index 0..ngpio-1 (see the
89 	 * ngpio field of struct gpio_chip) and the corresponding parent
90 	 * hardware IRQ and type (such as IRQ_TYPE_*) shall be returned by
91 	 * the driver. The driver can calculate this from an offset or using
92 	 * a lookup table or whatever method is best for this chip. Return
93 	 * 0 on successful translation in the driver.
94 	 *
95 	 * If some ranges of hardware IRQs do not have a corresponding parent
96 	 * HWIRQ, return -EINVAL, but also make sure to fill in @valid_mask and
97 	 * @need_valid_mask to make these GPIO lines unavailable for
98 	 * translation.
99 	 */
100 	int (*child_to_parent_hwirq)(struct gpio_chip *gc,
101 				     unsigned int child_hwirq,
102 				     unsigned int child_type,
103 				     unsigned int *parent_hwirq,
104 				     unsigned int *parent_type);
105 
106 	/**
107 	 * @populate_parent_alloc_arg :
108 	 *
109 	 * This optional callback allocates and populates the specific struct
110 	 * for the parent's IRQ domain. If this is not specified, then
111 	 * &gpiochip_populate_parent_fwspec_twocell will be used. A four-cell
112 	 * variant named &gpiochip_populate_parent_fwspec_fourcell is also
113 	 * available.
114 	 */
115 	int (*populate_parent_alloc_arg)(struct gpio_chip *gc,
116 					 union gpio_irq_fwspec *fwspec,
117 					 unsigned int parent_hwirq,
118 					 unsigned int parent_type);
119 
120 	/**
121 	 * @child_offset_to_irq:
122 	 *
123 	 * This optional callback is used to translate the child's GPIO line
124 	 * offset on the GPIO chip to an IRQ number for the GPIO to_irq()
125 	 * callback. If this is not specified, then a default callback will be
126 	 * provided that returns the line offset.
127 	 */
128 	unsigned int (*child_offset_to_irq)(struct gpio_chip *gc,
129 					    unsigned int pin);
130 
131 	/**
132 	 * @child_irq_domain_ops:
133 	 *
134 	 * The IRQ domain operations that will be used for this GPIO IRQ
135 	 * chip. If no operations are provided, then default callbacks will
136 	 * be populated to setup the IRQ hierarchy. Some drivers need to
137 	 * supply their own translate function.
138 	 */
139 	struct irq_domain_ops child_irq_domain_ops;
140 #endif
141 
142 	/**
143 	 * @handler:
144 	 *
145 	 * The IRQ handler to use (often a predefined IRQ core function) for
146 	 * GPIO IRQs, provided by GPIO driver.
147 	 */
148 	irq_flow_handler_t handler;
149 
150 	/**
151 	 * @default_type:
152 	 *
153 	 * Default IRQ triggering type applied during GPIO driver
154 	 * initialization, provided by GPIO driver.
155 	 */
156 	unsigned int default_type;
157 
158 	/**
159 	 * @lock_key:
160 	 *
161 	 * Per GPIO IRQ chip lockdep class for IRQ lock.
162 	 */
163 	struct lock_class_key *lock_key;
164 
165 	/**
166 	 * @request_key:
167 	 *
168 	 * Per GPIO IRQ chip lockdep class for IRQ request.
169 	 */
170 	struct lock_class_key *request_key;
171 
172 	/**
173 	 * @parent_handler:
174 	 *
175 	 * The interrupt handler for the GPIO chip's parent interrupts, may be
176 	 * NULL if the parent interrupts are nested rather than cascaded.
177 	 */
178 	irq_flow_handler_t parent_handler;
179 
180 	union {
181 		/**
182 		 * @parent_handler_data:
183 		 *
184 		 * If @per_parent_data is false, @parent_handler_data is a
185 		 * single pointer used as the data associated with every
186 		 * parent interrupt.
187 		 */
188 		void *parent_handler_data;
189 
190 		/**
191 		 * @parent_handler_data_array:
192 		 *
193 		 * If @per_parent_data is true, @parent_handler_data_array is
194 		 * an array of @num_parents pointers, and is used to associate
195 		 * different data for each parent. This cannot be NULL if
196 		 * @per_parent_data is true.
197 		 */
198 		void **parent_handler_data_array;
199 	};
200 
201 	/**
202 	 * @num_parents:
203 	 *
204 	 * The number of interrupt parents of a GPIO chip.
205 	 */
206 	unsigned int num_parents;
207 
208 	/**
209 	 * @parents:
210 	 *
211 	 * A list of interrupt parents of a GPIO chip. This is owned by the
212 	 * driver, so the core will only reference this list, not modify it.
213 	 */
214 	unsigned int *parents;
215 
216 	/**
217 	 * @map:
218 	 *
219 	 * A list of interrupt parents for each line of a GPIO chip.
220 	 */
221 	unsigned int *map;
222 
223 	/**
224 	 * @threaded:
225 	 *
226 	 * True if set the interrupt handling uses nested threads.
227 	 */
228 	bool threaded;
229 
230 	/**
231 	 * @per_parent_data:
232 	 *
233 	 * True if parent_handler_data_array describes a @num_parents
234 	 * sized array to be used as parent data.
235 	 */
236 	bool per_parent_data;
237 
238 	/**
239 	 * @initialized:
240 	 *
241 	 * Flag to track GPIO chip irq member's initialization.
242 	 * This flag will make sure GPIO chip irq members are not used
243 	 * before they are initialized.
244 	 */
245 	bool initialized;
246 
247 	/**
248 	 * @domain_is_allocated_externally:
249 	 *
250 	 * True it the irq_domain was allocated outside of gpiolib, in which
251 	 * case gpiolib won't free the irq_domain itself.
252 	 */
253 	bool domain_is_allocated_externally;
254 
255 	/**
256 	 * @init_hw: optional routine to initialize hardware before
257 	 * an IRQ chip will be added. This is quite useful when
258 	 * a particular driver wants to clear IRQ related registers
259 	 * in order to avoid undesired events.
260 	 */
261 	int (*init_hw)(struct gpio_chip *gc);
262 
263 	/**
264 	 * @init_valid_mask: optional routine to initialize @valid_mask, to be
265 	 * used if not all GPIO lines are valid interrupts. Sometimes some
266 	 * lines just cannot fire interrupts, and this routine, when defined,
267 	 * is passed a bitmap in "valid_mask" and it will have ngpios
268 	 * bits from 0..(ngpios-1) set to "1" as in valid. The callback can
269 	 * then directly set some bits to "0" if they cannot be used for
270 	 * interrupts.
271 	 */
272 	void (*init_valid_mask)(struct gpio_chip *gc,
273 				unsigned long *valid_mask,
274 				unsigned int ngpios);
275 
276 	/**
277 	 * @valid_mask:
278 	 *
279 	 * If not %NULL, holds bitmask of GPIOs which are valid to be included
280 	 * in IRQ domain of the chip.
281 	 */
282 	unsigned long *valid_mask;
283 
284 	/**
285 	 * @first:
286 	 *
287 	 * Required for static IRQ allocation. If set, irq_domain_add_simple()
288 	 * will allocate and map all IRQs during initialization.
289 	 */
290 	unsigned int first;
291 
292 	/**
293 	 * @irq_enable:
294 	 *
295 	 * Store old irq_chip irq_enable callback
296 	 */
297 	void		(*irq_enable)(struct irq_data *data);
298 
299 	/**
300 	 * @irq_disable:
301 	 *
302 	 * Store old irq_chip irq_disable callback
303 	 */
304 	void		(*irq_disable)(struct irq_data *data);
305 	/**
306 	 * @irq_unmask:
307 	 *
308 	 * Store old irq_chip irq_unmask callback
309 	 */
310 	void		(*irq_unmask)(struct irq_data *data);
311 
312 	/**
313 	 * @irq_mask:
314 	 *
315 	 * Store old irq_chip irq_mask callback
316 	 */
317 	void		(*irq_mask)(struct irq_data *data);
318 };
319 
320 /**
321  * struct gpio_chip - abstract a GPIO controller
322  * @label: a functional name for the GPIO device, such as a part
323  *	number or the name of the SoC IP-block implementing it.
324  * @gpiodev: the internal state holder, opaque struct
325  * @parent: optional parent device providing the GPIOs
326  * @fwnode: optional fwnode providing this controller's properties
327  * @owner: helps prevent removal of modules exporting active GPIOs
328  * @request: optional hook for chip-specific activation, such as
329  *	enabling module power and clock; may sleep
330  * @free: optional hook for chip-specific deactivation, such as
331  *	disabling module power and clock; may sleep
332  * @get_direction: returns direction for signal "offset", 0=out, 1=in,
333  *	(same as GPIO_LINE_DIRECTION_OUT / GPIO_LINE_DIRECTION_IN),
334  *	or negative error. It is recommended to always implement this
335  *	function, even on input-only or output-only gpio chips.
336  * @direction_input: configures signal "offset" as input, or returns error
337  *	This can be omitted on input-only or output-only gpio chips.
338  * @direction_output: configures signal "offset" as output, or returns error
339  *	This can be omitted on input-only or output-only gpio chips.
340  * @get: returns value for signal "offset", 0=low, 1=high, or negative error
341  * @get_multiple: reads values for multiple signals defined by "mask" and
342  *	stores them in "bits", returns 0 on success or negative error
343  * @set: assigns output value for signal "offset"
344  * @set_multiple: assigns output values for multiple signals defined by "mask"
345  * @set_config: optional hook for all kinds of settings. Uses the same
346  *	packed config format as generic pinconf.
347  * @to_irq: optional hook supporting non-static gpiod_to_irq() mappings;
348  *	implementation may not sleep
349  * @dbg_show: optional routine to show contents in debugfs; default code
350  *	will be used when this is omitted, but custom code can show extra
351  *	state (such as pullup/pulldown configuration).
352  * @init_valid_mask: optional routine to initialize @valid_mask, to be used if
353  *	not all GPIOs are valid.
354  * @add_pin_ranges: optional routine to initialize pin ranges, to be used when
355  *	requires special mapping of the pins that provides GPIO functionality.
356  *	It is called after adding GPIO chip and before adding IRQ chip.
357  * @en_hw_timestamp: Dependent on GPIO chip, an optional routine to
358  *	enable hardware timestamp.
359  * @dis_hw_timestamp: Dependent on GPIO chip, an optional routine to
360  *	disable hardware timestamp.
361  * @base: identifies the first GPIO number handled by this chip;
362  *	or, if negative during registration, requests dynamic ID allocation.
363  *	DEPRECATION: providing anything non-negative and nailing the base
364  *	offset of GPIO chips is deprecated. Please pass -1 as base to
365  *	let gpiolib select the chip base in all possible cases. We want to
366  *	get rid of the static GPIO number space in the long run.
367  * @ngpio: the number of GPIOs handled by this controller; the last GPIO
368  *	handled is (base + ngpio - 1).
369  * @offset: when multiple gpio chips belong to the same device this
370  *	can be used as offset within the device so friendly names can
371  *	be properly assigned.
372  * @names: if set, must be an array of strings to use as alternative
373  *      names for the GPIOs in this chip. Any entry in the array
374  *      may be NULL if there is no alias for the GPIO, however the
375  *      array must be @ngpio entries long.  A name can include a single printk
376  *      format specifier for an unsigned int.  It is substituted by the actual
377  *      number of the gpio.
378  * @can_sleep: flag must be set iff get()/set() methods sleep, as they
379  *	must while accessing GPIO expander chips over I2C or SPI. This
380  *	implies that if the chip supports IRQs, these IRQs need to be threaded
381  *	as the chip access may sleep when e.g. reading out the IRQ status
382  *	registers.
383  * @read_reg: reader function for generic GPIO
384  * @write_reg: writer function for generic GPIO
385  * @be_bits: if the generic GPIO has big endian bit order (bit 31 is representing
386  *	line 0, bit 30 is line 1 ... bit 0 is line 31) this is set to true by the
387  *	generic GPIO core. It is for internal housekeeping only.
388  * @reg_dat: data (in) register for generic GPIO
389  * @reg_set: output set register (out=high) for generic GPIO
390  * @reg_clr: output clear register (out=low) for generic GPIO
391  * @reg_dir_out: direction out setting register for generic GPIO
392  * @reg_dir_in: direction in setting register for generic GPIO
393  * @bgpio_dir_unreadable: indicates that the direction register(s) cannot
394  *	be read and we need to rely on out internal state tracking.
395  * @bgpio_bits: number of register bits used for a generic GPIO i.e.
396  *	<register width> * 8
397  * @bgpio_lock: used to lock chip->bgpio_data. Also, this is needed to keep
398  *	shadowed and real data registers writes together.
399  * @bgpio_data:	shadowed data register for generic GPIO to clear/set bits
400  *	safely.
401  * @bgpio_dir: shadowed direction register for generic GPIO to clear/set
402  *	direction safely. A "1" in this word means the line is set as
403  *	output.
404  *
405  * A gpio_chip can help platforms abstract various sources of GPIOs so
406  * they can all be accessed through a common programming interface.
407  * Example sources would be SOC controllers, FPGAs, multifunction
408  * chips, dedicated GPIO expanders, and so on.
409  *
410  * Each chip controls a number of signals, identified in method calls
411  * by "offset" values in the range 0..(@ngpio - 1).  When those signals
412  * are referenced through calls like gpio_get_value(gpio), the offset
413  * is calculated by subtracting @base from the gpio number.
414  */
415 struct gpio_chip {
416 	const char		*label;
417 	struct gpio_device	*gpiodev;
418 	struct device		*parent;
419 	struct fwnode_handle	*fwnode;
420 	struct module		*owner;
421 
422 	int			(*request)(struct gpio_chip *gc,
423 						unsigned int offset);
424 	void			(*free)(struct gpio_chip *gc,
425 						unsigned int offset);
426 	int			(*get_direction)(struct gpio_chip *gc,
427 						unsigned int offset);
428 	int			(*direction_input)(struct gpio_chip *gc,
429 						unsigned int offset);
430 	int			(*direction_output)(struct gpio_chip *gc,
431 						unsigned int offset, int value);
432 	int			(*get)(struct gpio_chip *gc,
433 						unsigned int offset);
434 	int			(*get_multiple)(struct gpio_chip *gc,
435 						unsigned long *mask,
436 						unsigned long *bits);
437 	void			(*set)(struct gpio_chip *gc,
438 						unsigned int offset, int value);
439 	void			(*set_multiple)(struct gpio_chip *gc,
440 						unsigned long *mask,
441 						unsigned long *bits);
442 	int			(*set_config)(struct gpio_chip *gc,
443 					      unsigned int offset,
444 					      unsigned long config);
445 	int			(*to_irq)(struct gpio_chip *gc,
446 						unsigned int offset);
447 
448 	void			(*dbg_show)(struct seq_file *s,
449 						struct gpio_chip *gc);
450 
451 	int			(*init_valid_mask)(struct gpio_chip *gc,
452 						   unsigned long *valid_mask,
453 						   unsigned int ngpios);
454 
455 	int			(*add_pin_ranges)(struct gpio_chip *gc);
456 
457 	int			(*en_hw_timestamp)(struct gpio_chip *gc,
458 						   u32 offset,
459 						   unsigned long flags);
460 	int			(*dis_hw_timestamp)(struct gpio_chip *gc,
461 						    u32 offset,
462 						    unsigned long flags);
463 	int			base;
464 	u16			ngpio;
465 	u16			offset;
466 	const char		*const *names;
467 	bool			can_sleep;
468 
469 #if IS_ENABLED(CONFIG_GPIO_GENERIC)
470 	unsigned long (*read_reg)(void __iomem *reg);
471 	void (*write_reg)(void __iomem *reg, unsigned long data);
472 	bool be_bits;
473 	void __iomem *reg_dat;
474 	void __iomem *reg_set;
475 	void __iomem *reg_clr;
476 	void __iomem *reg_dir_out;
477 	void __iomem *reg_dir_in;
478 	bool bgpio_dir_unreadable;
479 	int bgpio_bits;
480 	raw_spinlock_t bgpio_lock;
481 	unsigned long bgpio_data;
482 	unsigned long bgpio_dir;
483 #endif /* CONFIG_GPIO_GENERIC */
484 
485 #ifdef CONFIG_GPIOLIB_IRQCHIP
486 	/*
487 	 * With CONFIG_GPIOLIB_IRQCHIP we get an irqchip inside the gpiolib
488 	 * to handle IRQs for most practical cases.
489 	 */
490 
491 	/**
492 	 * @irq:
493 	 *
494 	 * Integrates interrupt chip functionality with the GPIO chip. Can be
495 	 * used to handle IRQs for most practical cases.
496 	 */
497 	struct gpio_irq_chip irq;
498 #endif /* CONFIG_GPIOLIB_IRQCHIP */
499 
500 	/**
501 	 * @valid_mask:
502 	 *
503 	 * If not %NULL, holds bitmask of GPIOs which are valid to be used
504 	 * from the chip.
505 	 */
506 	unsigned long *valid_mask;
507 
508 #if defined(CONFIG_OF_GPIO)
509 	/*
510 	 * If CONFIG_OF_GPIO is enabled, then all GPIO controllers described in
511 	 * the device tree automatically may have an OF translation
512 	 */
513 
514 	/**
515 	 * @of_gpio_n_cells:
516 	 *
517 	 * Number of cells used to form the GPIO specifier.
518 	 */
519 	unsigned int of_gpio_n_cells;
520 
521 	/**
522 	 * @of_xlate:
523 	 *
524 	 * Callback to translate a device tree GPIO specifier into a chip-
525 	 * relative GPIO number and flags.
526 	 */
527 	int (*of_xlate)(struct gpio_chip *gc,
528 			const struct of_phandle_args *gpiospec, u32 *flags);
529 #endif /* CONFIG_OF_GPIO */
530 };
531 
532 extern const char *gpiochip_is_requested(struct gpio_chip *gc,
533 			unsigned int offset);
534 
535 /**
536  * for_each_requested_gpio_in_range - iterates over requested GPIOs in a given range
537  * @chip:	the chip to query
538  * @i:		loop variable
539  * @base:	first GPIO in the range
540  * @size:	amount of GPIOs to check starting from @base
541  * @label:	label of current GPIO
542  */
543 #define for_each_requested_gpio_in_range(chip, i, base, size, label)			\
544 	for (i = 0; i < size; i++)							\
545 		if ((label = gpiochip_is_requested(chip, base + i)) == NULL) {} else
546 
547 /* Iterates over all requested GPIO of the given @chip */
548 #define for_each_requested_gpio(chip, i, label)						\
549 	for_each_requested_gpio_in_range(chip, i, 0, chip->ngpio, label)
550 
551 /* add/remove chips */
552 extern int gpiochip_add_data_with_key(struct gpio_chip *gc, void *data,
553 				      struct lock_class_key *lock_key,
554 				      struct lock_class_key *request_key);
555 
556 /**
557  * gpiochip_add_data() - register a gpio_chip
558  * @gc: the chip to register, with gc->base initialized
559  * @data: driver-private data associated with this chip
560  *
561  * Context: potentially before irqs will work
562  *
563  * When gpiochip_add_data() is called very early during boot, so that GPIOs
564  * can be freely used, the gc->parent device must be registered before
565  * the gpio framework's arch_initcall().  Otherwise sysfs initialization
566  * for GPIOs will fail rudely.
567  *
568  * gpiochip_add_data() must only be called after gpiolib initialization,
569  * i.e. after core_initcall().
570  *
571  * If gc->base is negative, this requests dynamic assignment of
572  * a range of valid GPIOs.
573  *
574  * Returns:
575  * A negative errno if the chip can't be registered, such as because the
576  * gc->base is invalid or already associated with a different chip.
577  * Otherwise it returns zero as a success code.
578  */
579 #ifdef CONFIG_LOCKDEP
580 #define gpiochip_add_data(gc, data) ({		\
581 		static struct lock_class_key lock_key;	\
582 		static struct lock_class_key request_key;	  \
583 		gpiochip_add_data_with_key(gc, data, &lock_key, \
584 					   &request_key);	  \
585 	})
586 #define devm_gpiochip_add_data(dev, gc, data) ({ \
587 		static struct lock_class_key lock_key;	\
588 		static struct lock_class_key request_key;	  \
589 		devm_gpiochip_add_data_with_key(dev, gc, data, &lock_key, \
590 					   &request_key);	  \
591 	})
592 #else
593 #define gpiochip_add_data(gc, data) gpiochip_add_data_with_key(gc, data, NULL, NULL)
594 #define devm_gpiochip_add_data(dev, gc, data) \
595 	devm_gpiochip_add_data_with_key(dev, gc, data, NULL, NULL)
596 #endif /* CONFIG_LOCKDEP */
597 
gpiochip_add(struct gpio_chip * gc)598 static inline int gpiochip_add(struct gpio_chip *gc)
599 {
600 	return gpiochip_add_data(gc, NULL);
601 }
602 extern void gpiochip_remove(struct gpio_chip *gc);
603 extern int devm_gpiochip_add_data_with_key(struct device *dev, struct gpio_chip *gc, void *data,
604 					   struct lock_class_key *lock_key,
605 					   struct lock_class_key *request_key);
606 
607 extern struct gpio_chip *gpiochip_find(void *data,
608 			      int (*match)(struct gpio_chip *gc, void *data));
609 
610 struct gpio_device *gpio_device_find(void *data,
611 				int (*match)(struct gpio_chip *gc, void *data));
612 
613 struct gpio_device *gpio_device_get(struct gpio_device *gdev);
614 void gpio_device_put(struct gpio_device *gdev);
615 
616 bool gpiochip_line_is_irq(struct gpio_chip *gc, unsigned int offset);
617 int gpiochip_reqres_irq(struct gpio_chip *gc, unsigned int offset);
618 void gpiochip_relres_irq(struct gpio_chip *gc, unsigned int offset);
619 void gpiochip_disable_irq(struct gpio_chip *gc, unsigned int offset);
620 void gpiochip_enable_irq(struct gpio_chip *gc, unsigned int offset);
621 
622 /* irq_data versions of the above */
623 int gpiochip_irq_reqres(struct irq_data *data);
624 void gpiochip_irq_relres(struct irq_data *data);
625 
626 /* Paste this in your irq_chip structure  */
627 #define	GPIOCHIP_IRQ_RESOURCE_HELPERS					\
628 		.irq_request_resources  = gpiochip_irq_reqres,		\
629 		.irq_release_resources  = gpiochip_irq_relres
630 
gpio_irq_chip_set_chip(struct gpio_irq_chip * girq,const struct irq_chip * chip)631 static inline void gpio_irq_chip_set_chip(struct gpio_irq_chip *girq,
632 					  const struct irq_chip *chip)
633 {
634 	/* Yes, dropping const is ugly, but it isn't like we have a choice */
635 	girq->chip = (struct irq_chip *)chip;
636 }
637 
638 /* Line status inquiry for drivers */
639 bool gpiochip_line_is_open_drain(struct gpio_chip *gc, unsigned int offset);
640 bool gpiochip_line_is_open_source(struct gpio_chip *gc, unsigned int offset);
641 
642 /* Sleep persistence inquiry for drivers */
643 bool gpiochip_line_is_persistent(struct gpio_chip *gc, unsigned int offset);
644 bool gpiochip_line_is_valid(const struct gpio_chip *gc, unsigned int offset);
645 
646 /* get driver data */
647 void *gpiochip_get_data(struct gpio_chip *gc);
648 
649 struct bgpio_pdata {
650 	const char *label;
651 	int base;
652 	int ngpio;
653 };
654 
655 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
656 
657 int gpiochip_populate_parent_fwspec_twocell(struct gpio_chip *gc,
658 					    union gpio_irq_fwspec *gfwspec,
659 					    unsigned int parent_hwirq,
660 					    unsigned int parent_type);
661 int gpiochip_populate_parent_fwspec_fourcell(struct gpio_chip *gc,
662 					     union gpio_irq_fwspec *gfwspec,
663 					     unsigned int parent_hwirq,
664 					     unsigned int parent_type);
665 
666 #endif /* CONFIG_IRQ_DOMAIN_HIERARCHY */
667 
668 int bgpio_init(struct gpio_chip *gc, struct device *dev,
669 	       unsigned long sz, void __iomem *dat, void __iomem *set,
670 	       void __iomem *clr, void __iomem *dirout, void __iomem *dirin,
671 	       unsigned long flags);
672 
673 #define BGPIOF_BIG_ENDIAN		BIT(0)
674 #define BGPIOF_UNREADABLE_REG_SET	BIT(1) /* reg_set is unreadable */
675 #define BGPIOF_UNREADABLE_REG_DIR	BIT(2) /* reg_dir is unreadable */
676 #define BGPIOF_BIG_ENDIAN_BYTE_ORDER	BIT(3)
677 #define BGPIOF_READ_OUTPUT_REG_SET	BIT(4) /* reg_set stores output value */
678 #define BGPIOF_NO_OUTPUT		BIT(5) /* only input */
679 #define BGPIOF_NO_SET_ON_INPUT		BIT(6)
680 
681 int gpiochip_irq_map(struct irq_domain *d, unsigned int irq,
682 		     irq_hw_number_t hwirq);
683 void gpiochip_irq_unmap(struct irq_domain *d, unsigned int irq);
684 
685 int gpiochip_irq_domain_activate(struct irq_domain *domain,
686 				 struct irq_data *data, bool reserve);
687 void gpiochip_irq_domain_deactivate(struct irq_domain *domain,
688 				    struct irq_data *data);
689 
690 bool gpiochip_irqchip_irq_valid(const struct gpio_chip *gc,
691 				unsigned int offset);
692 
693 #ifdef CONFIG_GPIOLIB_IRQCHIP
694 int gpiochip_irqchip_add_domain(struct gpio_chip *gc,
695 				struct irq_domain *domain);
696 #else
697 
698 #include <asm/bug.h>
699 #include <asm/errno.h>
700 
gpiochip_irqchip_add_domain(struct gpio_chip * gc,struct irq_domain * domain)701 static inline int gpiochip_irqchip_add_domain(struct gpio_chip *gc,
702 					      struct irq_domain *domain)
703 {
704 	WARN_ON(1);
705 	return -EINVAL;
706 }
707 #endif
708 
709 int gpiochip_generic_request(struct gpio_chip *gc, unsigned int offset);
710 void gpiochip_generic_free(struct gpio_chip *gc, unsigned int offset);
711 int gpiochip_generic_config(struct gpio_chip *gc, unsigned int offset,
712 			    unsigned long config);
713 
714 /**
715  * struct gpio_pin_range - pin range controlled by a gpio chip
716  * @node: list for maintaining set of pin ranges, used internally
717  * @pctldev: pinctrl device which handles corresponding pins
718  * @range: actual range of pins controlled by a gpio controller
719  */
720 struct gpio_pin_range {
721 	struct list_head node;
722 	struct pinctrl_dev *pctldev;
723 	struct pinctrl_gpio_range range;
724 };
725 
726 #ifdef CONFIG_PINCTRL
727 
728 int gpiochip_add_pin_range(struct gpio_chip *gc, const char *pinctl_name,
729 			   unsigned int gpio_offset, unsigned int pin_offset,
730 			   unsigned int npins);
731 int gpiochip_add_pingroup_range(struct gpio_chip *gc,
732 			struct pinctrl_dev *pctldev,
733 			unsigned int gpio_offset, const char *pin_group);
734 void gpiochip_remove_pin_ranges(struct gpio_chip *gc);
735 
736 #else /* ! CONFIG_PINCTRL */
737 
738 static inline int
gpiochip_add_pin_range(struct gpio_chip * gc,const char * pinctl_name,unsigned int gpio_offset,unsigned int pin_offset,unsigned int npins)739 gpiochip_add_pin_range(struct gpio_chip *gc, const char *pinctl_name,
740 		       unsigned int gpio_offset, unsigned int pin_offset,
741 		       unsigned int npins)
742 {
743 	return 0;
744 }
745 static inline int
gpiochip_add_pingroup_range(struct gpio_chip * gc,struct pinctrl_dev * pctldev,unsigned int gpio_offset,const char * pin_group)746 gpiochip_add_pingroup_range(struct gpio_chip *gc,
747 			struct pinctrl_dev *pctldev,
748 			unsigned int gpio_offset, const char *pin_group)
749 {
750 	return 0;
751 }
752 
753 static inline void
gpiochip_remove_pin_ranges(struct gpio_chip * gc)754 gpiochip_remove_pin_ranges(struct gpio_chip *gc)
755 {
756 }
757 
758 #endif /* CONFIG_PINCTRL */
759 
760 struct gpio_desc *gpiochip_request_own_desc(struct gpio_chip *gc,
761 					    unsigned int hwnum,
762 					    const char *label,
763 					    enum gpio_lookup_flags lflags,
764 					    enum gpiod_flags dflags);
765 void gpiochip_free_own_desc(struct gpio_desc *desc);
766 
767 #ifdef CONFIG_GPIOLIB
768 
769 /* lock/unlock as IRQ */
770 int gpiochip_lock_as_irq(struct gpio_chip *gc, unsigned int offset);
771 void gpiochip_unlock_as_irq(struct gpio_chip *gc, unsigned int offset);
772 
773 
774 struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc);
775 
776 #else /* CONFIG_GPIOLIB */
777 
778 #include <linux/err.h>
779 
780 #include <asm/bug.h>
781 
gpiod_to_chip(const struct gpio_desc * desc)782 static inline struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc)
783 {
784 	/* GPIO can never have been requested */
785 	WARN_ON(1);
786 	return ERR_PTR(-ENODEV);
787 }
788 
gpiochip_lock_as_irq(struct gpio_chip * gc,unsigned int offset)789 static inline int gpiochip_lock_as_irq(struct gpio_chip *gc,
790 				       unsigned int offset)
791 {
792 	WARN_ON(1);
793 	return -EINVAL;
794 }
795 
gpiochip_unlock_as_irq(struct gpio_chip * gc,unsigned int offset)796 static inline void gpiochip_unlock_as_irq(struct gpio_chip *gc,
797 					  unsigned int offset)
798 {
799 	WARN_ON(1);
800 }
801 #endif /* CONFIG_GPIOLIB */
802 
803 #define for_each_gpiochip_node(dev, child)					\
804 	device_for_each_child_node(dev, child)					\
805 		if (!fwnode_property_present(child, "gpio-controller")) {} else
806 
gpiochip_node_count(struct device * dev)807 static inline unsigned int gpiochip_node_count(struct device *dev)
808 {
809 	struct fwnode_handle *child;
810 	unsigned int count = 0;
811 
812 	for_each_gpiochip_node(dev, child)
813 		count++;
814 
815 	return count;
816 }
817 
gpiochip_node_get_first(struct device * dev)818 static inline struct fwnode_handle *gpiochip_node_get_first(struct device *dev)
819 {
820 	struct fwnode_handle *fwnode;
821 
822 	for_each_gpiochip_node(dev, fwnode)
823 		return fwnode;
824 
825 	return NULL;
826 }
827 
828 #endif /* __LINUX_GPIO_DRIVER_H */
829