1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Driver for Realtek PCI-Express card reader
4  *
5  * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
6  *
7  * Author:
8  *   Wei WANG (wei_wang@realsil.com.cn)
9  *   Micky Ching (micky_ching@realsil.com.cn)
10  */
11 
12 #include <linux/blkdev.h>
13 #include <linux/kthread.h>
14 #include <linux/sched.h>
15 
16 #include "rtsx.h"
17 #include "sd.h"
18 
19 #define SD_MAX_RETRY_COUNT	3
20 
21 static u16 REG_SD_CFG1;
22 static u16 REG_SD_CFG2;
23 static u16 REG_SD_CFG3;
24 static u16 REG_SD_STAT1;
25 static u16 REG_SD_STAT2;
26 static u16 REG_SD_BUS_STAT;
27 static u16 REG_SD_PAD_CTL;
28 static u16 REG_SD_SAMPLE_POINT_CTL;
29 static u16 REG_SD_PUSH_POINT_CTL;
30 static u16 REG_SD_CMD0;
31 static u16 REG_SD_CMD1;
32 static u16 REG_SD_CMD2;
33 static u16 REG_SD_CMD3;
34 static u16 REG_SD_CMD4;
35 static u16 REG_SD_CMD5;
36 static u16 REG_SD_BYTE_CNT_L;
37 static u16 REG_SD_BYTE_CNT_H;
38 static u16 REG_SD_BLOCK_CNT_L;
39 static u16 REG_SD_BLOCK_CNT_H;
40 static u16 REG_SD_TRANSFER;
41 static u16 REG_SD_VPCLK0_CTL;
42 static u16 REG_SD_VPCLK1_CTL;
43 static u16 REG_SD_DCMPS0_CTL;
44 static u16 REG_SD_DCMPS1_CTL;
45 
sd_set_err_code(struct rtsx_chip * chip,u8 err_code)46 static inline void sd_set_err_code(struct rtsx_chip *chip, u8 err_code)
47 {
48 	struct sd_info *sd_card = &chip->sd_card;
49 
50 	sd_card->err_code |= err_code;
51 }
52 
sd_clr_err_code(struct rtsx_chip * chip)53 static inline void sd_clr_err_code(struct rtsx_chip *chip)
54 {
55 	struct sd_info *sd_card = &chip->sd_card;
56 
57 	sd_card->err_code = 0;
58 }
59 
sd_check_err_code(struct rtsx_chip * chip,u8 err_code)60 static inline int sd_check_err_code(struct rtsx_chip *chip, u8 err_code)
61 {
62 	struct sd_info *sd_card = &chip->sd_card;
63 
64 	return sd_card->err_code & err_code;
65 }
66 
sd_init_reg_addr(struct rtsx_chip * chip)67 static void sd_init_reg_addr(struct rtsx_chip *chip)
68 {
69 	REG_SD_CFG1 = 0xFD31;
70 	REG_SD_CFG2 = 0xFD33;
71 	REG_SD_CFG3 = 0xFD3E;
72 	REG_SD_STAT1 = 0xFD30;
73 	REG_SD_STAT2 = 0;
74 	REG_SD_BUS_STAT = 0;
75 	REG_SD_PAD_CTL = 0;
76 	REG_SD_SAMPLE_POINT_CTL = 0;
77 	REG_SD_PUSH_POINT_CTL = 0;
78 	REG_SD_CMD0 = 0xFD34;
79 	REG_SD_CMD1 = 0xFD35;
80 	REG_SD_CMD2 = 0xFD36;
81 	REG_SD_CMD3 = 0xFD37;
82 	REG_SD_CMD4 = 0xFD38;
83 	REG_SD_CMD5 = 0xFD5A;
84 	REG_SD_BYTE_CNT_L = 0xFD39;
85 	REG_SD_BYTE_CNT_H = 0xFD3A;
86 	REG_SD_BLOCK_CNT_L = 0xFD3B;
87 	REG_SD_BLOCK_CNT_H = 0xFD3C;
88 	REG_SD_TRANSFER = 0xFD32;
89 	REG_SD_VPCLK0_CTL = 0;
90 	REG_SD_VPCLK1_CTL = 0;
91 	REG_SD_DCMPS0_CTL = 0;
92 	REG_SD_DCMPS1_CTL = 0;
93 }
94 
sd_check_data0_status(struct rtsx_chip * chip)95 static int sd_check_data0_status(struct rtsx_chip *chip)
96 {
97 	int retval;
98 	u8 stat;
99 
100 	retval = rtsx_read_register(chip, REG_SD_STAT1, &stat);
101 	if (retval)
102 		return retval;
103 
104 	if (!(stat & SD_DAT0_STATUS)) {
105 		sd_set_err_code(chip, SD_BUSY);
106 		return STATUS_FAIL;
107 	}
108 
109 	return STATUS_SUCCESS;
110 }
111 
sd_send_cmd_get_rsp(struct rtsx_chip * chip,u8 cmd_idx,u32 arg,u8 rsp_type,u8 * rsp,int rsp_len)112 static int sd_send_cmd_get_rsp(struct rtsx_chip *chip, u8 cmd_idx,
113 			       u32 arg, u8 rsp_type, u8 *rsp, int rsp_len)
114 {
115 	struct sd_info *sd_card = &chip->sd_card;
116 	int retval;
117 	int timeout = 100;
118 	u16 reg_addr;
119 	u8 *ptr;
120 	int stat_idx = 0;
121 	int rty_cnt = 0;
122 
123 	sd_clr_err_code(chip);
124 
125 	dev_dbg(rtsx_dev(chip), "SD/MMC CMD %d, arg = 0x%08x\n", cmd_idx, arg);
126 
127 	if (rsp_type == SD_RSP_TYPE_R1b)
128 		timeout = 3000;
129 
130 RTY_SEND_CMD:
131 
132 	rtsx_init_cmd(chip);
133 
134 	rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, 0x40 | cmd_idx);
135 	rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF, (u8)(arg >> 24));
136 	rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF, (u8)(arg >> 16));
137 	rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF, (u8)(arg >> 8));
138 	rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF, (u8)arg);
139 
140 	rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, rsp_type);
141 	rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
142 		     0x01, PINGPONG_BUFFER);
143 	rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER,
144 		     0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START);
145 	rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER,
146 		     SD_TRANSFER_END | SD_STAT_IDLE, SD_TRANSFER_END |
147 		     SD_STAT_IDLE);
148 
149 	if (rsp_type == SD_RSP_TYPE_R2) {
150 		for (reg_addr = PPBUF_BASE2; reg_addr < PPBUF_BASE2 + 16;
151 		     reg_addr++)
152 			rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);
153 
154 		stat_idx = 16;
155 	} else if (rsp_type != SD_RSP_TYPE_R0) {
156 		for (reg_addr = REG_SD_CMD0; reg_addr <= REG_SD_CMD4;
157 		     reg_addr++)
158 			rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);
159 
160 		stat_idx = 5;
161 	}
162 
163 	rtsx_add_cmd(chip, READ_REG_CMD, REG_SD_STAT1, 0, 0);
164 
165 	retval = rtsx_send_cmd(chip, SD_CARD, timeout);
166 	if (retval < 0) {
167 		u8 val;
168 
169 		rtsx_read_register(chip, REG_SD_STAT1, &val);
170 		dev_dbg(rtsx_dev(chip), "SD_STAT1: 0x%x\n", val);
171 
172 		rtsx_read_register(chip, REG_SD_CFG3, &val);
173 		dev_dbg(rtsx_dev(chip), "SD_CFG3: 0x%x\n", val);
174 
175 		if (retval == -ETIMEDOUT) {
176 			if (rsp_type & SD_WAIT_BUSY_END) {
177 				retval = sd_check_data0_status(chip);
178 				if (retval != STATUS_SUCCESS) {
179 					rtsx_clear_sd_error(chip);
180 					return retval;
181 				}
182 			} else {
183 				sd_set_err_code(chip, SD_TO_ERR);
184 			}
185 			retval = STATUS_TIMEDOUT;
186 		} else {
187 			retval = STATUS_FAIL;
188 		}
189 		rtsx_clear_sd_error(chip);
190 
191 		return retval;
192 	}
193 
194 	if (rsp_type == SD_RSP_TYPE_R0)
195 		return STATUS_SUCCESS;
196 
197 	ptr = rtsx_get_cmd_data(chip) + 1;
198 
199 	if ((ptr[0] & 0xC0) != 0) {
200 		sd_set_err_code(chip, SD_STS_ERR);
201 		return STATUS_FAIL;
202 	}
203 
204 	if (!(rsp_type & SD_NO_CHECK_CRC7)) {
205 		if (ptr[stat_idx] & SD_CRC7_ERR) {
206 			if (cmd_idx == WRITE_MULTIPLE_BLOCK) {
207 				sd_set_err_code(chip, SD_CRC_ERR);
208 				return STATUS_FAIL;
209 			}
210 			if (rty_cnt < SD_MAX_RETRY_COUNT) {
211 				wait_timeout(20);
212 				rty_cnt++;
213 				goto RTY_SEND_CMD;
214 			} else {
215 				sd_set_err_code(chip, SD_CRC_ERR);
216 				return STATUS_FAIL;
217 			}
218 		}
219 	}
220 
221 	if (rsp_type == SD_RSP_TYPE_R1 || rsp_type == SD_RSP_TYPE_R1b) {
222 		if (cmd_idx != SEND_RELATIVE_ADDR &&
223 		    cmd_idx != SEND_IF_COND) {
224 			if (cmd_idx != STOP_TRANSMISSION) {
225 				if (ptr[1] & 0x80)
226 					return STATUS_FAIL;
227 			}
228 #ifdef SUPPORT_SD_LOCK
229 			if (ptr[1] & 0x7D) {
230 #else
231 			if (ptr[1] & 0x7F) {
232 #endif
233 				dev_dbg(rtsx_dev(chip), "ptr[1]: 0x%02x\n",
234 					ptr[1]);
235 				return STATUS_FAIL;
236 			}
237 			if (ptr[2] & 0xFF) {
238 				dev_dbg(rtsx_dev(chip), "ptr[2]: 0x%02x\n",
239 					ptr[2]);
240 				return STATUS_FAIL;
241 			}
242 			if (ptr[3] & 0x80) {
243 				dev_dbg(rtsx_dev(chip), "ptr[3]: 0x%02x\n",
244 					ptr[3]);
245 				return STATUS_FAIL;
246 			}
247 			if (ptr[3] & 0x01)
248 				sd_card->sd_data_buf_ready = 1;
249 			else
250 				sd_card->sd_data_buf_ready = 0;
251 		}
252 	}
253 
254 	if (rsp && rsp_len)
255 		memcpy(rsp, ptr, rsp_len);
256 
257 	return STATUS_SUCCESS;
258 }
259 
260 static int sd_read_data(struct rtsx_chip *chip,
261 			u8 trans_mode, u8 *cmd, int cmd_len, u16 byte_cnt,
262 			u16 blk_cnt, u8 bus_width, u8 *buf, int buf_len,
263 			int timeout)
264 {
265 	struct sd_info *sd_card = &chip->sd_card;
266 	int retval;
267 	int i;
268 
269 	sd_clr_err_code(chip);
270 
271 	if (!buf)
272 		buf_len = 0;
273 
274 	if (buf_len > 512)
275 		return STATUS_FAIL;
276 
277 	rtsx_init_cmd(chip);
278 
279 	if (cmd_len) {
280 		dev_dbg(rtsx_dev(chip), "SD/MMC CMD %d\n", cmd[0] - 0x40);
281 		for (i = 0; i < (min(cmd_len, 6)); i++)
282 			rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0 + i,
283 				     0xFF, cmd[i]);
284 	}
285 	rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF,
286 		     (u8)byte_cnt);
287 	rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF,
288 		     (u8)(byte_cnt >> 8));
289 	rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF,
290 		     (u8)blk_cnt);
291 	rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF,
292 		     (u8)(blk_cnt >> 8));
293 
294 	rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 0x03, bus_width);
295 
296 	rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF,
297 		     SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END |
298 		     SD_CHECK_CRC7 | SD_RSP_LEN_6);
299 	if (trans_mode != SD_TM_AUTO_TUNING)
300 		rtsx_add_cmd(chip, WRITE_REG_CMD,
301 			     CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
302 
303 	rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
304 		     trans_mode | SD_TRANSFER_START);
305 	rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END,
306 		     SD_TRANSFER_END);
307 
308 	retval = rtsx_send_cmd(chip, SD_CARD, timeout);
309 	if (retval < 0) {
310 		if (retval == -ETIMEDOUT) {
311 			sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
312 					    SD_RSP_TYPE_R1, NULL, 0);
313 		}
314 
315 		return STATUS_FAIL;
316 	}
317 
318 	if (buf && buf_len) {
319 		retval = rtsx_read_ppbuf(chip, buf, buf_len);
320 		if (retval != STATUS_SUCCESS)
321 			return STATUS_FAIL;
322 	}
323 
324 	return STATUS_SUCCESS;
325 }
326 
327 static int sd_write_data(struct rtsx_chip *chip, u8 trans_mode,
328 			 u8 *cmd, int cmd_len, u16 byte_cnt, u16 blk_cnt,
329 			 u8 bus_width, u8 *buf, int buf_len, int timeout)
330 {
331 	struct sd_info *sd_card = &chip->sd_card;
332 	int retval;
333 	int i;
334 
335 	sd_clr_err_code(chip);
336 
337 	if (!buf)
338 		buf_len = 0;
339 
340 	if (buf_len > 512) {
341 		/* This function can't write data more than one page */
342 		return STATUS_FAIL;
343 	}
344 
345 	if (buf && buf_len) {
346 		retval = rtsx_write_ppbuf(chip, buf, buf_len);
347 		if (retval != STATUS_SUCCESS)
348 			return STATUS_FAIL;
349 	}
350 
351 	rtsx_init_cmd(chip);
352 
353 	if (cmd_len) {
354 		dev_dbg(rtsx_dev(chip), "SD/MMC CMD %d\n", cmd[0] - 0x40);
355 		for (i = 0; i < (min(cmd_len, 6)); i++) {
356 			rtsx_add_cmd(chip, WRITE_REG_CMD,
357 				     REG_SD_CMD0 + i, 0xFF, cmd[i]);
358 		}
359 	}
360 	rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF,
361 		     (u8)byte_cnt);
362 	rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF,
363 		     (u8)(byte_cnt >> 8));
364 	rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF,
365 		     (u8)blk_cnt);
366 	rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF,
367 		     (u8)(blk_cnt >> 8));
368 
369 	rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 0x03, bus_width);
370 
371 	rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF,
372 		     SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END |
373 		     SD_CHECK_CRC7 | SD_RSP_LEN_6);
374 
375 	rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
376 		     trans_mode | SD_TRANSFER_START);
377 	rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END,
378 		     SD_TRANSFER_END);
379 
380 	retval = rtsx_send_cmd(chip, SD_CARD, timeout);
381 	if (retval < 0) {
382 		if (retval == -ETIMEDOUT) {
383 			sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
384 					    SD_RSP_TYPE_R1, NULL, 0);
385 		}
386 
387 		return STATUS_FAIL;
388 	}
389 
390 	return STATUS_SUCCESS;
391 }
392 
393 static int sd_check_csd(struct rtsx_chip *chip, char check_wp)
394 {
395 	struct sd_info *sd_card = &chip->sd_card;
396 	int retval;
397 	int i;
398 	u8 csd_ver, trans_speed;
399 	u8 rsp[16];
400 
401 	for (i = 0; i < 6; i++) {
402 		if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
403 			sd_set_err_code(chip, SD_NO_CARD);
404 			return STATUS_FAIL;
405 		}
406 
407 		retval = sd_send_cmd_get_rsp(chip, SEND_CSD, sd_card->sd_addr,
408 					     SD_RSP_TYPE_R2, rsp, 16);
409 		if (retval == STATUS_SUCCESS)
410 			break;
411 	}
412 
413 	if (i == 6)
414 		return STATUS_FAIL;
415 
416 	memcpy(sd_card->raw_csd, rsp + 1, 15);
417 
418 	dev_dbg(rtsx_dev(chip), "CSD Response:\n");
419 	dev_dbg(rtsx_dev(chip), "%*ph\n", 16, sd_card->raw_csd);
420 
421 	csd_ver = (rsp[1] & 0xc0) >> 6;
422 	dev_dbg(rtsx_dev(chip), "csd_ver = %d\n", csd_ver);
423 
424 	trans_speed = rsp[4];
425 	if ((trans_speed & 0x07) == 0x02) {
426 		if ((trans_speed & 0xf8) >= 0x30) {
427 			if (chip->asic_code)
428 				sd_card->sd_clock = 47;
429 			else
430 				sd_card->sd_clock = CLK_50;
431 
432 		} else if ((trans_speed & 0xf8) == 0x28) {
433 			if (chip->asic_code)
434 				sd_card->sd_clock = 39;
435 			else
436 				sd_card->sd_clock = CLK_40;
437 
438 		} else if ((trans_speed & 0xf8) == 0x20) {
439 			if (chip->asic_code)
440 				sd_card->sd_clock = 29;
441 			else
442 				sd_card->sd_clock = CLK_30;
443 
444 		} else if ((trans_speed & 0xf8) >= 0x10) {
445 			if (chip->asic_code)
446 				sd_card->sd_clock = 23;
447 			else
448 				sd_card->sd_clock = CLK_20;
449 
450 		} else if ((trans_speed & 0x08) >= 0x08) {
451 			if (chip->asic_code)
452 				sd_card->sd_clock = 19;
453 			else
454 				sd_card->sd_clock = CLK_20;
455 		} else {
456 			return STATUS_FAIL;
457 		}
458 	} else {
459 		return STATUS_FAIL;
460 	}
461 
462 	if (CHK_MMC_SECTOR_MODE(sd_card)) {
463 		sd_card->capacity = 0;
464 	} else {
465 		if ((!CHK_SD_HCXC(sd_card)) || csd_ver == 0) {
466 			u8 blk_size, c_size_mult;
467 			u16 c_size;
468 
469 			blk_size = rsp[6] & 0x0F;
470 			c_size =  ((u16)(rsp[7] & 0x03) << 10)
471 					+ ((u16)rsp[8] << 2)
472 					+ ((u16)(rsp[9] & 0xC0) >> 6);
473 			c_size_mult = (u8)((rsp[10] & 0x03) << 1);
474 			c_size_mult += (rsp[11] & 0x80) >> 7;
475 			sd_card->capacity = (((u32)(c_size + 1)) *
476 					(1 << (c_size_mult + 2)))
477 				<< (blk_size - 9);
478 		} else {
479 			u32 total_sector = 0;
480 
481 			total_sector = (((u32)rsp[8] & 0x3f) << 16) |
482 				((u32)rsp[9] << 8) | (u32)rsp[10];
483 			sd_card->capacity = (total_sector + 1) << 10;
484 		}
485 	}
486 
487 	if (check_wp) {
488 		if (rsp[15] & 0x30)
489 			chip->card_wp |= SD_CARD;
490 
491 		dev_dbg(rtsx_dev(chip), "CSD WP Status: 0x%x\n", rsp[15]);
492 	}
493 
494 	return STATUS_SUCCESS;
495 }
496 
497 static int sd_set_sample_push_timing(struct rtsx_chip *chip)
498 {
499 	int retval;
500 	struct sd_info *sd_card = &chip->sd_card;
501 	u8 val = 0;
502 
503 	if ((chip->sd_ctl & SD_PUSH_POINT_CTL_MASK) == SD_PUSH_POINT_DELAY)
504 		val |= 0x10;
505 
506 	if ((chip->sd_ctl & SD_SAMPLE_POINT_CTL_MASK) == SD_SAMPLE_POINT_AUTO) {
507 		if (chip->asic_code) {
508 			if (CHK_SD_HS(sd_card) || CHK_MMC_52M(sd_card)) {
509 				if (val & 0x10)
510 					val |= 0x04;
511 				else
512 					val |= 0x08;
513 			}
514 		} else {
515 			if (val & 0x10)
516 				val |= 0x04;
517 			else
518 				val |= 0x08;
519 		}
520 	} else if ((chip->sd_ctl & SD_SAMPLE_POINT_CTL_MASK) ==
521 		SD_SAMPLE_POINT_DELAY) {
522 		if (val & 0x10)
523 			val |= 0x04;
524 		else
525 			val |= 0x08;
526 	}
527 
528 	retval = rtsx_write_register(chip, REG_SD_CFG1, 0x1C, val);
529 	if (retval)
530 		return retval;
531 
532 	return STATUS_SUCCESS;
533 }
534 
535 static void sd_choose_proper_clock(struct rtsx_chip *chip)
536 {
537 	struct sd_info *sd_card = &chip->sd_card;
538 
539 	if (CHK_SD_SDR104(sd_card)) {
540 		if (chip->asic_code)
541 			sd_card->sd_clock = chip->asic_sd_sdr104_clk;
542 		else
543 			sd_card->sd_clock = chip->fpga_sd_sdr104_clk;
544 
545 	} else if (CHK_SD_DDR50(sd_card)) {
546 		if (chip->asic_code)
547 			sd_card->sd_clock = chip->asic_sd_ddr50_clk;
548 		else
549 			sd_card->sd_clock = chip->fpga_sd_ddr50_clk;
550 
551 	} else if (CHK_SD_SDR50(sd_card)) {
552 		if (chip->asic_code)
553 			sd_card->sd_clock = chip->asic_sd_sdr50_clk;
554 		else
555 			sd_card->sd_clock = chip->fpga_sd_sdr50_clk;
556 
557 	} else if (CHK_SD_HS(sd_card)) {
558 		if (chip->asic_code)
559 			sd_card->sd_clock = chip->asic_sd_hs_clk;
560 		else
561 			sd_card->sd_clock = chip->fpga_sd_hs_clk;
562 
563 	} else if (CHK_MMC_52M(sd_card) || CHK_MMC_DDR52(sd_card)) {
564 		if (chip->asic_code)
565 			sd_card->sd_clock = chip->asic_mmc_52m_clk;
566 		else
567 			sd_card->sd_clock = chip->fpga_mmc_52m_clk;
568 
569 	} else if (CHK_MMC_26M(sd_card)) {
570 		if (chip->asic_code)
571 			sd_card->sd_clock = 48;
572 		else
573 			sd_card->sd_clock = CLK_50;
574 	}
575 }
576 
577 static int sd_set_clock_divider(struct rtsx_chip *chip, u8 clk_div)
578 {
579 	int retval;
580 	u8 mask = 0, val = 0;
581 
582 	mask = 0x60;
583 	if (clk_div == SD_CLK_DIVIDE_0)
584 		val = 0x00;
585 	else if (clk_div == SD_CLK_DIVIDE_128)
586 		val = 0x40;
587 	else if (clk_div == SD_CLK_DIVIDE_256)
588 		val = 0x20;
589 
590 	retval = rtsx_write_register(chip, REG_SD_CFG1, mask, val);
591 	if (retval)
592 		return retval;
593 
594 	return STATUS_SUCCESS;
595 }
596 
597 static int sd_set_init_para(struct rtsx_chip *chip)
598 {
599 	struct sd_info *sd_card = &chip->sd_card;
600 	int retval;
601 
602 	retval = sd_set_sample_push_timing(chip);
603 	if (retval != STATUS_SUCCESS)
604 		return STATUS_FAIL;
605 
606 	sd_choose_proper_clock(chip);
607 
608 	retval = switch_clock(chip, sd_card->sd_clock);
609 	if (retval != STATUS_SUCCESS)
610 		return STATUS_FAIL;
611 
612 	return STATUS_SUCCESS;
613 }
614 
615 int sd_select_card(struct rtsx_chip *chip, int select)
616 {
617 	struct sd_info *sd_card = &chip->sd_card;
618 	int retval;
619 	u8 cmd_idx, cmd_type;
620 	u32 addr;
621 
622 	if (select) {
623 		cmd_idx = SELECT_CARD;
624 		cmd_type = SD_RSP_TYPE_R1;
625 		addr = sd_card->sd_addr;
626 	} else {
627 		cmd_idx = DESELECT_CARD;
628 		cmd_type = SD_RSP_TYPE_R0;
629 		addr = 0;
630 	}
631 
632 	retval = sd_send_cmd_get_rsp(chip, cmd_idx, addr, cmd_type, NULL, 0);
633 	if (retval != STATUS_SUCCESS)
634 		return STATUS_FAIL;
635 
636 	return STATUS_SUCCESS;
637 }
638 
639 #ifdef SUPPORT_SD_LOCK
640 static int sd_update_lock_status(struct rtsx_chip *chip)
641 {
642 	struct sd_info *sd_card = &chip->sd_card;
643 	int retval;
644 	u8 rsp[5];
645 
646 	retval = sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
647 				     SD_RSP_TYPE_R1, rsp, 5);
648 	if (retval != STATUS_SUCCESS)
649 		return STATUS_FAIL;
650 
651 	if (rsp[1] & 0x02)
652 		sd_card->sd_lock_status |= SD_LOCKED;
653 	else
654 		sd_card->sd_lock_status &= ~SD_LOCKED;
655 
656 	dev_dbg(rtsx_dev(chip), "sd_card->sd_lock_status = 0x%x\n",
657 		sd_card->sd_lock_status);
658 
659 	if (rsp[1] & 0x01)
660 		return STATUS_FAIL;
661 
662 	return STATUS_SUCCESS;
663 }
664 #endif
665 
666 static int sd_wait_state_data_ready(struct rtsx_chip *chip, u8 state,
667 				    u8 data_ready, int polling_cnt)
668 {
669 	struct sd_info *sd_card = &chip->sd_card;
670 	int retval, i;
671 	u8 rsp[5];
672 
673 	for (i = 0; i < polling_cnt; i++) {
674 		retval = sd_send_cmd_get_rsp(chip, SEND_STATUS,
675 					     sd_card->sd_addr, SD_RSP_TYPE_R1,
676 					     rsp, 5);
677 		if (retval != STATUS_SUCCESS)
678 			return STATUS_FAIL;
679 
680 		if (((rsp[3] & 0x1E) == state) &&
681 		    ((rsp[3] & 0x01) == data_ready))
682 			return STATUS_SUCCESS;
683 	}
684 
685 	return STATUS_FAIL;
686 }
687 
688 static int sd_change_bank_voltage(struct rtsx_chip *chip, u8 voltage)
689 {
690 	int retval;
691 
692 	if (voltage == SD_IO_3V3) {
693 		if (chip->asic_code) {
694 			retval = rtsx_write_phy_register(chip, 0x08,
695 							 0x4FC0 |
696 							 chip->phy_voltage);
697 			if (retval != STATUS_SUCCESS)
698 				return STATUS_FAIL;
699 		} else {
700 			retval = rtsx_write_register(chip, SD_PAD_CTL,
701 						     SD_IO_USING_1V8, 0);
702 			if (retval)
703 				return retval;
704 		}
705 	} else if (voltage == SD_IO_1V8) {
706 		if (chip->asic_code) {
707 			retval = rtsx_write_phy_register(chip, 0x08,
708 							 0x4C40 |
709 							 chip->phy_voltage);
710 			if (retval != STATUS_SUCCESS)
711 				return STATUS_FAIL;
712 		} else {
713 			retval = rtsx_write_register(chip, SD_PAD_CTL,
714 						     SD_IO_USING_1V8,
715 						     SD_IO_USING_1V8);
716 			if (retval)
717 				return retval;
718 		}
719 	} else {
720 		return STATUS_FAIL;
721 	}
722 
723 	return STATUS_SUCCESS;
724 }
725 
726 static int sd_voltage_switch(struct rtsx_chip *chip)
727 {
728 	int retval;
729 	u8 stat;
730 
731 	retval = rtsx_write_register(chip, SD_BUS_STAT,
732 				     SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP,
733 				     SD_CLK_TOGGLE_EN);
734 	if (retval)
735 		return retval;
736 
737 	retval = sd_send_cmd_get_rsp(chip, VOLTAGE_SWITCH, 0, SD_RSP_TYPE_R1,
738 				     NULL, 0);
739 	if (retval != STATUS_SUCCESS)
740 		return STATUS_FAIL;
741 
742 	udelay(chip->sd_voltage_switch_delay);
743 
744 	retval = rtsx_read_register(chip, SD_BUS_STAT, &stat);
745 	if (retval)
746 		return retval;
747 	if (stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
748 				SD_DAT1_STATUS | SD_DAT0_STATUS)) {
749 		return STATUS_FAIL;
750 	}
751 
752 	retval = rtsx_write_register(chip, SD_BUS_STAT, 0xFF,
753 				     SD_CLK_FORCE_STOP);
754 	if (retval)
755 		return retval;
756 	retval = sd_change_bank_voltage(chip, SD_IO_1V8);
757 	if (retval != STATUS_SUCCESS)
758 		return STATUS_FAIL;
759 
760 	wait_timeout(50);
761 
762 	retval = rtsx_write_register(chip, SD_BUS_STAT, 0xFF,
763 				     SD_CLK_TOGGLE_EN);
764 	if (retval)
765 		return retval;
766 	wait_timeout(10);
767 
768 	retval = rtsx_read_register(chip, SD_BUS_STAT, &stat);
769 	if (retval)
770 		return retval;
771 	if ((stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
772 				SD_DAT1_STATUS | SD_DAT0_STATUS)) !=
773 			(SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
774 				SD_DAT1_STATUS | SD_DAT0_STATUS)) {
775 		dev_dbg(rtsx_dev(chip), "SD_BUS_STAT: 0x%x\n", stat);
776 		rtsx_write_register(chip, SD_BUS_STAT, SD_CLK_TOGGLE_EN |
777 				    SD_CLK_FORCE_STOP, 0);
778 		rtsx_write_register(chip, CARD_CLK_EN, 0xFF, 0);
779 		return STATUS_FAIL;
780 	}
781 
782 	retval = rtsx_write_register(chip, SD_BUS_STAT,
783 				     SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
784 	if (retval)
785 		return retval;
786 
787 	return STATUS_SUCCESS;
788 }
789 
790 static int sd_reset_dcm(struct rtsx_chip *chip, u8 tune_dir)
791 {
792 	int retval;
793 
794 	if (tune_dir == TUNE_RX) {
795 		retval = rtsx_write_register(chip, DCM_DRP_CTL, 0xFF,
796 					     DCM_RESET | DCM_RX);
797 		if (retval)
798 			return retval;
799 		retval = rtsx_write_register(chip, DCM_DRP_CTL, 0xFF, DCM_RX);
800 		if (retval)
801 			return retval;
802 	} else {
803 		retval = rtsx_write_register(chip, DCM_DRP_CTL, 0xFF,
804 					     DCM_RESET | DCM_TX);
805 		if (retval)
806 			return retval;
807 		retval = rtsx_write_register(chip, DCM_DRP_CTL, 0xFF, DCM_TX);
808 		if (retval)
809 			return retval;
810 	}
811 
812 	return STATUS_SUCCESS;
813 }
814 
815 static int sd_change_phase(struct rtsx_chip *chip, u8 sample_point, u8 tune_dir)
816 {
817 	struct sd_info *sd_card = &chip->sd_card;
818 	u16 SD_VP_CTL, SD_DCMPS_CTL;
819 	u8 val;
820 	int retval;
821 	bool ddr_rx = false;
822 
823 	dev_dbg(rtsx_dev(chip), "%s (sample_point = %d, tune_dir = %d)\n",
824 		__func__, sample_point, tune_dir);
825 
826 	if (tune_dir == TUNE_RX) {
827 		SD_VP_CTL = SD_VPRX_CTL;
828 		SD_DCMPS_CTL = SD_DCMPS_RX_CTL;
829 		if (CHK_SD_DDR50(sd_card))
830 			ddr_rx = true;
831 	} else {
832 		SD_VP_CTL = SD_VPTX_CTL;
833 		SD_DCMPS_CTL = SD_DCMPS_TX_CTL;
834 	}
835 
836 	if (chip->asic_code) {
837 		retval = rtsx_write_register(chip, CLK_CTL, CHANGE_CLK,
838 					     CHANGE_CLK);
839 		if (retval)
840 			return retval;
841 		retval = rtsx_write_register(chip, SD_VP_CTL, 0x1F,
842 					     sample_point);
843 		if (retval)
844 			return retval;
845 		retval = rtsx_write_register(chip, SD_VPCLK0_CTL,
846 					     PHASE_NOT_RESET, 0);
847 		if (retval)
848 			return retval;
849 		retval = rtsx_write_register(chip, SD_VPCLK0_CTL,
850 					     PHASE_NOT_RESET, PHASE_NOT_RESET);
851 		if (retval)
852 			return retval;
853 		retval = rtsx_write_register(chip, CLK_CTL, CHANGE_CLK, 0);
854 		if (retval)
855 			return retval;
856 	} else {
857 		rtsx_read_register(chip, SD_VP_CTL, &val);
858 		dev_dbg(rtsx_dev(chip), "SD_VP_CTL: 0x%x\n", val);
859 		rtsx_read_register(chip, SD_DCMPS_CTL, &val);
860 		dev_dbg(rtsx_dev(chip), "SD_DCMPS_CTL: 0x%x\n", val);
861 
862 		if (ddr_rx) {
863 			retval = rtsx_write_register(chip, SD_VP_CTL,
864 						     PHASE_CHANGE,
865 						     PHASE_CHANGE);
866 			if (retval)
867 				return retval;
868 			udelay(50);
869 			retval = rtsx_write_register(chip, SD_VP_CTL, 0xFF,
870 						     PHASE_CHANGE |
871 						     PHASE_NOT_RESET |
872 						     sample_point);
873 			if (retval)
874 				return retval;
875 		} else {
876 			retval = rtsx_write_register(chip, CLK_CTL,
877 						     CHANGE_CLK, CHANGE_CLK);
878 			if (retval)
879 				return retval;
880 			udelay(50);
881 			retval = rtsx_write_register(chip, SD_VP_CTL, 0xFF,
882 						     PHASE_NOT_RESET |
883 						     sample_point);
884 			if (retval)
885 				return retval;
886 		}
887 		udelay(100);
888 
889 		rtsx_init_cmd(chip);
890 		rtsx_add_cmd(chip, WRITE_REG_CMD, SD_DCMPS_CTL, DCMPS_CHANGE,
891 			     DCMPS_CHANGE);
892 		rtsx_add_cmd(chip, CHECK_REG_CMD, SD_DCMPS_CTL,
893 			     DCMPS_CHANGE_DONE, DCMPS_CHANGE_DONE);
894 		retval = rtsx_send_cmd(chip, SD_CARD, 100);
895 		if (retval != STATUS_SUCCESS)
896 			goto fail;
897 
898 		val = *rtsx_get_cmd_data(chip);
899 		if (val & DCMPS_ERROR)
900 			goto fail;
901 
902 		if ((val & DCMPS_CURRENT_PHASE) != sample_point)
903 			goto fail;
904 
905 		retval = rtsx_write_register(chip, SD_DCMPS_CTL,
906 					     DCMPS_CHANGE, 0);
907 		if (retval)
908 			return retval;
909 		if (ddr_rx) {
910 			retval = rtsx_write_register(chip, SD_VP_CTL,
911 						     PHASE_CHANGE, 0);
912 			if (retval)
913 				return retval;
914 		} else {
915 			retval = rtsx_write_register(chip, CLK_CTL,
916 						     CHANGE_CLK, 0);
917 			if (retval)
918 				return retval;
919 		}
920 
921 		udelay(50);
922 	}
923 
924 	retval = rtsx_write_register(chip, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);
925 	if (retval)
926 		return retval;
927 
928 	return STATUS_SUCCESS;
929 
930 fail:
931 	rtsx_read_register(chip, SD_VP_CTL, &val);
932 	dev_dbg(rtsx_dev(chip), "SD_VP_CTL: 0x%x\n", val);
933 	rtsx_read_register(chip, SD_DCMPS_CTL, &val);
934 	dev_dbg(rtsx_dev(chip), "SD_DCMPS_CTL: 0x%x\n", val);
935 
936 	rtsx_write_register(chip, SD_DCMPS_CTL, DCMPS_CHANGE, 0);
937 	rtsx_write_register(chip, SD_VP_CTL, PHASE_CHANGE, 0);
938 	mdelay(10);
939 	sd_reset_dcm(chip, tune_dir);
940 	return STATUS_FAIL;
941 }
942 
943 static int sd_check_spec(struct rtsx_chip *chip, u8 bus_width)
944 {
945 	struct sd_info *sd_card = &chip->sd_card;
946 	int retval;
947 	u8 cmd[5], buf[8];
948 
949 	retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr,
950 				     SD_RSP_TYPE_R1, NULL, 0);
951 	if (retval != STATUS_SUCCESS)
952 		return STATUS_FAIL;
953 
954 	cmd[0] = 0x40 | SEND_SCR;
955 	cmd[1] = 0;
956 	cmd[2] = 0;
957 	cmd[3] = 0;
958 	cmd[4] = 0;
959 
960 	retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 8, 1, bus_width,
961 			      buf, 8, 250);
962 	if (retval != STATUS_SUCCESS) {
963 		rtsx_clear_sd_error(chip);
964 		return STATUS_FAIL;
965 	}
966 
967 	memcpy(sd_card->raw_scr, buf, 8);
968 
969 	if ((buf[0] & 0x0F) == 0)
970 		return STATUS_FAIL;
971 
972 	return STATUS_SUCCESS;
973 }
974 
975 static int sd_query_switch_result(struct rtsx_chip *chip, u8 func_group,
976 				  u8 func_to_switch, u8 *buf, int buf_len)
977 {
978 	u8 support_mask = 0, query_switch = 0, switch_busy = 0;
979 	int support_offset = 0, query_switch_offset = 0, check_busy_offset = 0;
980 
981 	if (func_group == SD_FUNC_GROUP_1) {
982 		support_offset = FUNCTION_GROUP1_SUPPORT_OFFSET;
983 		query_switch_offset = FUNCTION_GROUP1_QUERY_SWITCH_OFFSET;
984 		check_busy_offset = FUNCTION_GROUP1_CHECK_BUSY_OFFSET;
985 
986 		switch (func_to_switch) {
987 		case HS_SUPPORT:
988 			support_mask = HS_SUPPORT_MASK;
989 			query_switch = HS_QUERY_SWITCH_OK;
990 			switch_busy = HS_SWITCH_BUSY;
991 			break;
992 
993 		case SDR50_SUPPORT:
994 			support_mask = SDR50_SUPPORT_MASK;
995 			query_switch = SDR50_QUERY_SWITCH_OK;
996 			switch_busy = SDR50_SWITCH_BUSY;
997 			break;
998 
999 		case SDR104_SUPPORT:
1000 			support_mask = SDR104_SUPPORT_MASK;
1001 			query_switch = SDR104_QUERY_SWITCH_OK;
1002 			switch_busy = SDR104_SWITCH_BUSY;
1003 			break;
1004 
1005 		case DDR50_SUPPORT:
1006 			support_mask = DDR50_SUPPORT_MASK;
1007 			query_switch = DDR50_QUERY_SWITCH_OK;
1008 			switch_busy = DDR50_SWITCH_BUSY;
1009 			break;
1010 
1011 		default:
1012 			return STATUS_FAIL;
1013 		}
1014 	} else if (func_group == SD_FUNC_GROUP_3) {
1015 		support_offset = FUNCTION_GROUP3_SUPPORT_OFFSET;
1016 		query_switch_offset = FUNCTION_GROUP3_QUERY_SWITCH_OFFSET;
1017 		check_busy_offset = FUNCTION_GROUP3_CHECK_BUSY_OFFSET;
1018 
1019 		switch (func_to_switch) {
1020 		case DRIVING_TYPE_A:
1021 			support_mask = DRIVING_TYPE_A_MASK;
1022 			query_switch = TYPE_A_QUERY_SWITCH_OK;
1023 			switch_busy = TYPE_A_SWITCH_BUSY;
1024 			break;
1025 
1026 		case DRIVING_TYPE_C:
1027 			support_mask = DRIVING_TYPE_C_MASK;
1028 			query_switch = TYPE_C_QUERY_SWITCH_OK;
1029 			switch_busy = TYPE_C_SWITCH_BUSY;
1030 			break;
1031 
1032 		case DRIVING_TYPE_D:
1033 			support_mask = DRIVING_TYPE_D_MASK;
1034 			query_switch = TYPE_D_QUERY_SWITCH_OK;
1035 			switch_busy = TYPE_D_SWITCH_BUSY;
1036 			break;
1037 
1038 		default:
1039 			return STATUS_FAIL;
1040 		}
1041 	} else if (func_group == SD_FUNC_GROUP_4) {
1042 		support_offset = FUNCTION_GROUP4_SUPPORT_OFFSET;
1043 		query_switch_offset = FUNCTION_GROUP4_QUERY_SWITCH_OFFSET;
1044 		check_busy_offset = FUNCTION_GROUP4_CHECK_BUSY_OFFSET;
1045 
1046 		switch (func_to_switch) {
1047 		case CURRENT_LIMIT_400:
1048 			support_mask = CURRENT_LIMIT_400_MASK;
1049 			query_switch = CURRENT_LIMIT_400_QUERY_SWITCH_OK;
1050 			switch_busy = CURRENT_LIMIT_400_SWITCH_BUSY;
1051 			break;
1052 
1053 		case CURRENT_LIMIT_600:
1054 			support_mask = CURRENT_LIMIT_600_MASK;
1055 			query_switch = CURRENT_LIMIT_600_QUERY_SWITCH_OK;
1056 			switch_busy = CURRENT_LIMIT_600_SWITCH_BUSY;
1057 			break;
1058 
1059 		case CURRENT_LIMIT_800:
1060 			support_mask = CURRENT_LIMIT_800_MASK;
1061 			query_switch = CURRENT_LIMIT_800_QUERY_SWITCH_OK;
1062 			switch_busy = CURRENT_LIMIT_800_SWITCH_BUSY;
1063 			break;
1064 
1065 		default:
1066 			return STATUS_FAIL;
1067 		}
1068 	} else {
1069 		return STATUS_FAIL;
1070 	}
1071 
1072 	if (func_group == SD_FUNC_GROUP_1) {
1073 		if (!(buf[support_offset] & support_mask) ||
1074 		    ((buf[query_switch_offset] & 0x0F) != query_switch)) {
1075 			return STATUS_FAIL;
1076 		}
1077 	}
1078 
1079 	/* Check 'Busy Status' */
1080 	if (buf[DATA_STRUCTURE_VER_OFFSET] == 0x01 &&
1081 	    ((buf[check_busy_offset] & switch_busy) == switch_busy)) {
1082 		return STATUS_FAIL;
1083 	}
1084 
1085 	return STATUS_SUCCESS;
1086 }
1087 
1088 static int sd_check_switch_mode(struct rtsx_chip *chip, u8 mode, u8 func_group,
1089 				u8 func_to_switch, u8 bus_width)
1090 {
1091 	struct sd_info *sd_card = &chip->sd_card;
1092 	int retval;
1093 	u8 cmd[5], buf[64];
1094 
1095 	dev_dbg(rtsx_dev(chip), "%s (mode = %d, func_group = %d, func_to_switch = %d)\n",
1096 		__func__, mode, func_group, func_to_switch);
1097 
1098 	cmd[0] = 0x40 | SWITCH;
1099 	cmd[1] = mode;
1100 
1101 	if (func_group == SD_FUNC_GROUP_1) {
1102 		cmd[2] = 0xFF;
1103 		cmd[3] = 0xFF;
1104 		cmd[4] = 0xF0 + func_to_switch;
1105 	} else if (func_group == SD_FUNC_GROUP_3) {
1106 		cmd[2] = 0xFF;
1107 		cmd[3] = 0xF0 + func_to_switch;
1108 		cmd[4] = 0xFF;
1109 	} else if (func_group == SD_FUNC_GROUP_4) {
1110 		cmd[2] = 0xFF;
1111 		cmd[3] = 0x0F + (func_to_switch << 4);
1112 		cmd[4] = 0xFF;
1113 	} else {
1114 		cmd[1] = SD_CHECK_MODE;
1115 		cmd[2] = 0xFF;
1116 		cmd[3] = 0xFF;
1117 		cmd[4] = 0xFF;
1118 	}
1119 
1120 	retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 64, 1, bus_width,
1121 			      buf, 64, 250);
1122 	if (retval != STATUS_SUCCESS) {
1123 		rtsx_clear_sd_error(chip);
1124 		return STATUS_FAIL;
1125 	}
1126 
1127 	dev_dbg(rtsx_dev(chip), "%*ph\n", 64, buf);
1128 
1129 	if (func_group == NO_ARGUMENT) {
1130 		sd_card->func_group1_mask = buf[0x0D];
1131 		sd_card->func_group2_mask = buf[0x0B];
1132 		sd_card->func_group3_mask = buf[0x09];
1133 		sd_card->func_group4_mask = buf[0x07];
1134 
1135 		dev_dbg(rtsx_dev(chip), "func_group1_mask = 0x%02x\n",
1136 			buf[0x0D]);
1137 		dev_dbg(rtsx_dev(chip), "func_group2_mask = 0x%02x\n",
1138 			buf[0x0B]);
1139 		dev_dbg(rtsx_dev(chip), "func_group3_mask = 0x%02x\n",
1140 			buf[0x09]);
1141 		dev_dbg(rtsx_dev(chip), "func_group4_mask = 0x%02x\n",
1142 			buf[0x07]);
1143 	} else {
1144 		/* Maximum current consumption, check whether current is
1145 		 * acceptable; bit[511:496] = 0x0000 means some error happened.
1146 		 */
1147 		u16 cc = ((u16)buf[0] << 8) | buf[1];
1148 
1149 		dev_dbg(rtsx_dev(chip), "Maximum current consumption: %dmA\n",
1150 			cc);
1151 		if (cc == 0 || cc > 800)
1152 			return STATUS_FAIL;
1153 
1154 		retval = sd_query_switch_result(chip, func_group,
1155 						func_to_switch, buf, 64);
1156 		if (retval != STATUS_SUCCESS)
1157 			return STATUS_FAIL;
1158 
1159 		if (cc > 400 || func_to_switch > CURRENT_LIMIT_400) {
1160 			retval = rtsx_write_register(chip, OCPPARA2,
1161 						     SD_OCP_THD_MASK,
1162 						     chip->sd_800mA_ocp_thd);
1163 			if (retval)
1164 				return retval;
1165 			retval = rtsx_write_register(chip, CARD_PWR_CTL,
1166 						     PMOS_STRG_MASK,
1167 						     PMOS_STRG_800mA);
1168 			if (retval)
1169 				return retval;
1170 		}
1171 	}
1172 
1173 	return STATUS_SUCCESS;
1174 }
1175 
1176 static u8 downgrade_switch_mode(u8 func_group, u8 func_to_switch)
1177 {
1178 	if (func_group == SD_FUNC_GROUP_1) {
1179 		if (func_to_switch > HS_SUPPORT)
1180 			func_to_switch--;
1181 
1182 	} else if (func_group == SD_FUNC_GROUP_4) {
1183 		if (func_to_switch > CURRENT_LIMIT_200)
1184 			func_to_switch--;
1185 	}
1186 
1187 	return func_to_switch;
1188 }
1189 
1190 static int sd_check_switch(struct rtsx_chip *chip,
1191 			   u8 func_group, u8 func_to_switch, u8 bus_width)
1192 {
1193 	int retval;
1194 	int i;
1195 	bool switch_good = false;
1196 
1197 	for (i = 0; i < 3; i++) {
1198 		if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
1199 			sd_set_err_code(chip, SD_NO_CARD);
1200 			return STATUS_FAIL;
1201 		}
1202 
1203 		retval = sd_check_switch_mode(chip, SD_CHECK_MODE, func_group,
1204 					      func_to_switch, bus_width);
1205 		if (retval == STATUS_SUCCESS) {
1206 			u8 stat;
1207 
1208 			retval = sd_check_switch_mode(chip, SD_SWITCH_MODE,
1209 						      func_group,
1210 						      func_to_switch,
1211 						      bus_width);
1212 			if (retval == STATUS_SUCCESS) {
1213 				switch_good = true;
1214 				break;
1215 			}
1216 
1217 			retval = rtsx_read_register(chip, SD_STAT1, &stat);
1218 			if (retval)
1219 				return retval;
1220 			if (stat & SD_CRC16_ERR) {
1221 				dev_dbg(rtsx_dev(chip), "SD CRC16 error when switching mode\n");
1222 				return STATUS_FAIL;
1223 			}
1224 		}
1225 
1226 		func_to_switch = downgrade_switch_mode(func_group,
1227 						       func_to_switch);
1228 
1229 		wait_timeout(20);
1230 	}
1231 
1232 	if (!switch_good)
1233 		return STATUS_FAIL;
1234 
1235 	return STATUS_SUCCESS;
1236 }
1237 
1238 static int sd_switch_function(struct rtsx_chip *chip, u8 bus_width)
1239 {
1240 	struct sd_info *sd_card = &chip->sd_card;
1241 	int retval;
1242 	int i;
1243 	u8 func_to_switch = 0;
1244 
1245 	/* Get supported functions */
1246 	retval = sd_check_switch_mode(chip, SD_CHECK_MODE, NO_ARGUMENT,
1247 				      NO_ARGUMENT, bus_width);
1248 	if (retval != STATUS_SUCCESS)
1249 		return STATUS_FAIL;
1250 
1251 	sd_card->func_group1_mask &= ~(sd_card->sd_switch_fail);
1252 
1253 	/* Function Group 1: Access Mode */
1254 	for (i = 0; i < 4; i++) {
1255 		switch ((u8)(chip->sd_speed_prior >> (i * 8))) {
1256 		case SDR104_SUPPORT:
1257 			if ((sd_card->func_group1_mask & SDR104_SUPPORT_MASK) &&
1258 			    chip->sdr104_en) {
1259 				func_to_switch = SDR104_SUPPORT;
1260 			}
1261 			break;
1262 
1263 		case DDR50_SUPPORT:
1264 			if ((sd_card->func_group1_mask & DDR50_SUPPORT_MASK) &&
1265 			    chip->ddr50_en) {
1266 				func_to_switch = DDR50_SUPPORT;
1267 			}
1268 			break;
1269 
1270 		case SDR50_SUPPORT:
1271 			if ((sd_card->func_group1_mask & SDR50_SUPPORT_MASK) &&
1272 			    chip->sdr50_en) {
1273 				func_to_switch = SDR50_SUPPORT;
1274 			}
1275 			break;
1276 
1277 		case HS_SUPPORT:
1278 			if (sd_card->func_group1_mask & HS_SUPPORT_MASK)
1279 				func_to_switch = HS_SUPPORT;
1280 
1281 			break;
1282 
1283 		default:
1284 			continue;
1285 		}
1286 
1287 		if (func_to_switch)
1288 			break;
1289 	}
1290 	dev_dbg(rtsx_dev(chip), "SD_FUNC_GROUP_1: func_to_switch = 0x%02x",
1291 		func_to_switch);
1292 
1293 #ifdef SUPPORT_SD_LOCK
1294 	if ((sd_card->sd_lock_status & SD_SDR_RST) &&
1295 	    func_to_switch == DDR50_SUPPORT &&
1296 	    (sd_card->func_group1_mask & SDR50_SUPPORT_MASK)) {
1297 		func_to_switch = SDR50_SUPPORT;
1298 		dev_dbg(rtsx_dev(chip), "Using SDR50 instead of DDR50 for SD Lock\n");
1299 	}
1300 #endif
1301 
1302 	if (func_to_switch) {
1303 		retval = sd_check_switch(chip, SD_FUNC_GROUP_1, func_to_switch,
1304 					 bus_width);
1305 		if (retval != STATUS_SUCCESS) {
1306 			if (func_to_switch == SDR104_SUPPORT) {
1307 				sd_card->sd_switch_fail = SDR104_SUPPORT_MASK;
1308 			} else if (func_to_switch == DDR50_SUPPORT) {
1309 				sd_card->sd_switch_fail = SDR104_SUPPORT_MASK |
1310 					DDR50_SUPPORT_MASK;
1311 			} else if (func_to_switch == SDR50_SUPPORT) {
1312 				sd_card->sd_switch_fail = SDR104_SUPPORT_MASK |
1313 					DDR50_SUPPORT_MASK | SDR50_SUPPORT_MASK;
1314 			}
1315 			return STATUS_FAIL;
1316 		}
1317 
1318 		if (func_to_switch == SDR104_SUPPORT)
1319 			SET_SD_SDR104(sd_card);
1320 		else if (func_to_switch == DDR50_SUPPORT)
1321 			SET_SD_DDR50(sd_card);
1322 		else if (func_to_switch == SDR50_SUPPORT)
1323 			SET_SD_SDR50(sd_card);
1324 		else
1325 			SET_SD_HS(sd_card);
1326 	}
1327 
1328 	if (CHK_SD_DDR50(sd_card)) {
1329 		retval = rtsx_write_register(chip, SD_PUSH_POINT_CTL, 0x06,
1330 					     0x04);
1331 		if (retval)
1332 			return retval;
1333 		retval = sd_set_sample_push_timing(chip);
1334 		if (retval != STATUS_SUCCESS)
1335 			return STATUS_FAIL;
1336 	}
1337 
1338 	if (!func_to_switch || func_to_switch == HS_SUPPORT) {
1339 		/* Do not try to switch current limit if the card doesn't
1340 		 * support UHS mode or we don't want it to support UHS mode
1341 		 */
1342 		return STATUS_SUCCESS;
1343 	}
1344 
1345 	/* Function Group 4: Current Limit */
1346 	func_to_switch = 0xFF;
1347 
1348 	for (i = 0; i < 4; i++) {
1349 		switch ((u8)(chip->sd_current_prior >> (i * 8))) {
1350 		case CURRENT_LIMIT_800:
1351 			if (sd_card->func_group4_mask & CURRENT_LIMIT_800_MASK)
1352 				func_to_switch = CURRENT_LIMIT_800;
1353 
1354 			break;
1355 
1356 		case CURRENT_LIMIT_600:
1357 			if (sd_card->func_group4_mask & CURRENT_LIMIT_600_MASK)
1358 				func_to_switch = CURRENT_LIMIT_600;
1359 
1360 			break;
1361 
1362 		case CURRENT_LIMIT_400:
1363 			if (sd_card->func_group4_mask & CURRENT_LIMIT_400_MASK)
1364 				func_to_switch = CURRENT_LIMIT_400;
1365 
1366 			break;
1367 
1368 		case CURRENT_LIMIT_200:
1369 			if (sd_card->func_group4_mask & CURRENT_LIMIT_200_MASK)
1370 				func_to_switch = CURRENT_LIMIT_200;
1371 
1372 			break;
1373 
1374 		default:
1375 			continue;
1376 		}
1377 
1378 		if (func_to_switch != 0xFF)
1379 			break;
1380 	}
1381 
1382 	dev_dbg(rtsx_dev(chip), "SD_FUNC_GROUP_4: func_to_switch = 0x%02x",
1383 		func_to_switch);
1384 
1385 	if (func_to_switch <= CURRENT_LIMIT_800) {
1386 		retval = sd_check_switch(chip, SD_FUNC_GROUP_4, func_to_switch,
1387 					 bus_width);
1388 		if (retval != STATUS_SUCCESS) {
1389 			if (sd_check_err_code(chip, SD_NO_CARD))
1390 				return STATUS_FAIL;
1391 		}
1392 		dev_dbg(rtsx_dev(chip), "Switch current limit finished! (%d)\n",
1393 			retval);
1394 	}
1395 
1396 	if (CHK_SD_DDR50(sd_card)) {
1397 		retval = rtsx_write_register(chip, SD_PUSH_POINT_CTL, 0x06, 0);
1398 		if (retval)
1399 			return retval;
1400 	}
1401 
1402 	return STATUS_SUCCESS;
1403 }
1404 
1405 static int sd_wait_data_idle(struct rtsx_chip *chip)
1406 {
1407 	int retval = STATUS_TIMEDOUT;
1408 	int i;
1409 	u8 val = 0;
1410 
1411 	for (i = 0; i < 100; i++) {
1412 		retval = rtsx_read_register(chip, SD_DATA_STATE, &val);
1413 		if (retval)
1414 			return retval;
1415 		if (val & SD_DATA_IDLE) {
1416 			retval = STATUS_SUCCESS;
1417 			break;
1418 		}
1419 		udelay(100);
1420 	}
1421 	dev_dbg(rtsx_dev(chip), "SD_DATA_STATE: 0x%02x\n", val);
1422 
1423 	return retval;
1424 }
1425 
1426 static int sd_sdr_tuning_rx_cmd(struct rtsx_chip *chip, u8 sample_point)
1427 {
1428 	int retval;
1429 	u8 cmd[5];
1430 
1431 	retval = sd_change_phase(chip, sample_point, TUNE_RX);
1432 	if (retval != STATUS_SUCCESS)
1433 		return STATUS_FAIL;
1434 
1435 	cmd[0] = 0x40 | SEND_TUNING_PATTERN;
1436 	cmd[1] = 0;
1437 	cmd[2] = 0;
1438 	cmd[3] = 0;
1439 	cmd[4] = 0;
1440 
1441 	retval = sd_read_data(chip, SD_TM_AUTO_TUNING, cmd, 5, 0x40, 1,
1442 			      SD_BUS_WIDTH_4, NULL, 0, 100);
1443 	if (retval != STATUS_SUCCESS) {
1444 		(void)sd_wait_data_idle(chip);
1445 
1446 		rtsx_clear_sd_error(chip);
1447 		return STATUS_FAIL;
1448 	}
1449 
1450 	return STATUS_SUCCESS;
1451 }
1452 
1453 static int sd_ddr_tuning_rx_cmd(struct rtsx_chip *chip, u8 sample_point)
1454 {
1455 	struct sd_info *sd_card = &chip->sd_card;
1456 	int retval;
1457 	u8 cmd[5];
1458 
1459 	retval = sd_change_phase(chip, sample_point, TUNE_RX);
1460 	if (retval != STATUS_SUCCESS)
1461 		return STATUS_FAIL;
1462 
1463 	dev_dbg(rtsx_dev(chip), "sd ddr tuning rx\n");
1464 
1465 	retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr,
1466 				     SD_RSP_TYPE_R1, NULL, 0);
1467 	if (retval != STATUS_SUCCESS)
1468 		return STATUS_FAIL;
1469 
1470 	cmd[0] = 0x40 | SD_STATUS;
1471 	cmd[1] = 0;
1472 	cmd[2] = 0;
1473 	cmd[3] = 0;
1474 	cmd[4] = 0;
1475 
1476 	retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 64, 1,
1477 			      SD_BUS_WIDTH_4, NULL, 0, 100);
1478 	if (retval != STATUS_SUCCESS) {
1479 		(void)sd_wait_data_idle(chip);
1480 
1481 		rtsx_clear_sd_error(chip);
1482 		return STATUS_FAIL;
1483 	}
1484 
1485 	return STATUS_SUCCESS;
1486 }
1487 
1488 static int mmc_ddr_tuning_rx_cmd(struct rtsx_chip *chip, u8 sample_point)
1489 {
1490 	struct sd_info *sd_card = &chip->sd_card;
1491 	int retval;
1492 	u8 cmd[5], bus_width;
1493 
1494 	if (CHK_MMC_8BIT(sd_card))
1495 		bus_width = SD_BUS_WIDTH_8;
1496 	else if (CHK_MMC_4BIT(sd_card))
1497 		bus_width = SD_BUS_WIDTH_4;
1498 	else
1499 		bus_width = SD_BUS_WIDTH_1;
1500 
1501 	retval = sd_change_phase(chip, sample_point, TUNE_RX);
1502 	if (retval != STATUS_SUCCESS)
1503 		return STATUS_FAIL;
1504 
1505 	dev_dbg(rtsx_dev(chip), "mmc ddr tuning rx\n");
1506 
1507 	cmd[0] = 0x40 | SEND_EXT_CSD;
1508 	cmd[1] = 0;
1509 	cmd[2] = 0;
1510 	cmd[3] = 0;
1511 	cmd[4] = 0;
1512 
1513 	retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 0x200, 1,
1514 			      bus_width, NULL, 0, 100);
1515 	if (retval != STATUS_SUCCESS) {
1516 		(void)sd_wait_data_idle(chip);
1517 
1518 		rtsx_clear_sd_error(chip);
1519 		return STATUS_FAIL;
1520 	}
1521 
1522 	return STATUS_SUCCESS;
1523 }
1524 
1525 static int sd_sdr_tuning_tx_cmd(struct rtsx_chip *chip, u8 sample_point)
1526 {
1527 	struct sd_info *sd_card = &chip->sd_card;
1528 	int retval;
1529 
1530 	retval = sd_change_phase(chip, sample_point, TUNE_TX);
1531 	if (retval != STATUS_SUCCESS)
1532 		return STATUS_FAIL;
1533 
1534 	retval = rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN,
1535 				     SD_RSP_80CLK_TIMEOUT_EN);
1536 	if (retval)
1537 		return retval;
1538 
1539 	retval = sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
1540 				     SD_RSP_TYPE_R1, NULL, 0);
1541 	if (retval != STATUS_SUCCESS) {
1542 		if (sd_check_err_code(chip, SD_RSP_TIMEOUT)) {
1543 			rtsx_write_register(chip, SD_CFG3,
1544 					    SD_RSP_80CLK_TIMEOUT_EN, 0);
1545 			return STATUS_FAIL;
1546 		}
1547 	}
1548 
1549 	retval = rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN,
1550 				     0);
1551 	if (retval)
1552 		return retval;
1553 
1554 	return STATUS_SUCCESS;
1555 }
1556 
1557 static int sd_ddr_tuning_tx_cmd(struct rtsx_chip *chip, u8 sample_point)
1558 {
1559 	struct sd_info *sd_card = &chip->sd_card;
1560 	int retval;
1561 	u8 cmd[5], bus_width;
1562 
1563 	retval = sd_change_phase(chip, sample_point, TUNE_TX);
1564 	if (retval != STATUS_SUCCESS)
1565 		return STATUS_FAIL;
1566 
1567 	if (CHK_SD(sd_card)) {
1568 		bus_width = SD_BUS_WIDTH_4;
1569 	} else {
1570 		if (CHK_MMC_8BIT(sd_card))
1571 			bus_width = SD_BUS_WIDTH_8;
1572 		else if (CHK_MMC_4BIT(sd_card))
1573 			bus_width = SD_BUS_WIDTH_4;
1574 		else
1575 			bus_width = SD_BUS_WIDTH_1;
1576 	}
1577 
1578 	retval = sd_wait_state_data_ready(chip, 0x08, 1, 1000);
1579 	if (retval != STATUS_SUCCESS)
1580 		return STATUS_FAIL;
1581 
1582 	retval = rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN,
1583 				     SD_RSP_80CLK_TIMEOUT_EN);
1584 	if (retval)
1585 		return retval;
1586 
1587 	cmd[0] = 0x40 | PROGRAM_CSD;
1588 	cmd[1] = 0;
1589 	cmd[2] = 0;
1590 	cmd[3] = 0;
1591 	cmd[4] = 0;
1592 
1593 	retval = sd_write_data(chip, SD_TM_AUTO_WRITE_2, cmd, 5, 16, 1,
1594 			       bus_width, sd_card->raw_csd, 16, 100);
1595 	if (retval != STATUS_SUCCESS) {
1596 		rtsx_clear_sd_error(chip);
1597 		rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0);
1598 		return STATUS_FAIL;
1599 	}
1600 
1601 	retval = rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN,
1602 				     0);
1603 	if (retval)
1604 		return retval;
1605 
1606 	sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, SD_RSP_TYPE_R1,
1607 			    NULL, 0);
1608 
1609 	return STATUS_SUCCESS;
1610 }
1611 
1612 static u8 sd_search_final_phase(struct rtsx_chip *chip, u32 phase_map,
1613 				u8 tune_dir)
1614 {
1615 	struct sd_info *sd_card = &chip->sd_card;
1616 	struct timing_phase_path path[MAX_PHASE + 1];
1617 	int i, j, cont_path_cnt;
1618 	bool new_block;
1619 	int max_len, final_path_idx;
1620 	u8 final_phase = 0xFF;
1621 
1622 	if (phase_map == 0xFFFFFFFF) {
1623 		if (tune_dir == TUNE_RX)
1624 			final_phase = (u8)chip->sd_default_rx_phase;
1625 		else
1626 			final_phase = (u8)chip->sd_default_tx_phase;
1627 
1628 		goto search_finish;
1629 	}
1630 
1631 	cont_path_cnt = 0;
1632 	new_block = true;
1633 	j = 0;
1634 	for (i = 0; i < MAX_PHASE + 1; i++) {
1635 		if (phase_map & (1 << i)) {
1636 			if (new_block) {
1637 				new_block = false;
1638 				j = cont_path_cnt++;
1639 				path[j].start = i;
1640 				path[j].end = i;
1641 			} else {
1642 				path[j].end = i;
1643 			}
1644 		} else {
1645 			new_block = true;
1646 			if (cont_path_cnt) {
1647 				int idx = cont_path_cnt - 1;
1648 
1649 				path[idx].len = path[idx].end -
1650 					path[idx].start + 1;
1651 				path[idx].mid = path[idx].start +
1652 					path[idx].len / 2;
1653 			}
1654 		}
1655 	}
1656 
1657 	if (cont_path_cnt == 0) {
1658 		dev_dbg(rtsx_dev(chip), "No continuous phase path\n");
1659 		goto search_finish;
1660 	} else {
1661 		int idx = cont_path_cnt - 1;
1662 
1663 		path[idx].len = path[idx].end - path[idx].start + 1;
1664 		path[idx].mid = path[idx].start + path[idx].len / 2;
1665 	}
1666 
1667 	if (path[0].start == 0 &&
1668 	    path[cont_path_cnt - 1].end == MAX_PHASE) {
1669 		path[0].start = path[cont_path_cnt - 1].start - MAX_PHASE - 1;
1670 		path[0].len += path[cont_path_cnt - 1].len;
1671 		path[0].mid = path[0].start + path[0].len / 2;
1672 		if (path[0].mid < 0)
1673 			path[0].mid += MAX_PHASE + 1;
1674 
1675 		cont_path_cnt--;
1676 	}
1677 
1678 	max_len = 0;
1679 	final_phase = 0;
1680 	final_path_idx = 0;
1681 	for (i = 0; i < cont_path_cnt; i++) {
1682 		if (path[i].len > max_len) {
1683 			max_len = path[i].len;
1684 			final_phase = (u8)path[i].mid;
1685 			final_path_idx = i;
1686 		}
1687 
1688 		dev_dbg(rtsx_dev(chip), "path[%d].start = %d\n",
1689 			i, path[i].start);
1690 		dev_dbg(rtsx_dev(chip), "path[%d].end = %d\n", i, path[i].end);
1691 		dev_dbg(rtsx_dev(chip), "path[%d].len = %d\n", i, path[i].len);
1692 		dev_dbg(rtsx_dev(chip), "path[%d].mid = %d\n", i, path[i].mid);
1693 		dev_dbg(rtsx_dev(chip), "\n");
1694 	}
1695 
1696 	if (tune_dir == TUNE_TX) {
1697 		if (CHK_SD_SDR104(sd_card)) {
1698 			if (max_len > 15) {
1699 				int temp_mid = (max_len - 16) / 2;
1700 				int temp_final_phase =
1701 					path[final_path_idx].end -
1702 					(max_len - (6 + temp_mid));
1703 
1704 				if (temp_final_phase < 0)
1705 					final_phase = (u8)(temp_final_phase +
1706 							MAX_PHASE + 1);
1707 				else
1708 					final_phase = (u8)temp_final_phase;
1709 			}
1710 		} else if (CHK_SD_SDR50(sd_card)) {
1711 			if (max_len > 12) {
1712 				int temp_mid = (max_len - 13) / 2;
1713 				int temp_final_phase =
1714 					path[final_path_idx].end -
1715 					(max_len - (3 + temp_mid));
1716 
1717 				if (temp_final_phase < 0)
1718 					final_phase = (u8)(temp_final_phase +
1719 							MAX_PHASE + 1);
1720 				else
1721 					final_phase = (u8)temp_final_phase;
1722 			}
1723 		}
1724 	}
1725 
1726 search_finish:
1727 	dev_dbg(rtsx_dev(chip), "Final chosen phase: %d\n", final_phase);
1728 	return final_phase;
1729 }
1730 
1731 static int sd_tuning_rx(struct rtsx_chip *chip)
1732 {
1733 	struct sd_info *sd_card = &chip->sd_card;
1734 	int retval;
1735 	int i, j;
1736 	u32 raw_phase_map[3], phase_map;
1737 	u8 final_phase;
1738 	int (*tuning_cmd)(struct rtsx_chip *chip, u8 sample_point);
1739 
1740 	if (CHK_SD(sd_card)) {
1741 		if (CHK_SD_DDR50(sd_card))
1742 			tuning_cmd = sd_ddr_tuning_rx_cmd;
1743 		else
1744 			tuning_cmd = sd_sdr_tuning_rx_cmd;
1745 
1746 	} else {
1747 		if (CHK_MMC_DDR52(sd_card))
1748 			tuning_cmd = mmc_ddr_tuning_rx_cmd;
1749 		else
1750 			return STATUS_FAIL;
1751 	}
1752 
1753 	for (i = 0; i < 3; i++) {
1754 		raw_phase_map[i] = 0;
1755 		for (j = MAX_PHASE; j >= 0; j--) {
1756 			if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
1757 				sd_set_err_code(chip, SD_NO_CARD);
1758 				return STATUS_FAIL;
1759 			}
1760 
1761 			retval = tuning_cmd(chip, (u8)j);
1762 			if (retval == STATUS_SUCCESS)
1763 				raw_phase_map[i] |= 1 << j;
1764 		}
1765 	}
1766 
1767 	phase_map = raw_phase_map[0] & raw_phase_map[1] & raw_phase_map[2];
1768 	for (i = 0; i < 3; i++)
1769 		dev_dbg(rtsx_dev(chip), "RX raw_phase_map[%d] = 0x%08x\n",
1770 			i, raw_phase_map[i]);
1771 
1772 	dev_dbg(rtsx_dev(chip), "RX phase_map = 0x%08x\n", phase_map);
1773 
1774 	final_phase = sd_search_final_phase(chip, phase_map, TUNE_RX);
1775 	if (final_phase == 0xFF)
1776 		return STATUS_FAIL;
1777 
1778 	retval = sd_change_phase(chip, final_phase, TUNE_RX);
1779 	if (retval != STATUS_SUCCESS)
1780 		return STATUS_FAIL;
1781 
1782 	return STATUS_SUCCESS;
1783 }
1784 
1785 static int sd_ddr_pre_tuning_tx(struct rtsx_chip *chip)
1786 {
1787 	struct sd_info *sd_card = &chip->sd_card;
1788 	int retval;
1789 	int i;
1790 	u32 phase_map;
1791 	u8 final_phase;
1792 
1793 	retval = rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN,
1794 				     SD_RSP_80CLK_TIMEOUT_EN);
1795 	if (retval)
1796 		return retval;
1797 
1798 	phase_map = 0;
1799 	for (i = MAX_PHASE; i >= 0; i--) {
1800 		if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
1801 			sd_set_err_code(chip, SD_NO_CARD);
1802 			rtsx_write_register(chip, SD_CFG3,
1803 					    SD_RSP_80CLK_TIMEOUT_EN, 0);
1804 			return STATUS_FAIL;
1805 		}
1806 
1807 		retval = sd_change_phase(chip, (u8)i, TUNE_TX);
1808 		if (retval != STATUS_SUCCESS)
1809 			continue;
1810 
1811 		retval = sd_send_cmd_get_rsp(chip, SEND_STATUS,
1812 					     sd_card->sd_addr, SD_RSP_TYPE_R1,
1813 					     NULL, 0);
1814 		if (retval == STATUS_SUCCESS ||
1815 		    !sd_check_err_code(chip, SD_RSP_TIMEOUT))
1816 			phase_map |= 1 << i;
1817 	}
1818 
1819 	retval = rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN,
1820 				     0);
1821 	if (retval)
1822 		return retval;
1823 
1824 	dev_dbg(rtsx_dev(chip), "DDR TX pre tune phase_map = 0x%08x\n",
1825 		phase_map);
1826 
1827 	final_phase = sd_search_final_phase(chip, phase_map, TUNE_TX);
1828 	if (final_phase == 0xFF)
1829 		return STATUS_FAIL;
1830 
1831 	retval = sd_change_phase(chip, final_phase, TUNE_TX);
1832 	if (retval != STATUS_SUCCESS)
1833 		return STATUS_FAIL;
1834 
1835 	dev_dbg(rtsx_dev(chip), "DDR TX pre tune phase: %d\n",
1836 		(int)final_phase);
1837 
1838 	return STATUS_SUCCESS;
1839 }
1840 
1841 static int sd_tuning_tx(struct rtsx_chip *chip)
1842 {
1843 	struct sd_info *sd_card = &chip->sd_card;
1844 	int retval;
1845 	int i, j;
1846 	u32 raw_phase_map[3], phase_map;
1847 	u8 final_phase;
1848 	int (*tuning_cmd)(struct rtsx_chip *chip, u8 sample_point);
1849 
1850 	if (CHK_SD(sd_card)) {
1851 		if (CHK_SD_DDR50(sd_card))
1852 			tuning_cmd = sd_ddr_tuning_tx_cmd;
1853 		else
1854 			tuning_cmd = sd_sdr_tuning_tx_cmd;
1855 
1856 	} else {
1857 		if (CHK_MMC_DDR52(sd_card))
1858 			tuning_cmd = sd_ddr_tuning_tx_cmd;
1859 		else
1860 			return STATUS_FAIL;
1861 	}
1862 
1863 	for (i = 0; i < 3; i++) {
1864 		raw_phase_map[i] = 0;
1865 		for (j = MAX_PHASE; j >= 0; j--) {
1866 			if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
1867 				sd_set_err_code(chip, SD_NO_CARD);
1868 				rtsx_write_register(chip, SD_CFG3,
1869 						    SD_RSP_80CLK_TIMEOUT_EN, 0);
1870 				return STATUS_FAIL;
1871 			}
1872 
1873 			retval = tuning_cmd(chip, (u8)j);
1874 			if (retval == STATUS_SUCCESS)
1875 				raw_phase_map[i] |= 1 << j;
1876 		}
1877 	}
1878 
1879 	phase_map = raw_phase_map[0] & raw_phase_map[1] & raw_phase_map[2];
1880 	for (i = 0; i < 3; i++)
1881 		dev_dbg(rtsx_dev(chip), "TX raw_phase_map[%d] = 0x%08x\n",
1882 			i, raw_phase_map[i]);
1883 
1884 	dev_dbg(rtsx_dev(chip), "TX phase_map = 0x%08x\n", phase_map);
1885 
1886 	final_phase = sd_search_final_phase(chip, phase_map, TUNE_TX);
1887 	if (final_phase == 0xFF)
1888 		return STATUS_FAIL;
1889 
1890 	retval = sd_change_phase(chip, final_phase, TUNE_TX);
1891 	if (retval != STATUS_SUCCESS)
1892 		return STATUS_FAIL;
1893 
1894 	return STATUS_SUCCESS;
1895 }
1896 
1897 static int sd_sdr_tuning(struct rtsx_chip *chip)
1898 {
1899 	int retval;
1900 
1901 	retval = sd_tuning_tx(chip);
1902 	if (retval != STATUS_SUCCESS)
1903 		return STATUS_FAIL;
1904 
1905 	retval = sd_tuning_rx(chip);
1906 	if (retval != STATUS_SUCCESS)
1907 		return STATUS_FAIL;
1908 
1909 	return STATUS_SUCCESS;
1910 }
1911 
1912 static int sd_ddr_tuning(struct rtsx_chip *chip)
1913 {
1914 	int retval;
1915 
1916 	if (!(chip->sd_ctl & SD_DDR_TX_PHASE_SET_BY_USER)) {
1917 		retval = sd_ddr_pre_tuning_tx(chip);
1918 		if (retval != STATUS_SUCCESS)
1919 			return STATUS_FAIL;
1920 	} else {
1921 		retval = sd_change_phase(chip, (u8)chip->sd_ddr_tx_phase,
1922 					 TUNE_TX);
1923 		if (retval != STATUS_SUCCESS)
1924 			return STATUS_FAIL;
1925 	}
1926 
1927 	retval = sd_tuning_rx(chip);
1928 	if (retval != STATUS_SUCCESS)
1929 		return STATUS_FAIL;
1930 
1931 	if (!(chip->sd_ctl & SD_DDR_TX_PHASE_SET_BY_USER)) {
1932 		retval = sd_tuning_tx(chip);
1933 		if (retval != STATUS_SUCCESS)
1934 			return STATUS_FAIL;
1935 	}
1936 
1937 	return STATUS_SUCCESS;
1938 }
1939 
1940 static int mmc_ddr_tuning(struct rtsx_chip *chip)
1941 {
1942 	int retval;
1943 
1944 	if (!(chip->sd_ctl & MMC_DDR_TX_PHASE_SET_BY_USER)) {
1945 		retval = sd_ddr_pre_tuning_tx(chip);
1946 		if (retval != STATUS_SUCCESS)
1947 			return STATUS_FAIL;
1948 	} else {
1949 		retval = sd_change_phase(chip, (u8)chip->mmc_ddr_tx_phase,
1950 					 TUNE_TX);
1951 		if (retval != STATUS_SUCCESS)
1952 			return STATUS_FAIL;
1953 	}
1954 
1955 	retval = sd_tuning_rx(chip);
1956 	if (retval != STATUS_SUCCESS)
1957 		return STATUS_FAIL;
1958 
1959 	if (!(chip->sd_ctl & MMC_DDR_TX_PHASE_SET_BY_USER)) {
1960 		retval = sd_tuning_tx(chip);
1961 		if (retval != STATUS_SUCCESS)
1962 			return STATUS_FAIL;
1963 	}
1964 
1965 	return STATUS_SUCCESS;
1966 }
1967 
1968 int sd_switch_clock(struct rtsx_chip *chip)
1969 {
1970 	struct sd_info *sd_card = &chip->sd_card;
1971 	int retval;
1972 	int re_tuning = 0;
1973 
1974 	retval = select_card(chip, SD_CARD);
1975 	if (retval != STATUS_SUCCESS)
1976 		return STATUS_FAIL;
1977 
1978 	retval = switch_clock(chip, sd_card->sd_clock);
1979 	if (retval != STATUS_SUCCESS)
1980 		return STATUS_FAIL;
1981 
1982 	if (re_tuning) {
1983 		if (CHK_SD(sd_card)) {
1984 			if (CHK_SD_DDR50(sd_card))
1985 				retval = sd_ddr_tuning(chip);
1986 			else
1987 				retval = sd_sdr_tuning(chip);
1988 		} else {
1989 			if (CHK_MMC_DDR52(sd_card))
1990 				retval = mmc_ddr_tuning(chip);
1991 		}
1992 
1993 		if (retval != STATUS_SUCCESS)
1994 			return STATUS_FAIL;
1995 	}
1996 
1997 	return STATUS_SUCCESS;
1998 }
1999 
2000 static int sd_prepare_reset(struct rtsx_chip *chip)
2001 {
2002 	struct sd_info *sd_card = &chip->sd_card;
2003 	int retval;
2004 
2005 	if (chip->asic_code)
2006 		sd_card->sd_clock = 29;
2007 	else
2008 		sd_card->sd_clock = CLK_30;
2009 
2010 	sd_card->sd_type = 0;
2011 	sd_card->seq_mode = 0;
2012 	sd_card->sd_data_buf_ready = 0;
2013 	sd_card->capacity = 0;
2014 
2015 #ifdef SUPPORT_SD_LOCK
2016 	sd_card->sd_lock_status = 0;
2017 	sd_card->sd_erase_status = 0;
2018 #endif
2019 
2020 	chip->capacity[chip->card2lun[SD_CARD]] = 0;
2021 	chip->sd_io = 0;
2022 
2023 	retval = sd_set_init_para(chip);
2024 	if (retval != STATUS_SUCCESS)
2025 		return retval;
2026 
2027 	retval = rtsx_write_register(chip, REG_SD_CFG1, 0xFF, 0x40);
2028 	if (retval)
2029 		return retval;
2030 
2031 	retval = rtsx_write_register(chip, CARD_STOP, SD_STOP | SD_CLR_ERR,
2032 				     SD_STOP | SD_CLR_ERR);
2033 	if (retval)
2034 		return retval;
2035 
2036 	retval = select_card(chip, SD_CARD);
2037 	if (retval != STATUS_SUCCESS)
2038 		return STATUS_FAIL;
2039 
2040 	return STATUS_SUCCESS;
2041 }
2042 
2043 static int sd_pull_ctl_disable(struct rtsx_chip *chip)
2044 {
2045 	int retval;
2046 
2047 	if (CHECK_PID(chip, 0x5208)) {
2048 		retval = rtsx_write_register(chip, CARD_PULL_CTL1, 0xFF,
2049 					     XD_D3_PD | SD_D7_PD | SD_CLK_PD |
2050 					     SD_D5_PD);
2051 		if (retval)
2052 			return retval;
2053 		retval = rtsx_write_register(chip, CARD_PULL_CTL2, 0xFF,
2054 					     SD_D6_PD | SD_D0_PD | SD_D1_PD |
2055 					     XD_D5_PD);
2056 		if (retval)
2057 			return retval;
2058 		retval = rtsx_write_register(chip, CARD_PULL_CTL3, 0xFF,
2059 					     SD_D4_PD | XD_CE_PD | XD_CLE_PD |
2060 					     XD_CD_PU);
2061 		if (retval)
2062 			return retval;
2063 		retval = rtsx_write_register(chip, CARD_PULL_CTL4, 0xFF,
2064 					     XD_RDY_PD | SD_D3_PD | SD_D2_PD |
2065 					     XD_ALE_PD);
2066 		if (retval)
2067 			return retval;
2068 		retval = rtsx_write_register(chip, CARD_PULL_CTL5, 0xFF,
2069 					     MS_INS_PU | SD_WP_PD | SD_CD_PU |
2070 					     SD_CMD_PD);
2071 		if (retval)
2072 			return retval;
2073 		retval = rtsx_write_register(chip, CARD_PULL_CTL6, 0xFF,
2074 					     MS_D5_PD | MS_D4_PD);
2075 		if (retval)
2076 			return retval;
2077 	} else if (CHECK_PID(chip, 0x5288)) {
2078 		if (CHECK_BARO_PKG(chip, QFN)) {
2079 			retval = rtsx_write_register(chip, CARD_PULL_CTL1,
2080 						     0xFF, 0x55);
2081 			if (retval)
2082 				return retval;
2083 			retval = rtsx_write_register(chip, CARD_PULL_CTL2,
2084 						     0xFF, 0x55);
2085 			if (retval)
2086 				return retval;
2087 			retval = rtsx_write_register(chip, CARD_PULL_CTL3,
2088 						     0xFF, 0x4B);
2089 			if (retval)
2090 				return retval;
2091 			retval = rtsx_write_register(chip, CARD_PULL_CTL4,
2092 						     0xFF, 0x69);
2093 			if (retval)
2094 				return retval;
2095 		}
2096 	}
2097 
2098 	return STATUS_SUCCESS;
2099 }
2100 
2101 int sd_pull_ctl_enable(struct rtsx_chip *chip)
2102 {
2103 	int retval;
2104 
2105 	rtsx_init_cmd(chip);
2106 
2107 	if (CHECK_PID(chip, 0x5208)) {
2108 		rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF,
2109 			     XD_D3_PD | SD_DAT7_PU | SD_CLK_NP | SD_D5_PU);
2110 		rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF,
2111 			     SD_D6_PU | SD_D0_PU | SD_D1_PU | XD_D5_PD);
2112 		rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF,
2113 			     SD_D4_PU | XD_CE_PD | XD_CLE_PD | XD_CD_PU);
2114 		rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF,
2115 			     XD_RDY_PD | SD_D3_PU | SD_D2_PU | XD_ALE_PD);
2116 		rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF,
2117 			     MS_INS_PU | SD_WP_PU | SD_CD_PU | SD_CMD_PU);
2118 		rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF,
2119 			     MS_D5_PD | MS_D4_PD);
2120 	} else if (CHECK_PID(chip, 0x5288)) {
2121 		if (CHECK_BARO_PKG(chip, QFN)) {
2122 			rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF,
2123 				     0xA8);
2124 			rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF,
2125 				     0x5A);
2126 			rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF,
2127 				     0x95);
2128 			rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF,
2129 				     0xAA);
2130 		}
2131 	}
2132 
2133 	retval = rtsx_send_cmd(chip, SD_CARD, 100);
2134 	if (retval < 0)
2135 		return STATUS_FAIL;
2136 
2137 	return STATUS_SUCCESS;
2138 }
2139 
2140 static int sd_init_power(struct rtsx_chip *chip)
2141 {
2142 	int retval;
2143 
2144 	retval = sd_power_off_card3v3(chip);
2145 	if (retval != STATUS_SUCCESS)
2146 		return STATUS_FAIL;
2147 
2148 	if (!chip->ft2_fast_mode)
2149 		wait_timeout(250);
2150 
2151 	retval = enable_card_clock(chip, SD_CARD);
2152 	if (retval != STATUS_SUCCESS)
2153 		return STATUS_FAIL;
2154 
2155 	if (chip->asic_code) {
2156 		retval = sd_pull_ctl_enable(chip);
2157 		if (retval != STATUS_SUCCESS)
2158 			return STATUS_FAIL;
2159 	} else {
2160 		retval = rtsx_write_register(chip, FPGA_PULL_CTL,
2161 					     FPGA_SD_PULL_CTL_BIT | 0x20, 0);
2162 		if (retval)
2163 			return retval;
2164 	}
2165 
2166 	if (!chip->ft2_fast_mode) {
2167 		retval = card_power_on(chip, SD_CARD);
2168 		if (retval != STATUS_SUCCESS)
2169 			return STATUS_FAIL;
2170 
2171 		wait_timeout(260);
2172 
2173 #ifdef SUPPORT_OCP
2174 		if (chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) {
2175 			dev_dbg(rtsx_dev(chip), "Over current, OCPSTAT is 0x%x\n",
2176 				chip->ocp_stat);
2177 			return STATUS_FAIL;
2178 		}
2179 #endif
2180 	}
2181 
2182 	retval = rtsx_write_register(chip, CARD_OE, SD_OUTPUT_EN,
2183 				     SD_OUTPUT_EN);
2184 	if (retval)
2185 		return retval;
2186 
2187 	return STATUS_SUCCESS;
2188 }
2189 
2190 static int sd_dummy_clock(struct rtsx_chip *chip)
2191 {
2192 	int retval;
2193 
2194 	retval = rtsx_write_register(chip, REG_SD_CFG3, 0x01, 0x01);
2195 	if (retval)
2196 		return retval;
2197 	wait_timeout(5);
2198 	retval = rtsx_write_register(chip, REG_SD_CFG3, 0x01, 0);
2199 	if (retval)
2200 		return retval;
2201 
2202 	return STATUS_SUCCESS;
2203 }
2204 
2205 static int sd_read_lba0(struct rtsx_chip *chip)
2206 {
2207 	struct sd_info *sd_card = &chip->sd_card;
2208 	int retval;
2209 	u8 cmd[5], bus_width;
2210 
2211 	cmd[0] = 0x40 | READ_SINGLE_BLOCK;
2212 	cmd[1] = 0;
2213 	cmd[2] = 0;
2214 	cmd[3] = 0;
2215 	cmd[4] = 0;
2216 
2217 	if (CHK_SD(sd_card)) {
2218 		bus_width = SD_BUS_WIDTH_4;
2219 	} else {
2220 		if (CHK_MMC_8BIT(sd_card))
2221 			bus_width = SD_BUS_WIDTH_8;
2222 		else if (CHK_MMC_4BIT(sd_card))
2223 			bus_width = SD_BUS_WIDTH_4;
2224 		else
2225 			bus_width = SD_BUS_WIDTH_1;
2226 	}
2227 
2228 	retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 512, 1,
2229 			      bus_width, NULL, 0, 100);
2230 	if (retval != STATUS_SUCCESS) {
2231 		rtsx_clear_sd_error(chip);
2232 		return STATUS_FAIL;
2233 	}
2234 
2235 	return STATUS_SUCCESS;
2236 }
2237 
2238 static int sd_check_wp_state(struct rtsx_chip *chip)
2239 {
2240 	struct sd_info *sd_card = &chip->sd_card;
2241 	int retval;
2242 	u32 val;
2243 	u16 sd_card_type;
2244 	u8 cmd[5], buf[64];
2245 
2246 	retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr,
2247 				     SD_RSP_TYPE_R1, NULL, 0);
2248 	if (retval != STATUS_SUCCESS)
2249 		return STATUS_FAIL;
2250 
2251 	cmd[0] = 0x40 | SD_STATUS;
2252 	cmd[1] = 0;
2253 	cmd[2] = 0;
2254 	cmd[3] = 0;
2255 	cmd[4] = 0;
2256 
2257 	retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 64, 1,
2258 			      SD_BUS_WIDTH_4, buf, 64, 250);
2259 	if (retval != STATUS_SUCCESS) {
2260 		rtsx_clear_sd_error(chip);
2261 
2262 		sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
2263 				    SD_RSP_TYPE_R1, NULL, 0);
2264 		return STATUS_FAIL;
2265 	}
2266 
2267 	dev_dbg(rtsx_dev(chip), "ACMD13:\n");
2268 	dev_dbg(rtsx_dev(chip), "%*ph\n", 64, buf);
2269 
2270 	sd_card_type = ((u16)buf[2] << 8) | buf[3];
2271 	dev_dbg(rtsx_dev(chip), "sd_card_type = 0x%04x\n", sd_card_type);
2272 	if (sd_card_type == 0x0001 || sd_card_type == 0x0002) {
2273 		/* ROM card or OTP */
2274 		chip->card_wp |= SD_CARD;
2275 	}
2276 
2277 	/* Check SD Machanical Write-Protect Switch */
2278 	val = rtsx_readl(chip, RTSX_BIPR);
2279 	if (val & SD_WRITE_PROTECT)
2280 		chip->card_wp |= SD_CARD;
2281 
2282 	return STATUS_SUCCESS;
2283 }
2284 
2285 static int reset_sd(struct rtsx_chip *chip)
2286 {
2287 	struct sd_info *sd_card = &chip->sd_card;
2288 	bool hi_cap_flow = false;
2289 	int retval, i = 0, j = 0, k = 0;
2290 	bool sd_dont_switch = false;
2291 	bool support_1v8 = false;
2292 	bool try_sdio = true;
2293 	u8 rsp[16];
2294 	u8 switch_bus_width;
2295 	u32 voltage = 0;
2296 	bool sd20_mode = false;
2297 
2298 	SET_SD(sd_card);
2299 
2300 switch_fail:
2301 
2302 	i = 0;
2303 	j = 0;
2304 	k = 0;
2305 	hi_cap_flow = false;
2306 
2307 #ifdef SUPPORT_SD_LOCK
2308 	if (sd_card->sd_lock_status & SD_UNLOCK_POW_ON)
2309 		goto SD_UNLOCK_ENTRY;
2310 #endif
2311 
2312 	retval = sd_prepare_reset(chip);
2313 	if (retval != STATUS_SUCCESS)
2314 		goto status_fail;
2315 
2316 	retval = sd_dummy_clock(chip);
2317 	if (retval != STATUS_SUCCESS)
2318 		goto status_fail;
2319 
2320 	if (CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip) && try_sdio) {
2321 		int rty_cnt = 0;
2322 
2323 		for (; rty_cnt < chip->sdio_retry_cnt; rty_cnt++) {
2324 			if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
2325 				sd_set_err_code(chip, SD_NO_CARD);
2326 				goto status_fail;
2327 			}
2328 
2329 			retval = sd_send_cmd_get_rsp(chip, IO_SEND_OP_COND, 0,
2330 						     SD_RSP_TYPE_R4, rsp, 5);
2331 			if (retval == STATUS_SUCCESS) {
2332 				int func_num = (rsp[1] >> 4) & 0x07;
2333 
2334 				if (func_num) {
2335 					dev_dbg(rtsx_dev(chip), "SD_IO card (Function number: %d)!\n",
2336 						func_num);
2337 					chip->sd_io = 1;
2338 					goto status_fail;
2339 				}
2340 
2341 				break;
2342 			}
2343 
2344 			sd_init_power(chip);
2345 
2346 			sd_dummy_clock(chip);
2347 		}
2348 
2349 		dev_dbg(rtsx_dev(chip), "Normal card!\n");
2350 	}
2351 
2352 	/* Start Initialization Process of SD Card */
2353 RTY_SD_RST:
2354 	retval = sd_send_cmd_get_rsp(chip, GO_IDLE_STATE, 0, SD_RSP_TYPE_R0,
2355 				     NULL, 0);
2356 	if (retval != STATUS_SUCCESS)
2357 		goto status_fail;
2358 
2359 	wait_timeout(20);
2360 
2361 	retval = sd_send_cmd_get_rsp(chip, SEND_IF_COND, 0x000001AA,
2362 				     SD_RSP_TYPE_R7, rsp, 5);
2363 	if (retval == STATUS_SUCCESS) {
2364 		if (rsp[4] == 0xAA && ((rsp[3] & 0x0f) == 0x01)) {
2365 			hi_cap_flow = true;
2366 			voltage = SUPPORT_VOLTAGE | 0x40000000;
2367 		}
2368 	}
2369 
2370 	if (!hi_cap_flow) {
2371 		voltage = SUPPORT_VOLTAGE;
2372 
2373 		retval = sd_send_cmd_get_rsp(chip, GO_IDLE_STATE, 0,
2374 					     SD_RSP_TYPE_R0, NULL, 0);
2375 		if (retval != STATUS_SUCCESS)
2376 			goto status_fail;
2377 
2378 		wait_timeout(20);
2379 	}
2380 
2381 	do {
2382 		retval = sd_send_cmd_get_rsp(chip, APP_CMD, 0, SD_RSP_TYPE_R1,
2383 					     NULL, 0);
2384 		if (retval != STATUS_SUCCESS) {
2385 			if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
2386 				sd_set_err_code(chip, SD_NO_CARD);
2387 				goto status_fail;
2388 			}
2389 
2390 			j++;
2391 			if (j < 3)
2392 				goto RTY_SD_RST;
2393 			else
2394 				goto status_fail;
2395 		}
2396 
2397 		retval = sd_send_cmd_get_rsp(chip, SD_APP_OP_COND, voltage,
2398 					     SD_RSP_TYPE_R3, rsp, 5);
2399 		if (retval != STATUS_SUCCESS) {
2400 			k++;
2401 			if (k < 3)
2402 				goto RTY_SD_RST;
2403 			else
2404 				goto status_fail;
2405 		}
2406 
2407 		i++;
2408 		wait_timeout(20);
2409 	} while (!(rsp[1] & 0x80) && (i < 255));
2410 
2411 	if (i == 255)
2412 		goto status_fail;
2413 
2414 	if (hi_cap_flow) {
2415 		if (rsp[1] & 0x40)
2416 			SET_SD_HCXC(sd_card);
2417 		else
2418 			CLR_SD_HCXC(sd_card);
2419 
2420 		support_1v8 = false;
2421 	} else {
2422 		CLR_SD_HCXC(sd_card);
2423 		support_1v8 = false;
2424 	}
2425 	dev_dbg(rtsx_dev(chip), "support_1v8 = %d\n", support_1v8);
2426 
2427 	if (support_1v8) {
2428 		retval = sd_voltage_switch(chip);
2429 		if (retval != STATUS_SUCCESS)
2430 			goto status_fail;
2431 	}
2432 
2433 	retval = sd_send_cmd_get_rsp(chip, ALL_SEND_CID, 0, SD_RSP_TYPE_R2,
2434 				     NULL, 0);
2435 	if (retval != STATUS_SUCCESS)
2436 		goto status_fail;
2437 
2438 	for (i = 0; i < 3; i++) {
2439 		retval = sd_send_cmd_get_rsp(chip, SEND_RELATIVE_ADDR, 0,
2440 					     SD_RSP_TYPE_R6, rsp, 5);
2441 		if (retval != STATUS_SUCCESS)
2442 			goto status_fail;
2443 
2444 		sd_card->sd_addr = (u32)rsp[1] << 24;
2445 		sd_card->sd_addr += (u32)rsp[2] << 16;
2446 
2447 		if (sd_card->sd_addr)
2448 			break;
2449 	}
2450 
2451 	retval = sd_check_csd(chip, 1);
2452 	if (retval != STATUS_SUCCESS)
2453 		goto status_fail;
2454 
2455 	retval = sd_select_card(chip, 1);
2456 	if (retval != STATUS_SUCCESS)
2457 		goto status_fail;
2458 
2459 #ifdef SUPPORT_SD_LOCK
2460 SD_UNLOCK_ENTRY:
2461 	retval = sd_update_lock_status(chip);
2462 	if (retval != STATUS_SUCCESS)
2463 		goto status_fail;
2464 
2465 	if (sd_card->sd_lock_status & SD_LOCKED) {
2466 		sd_card->sd_lock_status |= (SD_LOCK_1BIT_MODE | SD_PWD_EXIST);
2467 		return STATUS_SUCCESS;
2468 	} else if (!(sd_card->sd_lock_status & SD_UNLOCK_POW_ON)) {
2469 		sd_card->sd_lock_status &= ~SD_PWD_EXIST;
2470 	}
2471 #endif
2472 
2473 	retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr,
2474 				     SD_RSP_TYPE_R1, NULL, 0);
2475 	if (retval != STATUS_SUCCESS)
2476 		goto status_fail;
2477 
2478 	retval = sd_send_cmd_get_rsp(chip, SET_CLR_CARD_DETECT, 0,
2479 				     SD_RSP_TYPE_R1, NULL, 0);
2480 	if (retval != STATUS_SUCCESS)
2481 		goto status_fail;
2482 
2483 	if (support_1v8) {
2484 		retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr,
2485 					     SD_RSP_TYPE_R1, NULL, 0);
2486 		if (retval != STATUS_SUCCESS)
2487 			goto status_fail;
2488 
2489 		retval = sd_send_cmd_get_rsp(chip, SET_BUS_WIDTH, 2,
2490 					     SD_RSP_TYPE_R1, NULL, 0);
2491 		if (retval != STATUS_SUCCESS)
2492 			goto status_fail;
2493 
2494 		switch_bus_width = SD_BUS_WIDTH_4;
2495 	} else {
2496 		switch_bus_width = SD_BUS_WIDTH_1;
2497 	}
2498 
2499 	retval = sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, 0x200, SD_RSP_TYPE_R1,
2500 				     NULL, 0);
2501 	if (retval != STATUS_SUCCESS)
2502 		goto status_fail;
2503 
2504 	retval = sd_set_clock_divider(chip, SD_CLK_DIVIDE_0);
2505 	if (retval != STATUS_SUCCESS)
2506 		goto status_fail;
2507 
2508 	if (!(sd_card->raw_csd[4] & 0x40))
2509 		sd_dont_switch = true;
2510 
2511 	if (!sd_dont_switch) {
2512 		if (sd20_mode) {
2513 			/* Set sd_switch_fail here, because we needn't
2514 			 * switch to UHS mode
2515 			 */
2516 			sd_card->sd_switch_fail = SDR104_SUPPORT_MASK |
2517 				DDR50_SUPPORT_MASK | SDR50_SUPPORT_MASK;
2518 		}
2519 
2520 		/* Check the card whether follow SD1.1 spec or higher */
2521 		retval = sd_check_spec(chip, switch_bus_width);
2522 		if (retval == STATUS_SUCCESS) {
2523 			retval = sd_switch_function(chip, switch_bus_width);
2524 			if (retval != STATUS_SUCCESS) {
2525 				sd_init_power(chip);
2526 				sd_dont_switch = true;
2527 				try_sdio = false;
2528 
2529 				goto switch_fail;
2530 			}
2531 		} else {
2532 			if (support_1v8) {
2533 				sd_init_power(chip);
2534 				sd_dont_switch = true;
2535 				try_sdio = false;
2536 
2537 				goto switch_fail;
2538 			}
2539 		}
2540 	}
2541 
2542 	if (!support_1v8) {
2543 		retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr,
2544 					     SD_RSP_TYPE_R1, NULL, 0);
2545 		if (retval != STATUS_SUCCESS)
2546 			goto status_fail;
2547 
2548 		retval = sd_send_cmd_get_rsp(chip, SET_BUS_WIDTH, 2,
2549 					     SD_RSP_TYPE_R1, NULL, 0);
2550 		if (retval != STATUS_SUCCESS)
2551 			goto status_fail;
2552 	}
2553 
2554 #ifdef SUPPORT_SD_LOCK
2555 	sd_card->sd_lock_status &= ~SD_LOCK_1BIT_MODE;
2556 #endif
2557 
2558 	if (!sd20_mode && CHK_SD30_SPEED(sd_card)) {
2559 		int read_lba0 = 1;
2560 
2561 		retval = rtsx_write_register(chip, SD30_DRIVE_SEL, 0x07,
2562 					     chip->sd30_drive_sel_1v8);
2563 		if (retval)
2564 			return retval;
2565 
2566 		retval = sd_set_init_para(chip);
2567 		if (retval != STATUS_SUCCESS)
2568 			goto status_fail;
2569 
2570 		if (CHK_SD_DDR50(sd_card))
2571 			retval = sd_ddr_tuning(chip);
2572 		else
2573 			retval = sd_sdr_tuning(chip);
2574 
2575 		if (retval != STATUS_SUCCESS) {
2576 			retval = sd_init_power(chip);
2577 			if (retval != STATUS_SUCCESS)
2578 				goto status_fail;
2579 
2580 			try_sdio = false;
2581 			sd20_mode = true;
2582 			goto switch_fail;
2583 		}
2584 
2585 		sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
2586 				    SD_RSP_TYPE_R1, NULL, 0);
2587 
2588 		if (CHK_SD_DDR50(sd_card)) {
2589 			retval = sd_wait_state_data_ready(chip, 0x08, 1, 1000);
2590 			if (retval != STATUS_SUCCESS)
2591 				read_lba0 = 0;
2592 		}
2593 
2594 		if (read_lba0) {
2595 			retval = sd_read_lba0(chip);
2596 			if (retval != STATUS_SUCCESS) {
2597 				retval = sd_init_power(chip);
2598 				if (retval != STATUS_SUCCESS)
2599 					goto status_fail;
2600 
2601 				try_sdio = false;
2602 				sd20_mode = true;
2603 				goto switch_fail;
2604 			}
2605 		}
2606 	}
2607 
2608 	retval = sd_check_wp_state(chip);
2609 	if (retval != STATUS_SUCCESS)
2610 		goto status_fail;
2611 
2612 	chip->card_bus_width[chip->card2lun[SD_CARD]] = 4;
2613 
2614 #ifdef SUPPORT_SD_LOCK
2615 	if (sd_card->sd_lock_status & SD_UNLOCK_POW_ON) {
2616 		retval = rtsx_write_register(chip, REG_SD_BLOCK_CNT_H, 0xFF,
2617 					     0x02);
2618 		if (retval)
2619 			return retval;
2620 		retval = rtsx_write_register(chip, REG_SD_BLOCK_CNT_L, 0xFF,
2621 					     0x00);
2622 		if (retval)
2623 			return retval;
2624 	}
2625 #endif
2626 
2627 	return STATUS_SUCCESS;
2628 
2629 status_fail:
2630 	return STATUS_FAIL;
2631 }
2632 
2633 static int mmc_test_switch_bus(struct rtsx_chip *chip, u8 width)
2634 {
2635 	struct sd_info *sd_card = &chip->sd_card;
2636 	int retval;
2637 	u8 buf[8] = {0}, bus_width, *ptr;
2638 	u16 byte_cnt;
2639 	int len;
2640 
2641 	retval = sd_send_cmd_get_rsp(chip, BUSTEST_W, 0, SD_RSP_TYPE_R1, NULL,
2642 				     0);
2643 	if (retval != STATUS_SUCCESS)
2644 		return SWITCH_FAIL;
2645 
2646 	if (width == MMC_8BIT_BUS) {
2647 		buf[0] = 0x55;
2648 		buf[1] = 0xAA;
2649 		len = 8;
2650 		byte_cnt = 8;
2651 		bus_width = SD_BUS_WIDTH_8;
2652 	} else {
2653 		buf[0] = 0x5A;
2654 		len = 4;
2655 		byte_cnt = 4;
2656 		bus_width = SD_BUS_WIDTH_4;
2657 	}
2658 
2659 	retval = rtsx_write_register(chip, REG_SD_CFG3, 0x02, 0x02);
2660 	if (retval != STATUS_SUCCESS)
2661 		return SWITCH_ERR;
2662 
2663 	retval = sd_write_data(chip, SD_TM_AUTO_WRITE_3, NULL, 0, byte_cnt, 1,
2664 			       bus_width, buf, len, 100);
2665 	if (retval != STATUS_SUCCESS) {
2666 		rtsx_clear_sd_error(chip);
2667 		rtsx_write_register(chip, REG_SD_CFG3, 0x02, 0);
2668 		return SWITCH_ERR;
2669 	}
2670 
2671 	retval = rtsx_write_register(chip, REG_SD_CFG3, 0x02, 0);
2672 	if (retval != STATUS_SUCCESS)
2673 		return SWITCH_ERR;
2674 
2675 	dev_dbg(rtsx_dev(chip), "SD/MMC CMD %d\n", BUSTEST_R);
2676 
2677 	rtsx_init_cmd(chip);
2678 
2679 	rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, 0x40 | BUSTEST_R);
2680 
2681 	if (width == MMC_8BIT_BUS)
2682 		rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L,
2683 			     0xFF, 0x08);
2684 	else
2685 		rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L,
2686 			     0xFF, 0x04);
2687 
2688 	rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF, 1);
2689 	rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF, 0);
2690 
2691 	rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, SD_CALCULATE_CRC7 |
2692 		     SD_NO_CHECK_CRC16 | SD_NO_WAIT_BUSY_END |
2693 		     SD_CHECK_CRC7 | SD_RSP_LEN_6);
2694 	rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
2695 		     PINGPONG_BUFFER);
2696 	rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
2697 		     SD_TM_NORMAL_READ | SD_TRANSFER_START);
2698 	rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END,
2699 		     SD_TRANSFER_END);
2700 
2701 	rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2, 0, 0);
2702 	if (width == MMC_8BIT_BUS)
2703 		rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 1, 0, 0);
2704 
2705 	retval = rtsx_send_cmd(chip, SD_CARD, 100);
2706 	if (retval < 0) {
2707 		rtsx_clear_sd_error(chip);
2708 		return SWITCH_ERR;
2709 	}
2710 
2711 	ptr = rtsx_get_cmd_data(chip) + 1;
2712 
2713 	if (width == MMC_8BIT_BUS) {
2714 		dev_dbg(rtsx_dev(chip), "BUSTEST_R [8bits]: 0x%02x 0x%02x\n",
2715 			ptr[0], ptr[1]);
2716 		if (ptr[0] == 0xAA && ptr[1] == 0x55) {
2717 			u8 rsp[5];
2718 			u32 arg;
2719 
2720 			if (CHK_MMC_DDR52(sd_card))
2721 				arg = 0x03B70600;
2722 			else
2723 				arg = 0x03B70200;
2724 
2725 			retval = sd_send_cmd_get_rsp(chip, SWITCH, arg,
2726 						     SD_RSP_TYPE_R1b, rsp, 5);
2727 			if (retval == STATUS_SUCCESS &&
2728 			    !(rsp[4] & MMC_SWITCH_ERR))
2729 				return SWITCH_SUCCESS;
2730 		}
2731 	} else {
2732 		dev_dbg(rtsx_dev(chip), "BUSTEST_R [4bits]: 0x%02x\n", ptr[0]);
2733 		if (ptr[0] == 0xA5) {
2734 			u8 rsp[5];
2735 			u32 arg;
2736 
2737 			if (CHK_MMC_DDR52(sd_card))
2738 				arg = 0x03B70500;
2739 			else
2740 				arg = 0x03B70100;
2741 
2742 			retval = sd_send_cmd_get_rsp(chip, SWITCH, arg,
2743 						     SD_RSP_TYPE_R1b, rsp, 5);
2744 			if (retval == STATUS_SUCCESS &&
2745 			    !(rsp[4] & MMC_SWITCH_ERR))
2746 				return SWITCH_SUCCESS;
2747 		}
2748 	}
2749 
2750 	return SWITCH_FAIL;
2751 }
2752 
2753 static int mmc_switch_timing_bus(struct rtsx_chip *chip, bool switch_ddr)
2754 {
2755 	struct sd_info *sd_card = &chip->sd_card;
2756 	int retval;
2757 	u8 *ptr, card_type, card_type_mask = 0;
2758 
2759 	CLR_MMC_HS(sd_card);
2760 
2761 	dev_dbg(rtsx_dev(chip), "SD/MMC CMD %d\n", SEND_EXT_CSD);
2762 
2763 	rtsx_init_cmd(chip);
2764 
2765 	rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF,
2766 		     0x40 | SEND_EXT_CSD);
2767 	rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF, 0);
2768 	rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF, 0);
2769 	rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF, 0);
2770 	rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF, 0);
2771 
2772 	rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, 0);
2773 	rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, 2);
2774 	rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF, 1);
2775 	rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF, 0);
2776 
2777 	rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF,
2778 		     SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END |
2779 		     SD_CHECK_CRC7 | SD_RSP_LEN_6);
2780 	rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
2781 		     PINGPONG_BUFFER);
2782 	rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
2783 		     SD_TM_NORMAL_READ | SD_TRANSFER_START);
2784 	rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END,
2785 		     SD_TRANSFER_END);
2786 
2787 	rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 196, 0xFF, 0);
2788 	rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 212, 0xFF, 0);
2789 	rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 213, 0xFF, 0);
2790 	rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 214, 0xFF, 0);
2791 	rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 215, 0xFF, 0);
2792 
2793 	retval = rtsx_send_cmd(chip, SD_CARD, 1000);
2794 	if (retval < 0) {
2795 		if (retval == -ETIMEDOUT) {
2796 			rtsx_clear_sd_error(chip);
2797 			sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
2798 					    SD_RSP_TYPE_R1, NULL, 0);
2799 		}
2800 		return STATUS_FAIL;
2801 	}
2802 
2803 	ptr = rtsx_get_cmd_data(chip);
2804 	if (ptr[0] & SD_TRANSFER_ERR) {
2805 		sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
2806 				    SD_RSP_TYPE_R1, NULL, 0);
2807 		return STATUS_FAIL;
2808 	}
2809 
2810 	if (CHK_MMC_SECTOR_MODE(sd_card)) {
2811 		sd_card->capacity = ((u32)ptr[5] << 24) | ((u32)ptr[4] << 16) |
2812 			((u32)ptr[3] << 8) | ((u32)ptr[2]);
2813 	}
2814 
2815 	card_type_mask = 0x03;
2816 	card_type = ptr[1] & card_type_mask;
2817 	if (card_type) {
2818 		u8 rsp[5];
2819 
2820 		if (card_type & 0x04) {
2821 			if (switch_ddr)
2822 				SET_MMC_DDR52(sd_card);
2823 			else
2824 				SET_MMC_52M(sd_card);
2825 		} else if (card_type & 0x02) {
2826 			SET_MMC_52M(sd_card);
2827 		} else {
2828 			SET_MMC_26M(sd_card);
2829 		}
2830 
2831 		retval = sd_send_cmd_get_rsp(chip, SWITCH, 0x03B90100,
2832 					     SD_RSP_TYPE_R1b, rsp, 5);
2833 		if (retval != STATUS_SUCCESS || (rsp[4] & MMC_SWITCH_ERR))
2834 			CLR_MMC_HS(sd_card);
2835 	}
2836 
2837 	sd_choose_proper_clock(chip);
2838 	retval = switch_clock(chip, sd_card->sd_clock);
2839 	if (retval != STATUS_SUCCESS)
2840 		return STATUS_FAIL;
2841 
2842 	/* Test Bus Procedure */
2843 	retval = mmc_test_switch_bus(chip, MMC_8BIT_BUS);
2844 	if (retval == SWITCH_SUCCESS) {
2845 		SET_MMC_8BIT(sd_card);
2846 		chip->card_bus_width[chip->card2lun[SD_CARD]] = 8;
2847 #ifdef SUPPORT_SD_LOCK
2848 		sd_card->sd_lock_status &= ~SD_LOCK_1BIT_MODE;
2849 #endif
2850 	} else if (retval == SWITCH_FAIL) {
2851 		retval = mmc_test_switch_bus(chip, MMC_4BIT_BUS);
2852 		if (retval == SWITCH_SUCCESS) {
2853 			SET_MMC_4BIT(sd_card);
2854 			chip->card_bus_width[chip->card2lun[SD_CARD]] = 4;
2855 #ifdef SUPPORT_SD_LOCK
2856 			sd_card->sd_lock_status &= ~SD_LOCK_1BIT_MODE;
2857 #endif
2858 		} else if (retval == SWITCH_FAIL) {
2859 			CLR_MMC_8BIT(sd_card);
2860 			CLR_MMC_4BIT(sd_card);
2861 		} else {
2862 			return STATUS_FAIL;
2863 		}
2864 	} else {
2865 		return STATUS_FAIL;
2866 	}
2867 
2868 	return STATUS_SUCCESS;
2869 }
2870 
2871 static int reset_mmc(struct rtsx_chip *chip)
2872 {
2873 	struct sd_info *sd_card = &chip->sd_card;
2874 	int retval, i = 0, j = 0, k = 0;
2875 	bool switch_ddr = true;
2876 	u8 rsp[16];
2877 	u8 spec_ver = 0;
2878 	u32 temp;
2879 
2880 #ifdef SUPPORT_SD_LOCK
2881 	if (sd_card->sd_lock_status & SD_UNLOCK_POW_ON)
2882 		goto MMC_UNLOCK_ENTRY;
2883 #endif
2884 
2885 switch_fail:
2886 	retval = sd_prepare_reset(chip);
2887 	if (retval != STATUS_SUCCESS)
2888 		return retval;
2889 
2890 	SET_MMC(sd_card);
2891 
2892 RTY_MMC_RST:
2893 	retval = sd_send_cmd_get_rsp(chip, GO_IDLE_STATE, 0, SD_RSP_TYPE_R0,
2894 				     NULL, 0);
2895 	if (retval != STATUS_SUCCESS)
2896 		return STATUS_FAIL;
2897 
2898 	do {
2899 		if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
2900 			sd_set_err_code(chip, SD_NO_CARD);
2901 			return STATUS_FAIL;
2902 		}
2903 
2904 		retval = sd_send_cmd_get_rsp(chip, SEND_OP_COND,
2905 					     (SUPPORT_VOLTAGE | 0x40000000),
2906 					     SD_RSP_TYPE_R3, rsp, 5);
2907 		if (retval != STATUS_SUCCESS) {
2908 			if (sd_check_err_code(chip, SD_BUSY) ||
2909 			    sd_check_err_code(chip, SD_TO_ERR)) {
2910 				k++;
2911 				if (k < 20) {
2912 					sd_clr_err_code(chip);
2913 					goto RTY_MMC_RST;
2914 				} else {
2915 					return STATUS_FAIL;
2916 				}
2917 			} else {
2918 				j++;
2919 				if (j < 100) {
2920 					sd_clr_err_code(chip);
2921 					goto RTY_MMC_RST;
2922 				} else {
2923 					return STATUS_FAIL;
2924 				}
2925 			}
2926 		}
2927 
2928 		wait_timeout(20);
2929 		i++;
2930 	} while (!(rsp[1] & 0x80) && (i < 255));
2931 
2932 	if (i == 255)
2933 		return STATUS_FAIL;
2934 
2935 	if ((rsp[1] & 0x60) == 0x40)
2936 		SET_MMC_SECTOR_MODE(sd_card);
2937 	else
2938 		CLR_MMC_SECTOR_MODE(sd_card);
2939 
2940 	retval = sd_send_cmd_get_rsp(chip, ALL_SEND_CID, 0, SD_RSP_TYPE_R2,
2941 				     NULL, 0);
2942 	if (retval != STATUS_SUCCESS)
2943 		return STATUS_FAIL;
2944 
2945 	sd_card->sd_addr = 0x00100000;
2946 	retval = sd_send_cmd_get_rsp(chip, SET_RELATIVE_ADDR, sd_card->sd_addr,
2947 				     SD_RSP_TYPE_R6, rsp, 5);
2948 	if (retval != STATUS_SUCCESS)
2949 		return STATUS_FAIL;
2950 
2951 	retval = sd_check_csd(chip, 1);
2952 	if (retval != STATUS_SUCCESS)
2953 		return STATUS_FAIL;
2954 
2955 	spec_ver = (sd_card->raw_csd[0] & 0x3C) >> 2;
2956 
2957 	retval = sd_select_card(chip, 1);
2958 	if (retval != STATUS_SUCCESS)
2959 		return STATUS_FAIL;
2960 
2961 	retval = sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, 0x200, SD_RSP_TYPE_R1,
2962 				     NULL, 0);
2963 	if (retval != STATUS_SUCCESS)
2964 		return STATUS_FAIL;
2965 
2966 #ifdef SUPPORT_SD_LOCK
2967 MMC_UNLOCK_ENTRY:
2968 	retval = sd_update_lock_status(chip);
2969 	if (retval != STATUS_SUCCESS)
2970 		return STATUS_FAIL;
2971 #endif
2972 
2973 	retval = sd_set_clock_divider(chip, SD_CLK_DIVIDE_0);
2974 	if (retval != STATUS_SUCCESS)
2975 		return STATUS_FAIL;
2976 
2977 	chip->card_bus_width[chip->card2lun[SD_CARD]] = 1;
2978 
2979 	if (!sd_card->mmc_dont_switch_bus) {
2980 		if (spec_ver == 4) {
2981 			/* MMC 4.x Cards */
2982 			retval = mmc_switch_timing_bus(chip, switch_ddr);
2983 			if (retval != STATUS_SUCCESS) {
2984 				retval = sd_init_power(chip);
2985 				if (retval != STATUS_SUCCESS)
2986 					return STATUS_FAIL;
2987 				sd_card->mmc_dont_switch_bus = 1;
2988 				goto switch_fail;
2989 			}
2990 		}
2991 
2992 		if (CHK_MMC_SECTOR_MODE(sd_card) && sd_card->capacity == 0)
2993 			return STATUS_FAIL;
2994 
2995 		if (switch_ddr && CHK_MMC_DDR52(sd_card)) {
2996 			retval = sd_set_init_para(chip);
2997 			if (retval != STATUS_SUCCESS)
2998 				return STATUS_FAIL;
2999 
3000 			retval = mmc_ddr_tuning(chip);
3001 			if (retval != STATUS_SUCCESS) {
3002 				retval = sd_init_power(chip);
3003 				if (retval != STATUS_SUCCESS)
3004 					return STATUS_FAIL;
3005 
3006 				switch_ddr = false;
3007 				goto switch_fail;
3008 			}
3009 
3010 			retval = sd_wait_state_data_ready(chip, 0x08, 1, 1000);
3011 			if (retval == STATUS_SUCCESS) {
3012 				retval = sd_read_lba0(chip);
3013 				if (retval != STATUS_SUCCESS) {
3014 					retval = sd_init_power(chip);
3015 					if (retval != STATUS_SUCCESS)
3016 						return STATUS_FAIL;
3017 
3018 					switch_ddr = false;
3019 					goto switch_fail;
3020 				}
3021 			}
3022 		}
3023 	}
3024 
3025 #ifdef SUPPORT_SD_LOCK
3026 	if (sd_card->sd_lock_status & SD_UNLOCK_POW_ON) {
3027 		retval = rtsx_write_register(chip, REG_SD_BLOCK_CNT_H, 0xFF,
3028 					     0x02);
3029 		if (retval)
3030 			return retval;
3031 		retval = rtsx_write_register(chip, REG_SD_BLOCK_CNT_L, 0xFF,
3032 					     0x00);
3033 		if (retval)
3034 			return retval;
3035 	}
3036 #endif
3037 
3038 	temp = rtsx_readl(chip, RTSX_BIPR);
3039 	if (temp & SD_WRITE_PROTECT)
3040 		chip->card_wp |= SD_CARD;
3041 
3042 	return STATUS_SUCCESS;
3043 }
3044 
3045 int reset_sd_card(struct rtsx_chip *chip)
3046 {
3047 	struct sd_info *sd_card = &chip->sd_card;
3048 	int retval;
3049 
3050 	sd_init_reg_addr(chip);
3051 
3052 	memset(sd_card, 0, sizeof(struct sd_info));
3053 	chip->capacity[chip->card2lun[SD_CARD]] = 0;
3054 
3055 	retval = enable_card_clock(chip, SD_CARD);
3056 	if (retval != STATUS_SUCCESS)
3057 		return STATUS_FAIL;
3058 
3059 	if (chip->ignore_sd && CHK_SDIO_EXIST(chip) &&
3060 	    !CHK_SDIO_IGNORED(chip)) {
3061 		if (chip->asic_code) {
3062 			retval = sd_pull_ctl_enable(chip);
3063 			if (retval != STATUS_SUCCESS)
3064 				return STATUS_FAIL;
3065 		} else {
3066 			retval = rtsx_write_register(chip, FPGA_PULL_CTL,
3067 						     FPGA_SD_PULL_CTL_BIT |
3068 						     0x20, 0);
3069 			if (retval != STATUS_SUCCESS)
3070 				return STATUS_FAIL;
3071 		}
3072 		retval = card_share_mode(chip, SD_CARD);
3073 		if (retval != STATUS_SUCCESS)
3074 			return STATUS_FAIL;
3075 
3076 		chip->sd_io = 1;
3077 		return STATUS_FAIL;
3078 	}
3079 
3080 	retval = sd_init_power(chip);
3081 	if (retval != STATUS_SUCCESS)
3082 		return STATUS_FAIL;
3083 
3084 	if (chip->sd_ctl & RESET_MMC_FIRST) {
3085 		retval = reset_mmc(chip);
3086 		if (retval != STATUS_SUCCESS) {
3087 			if (sd_check_err_code(chip, SD_NO_CARD))
3088 				return STATUS_FAIL;
3089 
3090 			retval = reset_sd(chip);
3091 			if (retval != STATUS_SUCCESS)
3092 				return STATUS_FAIL;
3093 		}
3094 	} else {
3095 		retval = reset_sd(chip);
3096 		if (retval != STATUS_SUCCESS) {
3097 			if (sd_check_err_code(chip, SD_NO_CARD))
3098 				return STATUS_FAIL;
3099 
3100 			if (chip->sd_io)
3101 				return STATUS_FAIL;
3102 			retval = reset_mmc(chip);
3103 			if (retval != STATUS_SUCCESS)
3104 				return STATUS_FAIL;
3105 		}
3106 	}
3107 
3108 	retval = sd_set_clock_divider(chip, SD_CLK_DIVIDE_0);
3109 	if (retval != STATUS_SUCCESS)
3110 		return STATUS_FAIL;
3111 
3112 	retval = rtsx_write_register(chip, REG_SD_BYTE_CNT_L, 0xFF, 0);
3113 	if (retval)
3114 		return retval;
3115 	retval = rtsx_write_register(chip, REG_SD_BYTE_CNT_H, 0xFF, 2);
3116 	if (retval)
3117 		return retval;
3118 
3119 	chip->capacity[chip->card2lun[SD_CARD]] = sd_card->capacity;
3120 
3121 	retval = sd_set_init_para(chip);
3122 	if (retval != STATUS_SUCCESS)
3123 		return STATUS_FAIL;
3124 
3125 	dev_dbg(rtsx_dev(chip), "sd_card->sd_type = 0x%x\n", sd_card->sd_type);
3126 
3127 	return STATUS_SUCCESS;
3128 }
3129 
3130 static int reset_mmc_only(struct rtsx_chip *chip)
3131 {
3132 	struct sd_info *sd_card = &chip->sd_card;
3133 	int retval;
3134 
3135 	sd_card->sd_type = 0;
3136 	sd_card->seq_mode = 0;
3137 	sd_card->sd_data_buf_ready = 0;
3138 	sd_card->capacity = 0;
3139 	sd_card->sd_switch_fail = 0;
3140 
3141 #ifdef SUPPORT_SD_LOCK
3142 	sd_card->sd_lock_status = 0;
3143 	sd_card->sd_erase_status = 0;
3144 #endif
3145 
3146 	chip->capacity[chip->card2lun[SD_CARD]] = sd_card->capacity = 0;
3147 
3148 	retval = enable_card_clock(chip, SD_CARD);
3149 	if (retval != STATUS_SUCCESS)
3150 		return STATUS_FAIL;
3151 
3152 	retval = sd_init_power(chip);
3153 	if (retval != STATUS_SUCCESS)
3154 		return STATUS_FAIL;
3155 
3156 	retval = reset_mmc(chip);
3157 	if (retval != STATUS_SUCCESS)
3158 		return STATUS_FAIL;
3159 
3160 	retval = sd_set_clock_divider(chip, SD_CLK_DIVIDE_0);
3161 	if (retval != STATUS_SUCCESS)
3162 		return STATUS_FAIL;
3163 
3164 	retval = rtsx_write_register(chip, REG_SD_BYTE_CNT_L, 0xFF, 0);
3165 	if (retval)
3166 		return retval;
3167 	retval = rtsx_write_register(chip, REG_SD_BYTE_CNT_H, 0xFF, 2);
3168 	if (retval)
3169 		return retval;
3170 
3171 	chip->capacity[chip->card2lun[SD_CARD]] = sd_card->capacity;
3172 
3173 	retval = sd_set_init_para(chip);
3174 	if (retval != STATUS_SUCCESS)
3175 		return STATUS_FAIL;
3176 
3177 	dev_dbg(rtsx_dev(chip), "In %s, sd_card->sd_type = 0x%x\n",
3178 		__func__, sd_card->sd_type);
3179 
3180 	return STATUS_SUCCESS;
3181 }
3182 
3183 #define WAIT_DATA_READY_RTY_CNT		255
3184 
3185 static int wait_data_buf_ready(struct rtsx_chip *chip)
3186 {
3187 	struct sd_info *sd_card = &chip->sd_card;
3188 	int i, retval;
3189 
3190 	for (i = 0; i < WAIT_DATA_READY_RTY_CNT; i++) {
3191 		if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
3192 			sd_set_err_code(chip, SD_NO_CARD);
3193 			return STATUS_FAIL;
3194 		}
3195 
3196 		sd_card->sd_data_buf_ready = 0;
3197 
3198 		retval = sd_send_cmd_get_rsp(chip, SEND_STATUS,
3199 					     sd_card->sd_addr, SD_RSP_TYPE_R1,
3200 					     NULL, 0);
3201 		if (retval != STATUS_SUCCESS)
3202 			return STATUS_FAIL;
3203 
3204 		if (sd_card->sd_data_buf_ready) {
3205 			return sd_send_cmd_get_rsp(chip, SEND_STATUS,
3206 				sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
3207 		}
3208 	}
3209 
3210 	sd_set_err_code(chip, SD_TO_ERR);
3211 
3212 	return STATUS_FAIL;
3213 }
3214 
3215 void sd_stop_seq_mode(struct rtsx_chip *chip)
3216 {
3217 	struct sd_info *sd_card = &chip->sd_card;
3218 	int retval;
3219 
3220 	if (sd_card->seq_mode) {
3221 		retval = sd_switch_clock(chip);
3222 		if (retval != STATUS_SUCCESS)
3223 			return;
3224 
3225 		retval = sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION, 0,
3226 					     SD_RSP_TYPE_R1b, NULL, 0);
3227 		if (retval != STATUS_SUCCESS)
3228 			sd_set_err_code(chip, SD_STS_ERR);
3229 
3230 		retval = sd_wait_state_data_ready(chip, 0x08, 1, 1000);
3231 		if (retval != STATUS_SUCCESS)
3232 			sd_set_err_code(chip, SD_STS_ERR);
3233 
3234 		sd_card->seq_mode = 0;
3235 
3236 		rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH);
3237 	}
3238 }
3239 
3240 static inline int sd_auto_tune_clock(struct rtsx_chip *chip)
3241 {
3242 	struct sd_info *sd_card = &chip->sd_card;
3243 	int retval;
3244 
3245 	if (chip->asic_code) {
3246 		if (sd_card->sd_clock > 30)
3247 			sd_card->sd_clock -= 20;
3248 	} else {
3249 		switch (sd_card->sd_clock) {
3250 		case CLK_200:
3251 			sd_card->sd_clock = CLK_150;
3252 			break;
3253 
3254 		case CLK_150:
3255 			sd_card->sd_clock = CLK_120;
3256 			break;
3257 
3258 		case CLK_120:
3259 			sd_card->sd_clock = CLK_100;
3260 			break;
3261 
3262 		case CLK_100:
3263 			sd_card->sd_clock = CLK_80;
3264 			break;
3265 
3266 		case CLK_80:
3267 			sd_card->sd_clock = CLK_60;
3268 			break;
3269 
3270 		case CLK_60:
3271 			sd_card->sd_clock = CLK_50;
3272 			break;
3273 
3274 		default:
3275 			break;
3276 		}
3277 	}
3278 
3279 	retval = sd_switch_clock(chip);
3280 	if (retval != STATUS_SUCCESS)
3281 		return STATUS_FAIL;
3282 
3283 	return STATUS_SUCCESS;
3284 }
3285 
3286 int sd_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip, u32 start_sector,
3287 	  u16 sector_cnt)
3288 {
3289 	struct sd_info *sd_card = &chip->sd_card;
3290 	u32 data_addr;
3291 	u8 cfg2;
3292 	int retval;
3293 
3294 	if (srb->sc_data_direction == DMA_FROM_DEVICE) {
3295 		dev_dbg(rtsx_dev(chip), "%s: Read %d %s from 0x%x\n", __func__,
3296 			sector_cnt, (sector_cnt > 1) ? "sectors" : "sector",
3297 			start_sector);
3298 	} else {
3299 		dev_dbg(rtsx_dev(chip), "%s: Write %d %s to 0x%x\n", __func__,
3300 			sector_cnt, (sector_cnt > 1) ? "sectors" : "sector",
3301 			start_sector);
3302 	}
3303 
3304 	sd_card->cleanup_counter = 0;
3305 
3306 	if (!(chip->card_ready & SD_CARD)) {
3307 		sd_card->seq_mode = 0;
3308 
3309 		retval = reset_sd_card(chip);
3310 		if (retval == STATUS_SUCCESS) {
3311 			chip->card_ready |= SD_CARD;
3312 			chip->card_fail &= ~SD_CARD;
3313 		} else {
3314 			chip->card_ready &= ~SD_CARD;
3315 			chip->card_fail |= SD_CARD;
3316 			chip->capacity[chip->card2lun[SD_CARD]] = 0;
3317 			chip->rw_need_retry = 1;
3318 			return STATUS_FAIL;
3319 		}
3320 	}
3321 
3322 	if (!CHK_SD_HCXC(sd_card) && !CHK_MMC_SECTOR_MODE(sd_card))
3323 		data_addr = start_sector << 9;
3324 	else
3325 		data_addr = start_sector;
3326 
3327 	sd_clr_err_code(chip);
3328 
3329 	retval = sd_switch_clock(chip);
3330 	if (retval != STATUS_SUCCESS) {
3331 		sd_set_err_code(chip, SD_IO_ERR);
3332 		goto RW_FAIL;
3333 	}
3334 
3335 	if (sd_card->seq_mode &&
3336 	    (sd_card->pre_dir != srb->sc_data_direction ||
3337 	    ((sd_card->pre_sec_addr + sd_card->pre_sec_cnt) !=
3338 	    start_sector))) {
3339 		if (sd_card->pre_sec_cnt < 0x80 &&
3340 		    sd_card->pre_dir == DMA_FROM_DEVICE &&
3341 		    !CHK_SD30_SPEED(sd_card) &&
3342 		    !CHK_SD_HS(sd_card) &&
3343 		    !CHK_MMC_HS(sd_card)) {
3344 			sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
3345 					    SD_RSP_TYPE_R1, NULL, 0);
3346 		}
3347 
3348 		retval = sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION, 0,
3349 					     SD_RSP_TYPE_R1b, NULL, 0);
3350 		if (retval != STATUS_SUCCESS) {
3351 			chip->rw_need_retry = 1;
3352 			sd_set_err_code(chip, SD_STS_ERR);
3353 			goto RW_FAIL;
3354 		}
3355 
3356 		sd_card->seq_mode = 0;
3357 
3358 		retval = rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH);
3359 		if (retval != STATUS_SUCCESS) {
3360 			sd_set_err_code(chip, SD_IO_ERR);
3361 			goto RW_FAIL;
3362 		}
3363 
3364 		if (sd_card->pre_sec_cnt < 0x80 &&
3365 		    !CHK_SD30_SPEED(sd_card) &&
3366 		    !CHK_SD_HS(sd_card) &&
3367 		    !CHK_MMC_HS(sd_card)) {
3368 			sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
3369 					    SD_RSP_TYPE_R1, NULL, 0);
3370 		}
3371 	}
3372 
3373 	rtsx_init_cmd(chip);
3374 
3375 	rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, 0x00);
3376 	rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, 0x02);
3377 	rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF,
3378 		     (u8)sector_cnt);
3379 	rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF,
3380 		     (u8)(sector_cnt >> 8));
3381 
3382 	rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
3383 
3384 	if (CHK_MMC_8BIT(sd_card))
3385 		rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1,
3386 			     0x03, SD_BUS_WIDTH_8);
3387 	else if (CHK_MMC_4BIT(sd_card) || CHK_SD(sd_card))
3388 		rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1,
3389 			     0x03, SD_BUS_WIDTH_4);
3390 	else
3391 		rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1,
3392 			     0x03, SD_BUS_WIDTH_1);
3393 
3394 	if (sd_card->seq_mode) {
3395 		cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 |
3396 			SD_NO_WAIT_BUSY_END | SD_NO_CHECK_CRC7 |
3397 			SD_RSP_LEN_0;
3398 		rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, cfg2);
3399 
3400 		trans_dma_enable(srb->sc_data_direction, chip, sector_cnt * 512,
3401 				 DMA_512);
3402 
3403 		if (srb->sc_data_direction == DMA_FROM_DEVICE) {
3404 			rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
3405 				     SD_TM_AUTO_READ_3 | SD_TRANSFER_START);
3406 		} else {
3407 			rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
3408 				     SD_TM_AUTO_WRITE_3 | SD_TRANSFER_START);
3409 		}
3410 
3411 		rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER,
3412 			     SD_TRANSFER_END, SD_TRANSFER_END);
3413 
3414 		rtsx_send_cmd_no_wait(chip);
3415 	} else {
3416 		if (srb->sc_data_direction == DMA_FROM_DEVICE) {
3417 			dev_dbg(rtsx_dev(chip), "SD/MMC CMD %d\n",
3418 				READ_MULTIPLE_BLOCK);
3419 			rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF,
3420 				     0x40 | READ_MULTIPLE_BLOCK);
3421 			rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF,
3422 				     (u8)(data_addr >> 24));
3423 			rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF,
3424 				     (u8)(data_addr >> 16));
3425 			rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF,
3426 				     (u8)(data_addr >> 8));
3427 			rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF,
3428 				     (u8)data_addr);
3429 
3430 			cfg2 = SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
3431 				SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 |
3432 				SD_RSP_LEN_6;
3433 			rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF,
3434 				     cfg2);
3435 
3436 			trans_dma_enable(srb->sc_data_direction, chip,
3437 					 sector_cnt * 512, DMA_512);
3438 
3439 			rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
3440 				     SD_TM_AUTO_READ_2 | SD_TRANSFER_START);
3441 			rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER,
3442 				     SD_TRANSFER_END, SD_TRANSFER_END);
3443 
3444 			rtsx_send_cmd_no_wait(chip);
3445 		} else {
3446 			retval = rtsx_send_cmd(chip, SD_CARD, 50);
3447 			if (retval < 0) {
3448 				rtsx_clear_sd_error(chip);
3449 
3450 				chip->rw_need_retry = 1;
3451 				sd_set_err_code(chip, SD_TO_ERR);
3452 				goto RW_FAIL;
3453 			}
3454 
3455 			retval = wait_data_buf_ready(chip);
3456 			if (retval != STATUS_SUCCESS) {
3457 				chip->rw_need_retry = 1;
3458 				sd_set_err_code(chip, SD_TO_ERR);
3459 				goto RW_FAIL;
3460 			}
3461 
3462 			retval = sd_send_cmd_get_rsp(chip, WRITE_MULTIPLE_BLOCK,
3463 						     data_addr, SD_RSP_TYPE_R1,
3464 						     NULL, 0);
3465 			if (retval != STATUS_SUCCESS) {
3466 				chip->rw_need_retry = 1;
3467 				goto RW_FAIL;
3468 			}
3469 
3470 			rtsx_init_cmd(chip);
3471 
3472 			cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 |
3473 				SD_NO_WAIT_BUSY_END |
3474 				SD_NO_CHECK_CRC7 | SD_RSP_LEN_0;
3475 			rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF,
3476 				     cfg2);
3477 
3478 			trans_dma_enable(srb->sc_data_direction, chip,
3479 					 sector_cnt * 512, DMA_512);
3480 
3481 			rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
3482 				     SD_TM_AUTO_WRITE_3 | SD_TRANSFER_START);
3483 			rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER,
3484 				     SD_TRANSFER_END, SD_TRANSFER_END);
3485 
3486 			rtsx_send_cmd_no_wait(chip);
3487 		}
3488 
3489 		sd_card->seq_mode = 1;
3490 	}
3491 
3492 	retval = rtsx_transfer_data(chip, SD_CARD, scsi_sglist(srb),
3493 				    scsi_bufflen(srb), scsi_sg_count(srb),
3494 				srb->sc_data_direction, chip->sd_timeout);
3495 	if (retval < 0) {
3496 		u8 stat = 0;
3497 		int err;
3498 
3499 		sd_card->seq_mode = 0;
3500 
3501 		if (retval == -ETIMEDOUT)
3502 			err = STATUS_TIMEDOUT;
3503 		else
3504 			err = STATUS_FAIL;
3505 
3506 		rtsx_read_register(chip, REG_SD_STAT1, &stat);
3507 		rtsx_clear_sd_error(chip);
3508 		if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
3509 			chip->rw_need_retry = 0;
3510 			dev_dbg(rtsx_dev(chip), "No card exist, exit %s\n",
3511 				__func__);
3512 			return STATUS_FAIL;
3513 		}
3514 
3515 		chip->rw_need_retry = 1;
3516 
3517 		retval = sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION, 0,
3518 					     SD_RSP_TYPE_R1b, NULL, 0);
3519 		if (retval != STATUS_SUCCESS) {
3520 			sd_set_err_code(chip, SD_STS_ERR);
3521 			goto RW_FAIL;
3522 		}
3523 
3524 		if (stat & (SD_CRC7_ERR | SD_CRC16_ERR | SD_CRC_WRITE_ERR)) {
3525 			dev_dbg(rtsx_dev(chip), "SD CRC error, tune clock!\n");
3526 			sd_set_err_code(chip, SD_CRC_ERR);
3527 			goto RW_FAIL;
3528 		}
3529 
3530 		if (err == STATUS_TIMEDOUT) {
3531 			sd_set_err_code(chip, SD_TO_ERR);
3532 			goto RW_FAIL;
3533 		}
3534 
3535 		return err;
3536 	}
3537 
3538 	sd_card->pre_sec_addr = start_sector;
3539 	sd_card->pre_sec_cnt = sector_cnt;
3540 	sd_card->pre_dir = srb->sc_data_direction;
3541 
3542 	return STATUS_SUCCESS;
3543 
3544 RW_FAIL:
3545 	sd_card->seq_mode = 0;
3546 
3547 	if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
3548 		chip->rw_need_retry = 0;
3549 		dev_dbg(rtsx_dev(chip), "No card exist, exit %s\n", __func__);
3550 		return STATUS_FAIL;
3551 	}
3552 
3553 	if (sd_check_err_code(chip, SD_CRC_ERR)) {
3554 		if (CHK_MMC_4BIT(sd_card) || CHK_MMC_8BIT(sd_card)) {
3555 			sd_card->mmc_dont_switch_bus = 1;
3556 			reset_mmc_only(chip);
3557 			sd_card->mmc_dont_switch_bus = 0;
3558 		} else {
3559 			sd_card->need_retune = 1;
3560 			sd_auto_tune_clock(chip);
3561 		}
3562 	} else if (sd_check_err_code(chip, SD_TO_ERR | SD_STS_ERR)) {
3563 		retval = reset_sd_card(chip);
3564 		if (retval != STATUS_SUCCESS) {
3565 			chip->card_ready &= ~SD_CARD;
3566 			chip->card_fail |= SD_CARD;
3567 			chip->capacity[chip->card2lun[SD_CARD]] = 0;
3568 		}
3569 	}
3570 
3571 	return STATUS_FAIL;
3572 }
3573 
3574 #ifdef SUPPORT_CPRM
3575 int ext_sd_send_cmd_get_rsp(struct rtsx_chip *chip, u8 cmd_idx, u32 arg,
3576 			    u8 rsp_type, u8 *rsp, int rsp_len,
3577 			    bool special_check)
3578 {
3579 	int retval;
3580 	int timeout = 100;
3581 	u16 reg_addr;
3582 	u8 *ptr;
3583 	int stat_idx = 0;
3584 	int rty_cnt = 0;
3585 
3586 	dev_dbg(rtsx_dev(chip), "EXT SD/MMC CMD %d\n", cmd_idx);
3587 
3588 	if (rsp_type == SD_RSP_TYPE_R1b)
3589 		timeout = 3000;
3590 
3591 RTY_SEND_CMD:
3592 
3593 	rtsx_init_cmd(chip);
3594 
3595 	rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, 0x40 | cmd_idx);
3596 	rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF, (u8)(arg >> 24));
3597 	rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF, (u8)(arg >> 16));
3598 	rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF, (u8)(arg >> 8));
3599 	rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF, (u8)arg);
3600 
3601 	rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, rsp_type);
3602 	rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
3603 		     0x01, PINGPONG_BUFFER);
3604 	rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER,
3605 		     0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START);
3606 	rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END,
3607 		     SD_TRANSFER_END);
3608 
3609 	if (rsp_type == SD_RSP_TYPE_R2) {
3610 		for (reg_addr = PPBUF_BASE2; reg_addr < PPBUF_BASE2 + 16;
3611 		     reg_addr++)
3612 			rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);
3613 
3614 		stat_idx = 17;
3615 	} else if (rsp_type != SD_RSP_TYPE_R0) {
3616 		for (reg_addr = REG_SD_CMD0; reg_addr <= REG_SD_CMD4;
3617 		     reg_addr++)
3618 			rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);
3619 
3620 		stat_idx = 6;
3621 	}
3622 	rtsx_add_cmd(chip, READ_REG_CMD, REG_SD_CMD5, 0, 0);
3623 
3624 	rtsx_add_cmd(chip, READ_REG_CMD, REG_SD_STAT1, 0, 0);
3625 
3626 	retval = rtsx_send_cmd(chip, SD_CARD, timeout);
3627 	if (retval < 0) {
3628 		if (retval == -ETIMEDOUT) {
3629 			rtsx_clear_sd_error(chip);
3630 
3631 			if (rsp_type & SD_WAIT_BUSY_END) {
3632 				retval = sd_check_data0_status(chip);
3633 				if (retval != STATUS_SUCCESS)
3634 					return retval;
3635 			} else {
3636 				sd_set_err_code(chip, SD_TO_ERR);
3637 			}
3638 		}
3639 		return STATUS_FAIL;
3640 	}
3641 
3642 	if (rsp_type == SD_RSP_TYPE_R0)
3643 		return STATUS_SUCCESS;
3644 
3645 	ptr = rtsx_get_cmd_data(chip) + 1;
3646 
3647 	if ((ptr[0] & 0xC0) != 0) {
3648 		sd_set_err_code(chip, SD_STS_ERR);
3649 		return STATUS_FAIL;
3650 	}
3651 
3652 	if (!(rsp_type & SD_NO_CHECK_CRC7)) {
3653 		if (ptr[stat_idx] & SD_CRC7_ERR) {
3654 			if (cmd_idx == WRITE_MULTIPLE_BLOCK) {
3655 				sd_set_err_code(chip, SD_CRC_ERR);
3656 				return STATUS_FAIL;
3657 			}
3658 			if (rty_cnt < SD_MAX_RETRY_COUNT) {
3659 				wait_timeout(20);
3660 				rty_cnt++;
3661 				goto RTY_SEND_CMD;
3662 			} else {
3663 				sd_set_err_code(chip, SD_CRC_ERR);
3664 				return STATUS_FAIL;
3665 			}
3666 		}
3667 	}
3668 
3669 	if (cmd_idx == SELECT_CARD || cmd_idx == APP_CMD ||
3670 	    cmd_idx == SEND_STATUS || cmd_idx == STOP_TRANSMISSION) {
3671 		if (cmd_idx != STOP_TRANSMISSION && !special_check) {
3672 			if (ptr[1] & 0x80)
3673 				return STATUS_FAIL;
3674 		}
3675 #ifdef SUPPORT_SD_LOCK
3676 		if (ptr[1] & 0x7D) {
3677 #else
3678 		if (ptr[1] & 0x7F) {
3679 #endif
3680 			return STATUS_FAIL;
3681 		}
3682 		if (ptr[2] & 0xF8)
3683 			return STATUS_FAIL;
3684 
3685 		if (cmd_idx == SELECT_CARD) {
3686 			if (rsp_type == SD_RSP_TYPE_R2) {
3687 				if ((ptr[3] & 0x1E) != 0x04)
3688 					return STATUS_FAIL;
3689 			}
3690 		}
3691 	}
3692 
3693 	if (rsp && rsp_len)
3694 		memcpy(rsp, ptr, rsp_len);
3695 
3696 	return STATUS_SUCCESS;
3697 }
3698 
3699 int ext_sd_get_rsp(struct rtsx_chip *chip, int len, u8 *rsp, u8 rsp_type)
3700 {
3701 	int retval, rsp_len;
3702 	u16 reg_addr;
3703 
3704 	if (rsp_type == SD_RSP_TYPE_R0)
3705 		return STATUS_SUCCESS;
3706 
3707 	rtsx_init_cmd(chip);
3708 
3709 	if (rsp_type == SD_RSP_TYPE_R2) {
3710 		for (reg_addr = PPBUF_BASE2; reg_addr < PPBUF_BASE2 + 16;
3711 		     reg_addr++)
3712 			rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0xFF, 0);
3713 
3714 		rsp_len = 17;
3715 	} else if (rsp_type != SD_RSP_TYPE_R0) {
3716 		for (reg_addr = REG_SD_CMD0; reg_addr <= REG_SD_CMD4;
3717 		     reg_addr++)
3718 			rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0xFF, 0);
3719 
3720 		rsp_len = 6;
3721 	}
3722 	rtsx_add_cmd(chip, READ_REG_CMD, REG_SD_CMD5, 0xFF, 0);
3723 
3724 	retval = rtsx_send_cmd(chip, SD_CARD, 100);
3725 	if (retval != STATUS_SUCCESS)
3726 		return STATUS_FAIL;
3727 
3728 	if (rsp) {
3729 		int min_len = (rsp_len < len) ? rsp_len : len;
3730 
3731 		memcpy(rsp, rtsx_get_cmd_data(chip), min_len);
3732 
3733 		dev_dbg(rtsx_dev(chip), "min_len = %d\n", min_len);
3734 		dev_dbg(rtsx_dev(chip), "Response in cmd buf: 0x%x 0x%x 0x%x 0x%x\n",
3735 			rsp[0], rsp[1], rsp[2], rsp[3]);
3736 	}
3737 
3738 	return STATUS_SUCCESS;
3739 }
3740 
3741 int sd_pass_thru_mode(struct scsi_cmnd *srb, struct rtsx_chip *chip)
3742 {
3743 	struct sd_info *sd_card = &chip->sd_card;
3744 	unsigned int lun = SCSI_LUN(srb);
3745 	int len;
3746 	u8 buf[18] = {
3747 		0x00,
3748 		0x00,
3749 		0x00,
3750 		0x0E,
3751 		0x00,
3752 		0x00,
3753 		0x00,
3754 		0x00,
3755 		0x53,
3756 		0x44,
3757 		0x20,
3758 		0x43,
3759 		0x61,
3760 		0x72,
3761 		0x64,
3762 		0x00,
3763 		0x00,
3764 		0x00,
3765 	};
3766 
3767 	sd_card->pre_cmd_err = 0;
3768 
3769 	if (!(CHK_BIT(chip->lun_mc, lun))) {
3770 		SET_BIT(chip->lun_mc, lun);
3771 		set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
3772 		return TRANSPORT_FAILED;
3773 	}
3774 
3775 	if (srb->cmnd[2] != 0x53 || srb->cmnd[3] != 0x44 ||
3776 	    srb->cmnd[4] != 0x20 || srb->cmnd[5] != 0x43 ||
3777 	    srb->cmnd[6] != 0x61 || srb->cmnd[7] != 0x72 ||
3778 	    srb->cmnd[8] != 0x64) {
3779 		set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
3780 		return TRANSPORT_FAILED;
3781 	}
3782 
3783 	switch (srb->cmnd[1] & 0x0F) {
3784 	case 0:
3785 		sd_card->sd_pass_thru_en = 0;
3786 		break;
3787 
3788 	case 1:
3789 		sd_card->sd_pass_thru_en = 1;
3790 		break;
3791 
3792 	default:
3793 		set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
3794 		return TRANSPORT_FAILED;
3795 	}
3796 
3797 	buf[5] = (CHK_SD(sd_card) == 1) ? 0x01 : 0x02;
3798 	if (chip->card_wp & SD_CARD)
3799 		buf[5] |= 0x80;
3800 
3801 	buf[6] = (u8)(sd_card->sd_addr >> 16);
3802 	buf[7] = (u8)(sd_card->sd_addr >> 24);
3803 
3804 	buf[15] = chip->max_lun;
3805 
3806 	len = min_t(int, 18, scsi_bufflen(srb));
3807 	rtsx_stor_set_xfer_buf(buf, len, srb);
3808 
3809 	return TRANSPORT_GOOD;
3810 }
3811 
3812 static inline int get_rsp_type(struct scsi_cmnd *srb, u8 *rsp_type,
3813 			       int *rsp_len)
3814 {
3815 	if (!rsp_type || !rsp_len)
3816 		return STATUS_FAIL;
3817 
3818 	switch (srb->cmnd[10]) {
3819 	case 0x03:
3820 		*rsp_type = SD_RSP_TYPE_R0;
3821 		*rsp_len = 0;
3822 		break;
3823 
3824 	case 0x04:
3825 		*rsp_type = SD_RSP_TYPE_R1;
3826 		*rsp_len = 6;
3827 		break;
3828 
3829 	case 0x05:
3830 		*rsp_type = SD_RSP_TYPE_R1b;
3831 		*rsp_len = 6;
3832 		break;
3833 
3834 	case 0x06:
3835 		*rsp_type = SD_RSP_TYPE_R2;
3836 		*rsp_len = 17;
3837 		break;
3838 
3839 	case 0x07:
3840 		*rsp_type = SD_RSP_TYPE_R3;
3841 		*rsp_len = 6;
3842 		break;
3843 
3844 	default:
3845 		return STATUS_FAIL;
3846 	}
3847 
3848 	return STATUS_SUCCESS;
3849 }
3850 
3851 int sd_execute_no_data(struct scsi_cmnd *srb, struct rtsx_chip *chip)
3852 {
3853 	struct sd_info *sd_card = &chip->sd_card;
3854 	unsigned int lun = SCSI_LUN(srb);
3855 	int retval, rsp_len;
3856 	u8 cmd_idx, rsp_type;
3857 	bool standby = false, acmd = false;
3858 	u32 arg;
3859 
3860 	if (!sd_card->sd_pass_thru_en) {
3861 		set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
3862 		return TRANSPORT_FAILED;
3863 	}
3864 
3865 	retval = sd_switch_clock(chip);
3866 	if (retval != STATUS_SUCCESS)
3867 		return TRANSPORT_FAILED;
3868 
3869 	if (sd_card->pre_cmd_err) {
3870 		sd_card->pre_cmd_err = 0;
3871 		set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
3872 		return TRANSPORT_FAILED;
3873 	}
3874 
3875 	cmd_idx = srb->cmnd[2] & 0x3F;
3876 	if (srb->cmnd[1] & 0x02)
3877 		standby = true;
3878 
3879 	if (srb->cmnd[1] & 0x01)
3880 		acmd = true;
3881 
3882 	arg = ((u32)srb->cmnd[3] << 24) | ((u32)srb->cmnd[4] << 16) |
3883 		((u32)srb->cmnd[5] << 8) | srb->cmnd[6];
3884 
3885 	retval = get_rsp_type(srb, &rsp_type, &rsp_len);
3886 	if (retval != STATUS_SUCCESS) {
3887 		set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
3888 		return TRANSPORT_FAILED;
3889 	}
3890 	sd_card->last_rsp_type = rsp_type;
3891 
3892 	retval = sd_switch_clock(chip);
3893 	if (retval != STATUS_SUCCESS)
3894 		return TRANSPORT_FAILED;
3895 
3896 #ifdef SUPPORT_SD_LOCK
3897 	if ((sd_card->sd_lock_status & SD_LOCK_1BIT_MODE) == 0) {
3898 		if (CHK_MMC_8BIT(sd_card)) {
3899 			retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03,
3900 						     SD_BUS_WIDTH_8);
3901 			if (retval != STATUS_SUCCESS)
3902 				return TRANSPORT_FAILED;
3903 
3904 		} else if (CHK_SD(sd_card) || CHK_MMC_4BIT(sd_card)) {
3905 			retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03,
3906 						     SD_BUS_WIDTH_4);
3907 			if (retval != STATUS_SUCCESS)
3908 				return TRANSPORT_FAILED;
3909 		}
3910 	}
3911 #else
3912 	retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_4);
3913 	if (retval != STATUS_SUCCESS)
3914 		return TRANSPORT_FAILED;
3915 #endif
3916 
3917 	if (standby) {
3918 		retval = sd_select_card(chip, 0);
3919 		if (retval != STATUS_SUCCESS)
3920 			goto sd_execute_cmd_failed;
3921 	}
3922 
3923 	if (acmd) {
3924 		retval = ext_sd_send_cmd_get_rsp(chip, APP_CMD,
3925 						 sd_card->sd_addr,
3926 						 SD_RSP_TYPE_R1, NULL, 0,
3927 						 false);
3928 		if (retval != STATUS_SUCCESS)
3929 			goto sd_execute_cmd_failed;
3930 	}
3931 
3932 	retval = ext_sd_send_cmd_get_rsp(chip, cmd_idx, arg, rsp_type,
3933 					 sd_card->rsp, rsp_len, false);
3934 	if (retval != STATUS_SUCCESS)
3935 		goto sd_execute_cmd_failed;
3936 
3937 	if (standby) {
3938 		retval = sd_select_card(chip, 1);
3939 		if (retval != STATUS_SUCCESS)
3940 			goto sd_execute_cmd_failed;
3941 	}
3942 
3943 #ifdef SUPPORT_SD_LOCK
3944 	retval = sd_update_lock_status(chip);
3945 	if (retval != STATUS_SUCCESS)
3946 		goto sd_execute_cmd_failed;
3947 #endif
3948 
3949 	scsi_set_resid(srb, 0);
3950 	return TRANSPORT_GOOD;
3951 
3952 sd_execute_cmd_failed:
3953 	sd_card->pre_cmd_err = 1;
3954 	set_sense_type(chip, lun, SENSE_TYPE_NO_SENSE);
3955 	release_sd_card(chip);
3956 	do_reset_sd_card(chip);
3957 	if (!(chip->card_ready & SD_CARD))
3958 		set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
3959 
3960 	return TRANSPORT_FAILED;
3961 }
3962 
3963 int sd_execute_read_data(struct scsi_cmnd *srb, struct rtsx_chip *chip)
3964 {
3965 	struct sd_info *sd_card = &chip->sd_card;
3966 	unsigned int lun = SCSI_LUN(srb);
3967 	int retval, rsp_len, i;
3968 	bool read_err = false, cmd13_checkbit = false;
3969 	u8 cmd_idx, rsp_type, bus_width;
3970 	bool standby = false, send_cmd12 = false, acmd = false;
3971 	u32 data_len;
3972 
3973 	if (!sd_card->sd_pass_thru_en) {
3974 		set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
3975 		return TRANSPORT_FAILED;
3976 	}
3977 
3978 	if (sd_card->pre_cmd_err) {
3979 		sd_card->pre_cmd_err = 0;
3980 		set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
3981 		return TRANSPORT_FAILED;
3982 	}
3983 
3984 	retval = sd_switch_clock(chip);
3985 	if (retval != STATUS_SUCCESS)
3986 		return TRANSPORT_FAILED;
3987 
3988 	cmd_idx = srb->cmnd[2] & 0x3F;
3989 	if (srb->cmnd[1] & 0x04)
3990 		send_cmd12 = true;
3991 
3992 	if (srb->cmnd[1] & 0x02)
3993 		standby = true;
3994 
3995 	if (srb->cmnd[1] & 0x01)
3996 		acmd = true;
3997 
3998 	data_len = ((u32)srb->cmnd[7] << 16) | ((u32)srb->cmnd[8]
3999 						<< 8) | srb->cmnd[9];
4000 
4001 	retval = get_rsp_type(srb, &rsp_type, &rsp_len);
4002 	if (retval != STATUS_SUCCESS) {
4003 		set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4004 		return TRANSPORT_FAILED;
4005 	}
4006 	sd_card->last_rsp_type = rsp_type;
4007 
4008 	retval = sd_switch_clock(chip);
4009 	if (retval != STATUS_SUCCESS)
4010 		return TRANSPORT_FAILED;
4011 
4012 #ifdef SUPPORT_SD_LOCK
4013 	if ((sd_card->sd_lock_status & SD_LOCK_1BIT_MODE) == 0) {
4014 		if (CHK_MMC_8BIT(sd_card))
4015 			bus_width = SD_BUS_WIDTH_8;
4016 		else if (CHK_SD(sd_card) || CHK_MMC_4BIT(sd_card))
4017 			bus_width = SD_BUS_WIDTH_4;
4018 		else
4019 			bus_width = SD_BUS_WIDTH_1;
4020 	} else {
4021 		bus_width = SD_BUS_WIDTH_4;
4022 	}
4023 	dev_dbg(rtsx_dev(chip), "bus_width = %d\n", bus_width);
4024 #else
4025 	bus_width = SD_BUS_WIDTH_4;
4026 #endif
4027 
4028 	if (data_len < 512) {
4029 		retval = ext_sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, data_len,
4030 						 SD_RSP_TYPE_R1, NULL, 0,
4031 						 false);
4032 		if (retval != STATUS_SUCCESS)
4033 			goto sd_execute_read_cmd_failed;
4034 	}
4035 
4036 	if (standby) {
4037 		retval = sd_select_card(chip, 0);
4038 		if (retval != STATUS_SUCCESS)
4039 			goto sd_execute_read_cmd_failed;
4040 	}
4041 
4042 	if (acmd) {
4043 		retval = ext_sd_send_cmd_get_rsp(chip, APP_CMD,
4044 						 sd_card->sd_addr,
4045 						 SD_RSP_TYPE_R1, NULL, 0,
4046 						 false);
4047 		if (retval != STATUS_SUCCESS)
4048 			goto sd_execute_read_cmd_failed;
4049 	}
4050 
4051 	if (data_len <= 512) {
4052 		int min_len;
4053 		u8 *buf;
4054 		u16 byte_cnt, blk_cnt;
4055 		u8 cmd[5];
4056 
4057 		byte_cnt = ((u16)(srb->cmnd[8] & 0x03) << 8) | srb->cmnd[9];
4058 		blk_cnt = 1;
4059 
4060 		cmd[0] = 0x40 | cmd_idx;
4061 		cmd[1] = srb->cmnd[3];
4062 		cmd[2] = srb->cmnd[4];
4063 		cmd[3] = srb->cmnd[5];
4064 		cmd[4] = srb->cmnd[6];
4065 
4066 		buf = kmalloc(data_len, GFP_KERNEL);
4067 		if (!buf)
4068 			return TRANSPORT_ERROR;
4069 
4070 		retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, byte_cnt,
4071 				      blk_cnt, bus_width, buf, data_len, 2000);
4072 		if (retval != STATUS_SUCCESS) {
4073 			read_err = true;
4074 			kfree(buf);
4075 			rtsx_clear_sd_error(chip);
4076 			goto sd_execute_read_cmd_failed;
4077 		}
4078 
4079 		min_len = min(data_len, scsi_bufflen(srb));
4080 		rtsx_stor_set_xfer_buf(buf, min_len, srb);
4081 
4082 		kfree(buf);
4083 	} else if (!(data_len & 0x1FF)) {
4084 		rtsx_init_cmd(chip);
4085 
4086 		trans_dma_enable(DMA_FROM_DEVICE, chip, data_len, DMA_512);
4087 
4088 		rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF,
4089 			     0x02);
4090 		rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF,
4091 			     0x00);
4092 		rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H,
4093 			     0xFF, (srb->cmnd[7] & 0xFE) >> 1);
4094 		rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L,
4095 			     0xFF, (u8)((data_len & 0x0001FE00) >> 9));
4096 
4097 		rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF,
4098 			     0x40 | cmd_idx);
4099 		rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF,
4100 			     srb->cmnd[3]);
4101 		rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF,
4102 			     srb->cmnd[4]);
4103 		rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF,
4104 			     srb->cmnd[5]);
4105 		rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF,
4106 			     srb->cmnd[6]);
4107 
4108 		rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 0x03, bus_width);
4109 		rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, rsp_type);
4110 
4111 		rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER,
4112 			     0xFF, SD_TM_AUTO_READ_2 | SD_TRANSFER_START);
4113 		rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER,
4114 			     SD_TRANSFER_END, SD_TRANSFER_END);
4115 
4116 		rtsx_send_cmd_no_wait(chip);
4117 
4118 		retval = rtsx_transfer_data(chip, SD_CARD, scsi_sglist(srb),
4119 					    scsi_bufflen(srb),
4120 					    scsi_sg_count(srb),
4121 					    DMA_FROM_DEVICE, 10000);
4122 		if (retval < 0) {
4123 			read_err = true;
4124 			rtsx_clear_sd_error(chip);
4125 			goto sd_execute_read_cmd_failed;
4126 		}
4127 
4128 	} else {
4129 		goto sd_execute_read_cmd_failed;
4130 	}
4131 
4132 	retval = ext_sd_get_rsp(chip, rsp_len, sd_card->rsp, rsp_type);
4133 	if (retval != STATUS_SUCCESS)
4134 		goto sd_execute_read_cmd_failed;
4135 
4136 	if (standby) {
4137 		retval = sd_select_card(chip, 1);
4138 		if (retval != STATUS_SUCCESS)
4139 			goto sd_execute_read_cmd_failed;
4140 	}
4141 
4142 	if (send_cmd12) {
4143 		retval = ext_sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION, 0,
4144 						 SD_RSP_TYPE_R1b, NULL, 0,
4145 						 false);
4146 		if (retval != STATUS_SUCCESS)
4147 			goto sd_execute_read_cmd_failed;
4148 	}
4149 
4150 	if (data_len < 512) {
4151 		retval = ext_sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, 0x200,
4152 						 SD_RSP_TYPE_R1, NULL, 0,
4153 						 false);
4154 		if (retval != STATUS_SUCCESS)
4155 			goto sd_execute_read_cmd_failed;
4156 
4157 		retval = rtsx_write_register(chip, SD_BYTE_CNT_H, 0xFF, 0x02);
4158 		if (retval != STATUS_SUCCESS)
4159 			goto sd_execute_read_cmd_failed;
4160 
4161 		retval = rtsx_write_register(chip, SD_BYTE_CNT_L, 0xFF, 0x00);
4162 		if (retval != STATUS_SUCCESS)
4163 			goto sd_execute_read_cmd_failed;
4164 	}
4165 
4166 	if ((srb->cmnd[1] & 0x02) || (srb->cmnd[1] & 0x04))
4167 		cmd13_checkbit = true;
4168 
4169 	for (i = 0; i < 3; i++) {
4170 		retval = ext_sd_send_cmd_get_rsp(chip, SEND_STATUS,
4171 						 sd_card->sd_addr,
4172 						SD_RSP_TYPE_R1, NULL, 0,
4173 						cmd13_checkbit);
4174 		if (retval == STATUS_SUCCESS)
4175 			break;
4176 	}
4177 	if (retval != STATUS_SUCCESS)
4178 		goto sd_execute_read_cmd_failed;
4179 
4180 	scsi_set_resid(srb, 0);
4181 	return TRANSPORT_GOOD;
4182 
4183 sd_execute_read_cmd_failed:
4184 	sd_card->pre_cmd_err = 1;
4185 	set_sense_type(chip, lun, SENSE_TYPE_NO_SENSE);
4186 	if (read_err)
4187 		set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
4188 
4189 	release_sd_card(chip);
4190 	do_reset_sd_card(chip);
4191 	if (!(chip->card_ready & SD_CARD))
4192 		set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
4193 
4194 	return TRANSPORT_FAILED;
4195 }
4196 
4197 int sd_execute_write_data(struct scsi_cmnd *srb, struct rtsx_chip *chip)
4198 {
4199 	struct sd_info *sd_card = &chip->sd_card;
4200 	unsigned int lun = SCSI_LUN(srb);
4201 	int retval, rsp_len, i;
4202 	bool write_err = false, cmd13_checkbit = false;
4203 	u8 cmd_idx, rsp_type;
4204 	bool standby = false, send_cmd12 = false, acmd = false;
4205 	u32 data_len, arg;
4206 #ifdef SUPPORT_SD_LOCK
4207 	int lock_cmd_fail = 0;
4208 	u8 sd_lock_state = 0;
4209 	u8 lock_cmd_type = 0;
4210 #endif
4211 
4212 	if (!sd_card->sd_pass_thru_en) {
4213 		set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4214 		return TRANSPORT_FAILED;
4215 	}
4216 
4217 	if (sd_card->pre_cmd_err) {
4218 		sd_card->pre_cmd_err = 0;
4219 		set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
4220 		return TRANSPORT_FAILED;
4221 	}
4222 
4223 	retval = sd_switch_clock(chip);
4224 	if (retval != STATUS_SUCCESS)
4225 		return TRANSPORT_FAILED;
4226 
4227 	cmd_idx = srb->cmnd[2] & 0x3F;
4228 	if (srb->cmnd[1] & 0x04)
4229 		send_cmd12 = true;
4230 
4231 	if (srb->cmnd[1] & 0x02)
4232 		standby = true;
4233 
4234 	if (srb->cmnd[1] & 0x01)
4235 		acmd = true;
4236 
4237 	data_len = ((u32)srb->cmnd[7] << 16) | ((u32)srb->cmnd[8]
4238 						<< 8) | srb->cmnd[9];
4239 	arg = ((u32)srb->cmnd[3] << 24) | ((u32)srb->cmnd[4] << 16) |
4240 		((u32)srb->cmnd[5] << 8) | srb->cmnd[6];
4241 
4242 #ifdef SUPPORT_SD_LOCK
4243 	if (cmd_idx == LOCK_UNLOCK) {
4244 		sd_lock_state = sd_card->sd_lock_status;
4245 		sd_lock_state &= SD_LOCKED;
4246 	}
4247 #endif
4248 
4249 	retval = get_rsp_type(srb, &rsp_type, &rsp_len);
4250 	if (retval != STATUS_SUCCESS) {
4251 		set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4252 		return TRANSPORT_FAILED;
4253 	}
4254 	sd_card->last_rsp_type = rsp_type;
4255 
4256 	retval = sd_switch_clock(chip);
4257 	if (retval != STATUS_SUCCESS)
4258 		return TRANSPORT_FAILED;
4259 
4260 #ifdef SUPPORT_SD_LOCK
4261 	if ((sd_card->sd_lock_status & SD_LOCK_1BIT_MODE) == 0) {
4262 		if (CHK_MMC_8BIT(sd_card)) {
4263 			retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03,
4264 						     SD_BUS_WIDTH_8);
4265 			if (retval != STATUS_SUCCESS)
4266 				return TRANSPORT_FAILED;
4267 
4268 		} else if (CHK_SD(sd_card) || CHK_MMC_4BIT(sd_card)) {
4269 			retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03,
4270 						     SD_BUS_WIDTH_4);
4271 			if (retval != STATUS_SUCCESS)
4272 				return TRANSPORT_FAILED;
4273 		}
4274 	}
4275 #else
4276 	retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_4);
4277 	if (retval != STATUS_SUCCESS)
4278 		return TRANSPORT_FAILED;
4279 #endif
4280 
4281 	if (data_len < 512) {
4282 		retval = ext_sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, data_len,
4283 						 SD_RSP_TYPE_R1, NULL, 0,
4284 						 false);
4285 		if (retval != STATUS_SUCCESS)
4286 			goto sd_execute_write_cmd_failed;
4287 	}
4288 
4289 	if (standby) {
4290 		retval = sd_select_card(chip, 0);
4291 		if (retval != STATUS_SUCCESS)
4292 			goto sd_execute_write_cmd_failed;
4293 	}
4294 
4295 	if (acmd) {
4296 		retval = ext_sd_send_cmd_get_rsp(chip, APP_CMD,
4297 						 sd_card->sd_addr,
4298 						 SD_RSP_TYPE_R1, NULL, 0,
4299 						 false);
4300 		if (retval != STATUS_SUCCESS)
4301 			goto sd_execute_write_cmd_failed;
4302 	}
4303 
4304 	retval = ext_sd_send_cmd_get_rsp(chip, cmd_idx, arg, rsp_type,
4305 					 sd_card->rsp, rsp_len, false);
4306 	if (retval != STATUS_SUCCESS)
4307 		goto sd_execute_write_cmd_failed;
4308 
4309 	if (data_len <= 512) {
4310 		u16 i;
4311 		u8 *buf;
4312 
4313 		buf = kmalloc(data_len, GFP_KERNEL);
4314 		if (!buf)
4315 			return TRANSPORT_ERROR;
4316 
4317 		rtsx_stor_get_xfer_buf(buf, data_len, srb);
4318 
4319 #ifdef SUPPORT_SD_LOCK
4320 		if (cmd_idx == LOCK_UNLOCK)
4321 			lock_cmd_type = buf[0] & 0x0F;
4322 #endif
4323 
4324 		if (data_len > 256) {
4325 			rtsx_init_cmd(chip);
4326 			for (i = 0; i < 256; i++) {
4327 				rtsx_add_cmd(chip, WRITE_REG_CMD,
4328 					     PPBUF_BASE2 + i, 0xFF, buf[i]);
4329 			}
4330 			retval = rtsx_send_cmd(chip, 0, 250);
4331 			if (retval != STATUS_SUCCESS) {
4332 				kfree(buf);
4333 				goto sd_execute_write_cmd_failed;
4334 			}
4335 
4336 			rtsx_init_cmd(chip);
4337 			for (i = 256; i < data_len; i++) {
4338 				rtsx_add_cmd(chip, WRITE_REG_CMD,
4339 					     PPBUF_BASE2 + i, 0xFF, buf[i]);
4340 			}
4341 			retval = rtsx_send_cmd(chip, 0, 250);
4342 			if (retval != STATUS_SUCCESS) {
4343 				kfree(buf);
4344 				goto sd_execute_write_cmd_failed;
4345 			}
4346 		} else {
4347 			rtsx_init_cmd(chip);
4348 			for (i = 0; i < data_len; i++) {
4349 				rtsx_add_cmd(chip, WRITE_REG_CMD,
4350 					     PPBUF_BASE2 + i, 0xFF, buf[i]);
4351 			}
4352 			retval = rtsx_send_cmd(chip, 0, 250);
4353 			if (retval != STATUS_SUCCESS) {
4354 				kfree(buf);
4355 				goto sd_execute_write_cmd_failed;
4356 			}
4357 		}
4358 
4359 		kfree(buf);
4360 
4361 		rtsx_init_cmd(chip);
4362 
4363 		rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF,
4364 			     srb->cmnd[8] & 0x03);
4365 		rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF,
4366 			     srb->cmnd[9]);
4367 		rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF,
4368 			     0x00);
4369 		rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF,
4370 			     0x01);
4371 		rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
4372 			     PINGPONG_BUFFER);
4373 
4374 		rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
4375 			     SD_TM_AUTO_WRITE_3 | SD_TRANSFER_START);
4376 		rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER,
4377 			     SD_TRANSFER_END, SD_TRANSFER_END);
4378 
4379 		retval = rtsx_send_cmd(chip, SD_CARD, 250);
4380 	} else if (!(data_len & 0x1FF)) {
4381 		rtsx_init_cmd(chip);
4382 
4383 		trans_dma_enable(DMA_TO_DEVICE, chip, data_len, DMA_512);
4384 
4385 		rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF,
4386 			     0x02);
4387 		rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF,
4388 			     0x00);
4389 		rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H,
4390 			     0xFF, (srb->cmnd[7] & 0xFE) >> 1);
4391 		rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L,
4392 			     0xFF, (u8)((data_len & 0x0001FE00) >> 9));
4393 
4394 		rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
4395 			     SD_TM_AUTO_WRITE_3 | SD_TRANSFER_START);
4396 		rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER,
4397 			     SD_TRANSFER_END, SD_TRANSFER_END);
4398 
4399 		rtsx_send_cmd_no_wait(chip);
4400 
4401 		retval = rtsx_transfer_data(chip, SD_CARD, scsi_sglist(srb),
4402 					    scsi_bufflen(srb),
4403 					    scsi_sg_count(srb),
4404 					    DMA_TO_DEVICE, 10000);
4405 
4406 	} else {
4407 		goto sd_execute_write_cmd_failed;
4408 	}
4409 
4410 	if (retval < 0) {
4411 		write_err = true;
4412 		rtsx_clear_sd_error(chip);
4413 		goto sd_execute_write_cmd_failed;
4414 	}
4415 
4416 #ifdef SUPPORT_SD_LOCK
4417 	if (cmd_idx == LOCK_UNLOCK) {
4418 		if (lock_cmd_type == SD_ERASE) {
4419 			sd_card->sd_erase_status = SD_UNDER_ERASING;
4420 			scsi_set_resid(srb, 0);
4421 			return TRANSPORT_GOOD;
4422 		}
4423 
4424 		rtsx_init_cmd(chip);
4425 		rtsx_add_cmd(chip, CHECK_REG_CMD, 0xFD30, 0x02, 0x02);
4426 
4427 		retval = rtsx_send_cmd(chip, SD_CARD, 250);
4428 		if (retval < 0) {
4429 			write_err = true;
4430 			rtsx_clear_sd_error(chip);
4431 			goto sd_execute_write_cmd_failed;
4432 		}
4433 
4434 		retval = sd_update_lock_status(chip);
4435 		if (retval != STATUS_SUCCESS) {
4436 			dev_dbg(rtsx_dev(chip), "Lock command fail!\n");
4437 			lock_cmd_fail = 1;
4438 		}
4439 	}
4440 #endif /* SUPPORT_SD_LOCK */
4441 
4442 	if (standby) {
4443 		retval = sd_select_card(chip, 1);
4444 		if (retval != STATUS_SUCCESS)
4445 			goto sd_execute_write_cmd_failed;
4446 	}
4447 
4448 	if (send_cmd12) {
4449 		retval = ext_sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION, 0,
4450 						 SD_RSP_TYPE_R1b, NULL, 0,
4451 						 false);
4452 		if (retval != STATUS_SUCCESS)
4453 			goto sd_execute_write_cmd_failed;
4454 	}
4455 
4456 	if (data_len < 512) {
4457 		retval = ext_sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, 0x200,
4458 						 SD_RSP_TYPE_R1, NULL, 0,
4459 						 false);
4460 		if (retval != STATUS_SUCCESS)
4461 			goto sd_execute_write_cmd_failed;
4462 
4463 		retval = rtsx_write_register(chip, SD_BYTE_CNT_H, 0xFF, 0x02);
4464 		if (retval != STATUS_SUCCESS)
4465 			goto sd_execute_write_cmd_failed;
4466 
4467 		retval = rtsx_write_register(chip, SD_BYTE_CNT_L, 0xFF, 0x00);
4468 		if (retval != STATUS_SUCCESS)
4469 			goto sd_execute_write_cmd_failed;
4470 	}
4471 
4472 	if ((srb->cmnd[1] & 0x02) || (srb->cmnd[1] & 0x04))
4473 		cmd13_checkbit = true;
4474 
4475 	for (i = 0; i < 3; i++) {
4476 		retval = ext_sd_send_cmd_get_rsp(chip, SEND_STATUS,
4477 						 sd_card->sd_addr,
4478 						 SD_RSP_TYPE_R1, NULL, 0,
4479 						 cmd13_checkbit);
4480 		if (retval == STATUS_SUCCESS)
4481 			break;
4482 	}
4483 	if (retval != STATUS_SUCCESS)
4484 		goto sd_execute_write_cmd_failed;
4485 
4486 #ifdef SUPPORT_SD_LOCK
4487 	if (cmd_idx == LOCK_UNLOCK) {
4488 		if (!lock_cmd_fail) {
4489 			dev_dbg(rtsx_dev(chip), "lock_cmd_type = 0x%x\n",
4490 				lock_cmd_type);
4491 			if (lock_cmd_type & SD_CLR_PWD)
4492 				sd_card->sd_lock_status &= ~SD_PWD_EXIST;
4493 
4494 			if (lock_cmd_type & SD_SET_PWD)
4495 				sd_card->sd_lock_status |= SD_PWD_EXIST;
4496 		}
4497 
4498 		dev_dbg(rtsx_dev(chip), "sd_lock_state = 0x%x, sd_card->sd_lock_status = 0x%x\n",
4499 			sd_lock_state, sd_card->sd_lock_status);
4500 		if (sd_lock_state ^ (sd_card->sd_lock_status & SD_LOCKED)) {
4501 			sd_card->sd_lock_notify = 1;
4502 			if (sd_lock_state &&
4503 			    (sd_card->sd_lock_status & SD_LOCK_1BIT_MODE)) {
4504 				sd_card->sd_lock_status |= (SD_UNLOCK_POW_ON | SD_SDR_RST);
4505 				if (CHK_SD(sd_card)) {
4506 					retval = reset_sd(chip);
4507 					if (retval != STATUS_SUCCESS) {
4508 						sd_card->sd_lock_status &=
4509 							~(SD_UNLOCK_POW_ON | SD_SDR_RST);
4510 						goto sd_execute_write_cmd_failed;
4511 					}
4512 				}
4513 
4514 				sd_card->sd_lock_status &= ~(SD_UNLOCK_POW_ON | SD_SDR_RST);
4515 			}
4516 		}
4517 	}
4518 
4519 	if (lock_cmd_fail) {
4520 		scsi_set_resid(srb, 0);
4521 		set_sense_type(chip, lun, SENSE_TYPE_NO_SENSE);
4522 		return TRANSPORT_FAILED;
4523 	}
4524 #endif  /* SUPPORT_SD_LOCK */
4525 
4526 	scsi_set_resid(srb, 0);
4527 	return TRANSPORT_GOOD;
4528 
4529 sd_execute_write_cmd_failed:
4530 	sd_card->pre_cmd_err = 1;
4531 	set_sense_type(chip, lun, SENSE_TYPE_NO_SENSE);
4532 	if (write_err)
4533 		set_sense_type(chip, lun, SENSE_TYPE_MEDIA_WRITE_ERR);
4534 
4535 	release_sd_card(chip);
4536 	do_reset_sd_card(chip);
4537 	if (!(chip->card_ready & SD_CARD))
4538 		set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
4539 
4540 	return TRANSPORT_FAILED;
4541 }
4542 
4543 int sd_get_cmd_rsp(struct scsi_cmnd *srb, struct rtsx_chip *chip)
4544 {
4545 	struct sd_info *sd_card = &chip->sd_card;
4546 	unsigned int lun = SCSI_LUN(srb);
4547 	int count;
4548 	u16 data_len;
4549 
4550 	if (!sd_card->sd_pass_thru_en) {
4551 		set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4552 		return TRANSPORT_FAILED;
4553 	}
4554 
4555 	if (sd_card->pre_cmd_err) {
4556 		sd_card->pre_cmd_err = 0;
4557 		set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
4558 		return TRANSPORT_FAILED;
4559 	}
4560 
4561 	data_len = ((u16)srb->cmnd[7] << 8) | srb->cmnd[8];
4562 
4563 	if (sd_card->last_rsp_type == SD_RSP_TYPE_R0) {
4564 		set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4565 		return TRANSPORT_FAILED;
4566 	} else if (sd_card->last_rsp_type == SD_RSP_TYPE_R2) {
4567 		count = (data_len < 17) ? data_len : 17;
4568 	} else {
4569 		count = (data_len < 6) ? data_len : 6;
4570 	}
4571 	rtsx_stor_set_xfer_buf(sd_card->rsp, count, srb);
4572 
4573 	dev_dbg(rtsx_dev(chip), "Response length: %d\n", data_len);
4574 	dev_dbg(rtsx_dev(chip), "Response: 0x%x 0x%x 0x%x 0x%x\n",
4575 		sd_card->rsp[0], sd_card->rsp[1],
4576 		sd_card->rsp[2], sd_card->rsp[3]);
4577 
4578 	scsi_set_resid(srb, 0);
4579 	return TRANSPORT_GOOD;
4580 }
4581 
4582 int sd_hw_rst(struct scsi_cmnd *srb, struct rtsx_chip *chip)
4583 {
4584 	struct sd_info *sd_card = &chip->sd_card;
4585 	unsigned int lun = SCSI_LUN(srb);
4586 	int retval;
4587 
4588 	if (!sd_card->sd_pass_thru_en) {
4589 		set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4590 		return TRANSPORT_FAILED;
4591 	}
4592 
4593 	if (sd_card->pre_cmd_err) {
4594 		sd_card->pre_cmd_err = 0;
4595 		set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
4596 		return TRANSPORT_FAILED;
4597 	}
4598 
4599 	if (srb->cmnd[2] != 0x53 || srb->cmnd[3] != 0x44 ||
4600 	    srb->cmnd[4] != 0x20 || srb->cmnd[5] != 0x43 ||
4601 	    srb->cmnd[6] != 0x61 || srb->cmnd[7] != 0x72 ||
4602 	    srb->cmnd[8] != 0x64) {
4603 		set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4604 		return TRANSPORT_FAILED;
4605 	}
4606 
4607 	switch (srb->cmnd[1] & 0x0F) {
4608 	case 0:
4609 #ifdef SUPPORT_SD_LOCK
4610 		if (srb->cmnd[9] == 0x64)
4611 			sd_card->sd_lock_status |= SD_SDR_RST;
4612 #endif
4613 		retval = reset_sd_card(chip);
4614 		if (retval != STATUS_SUCCESS) {
4615 #ifdef SUPPORT_SD_LOCK
4616 			sd_card->sd_lock_status &= ~SD_SDR_RST;
4617 #endif
4618 			set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
4619 			sd_card->pre_cmd_err = 1;
4620 			return TRANSPORT_FAILED;
4621 		}
4622 #ifdef SUPPORT_SD_LOCK
4623 		sd_card->sd_lock_status &= ~SD_SDR_RST;
4624 #endif
4625 		break;
4626 
4627 	case 1:
4628 		retval = reset_sd(chip);
4629 		if (retval != STATUS_SUCCESS) {
4630 			set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
4631 			sd_card->pre_cmd_err = 1;
4632 			return TRANSPORT_FAILED;
4633 		}
4634 		break;
4635 
4636 	default:
4637 		set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4638 		return TRANSPORT_FAILED;
4639 	}
4640 
4641 	scsi_set_resid(srb, 0);
4642 	return TRANSPORT_GOOD;
4643 }
4644 #endif
4645 
4646 void sd_cleanup_work(struct rtsx_chip *chip)
4647 {
4648 	struct sd_info *sd_card = &chip->sd_card;
4649 
4650 	if (sd_card->seq_mode) {
4651 		dev_dbg(rtsx_dev(chip), "SD: stop transmission\n");
4652 		sd_stop_seq_mode(chip);
4653 		sd_card->cleanup_counter = 0;
4654 	}
4655 }
4656 
4657 int sd_power_off_card3v3(struct rtsx_chip *chip)
4658 {
4659 	int retval;
4660 
4661 	retval = disable_card_clock(chip, SD_CARD);
4662 	if (retval != STATUS_SUCCESS)
4663 		return STATUS_FAIL;
4664 
4665 	retval = rtsx_write_register(chip, CARD_OE, SD_OUTPUT_EN, 0);
4666 	if (retval)
4667 		return retval;
4668 
4669 	if (!chip->ft2_fast_mode) {
4670 		retval = card_power_off(chip, SD_CARD);
4671 		if (retval != STATUS_SUCCESS)
4672 			return STATUS_FAIL;
4673 
4674 		mdelay(50);
4675 	}
4676 
4677 	if (chip->asic_code) {
4678 		retval = sd_pull_ctl_disable(chip);
4679 		if (retval != STATUS_SUCCESS)
4680 			return STATUS_FAIL;
4681 	} else {
4682 		retval = rtsx_write_register(chip, FPGA_PULL_CTL,
4683 					     FPGA_SD_PULL_CTL_BIT | 0x20,
4684 					     FPGA_SD_PULL_CTL_BIT);
4685 		if (retval)
4686 			return retval;
4687 	}
4688 
4689 	return STATUS_SUCCESS;
4690 }
4691 
4692 int release_sd_card(struct rtsx_chip *chip)
4693 {
4694 	struct sd_info *sd_card = &chip->sd_card;
4695 	int retval;
4696 
4697 	chip->card_ready &= ~SD_CARD;
4698 	chip->card_fail &= ~SD_CARD;
4699 	chip->card_wp &= ~SD_CARD;
4700 
4701 	chip->sd_io = 0;
4702 	chip->sd_int = 0;
4703 
4704 #ifdef SUPPORT_SD_LOCK
4705 	sd_card->sd_lock_status = 0;
4706 	sd_card->sd_erase_status = 0;
4707 #endif
4708 
4709 	memset(sd_card->raw_csd, 0, 16);
4710 	memset(sd_card->raw_scr, 0, 8);
4711 
4712 	retval = sd_power_off_card3v3(chip);
4713 	if (retval != STATUS_SUCCESS)
4714 		return STATUS_FAIL;
4715 
4716 	return STATUS_SUCCESS;
4717 }
4718