1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * drivers/soc/tegra/pmc.c
4  *
5  * Copyright (c) 2010 Google, Inc
6  * Copyright (c) 2018-2023, NVIDIA CORPORATION. All rights reserved.
7  *
8  * Author:
9  *	Colin Cross <ccross@google.com>
10  */
11 
12 #define pr_fmt(fmt) "tegra-pmc: " fmt
13 
14 #include <linux/arm-smccc.h>
15 #include <linux/clk.h>
16 #include <linux/clk-provider.h>
17 #include <linux/clkdev.h>
18 #include <linux/clk/clk-conf.h>
19 #include <linux/clk/tegra.h>
20 #include <linux/debugfs.h>
21 #include <linux/delay.h>
22 #include <linux/device.h>
23 #include <linux/err.h>
24 #include <linux/export.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
27 #include <linux/io.h>
28 #include <linux/iopoll.h>
29 #include <linux/irqdomain.h>
30 #include <linux/irq.h>
31 #include <linux/kernel.h>
32 #include <linux/of_address.h>
33 #include <linux/of_clk.h>
34 #include <linux/of.h>
35 #include <linux/of_irq.h>
36 #include <linux/of_platform.h>
37 #include <linux/pinctrl/pinconf-generic.h>
38 #include <linux/pinctrl/pinconf.h>
39 #include <linux/pinctrl/pinctrl.h>
40 #include <linux/platform_device.h>
41 #include <linux/pm_domain.h>
42 #include <linux/pm_opp.h>
43 #include <linux/power_supply.h>
44 #include <linux/reboot.h>
45 #include <linux/regmap.h>
46 #include <linux/reset.h>
47 #include <linux/seq_file.h>
48 #include <linux/slab.h>
49 #include <linux/spinlock.h>
50 #include <linux/syscore_ops.h>
51 
52 #include <soc/tegra/common.h>
53 #include <soc/tegra/fuse.h>
54 #include <soc/tegra/pmc.h>
55 
56 #include <dt-bindings/interrupt-controller/arm-gic.h>
57 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
58 #include <dt-bindings/gpio/tegra186-gpio.h>
59 #include <dt-bindings/gpio/tegra194-gpio.h>
60 #include <dt-bindings/gpio/tegra234-gpio.h>
61 #include <dt-bindings/soc/tegra-pmc.h>
62 
63 #define PMC_CNTRL			0x0
64 #define  PMC_CNTRL_INTR_POLARITY	BIT(17) /* inverts INTR polarity */
65 #define  PMC_CNTRL_CPU_PWRREQ_OE	BIT(16) /* CPU pwr req enable */
66 #define  PMC_CNTRL_CPU_PWRREQ_POLARITY	BIT(15) /* CPU pwr req polarity */
67 #define  PMC_CNTRL_SIDE_EFFECT_LP0	BIT(14) /* LP0 when CPU pwr gated */
68 #define  PMC_CNTRL_SYSCLK_OE		BIT(11) /* system clock enable */
69 #define  PMC_CNTRL_SYSCLK_POLARITY	BIT(10) /* sys clk polarity */
70 #define  PMC_CNTRL_PWRREQ_POLARITY	BIT(8)
71 #define  PMC_CNTRL_BLINK_EN		7
72 #define  PMC_CNTRL_MAIN_RST		BIT(4)
73 
74 #define PMC_WAKE_MASK			0x0c
75 #define PMC_WAKE_LEVEL			0x10
76 #define PMC_WAKE_STATUS			0x14
77 #define PMC_SW_WAKE_STATUS		0x18
78 #define PMC_DPD_PADS_ORIDE		0x1c
79 #define  PMC_DPD_PADS_ORIDE_BLINK	20
80 
81 #define DPD_SAMPLE			0x020
82 #define  DPD_SAMPLE_ENABLE		BIT(0)
83 #define  DPD_SAMPLE_DISABLE		(0 << 0)
84 
85 #define PWRGATE_TOGGLE			0x30
86 #define  PWRGATE_TOGGLE_START		BIT(8)
87 
88 #define REMOVE_CLAMPING			0x34
89 
90 #define PWRGATE_STATUS			0x38
91 
92 #define PMC_BLINK_TIMER			0x40
93 #define PMC_IMPL_E_33V_PWR		0x40
94 
95 #define PMC_PWR_DET			0x48
96 
97 #define PMC_SCRATCH0_MODE_RECOVERY	BIT(31)
98 #define PMC_SCRATCH0_MODE_BOOTLOADER	BIT(30)
99 #define PMC_SCRATCH0_MODE_RCM		BIT(1)
100 #define PMC_SCRATCH0_MODE_MASK		(PMC_SCRATCH0_MODE_RECOVERY | \
101 					 PMC_SCRATCH0_MODE_BOOTLOADER | \
102 					 PMC_SCRATCH0_MODE_RCM)
103 
104 #define PMC_CPUPWRGOOD_TIMER		0xc8
105 #define PMC_CPUPWROFF_TIMER		0xcc
106 #define PMC_COREPWRGOOD_TIMER		0x3c
107 #define PMC_COREPWROFF_TIMER		0xe0
108 
109 #define PMC_PWR_DET_VALUE		0xe4
110 
111 #define PMC_USB_DEBOUNCE_DEL		0xec
112 #define PMC_USB_AO			0xf0
113 
114 #define PMC_SCRATCH37			0x130
115 #define PMC_SCRATCH41			0x140
116 
117 #define PMC_WAKE2_MASK			0x160
118 #define PMC_WAKE2_LEVEL			0x164
119 #define PMC_WAKE2_STATUS		0x168
120 #define PMC_SW_WAKE2_STATUS		0x16c
121 
122 #define PMC_CLK_OUT_CNTRL		0x1a8
123 #define  PMC_CLK_OUT_MUX_MASK		GENMASK(1, 0)
124 #define PMC_SENSOR_CTRL			0x1b0
125 #define  PMC_SENSOR_CTRL_SCRATCH_WRITE	BIT(2)
126 #define  PMC_SENSOR_CTRL_ENABLE_RST	BIT(1)
127 
128 #define  PMC_RST_STATUS_POR		0
129 #define  PMC_RST_STATUS_WATCHDOG	1
130 #define  PMC_RST_STATUS_SENSOR		2
131 #define  PMC_RST_STATUS_SW_MAIN		3
132 #define  PMC_RST_STATUS_LP0		4
133 #define  PMC_RST_STATUS_AOTAG		5
134 
135 #define IO_DPD_REQ			0x1b8
136 #define  IO_DPD_REQ_CODE_IDLE		(0U << 30)
137 #define  IO_DPD_REQ_CODE_OFF		(1U << 30)
138 #define  IO_DPD_REQ_CODE_ON		(2U << 30)
139 #define  IO_DPD_REQ_CODE_MASK		(3U << 30)
140 
141 #define IO_DPD_STATUS			0x1bc
142 #define IO_DPD2_REQ			0x1c0
143 #define IO_DPD2_STATUS			0x1c4
144 #define SEL_DPD_TIM			0x1c8
145 
146 #define PMC_UTMIP_UHSIC_TRIGGERS	0x1ec
147 #define PMC_UTMIP_UHSIC_SAVED_STATE	0x1f0
148 
149 #define PMC_UTMIP_TERM_PAD_CFG		0x1f8
150 #define PMC_UTMIP_UHSIC_SLEEP_CFG	0x1fc
151 #define PMC_UTMIP_UHSIC_FAKE		0x218
152 
153 #define PMC_SCRATCH54			0x258
154 #define  PMC_SCRATCH54_DATA_SHIFT	8
155 #define  PMC_SCRATCH54_ADDR_SHIFT	0
156 
157 #define PMC_SCRATCH55			0x25c
158 #define  PMC_SCRATCH55_RESET_TEGRA	BIT(31)
159 #define  PMC_SCRATCH55_CNTRL_ID_SHIFT	27
160 #define  PMC_SCRATCH55_PINMUX_SHIFT	24
161 #define  PMC_SCRATCH55_16BITOP		BIT(15)
162 #define  PMC_SCRATCH55_CHECKSUM_SHIFT	16
163 #define  PMC_SCRATCH55_I2CSLV1_SHIFT	0
164 
165 #define  PMC_UTMIP_UHSIC_LINE_WAKEUP	0x26c
166 
167 #define PMC_UTMIP_BIAS_MASTER_CNTRL	0x270
168 #define PMC_UTMIP_MASTER_CONFIG		0x274
169 #define PMC_UTMIP_UHSIC2_TRIGGERS	0x27c
170 #define PMC_UTMIP_MASTER2_CONFIG	0x29c
171 
172 #define GPU_RG_CNTRL			0x2d4
173 
174 #define PMC_UTMIP_PAD_CFG0		0x4c0
175 #define PMC_UTMIP_UHSIC_SLEEP_CFG1	0x4d0
176 #define PMC_UTMIP_SLEEPWALK_P3		0x4e0
177 /* Tegra186 and later */
178 #define WAKE_AOWAKE_CNTRL(x) (0x000 + ((x) << 2))
179 #define WAKE_AOWAKE_CNTRL_LEVEL (1 << 3)
180 #define WAKE_AOWAKE_CNTRL_SR_CAPTURE_EN (1 << 1)
181 #define WAKE_AOWAKE_MASK_W(x) (0x180 + ((x) << 2))
182 #define WAKE_AOWAKE_MASK_R(x) (0x300 + ((x) << 2))
183 #define WAKE_AOWAKE_STATUS_W(x) (0x30c + ((x) << 2))
184 #define WAKE_AOWAKE_STATUS_R(x) (0x48c + ((x) << 2))
185 #define WAKE_AOWAKE_TIER0_ROUTING(x) (0x4b4 + ((x) << 2))
186 #define WAKE_AOWAKE_TIER1_ROUTING(x) (0x4c0 + ((x) << 2))
187 #define WAKE_AOWAKE_TIER2_ROUTING(x) (0x4cc + ((x) << 2))
188 #define WAKE_AOWAKE_SW_STATUS_W_0	0x49c
189 #define WAKE_AOWAKE_SW_STATUS(x)	(0x4a0 + ((x) << 2))
190 #define WAKE_LATCH_SW			0x498
191 
192 #define WAKE_AOWAKE_CTRL 0x4f4
193 #define  WAKE_AOWAKE_CTRL_INTR_POLARITY BIT(0)
194 
195 #define SW_WAKE_ID		83 /* wake83 */
196 
197 /* for secure PMC */
198 #define TEGRA_SMC_PMC		0xc2fffe00
199 #define  TEGRA_SMC_PMC_READ	0xaa
200 #define  TEGRA_SMC_PMC_WRITE	0xbb
201 
202 struct pmc_clk {
203 	struct clk_hw	hw;
204 	unsigned long	offs;
205 	u32		mux_shift;
206 	u32		force_en_shift;
207 };
208 
209 #define to_pmc_clk(_hw) container_of(_hw, struct pmc_clk, hw)
210 
211 struct pmc_clk_gate {
212 	struct clk_hw	hw;
213 	unsigned long	offs;
214 	u32		shift;
215 };
216 
217 #define to_pmc_clk_gate(_hw) container_of(_hw, struct pmc_clk_gate, hw)
218 
219 struct pmc_clk_init_data {
220 	char *name;
221 	const char *const *parents;
222 	int num_parents;
223 	int clk_id;
224 	u8 mux_shift;
225 	u8 force_en_shift;
226 };
227 
228 static const char * const clk_out1_parents[] = { "osc", "osc_div2",
229 	"osc_div4", "extern1",
230 };
231 
232 static const char * const clk_out2_parents[] = { "osc", "osc_div2",
233 	"osc_div4", "extern2",
234 };
235 
236 static const char * const clk_out3_parents[] = { "osc", "osc_div2",
237 	"osc_div4", "extern3",
238 };
239 
240 static const struct pmc_clk_init_data tegra_pmc_clks_data[] = {
241 	{
242 		.name = "pmc_clk_out_1",
243 		.parents = clk_out1_parents,
244 		.num_parents = ARRAY_SIZE(clk_out1_parents),
245 		.clk_id = TEGRA_PMC_CLK_OUT_1,
246 		.mux_shift = 6,
247 		.force_en_shift = 2,
248 	},
249 	{
250 		.name = "pmc_clk_out_2",
251 		.parents = clk_out2_parents,
252 		.num_parents = ARRAY_SIZE(clk_out2_parents),
253 		.clk_id = TEGRA_PMC_CLK_OUT_2,
254 		.mux_shift = 14,
255 		.force_en_shift = 10,
256 	},
257 	{
258 		.name = "pmc_clk_out_3",
259 		.parents = clk_out3_parents,
260 		.num_parents = ARRAY_SIZE(clk_out3_parents),
261 		.clk_id = TEGRA_PMC_CLK_OUT_3,
262 		.mux_shift = 22,
263 		.force_en_shift = 18,
264 	},
265 };
266 
267 struct tegra_powergate {
268 	struct generic_pm_domain genpd;
269 	struct tegra_pmc *pmc;
270 	unsigned int id;
271 	struct clk **clks;
272 	unsigned int num_clks;
273 	unsigned long *clk_rates;
274 	struct reset_control *reset;
275 };
276 
277 struct tegra_io_pad_soc {
278 	enum tegra_io_pad id;
279 	unsigned int dpd;
280 	unsigned int request;
281 	unsigned int status;
282 	unsigned int voltage;
283 	const char *name;
284 };
285 
286 struct tegra_pmc_regs {
287 	unsigned int scratch0;
288 	unsigned int rst_status;
289 	unsigned int rst_source_shift;
290 	unsigned int rst_source_mask;
291 	unsigned int rst_level_shift;
292 	unsigned int rst_level_mask;
293 };
294 
295 struct tegra_wake_event {
296 	const char *name;
297 	unsigned int id;
298 	unsigned int irq;
299 	struct {
300 		unsigned int instance;
301 		unsigned int pin;
302 	} gpio;
303 };
304 
305 #define TEGRA_WAKE_SIMPLE(_name, _id)			\
306 	{						\
307 		.name = _name,				\
308 		.id = _id,				\
309 		.irq = 0,				\
310 		.gpio = {				\
311 			.instance = UINT_MAX,		\
312 			.pin = UINT_MAX,		\
313 		},					\
314 	}
315 
316 #define TEGRA_WAKE_IRQ(_name, _id, _irq)		\
317 	{						\
318 		.name = _name,				\
319 		.id = _id,				\
320 		.irq = _irq,				\
321 		.gpio = {				\
322 			.instance = UINT_MAX,		\
323 			.pin = UINT_MAX,		\
324 		},					\
325 	}
326 
327 #define TEGRA_WAKE_GPIO(_name, _id, _instance, _pin)	\
328 	{						\
329 		.name = _name,				\
330 		.id = _id,				\
331 		.irq = 0,				\
332 		.gpio = {				\
333 			.instance = _instance,		\
334 			.pin = _pin,			\
335 		},					\
336 	}
337 
338 struct tegra_pmc_soc {
339 	unsigned int num_powergates;
340 	const char *const *powergates;
341 	unsigned int num_cpu_powergates;
342 	const u8 *cpu_powergates;
343 
344 	bool has_tsense_reset;
345 	bool has_gpu_clamps;
346 	bool needs_mbist_war;
347 	bool has_impl_33v_pwr;
348 	bool maybe_tz_only;
349 
350 	const struct tegra_io_pad_soc *io_pads;
351 	unsigned int num_io_pads;
352 
353 	const struct pinctrl_pin_desc *pin_descs;
354 	unsigned int num_pin_descs;
355 
356 	const struct tegra_pmc_regs *regs;
357 	void (*init)(struct tegra_pmc *pmc);
358 	void (*setup_irq_polarity)(struct tegra_pmc *pmc,
359 				   struct device_node *np,
360 				   bool invert);
361 	void (*set_wake_filters)(struct tegra_pmc *pmc);
362 	int (*irq_set_wake)(struct irq_data *data, unsigned int on);
363 	int (*irq_set_type)(struct irq_data *data, unsigned int type);
364 	int (*powergate_set)(struct tegra_pmc *pmc, unsigned int id,
365 			     bool new_state);
366 
367 	const char * const *reset_sources;
368 	unsigned int num_reset_sources;
369 	const char * const *reset_levels;
370 	unsigned int num_reset_levels;
371 
372 	/*
373 	 * These describe events that can wake the system from sleep (i.e.
374 	 * LP0 or SC7). Wakeup from other sleep states (such as LP1 or LP2)
375 	 * are dealt with in the LIC.
376 	 */
377 	const struct tegra_wake_event *wake_events;
378 	unsigned int num_wake_events;
379 	unsigned int max_wake_events;
380 	unsigned int max_wake_vectors;
381 
382 	const struct pmc_clk_init_data *pmc_clks_data;
383 	unsigned int num_pmc_clks;
384 	bool has_blink_output;
385 	bool has_usb_sleepwalk;
386 	bool supports_core_domain;
387 };
388 
389 /**
390  * struct tegra_pmc - NVIDIA Tegra PMC
391  * @dev: pointer to PMC device structure
392  * @base: pointer to I/O remapped register region
393  * @wake: pointer to I/O remapped region for WAKE registers
394  * @aotag: pointer to I/O remapped region for AOTAG registers
395  * @scratch: pointer to I/O remapped region for scratch registers
396  * @clk: pointer to pclk clock
397  * @soc: pointer to SoC data structure
398  * @tz_only: flag specifying if the PMC can only be accessed via TrustZone
399  * @rate: currently configured rate of pclk
400  * @suspend_mode: lowest suspend mode available
401  * @cpu_good_time: CPU power good time (in microseconds)
402  * @cpu_off_time: CPU power off time (in microsecends)
403  * @core_osc_time: core power good OSC time (in microseconds)
404  * @core_pmu_time: core power good PMU time (in microseconds)
405  * @core_off_time: core power off time (in microseconds)
406  * @corereq_high: core power request is active-high
407  * @sysclkreq_high: system clock request is active-high
408  * @combined_req: combined power request for CPU & core
409  * @cpu_pwr_good_en: CPU power good signal is enabled
410  * @lp0_vec_phys: physical base address of the LP0 warm boot code
411  * @lp0_vec_size: size of the LP0 warm boot code
412  * @powergates_available: Bitmap of available power gates
413  * @powergates_lock: mutex for power gate register access
414  * @pctl_dev: pin controller exposed by the PMC
415  * @domain: IRQ domain provided by the PMC
416  * @irq: chip implementation for the IRQ domain
417  * @clk_nb: pclk clock changes handler
418  * @core_domain_state_synced: flag marking the core domain's state as synced
419  * @core_domain_registered: flag marking the core domain as registered
420  * @wake_type_level_map: Bitmap indicating level type for non-dual edge wakes
421  * @wake_type_dual_edge_map: Bitmap indicating if a wake is dual-edge or not
422  * @wake_sw_status_map: Bitmap to hold raw status of wakes without mask
423  * @wake_cntrl_level_map: Bitmap to hold wake levels to be programmed in
424  *     cntrl register associated with each wake during system suspend.
425  */
426 struct tegra_pmc {
427 	struct device *dev;
428 	void __iomem *base;
429 	void __iomem *wake;
430 	void __iomem *aotag;
431 	void __iomem *scratch;
432 	struct clk *clk;
433 
434 	const struct tegra_pmc_soc *soc;
435 	bool tz_only;
436 
437 	unsigned long rate;
438 
439 	enum tegra_suspend_mode suspend_mode;
440 	u32 cpu_good_time;
441 	u32 cpu_off_time;
442 	u32 core_osc_time;
443 	u32 core_pmu_time;
444 	u32 core_off_time;
445 	bool corereq_high;
446 	bool sysclkreq_high;
447 	bool combined_req;
448 	bool cpu_pwr_good_en;
449 	u32 lp0_vec_phys;
450 	u32 lp0_vec_size;
451 	DECLARE_BITMAP(powergates_available, TEGRA_POWERGATE_MAX);
452 
453 	struct mutex powergates_lock;
454 
455 	struct pinctrl_dev *pctl_dev;
456 
457 	struct irq_domain *domain;
458 	struct irq_chip irq;
459 
460 	struct notifier_block clk_nb;
461 
462 	bool core_domain_state_synced;
463 	bool core_domain_registered;
464 
465 	unsigned long *wake_type_level_map;
466 	unsigned long *wake_type_dual_edge_map;
467 	unsigned long *wake_sw_status_map;
468 	unsigned long *wake_cntrl_level_map;
469 	struct syscore_ops syscore;
470 };
471 
472 static struct tegra_pmc *pmc = &(struct tegra_pmc) {
473 	.base = NULL,
474 	.suspend_mode = TEGRA_SUSPEND_NOT_READY,
475 };
476 
477 static inline struct tegra_powergate *
to_powergate(struct generic_pm_domain * domain)478 to_powergate(struct generic_pm_domain *domain)
479 {
480 	return container_of(domain, struct tegra_powergate, genpd);
481 }
482 
tegra_pmc_readl(struct tegra_pmc * pmc,unsigned long offset)483 static u32 tegra_pmc_readl(struct tegra_pmc *pmc, unsigned long offset)
484 {
485 	struct arm_smccc_res res;
486 
487 	if (pmc->tz_only) {
488 		arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_READ, offset, 0, 0,
489 			      0, 0, 0, &res);
490 		if (res.a0) {
491 			if (pmc->dev)
492 				dev_warn(pmc->dev, "%s(): SMC failed: %lu\n",
493 					 __func__, res.a0);
494 			else
495 				pr_warn("%s(): SMC failed: %lu\n", __func__,
496 					res.a0);
497 		}
498 
499 		return res.a1;
500 	}
501 
502 	return readl(pmc->base + offset);
503 }
504 
tegra_pmc_writel(struct tegra_pmc * pmc,u32 value,unsigned long offset)505 static void tegra_pmc_writel(struct tegra_pmc *pmc, u32 value,
506 			     unsigned long offset)
507 {
508 	struct arm_smccc_res res;
509 
510 	if (pmc->tz_only) {
511 		arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_WRITE, offset,
512 			      value, 0, 0, 0, 0, &res);
513 		if (res.a0) {
514 			if (pmc->dev)
515 				dev_warn(pmc->dev, "%s(): SMC failed: %lu\n",
516 					 __func__, res.a0);
517 			else
518 				pr_warn("%s(): SMC failed: %lu\n", __func__,
519 					res.a0);
520 		}
521 	} else {
522 		writel(value, pmc->base + offset);
523 	}
524 }
525 
tegra_pmc_scratch_readl(struct tegra_pmc * pmc,unsigned long offset)526 static u32 tegra_pmc_scratch_readl(struct tegra_pmc *pmc, unsigned long offset)
527 {
528 	if (pmc->tz_only)
529 		return tegra_pmc_readl(pmc, offset);
530 
531 	return readl(pmc->scratch + offset);
532 }
533 
tegra_pmc_scratch_writel(struct tegra_pmc * pmc,u32 value,unsigned long offset)534 static void tegra_pmc_scratch_writel(struct tegra_pmc *pmc, u32 value,
535 				     unsigned long offset)
536 {
537 	if (pmc->tz_only)
538 		tegra_pmc_writel(pmc, value, offset);
539 	else
540 		writel(value, pmc->scratch + offset);
541 }
542 
543 /*
544  * TODO Figure out a way to call this with the struct tegra_pmc * passed in.
545  * This currently doesn't work because readx_poll_timeout() can only operate
546  * on functions that take a single argument.
547  */
tegra_powergate_state(int id)548 static inline bool tegra_powergate_state(int id)
549 {
550 	if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps)
551 		return (tegra_pmc_readl(pmc, GPU_RG_CNTRL) & 0x1) == 0;
552 	else
553 		return (tegra_pmc_readl(pmc, PWRGATE_STATUS) & BIT(id)) != 0;
554 }
555 
tegra_powergate_is_valid(struct tegra_pmc * pmc,int id)556 static inline bool tegra_powergate_is_valid(struct tegra_pmc *pmc, int id)
557 {
558 	return (pmc->soc && pmc->soc->powergates[id]);
559 }
560 
tegra_powergate_is_available(struct tegra_pmc * pmc,int id)561 static inline bool tegra_powergate_is_available(struct tegra_pmc *pmc, int id)
562 {
563 	return test_bit(id, pmc->powergates_available);
564 }
565 
tegra_powergate_lookup(struct tegra_pmc * pmc,const char * name)566 static int tegra_powergate_lookup(struct tegra_pmc *pmc, const char *name)
567 {
568 	unsigned int i;
569 
570 	if (!pmc || !pmc->soc || !name)
571 		return -EINVAL;
572 
573 	for (i = 0; i < pmc->soc->num_powergates; i++) {
574 		if (!tegra_powergate_is_valid(pmc, i))
575 			continue;
576 
577 		if (!strcmp(name, pmc->soc->powergates[i]))
578 			return i;
579 	}
580 
581 	return -ENODEV;
582 }
583 
tegra20_powergate_set(struct tegra_pmc * pmc,unsigned int id,bool new_state)584 static int tegra20_powergate_set(struct tegra_pmc *pmc, unsigned int id,
585 				 bool new_state)
586 {
587 	unsigned int retries = 100;
588 	bool status;
589 	int ret;
590 
591 	/*
592 	 * As per TRM documentation, the toggle command will be dropped by PMC
593 	 * if there is contention with a HW-initiated toggling (i.e. CPU core
594 	 * power-gated), the command should be retried in that case.
595 	 */
596 	do {
597 		tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
598 
599 		/* wait for PMC to execute the command */
600 		ret = readx_poll_timeout(tegra_powergate_state, id, status,
601 					 status == new_state, 1, 10);
602 	} while (ret == -ETIMEDOUT && retries--);
603 
604 	return ret;
605 }
606 
tegra_powergate_toggle_ready(struct tegra_pmc * pmc)607 static inline bool tegra_powergate_toggle_ready(struct tegra_pmc *pmc)
608 {
609 	return !(tegra_pmc_readl(pmc, PWRGATE_TOGGLE) & PWRGATE_TOGGLE_START);
610 }
611 
tegra114_powergate_set(struct tegra_pmc * pmc,unsigned int id,bool new_state)612 static int tegra114_powergate_set(struct tegra_pmc *pmc, unsigned int id,
613 				  bool new_state)
614 {
615 	bool status;
616 	int err;
617 
618 	/* wait while PMC power gating is contended */
619 	err = readx_poll_timeout(tegra_powergate_toggle_ready, pmc, status,
620 				 status == true, 1, 100);
621 	if (err)
622 		return err;
623 
624 	tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
625 
626 	/* wait for PMC to accept the command */
627 	err = readx_poll_timeout(tegra_powergate_toggle_ready, pmc, status,
628 				 status == true, 1, 100);
629 	if (err)
630 		return err;
631 
632 	/* wait for PMC to execute the command */
633 	err = readx_poll_timeout(tegra_powergate_state, id, status,
634 				 status == new_state, 10, 100000);
635 	if (err)
636 		return err;
637 
638 	return 0;
639 }
640 
641 /**
642  * tegra_powergate_set() - set the state of a partition
643  * @pmc: power management controller
644  * @id: partition ID
645  * @new_state: new state of the partition
646  */
tegra_powergate_set(struct tegra_pmc * pmc,unsigned int id,bool new_state)647 static int tegra_powergate_set(struct tegra_pmc *pmc, unsigned int id,
648 			       bool new_state)
649 {
650 	int err;
651 
652 	if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps)
653 		return -EINVAL;
654 
655 	mutex_lock(&pmc->powergates_lock);
656 
657 	if (tegra_powergate_state(id) == new_state) {
658 		mutex_unlock(&pmc->powergates_lock);
659 		return 0;
660 	}
661 
662 	err = pmc->soc->powergate_set(pmc, id, new_state);
663 
664 	mutex_unlock(&pmc->powergates_lock);
665 
666 	return err;
667 }
668 
__tegra_powergate_remove_clamping(struct tegra_pmc * pmc,unsigned int id)669 static int __tegra_powergate_remove_clamping(struct tegra_pmc *pmc,
670 					     unsigned int id)
671 {
672 	u32 mask;
673 
674 	mutex_lock(&pmc->powergates_lock);
675 
676 	/*
677 	 * On Tegra124 and later, the clamps for the GPU are controlled by a
678 	 * separate register (with different semantics).
679 	 */
680 	if (id == TEGRA_POWERGATE_3D) {
681 		if (pmc->soc->has_gpu_clamps) {
682 			tegra_pmc_writel(pmc, 0, GPU_RG_CNTRL);
683 			goto out;
684 		}
685 	}
686 
687 	/*
688 	 * Tegra 2 has a bug where PCIE and VDE clamping masks are
689 	 * swapped relatively to the partition ids
690 	 */
691 	if (id == TEGRA_POWERGATE_VDEC)
692 		mask = (1 << TEGRA_POWERGATE_PCIE);
693 	else if (id == TEGRA_POWERGATE_PCIE)
694 		mask = (1 << TEGRA_POWERGATE_VDEC);
695 	else
696 		mask = (1 << id);
697 
698 	tegra_pmc_writel(pmc, mask, REMOVE_CLAMPING);
699 
700 out:
701 	mutex_unlock(&pmc->powergates_lock);
702 
703 	return 0;
704 }
705 
tegra_powergate_prepare_clocks(struct tegra_powergate * pg)706 static int tegra_powergate_prepare_clocks(struct tegra_powergate *pg)
707 {
708 	unsigned long safe_rate = 100 * 1000 * 1000;
709 	unsigned int i;
710 	int err;
711 
712 	for (i = 0; i < pg->num_clks; i++) {
713 		pg->clk_rates[i] = clk_get_rate(pg->clks[i]);
714 
715 		if (!pg->clk_rates[i]) {
716 			err = -EINVAL;
717 			goto out;
718 		}
719 
720 		if (pg->clk_rates[i] <= safe_rate)
721 			continue;
722 
723 		/*
724 		 * We don't know whether voltage state is okay for the
725 		 * current clock rate, hence it's better to temporally
726 		 * switch clock to a safe rate which is suitable for
727 		 * all voltages, before enabling the clock.
728 		 */
729 		err = clk_set_rate(pg->clks[i], safe_rate);
730 		if (err)
731 			goto out;
732 	}
733 
734 	return 0;
735 
736 out:
737 	while (i--)
738 		clk_set_rate(pg->clks[i], pg->clk_rates[i]);
739 
740 	return err;
741 }
742 
tegra_powergate_unprepare_clocks(struct tegra_powergate * pg)743 static int tegra_powergate_unprepare_clocks(struct tegra_powergate *pg)
744 {
745 	unsigned int i;
746 	int err;
747 
748 	for (i = 0; i < pg->num_clks; i++) {
749 		err = clk_set_rate(pg->clks[i], pg->clk_rates[i]);
750 		if (err)
751 			return err;
752 	}
753 
754 	return 0;
755 }
756 
tegra_powergate_disable_clocks(struct tegra_powergate * pg)757 static void tegra_powergate_disable_clocks(struct tegra_powergate *pg)
758 {
759 	unsigned int i;
760 
761 	for (i = 0; i < pg->num_clks; i++)
762 		clk_disable_unprepare(pg->clks[i]);
763 }
764 
tegra_powergate_enable_clocks(struct tegra_powergate * pg)765 static int tegra_powergate_enable_clocks(struct tegra_powergate *pg)
766 {
767 	unsigned int i;
768 	int err;
769 
770 	for (i = 0; i < pg->num_clks; i++) {
771 		err = clk_prepare_enable(pg->clks[i]);
772 		if (err)
773 			goto out;
774 	}
775 
776 	return 0;
777 
778 out:
779 	while (i--)
780 		clk_disable_unprepare(pg->clks[i]);
781 
782 	return err;
783 }
784 
tegra_powergate_power_up(struct tegra_powergate * pg,bool disable_clocks)785 static int tegra_powergate_power_up(struct tegra_powergate *pg,
786 				    bool disable_clocks)
787 {
788 	int err;
789 
790 	err = reset_control_assert(pg->reset);
791 	if (err)
792 		return err;
793 
794 	usleep_range(10, 20);
795 
796 	err = tegra_powergate_set(pg->pmc, pg->id, true);
797 	if (err < 0)
798 		return err;
799 
800 	usleep_range(10, 20);
801 
802 	err = tegra_powergate_prepare_clocks(pg);
803 	if (err)
804 		goto powergate_off;
805 
806 	err = tegra_powergate_enable_clocks(pg);
807 	if (err)
808 		goto unprepare_clks;
809 
810 	usleep_range(10, 20);
811 
812 	err = __tegra_powergate_remove_clamping(pg->pmc, pg->id);
813 	if (err)
814 		goto disable_clks;
815 
816 	usleep_range(10, 20);
817 
818 	err = reset_control_deassert(pg->reset);
819 	if (err)
820 		goto disable_clks;
821 
822 	usleep_range(10, 20);
823 
824 	if (pg->pmc->soc->needs_mbist_war)
825 		err = tegra210_clk_handle_mbist_war(pg->id);
826 	if (err)
827 		goto disable_clks;
828 
829 	if (disable_clocks)
830 		tegra_powergate_disable_clocks(pg);
831 
832 	err = tegra_powergate_unprepare_clocks(pg);
833 	if (err)
834 		return err;
835 
836 	return 0;
837 
838 disable_clks:
839 	tegra_powergate_disable_clocks(pg);
840 	usleep_range(10, 20);
841 
842 unprepare_clks:
843 	tegra_powergate_unprepare_clocks(pg);
844 
845 powergate_off:
846 	tegra_powergate_set(pg->pmc, pg->id, false);
847 
848 	return err;
849 }
850 
tegra_powergate_power_down(struct tegra_powergate * pg)851 static int tegra_powergate_power_down(struct tegra_powergate *pg)
852 {
853 	int err;
854 
855 	err = tegra_powergate_prepare_clocks(pg);
856 	if (err)
857 		return err;
858 
859 	err = tegra_powergate_enable_clocks(pg);
860 	if (err)
861 		goto unprepare_clks;
862 
863 	usleep_range(10, 20);
864 
865 	err = reset_control_assert(pg->reset);
866 	if (err)
867 		goto disable_clks;
868 
869 	usleep_range(10, 20);
870 
871 	tegra_powergate_disable_clocks(pg);
872 
873 	usleep_range(10, 20);
874 
875 	err = tegra_powergate_set(pg->pmc, pg->id, false);
876 	if (err)
877 		goto assert_resets;
878 
879 	err = tegra_powergate_unprepare_clocks(pg);
880 	if (err)
881 		return err;
882 
883 	return 0;
884 
885 assert_resets:
886 	tegra_powergate_enable_clocks(pg);
887 	usleep_range(10, 20);
888 	reset_control_deassert(pg->reset);
889 	usleep_range(10, 20);
890 
891 disable_clks:
892 	tegra_powergate_disable_clocks(pg);
893 
894 unprepare_clks:
895 	tegra_powergate_unprepare_clocks(pg);
896 
897 	return err;
898 }
899 
tegra_genpd_power_on(struct generic_pm_domain * domain)900 static int tegra_genpd_power_on(struct generic_pm_domain *domain)
901 {
902 	struct tegra_powergate *pg = to_powergate(domain);
903 	struct device *dev = pg->pmc->dev;
904 	int err;
905 
906 	err = tegra_powergate_power_up(pg, true);
907 	if (err) {
908 		dev_err(dev, "failed to turn on PM domain %s: %d\n",
909 			pg->genpd.name, err);
910 		goto out;
911 	}
912 
913 	reset_control_release(pg->reset);
914 
915 out:
916 	return err;
917 }
918 
tegra_genpd_power_off(struct generic_pm_domain * domain)919 static int tegra_genpd_power_off(struct generic_pm_domain *domain)
920 {
921 	struct tegra_powergate *pg = to_powergate(domain);
922 	struct device *dev = pg->pmc->dev;
923 	int err;
924 
925 	err = reset_control_acquire(pg->reset);
926 	if (err < 0) {
927 		dev_err(dev, "failed to acquire resets for PM domain %s: %d\n",
928 			pg->genpd.name, err);
929 		return err;
930 	}
931 
932 	err = tegra_powergate_power_down(pg);
933 	if (err) {
934 		dev_err(dev, "failed to turn off PM domain %s: %d\n",
935 			pg->genpd.name, err);
936 		reset_control_release(pg->reset);
937 	}
938 
939 	return err;
940 }
941 
942 /**
943  * tegra_powergate_power_on() - power on partition
944  * @id: partition ID
945  */
tegra_powergate_power_on(unsigned int id)946 int tegra_powergate_power_on(unsigned int id)
947 {
948 	if (!tegra_powergate_is_available(pmc, id))
949 		return -EINVAL;
950 
951 	return tegra_powergate_set(pmc, id, true);
952 }
953 EXPORT_SYMBOL(tegra_powergate_power_on);
954 
955 /**
956  * tegra_powergate_power_off() - power off partition
957  * @id: partition ID
958  */
tegra_powergate_power_off(unsigned int id)959 int tegra_powergate_power_off(unsigned int id)
960 {
961 	if (!tegra_powergate_is_available(pmc, id))
962 		return -EINVAL;
963 
964 	return tegra_powergate_set(pmc, id, false);
965 }
966 EXPORT_SYMBOL(tegra_powergate_power_off);
967 
968 /**
969  * tegra_powergate_is_powered() - check if partition is powered
970  * @pmc: power management controller
971  * @id: partition ID
972  */
tegra_powergate_is_powered(struct tegra_pmc * pmc,unsigned int id)973 static int tegra_powergate_is_powered(struct tegra_pmc *pmc, unsigned int id)
974 {
975 	if (!tegra_powergate_is_valid(pmc, id))
976 		return -EINVAL;
977 
978 	return tegra_powergate_state(id);
979 }
980 
981 /**
982  * tegra_powergate_remove_clamping() - remove power clamps for partition
983  * @id: partition ID
984  */
tegra_powergate_remove_clamping(unsigned int id)985 int tegra_powergate_remove_clamping(unsigned int id)
986 {
987 	if (!tegra_powergate_is_available(pmc, id))
988 		return -EINVAL;
989 
990 	return __tegra_powergate_remove_clamping(pmc, id);
991 }
992 EXPORT_SYMBOL(tegra_powergate_remove_clamping);
993 
994 /**
995  * tegra_powergate_sequence_power_up() - power up partition
996  * @id: partition ID
997  * @clk: clock for partition
998  * @rst: reset for partition
999  *
1000  * Must be called with clk disabled, and returns with clk enabled.
1001  */
tegra_powergate_sequence_power_up(unsigned int id,struct clk * clk,struct reset_control * rst)1002 int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk,
1003 				      struct reset_control *rst)
1004 {
1005 	struct tegra_powergate *pg;
1006 	int err;
1007 
1008 	if (!tegra_powergate_is_available(pmc, id))
1009 		return -EINVAL;
1010 
1011 	pg = kzalloc(sizeof(*pg), GFP_KERNEL);
1012 	if (!pg)
1013 		return -ENOMEM;
1014 
1015 	pg->clk_rates = kzalloc(sizeof(*pg->clk_rates), GFP_KERNEL);
1016 	if (!pg->clk_rates) {
1017 		kfree(pg->clks);
1018 		return -ENOMEM;
1019 	}
1020 
1021 	pg->id = id;
1022 	pg->clks = &clk;
1023 	pg->num_clks = 1;
1024 	pg->reset = rst;
1025 	pg->pmc = pmc;
1026 
1027 	err = tegra_powergate_power_up(pg, false);
1028 	if (err)
1029 		dev_err(pmc->dev, "failed to turn on partition %d: %d\n", id,
1030 			err);
1031 
1032 	kfree(pg->clk_rates);
1033 	kfree(pg);
1034 
1035 	return err;
1036 }
1037 EXPORT_SYMBOL(tegra_powergate_sequence_power_up);
1038 
1039 /**
1040  * tegra_get_cpu_powergate_id() - convert from CPU ID to partition ID
1041  * @pmc: power management controller
1042  * @cpuid: CPU partition ID
1043  *
1044  * Returns the partition ID corresponding to the CPU partition ID or a
1045  * negative error code on failure.
1046  */
tegra_get_cpu_powergate_id(struct tegra_pmc * pmc,unsigned int cpuid)1047 static int tegra_get_cpu_powergate_id(struct tegra_pmc *pmc,
1048 				      unsigned int cpuid)
1049 {
1050 	if (pmc->soc && cpuid < pmc->soc->num_cpu_powergates)
1051 		return pmc->soc->cpu_powergates[cpuid];
1052 
1053 	return -EINVAL;
1054 }
1055 
1056 /**
1057  * tegra_pmc_cpu_is_powered() - check if CPU partition is powered
1058  * @cpuid: CPU partition ID
1059  */
tegra_pmc_cpu_is_powered(unsigned int cpuid)1060 bool tegra_pmc_cpu_is_powered(unsigned int cpuid)
1061 {
1062 	int id;
1063 
1064 	id = tegra_get_cpu_powergate_id(pmc, cpuid);
1065 	if (id < 0)
1066 		return false;
1067 
1068 	return tegra_powergate_is_powered(pmc, id);
1069 }
1070 
1071 /**
1072  * tegra_pmc_cpu_power_on() - power on CPU partition
1073  * @cpuid: CPU partition ID
1074  */
tegra_pmc_cpu_power_on(unsigned int cpuid)1075 int tegra_pmc_cpu_power_on(unsigned int cpuid)
1076 {
1077 	int id;
1078 
1079 	id = tegra_get_cpu_powergate_id(pmc, cpuid);
1080 	if (id < 0)
1081 		return id;
1082 
1083 	return tegra_powergate_set(pmc, id, true);
1084 }
1085 
1086 /**
1087  * tegra_pmc_cpu_remove_clamping() - remove power clamps for CPU partition
1088  * @cpuid: CPU partition ID
1089  */
tegra_pmc_cpu_remove_clamping(unsigned int cpuid)1090 int tegra_pmc_cpu_remove_clamping(unsigned int cpuid)
1091 {
1092 	int id;
1093 
1094 	id = tegra_get_cpu_powergate_id(pmc, cpuid);
1095 	if (id < 0)
1096 		return id;
1097 
1098 	return tegra_powergate_remove_clamping(id);
1099 }
1100 
tegra_pmc_program_reboot_reason(const char * cmd)1101 static void tegra_pmc_program_reboot_reason(const char *cmd)
1102 {
1103 	u32 value;
1104 
1105 	value = tegra_pmc_scratch_readl(pmc, pmc->soc->regs->scratch0);
1106 	value &= ~PMC_SCRATCH0_MODE_MASK;
1107 
1108 	if (cmd) {
1109 		if (strcmp(cmd, "recovery") == 0)
1110 			value |= PMC_SCRATCH0_MODE_RECOVERY;
1111 
1112 		if (strcmp(cmd, "bootloader") == 0)
1113 			value |= PMC_SCRATCH0_MODE_BOOTLOADER;
1114 
1115 		if (strcmp(cmd, "forced-recovery") == 0)
1116 			value |= PMC_SCRATCH0_MODE_RCM;
1117 	}
1118 
1119 	tegra_pmc_scratch_writel(pmc, value, pmc->soc->regs->scratch0);
1120 }
1121 
tegra_pmc_reboot_notify(struct notifier_block * this,unsigned long action,void * data)1122 static int tegra_pmc_reboot_notify(struct notifier_block *this,
1123 				   unsigned long action, void *data)
1124 {
1125 	if (action == SYS_RESTART)
1126 		tegra_pmc_program_reboot_reason(data);
1127 
1128 	return NOTIFY_DONE;
1129 }
1130 
1131 static struct notifier_block tegra_pmc_reboot_notifier = {
1132 	.notifier_call = tegra_pmc_reboot_notify,
1133 };
1134 
tegra_pmc_restart(void)1135 static void tegra_pmc_restart(void)
1136 {
1137 	u32 value;
1138 
1139 	/* reset everything but PMC_SCRATCH0 and PMC_RST_STATUS */
1140 	value = tegra_pmc_readl(pmc, PMC_CNTRL);
1141 	value |= PMC_CNTRL_MAIN_RST;
1142 	tegra_pmc_writel(pmc, value, PMC_CNTRL);
1143 }
1144 
tegra_pmc_restart_handler(struct sys_off_data * data)1145 static int tegra_pmc_restart_handler(struct sys_off_data *data)
1146 {
1147 	tegra_pmc_restart();
1148 
1149 	return NOTIFY_DONE;
1150 }
1151 
tegra_pmc_power_off_handler(struct sys_off_data * data)1152 static int tegra_pmc_power_off_handler(struct sys_off_data *data)
1153 {
1154 	/*
1155 	 * Reboot Nexus 7 into special bootloader mode if USB cable is
1156 	 * connected in order to display battery status and power off.
1157 	 */
1158 	if (of_machine_is_compatible("asus,grouper") &&
1159 	    power_supply_is_system_supplied()) {
1160 		const u32 go_to_charger_mode = 0xa5a55a5a;
1161 
1162 		tegra_pmc_writel(pmc, go_to_charger_mode, PMC_SCRATCH37);
1163 		tegra_pmc_restart();
1164 	}
1165 
1166 	return NOTIFY_DONE;
1167 }
1168 
powergate_show(struct seq_file * s,void * data)1169 static int powergate_show(struct seq_file *s, void *data)
1170 {
1171 	unsigned int i;
1172 	int status;
1173 
1174 	seq_printf(s, " powergate powered\n");
1175 	seq_printf(s, "------------------\n");
1176 
1177 	for (i = 0; i < pmc->soc->num_powergates; i++) {
1178 		status = tegra_powergate_is_powered(pmc, i);
1179 		if (status < 0)
1180 			continue;
1181 
1182 		seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i],
1183 			   status ? "yes" : "no");
1184 	}
1185 
1186 	return 0;
1187 }
1188 
1189 DEFINE_SHOW_ATTRIBUTE(powergate);
1190 
tegra_powergate_of_get_clks(struct tegra_powergate * pg,struct device_node * np)1191 static int tegra_powergate_of_get_clks(struct tegra_powergate *pg,
1192 				       struct device_node *np)
1193 {
1194 	struct clk *clk;
1195 	unsigned int i, count;
1196 	int err;
1197 
1198 	count = of_clk_get_parent_count(np);
1199 	if (count == 0)
1200 		return -ENODEV;
1201 
1202 	pg->clks = kcalloc(count, sizeof(clk), GFP_KERNEL);
1203 	if (!pg->clks)
1204 		return -ENOMEM;
1205 
1206 	pg->clk_rates = kcalloc(count, sizeof(*pg->clk_rates), GFP_KERNEL);
1207 	if (!pg->clk_rates) {
1208 		kfree(pg->clks);
1209 		return -ENOMEM;
1210 	}
1211 
1212 	for (i = 0; i < count; i++) {
1213 		pg->clks[i] = of_clk_get(np, i);
1214 		if (IS_ERR(pg->clks[i])) {
1215 			err = PTR_ERR(pg->clks[i]);
1216 			goto err;
1217 		}
1218 	}
1219 
1220 	pg->num_clks = count;
1221 
1222 	return 0;
1223 
1224 err:
1225 	while (i--)
1226 		clk_put(pg->clks[i]);
1227 
1228 	kfree(pg->clk_rates);
1229 	kfree(pg->clks);
1230 
1231 	return err;
1232 }
1233 
tegra_powergate_of_get_resets(struct tegra_powergate * pg,struct device_node * np,bool off)1234 static int tegra_powergate_of_get_resets(struct tegra_powergate *pg,
1235 					 struct device_node *np, bool off)
1236 {
1237 	struct device *dev = pg->pmc->dev;
1238 	int err;
1239 
1240 	pg->reset = of_reset_control_array_get_exclusive_released(np);
1241 	if (IS_ERR(pg->reset)) {
1242 		err = PTR_ERR(pg->reset);
1243 		dev_err(dev, "failed to get device resets: %d\n", err);
1244 		return err;
1245 	}
1246 
1247 	err = reset_control_acquire(pg->reset);
1248 	if (err < 0) {
1249 		pr_err("failed to acquire resets: %d\n", err);
1250 		goto out;
1251 	}
1252 
1253 	if (off) {
1254 		err = reset_control_assert(pg->reset);
1255 	} else {
1256 		err = reset_control_deassert(pg->reset);
1257 		if (err < 0)
1258 			goto out;
1259 
1260 		reset_control_release(pg->reset);
1261 	}
1262 
1263 out:
1264 	if (err) {
1265 		reset_control_release(pg->reset);
1266 		reset_control_put(pg->reset);
1267 	}
1268 
1269 	return err;
1270 }
1271 
tegra_powergate_add(struct tegra_pmc * pmc,struct device_node * np)1272 static int tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np)
1273 {
1274 	struct device *dev = pmc->dev;
1275 	struct tegra_powergate *pg;
1276 	int id, err = 0;
1277 	bool off;
1278 
1279 	pg = kzalloc(sizeof(*pg), GFP_KERNEL);
1280 	if (!pg)
1281 		return -ENOMEM;
1282 
1283 	id = tegra_powergate_lookup(pmc, np->name);
1284 	if (id < 0) {
1285 		dev_err(dev, "powergate lookup failed for %pOFn: %d\n", np, id);
1286 		err = -ENODEV;
1287 		goto free_mem;
1288 	}
1289 
1290 	/*
1291 	 * Clear the bit for this powergate so it cannot be managed
1292 	 * directly via the legacy APIs for controlling powergates.
1293 	 */
1294 	clear_bit(id, pmc->powergates_available);
1295 
1296 	pg->id = id;
1297 	pg->genpd.name = np->name;
1298 	pg->genpd.power_off = tegra_genpd_power_off;
1299 	pg->genpd.power_on = tegra_genpd_power_on;
1300 	pg->pmc = pmc;
1301 
1302 	off = !tegra_powergate_is_powered(pmc, pg->id);
1303 
1304 	err = tegra_powergate_of_get_clks(pg, np);
1305 	if (err < 0) {
1306 		dev_err(dev, "failed to get clocks for %pOFn: %d\n", np, err);
1307 		goto set_available;
1308 	}
1309 
1310 	err = tegra_powergate_of_get_resets(pg, np, off);
1311 	if (err < 0) {
1312 		dev_err(dev, "failed to get resets for %pOFn: %d\n", np, err);
1313 		goto remove_clks;
1314 	}
1315 
1316 	if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) {
1317 		if (off)
1318 			WARN_ON(tegra_powergate_power_up(pg, true));
1319 
1320 		goto remove_resets;
1321 	}
1322 
1323 	err = pm_genpd_init(&pg->genpd, NULL, off);
1324 	if (err < 0) {
1325 		dev_err(dev, "failed to initialise PM domain %pOFn: %d\n", np,
1326 		       err);
1327 		goto remove_resets;
1328 	}
1329 
1330 	err = of_genpd_add_provider_simple(np, &pg->genpd);
1331 	if (err < 0) {
1332 		dev_err(dev, "failed to add PM domain provider for %pOFn: %d\n",
1333 			np, err);
1334 		goto remove_genpd;
1335 	}
1336 
1337 	dev_dbg(dev, "added PM domain %s\n", pg->genpd.name);
1338 
1339 	return 0;
1340 
1341 remove_genpd:
1342 	pm_genpd_remove(&pg->genpd);
1343 
1344 remove_resets:
1345 	reset_control_put(pg->reset);
1346 
1347 remove_clks:
1348 	while (pg->num_clks--)
1349 		clk_put(pg->clks[pg->num_clks]);
1350 
1351 	kfree(pg->clks);
1352 
1353 set_available:
1354 	set_bit(id, pmc->powergates_available);
1355 
1356 free_mem:
1357 	kfree(pg);
1358 
1359 	return err;
1360 }
1361 
tegra_pmc_core_domain_state_synced(void)1362 bool tegra_pmc_core_domain_state_synced(void)
1363 {
1364 	return pmc->core_domain_state_synced;
1365 }
1366 
1367 static int
tegra_pmc_core_pd_set_performance_state(struct generic_pm_domain * genpd,unsigned int level)1368 tegra_pmc_core_pd_set_performance_state(struct generic_pm_domain *genpd,
1369 					unsigned int level)
1370 {
1371 	struct dev_pm_opp *opp;
1372 	int err;
1373 
1374 	opp = dev_pm_opp_find_level_ceil(&genpd->dev, &level);
1375 	if (IS_ERR(opp)) {
1376 		dev_err(&genpd->dev, "failed to find OPP for level %u: %pe\n",
1377 			level, opp);
1378 		return PTR_ERR(opp);
1379 	}
1380 
1381 	mutex_lock(&pmc->powergates_lock);
1382 	err = dev_pm_opp_set_opp(pmc->dev, opp);
1383 	mutex_unlock(&pmc->powergates_lock);
1384 
1385 	dev_pm_opp_put(opp);
1386 
1387 	if (err) {
1388 		dev_err(&genpd->dev, "failed to set voltage to %duV: %d\n",
1389 			level, err);
1390 		return err;
1391 	}
1392 
1393 	return 0;
1394 }
1395 
1396 static unsigned int
tegra_pmc_core_pd_opp_to_performance_state(struct generic_pm_domain * genpd,struct dev_pm_opp * opp)1397 tegra_pmc_core_pd_opp_to_performance_state(struct generic_pm_domain *genpd,
1398 					   struct dev_pm_opp *opp)
1399 {
1400 	return dev_pm_opp_get_level(opp);
1401 }
1402 
tegra_pmc_core_pd_add(struct tegra_pmc * pmc,struct device_node * np)1403 static int tegra_pmc_core_pd_add(struct tegra_pmc *pmc, struct device_node *np)
1404 {
1405 	struct generic_pm_domain *genpd;
1406 	const char *rname[] = { "core", NULL};
1407 	int err;
1408 
1409 	genpd = devm_kzalloc(pmc->dev, sizeof(*genpd), GFP_KERNEL);
1410 	if (!genpd)
1411 		return -ENOMEM;
1412 
1413 	genpd->name = "core";
1414 	genpd->set_performance_state = tegra_pmc_core_pd_set_performance_state;
1415 	genpd->opp_to_performance_state = tegra_pmc_core_pd_opp_to_performance_state;
1416 
1417 	err = devm_pm_opp_set_regulators(pmc->dev, rname);
1418 	if (err)
1419 		return dev_err_probe(pmc->dev, err,
1420 				     "failed to set core OPP regulator\n");
1421 
1422 	err = pm_genpd_init(genpd, NULL, false);
1423 	if (err) {
1424 		dev_err(pmc->dev, "failed to init core genpd: %d\n", err);
1425 		return err;
1426 	}
1427 
1428 	err = of_genpd_add_provider_simple(np, genpd);
1429 	if (err) {
1430 		dev_err(pmc->dev, "failed to add core genpd: %d\n", err);
1431 		goto remove_genpd;
1432 	}
1433 
1434 	pmc->core_domain_registered = true;
1435 
1436 	return 0;
1437 
1438 remove_genpd:
1439 	pm_genpd_remove(genpd);
1440 
1441 	return err;
1442 }
1443 
tegra_powergate_init(struct tegra_pmc * pmc,struct device_node * parent)1444 static int tegra_powergate_init(struct tegra_pmc *pmc,
1445 				struct device_node *parent)
1446 {
1447 	struct of_phandle_args child_args, parent_args;
1448 	struct device_node *np, *child;
1449 	int err = 0;
1450 
1451 	/*
1452 	 * Core power domain is the parent of powergate domains, hence it
1453 	 * should be registered first.
1454 	 */
1455 	np = of_get_child_by_name(parent, "core-domain");
1456 	if (np) {
1457 		err = tegra_pmc_core_pd_add(pmc, np);
1458 		of_node_put(np);
1459 		if (err)
1460 			return err;
1461 	}
1462 
1463 	np = of_get_child_by_name(parent, "powergates");
1464 	if (!np)
1465 		return 0;
1466 
1467 	for_each_child_of_node(np, child) {
1468 		err = tegra_powergate_add(pmc, child);
1469 		if (err < 0) {
1470 			of_node_put(child);
1471 			break;
1472 		}
1473 
1474 		if (of_parse_phandle_with_args(child, "power-domains",
1475 					       "#power-domain-cells",
1476 					       0, &parent_args))
1477 			continue;
1478 
1479 		child_args.np = child;
1480 		child_args.args_count = 0;
1481 
1482 		err = of_genpd_add_subdomain(&parent_args, &child_args);
1483 		of_node_put(parent_args.np);
1484 		if (err) {
1485 			of_node_put(child);
1486 			break;
1487 		}
1488 	}
1489 
1490 	of_node_put(np);
1491 
1492 	return err;
1493 }
1494 
tegra_powergate_remove(struct generic_pm_domain * genpd)1495 static void tegra_powergate_remove(struct generic_pm_domain *genpd)
1496 {
1497 	struct tegra_powergate *pg = to_powergate(genpd);
1498 
1499 	reset_control_put(pg->reset);
1500 
1501 	while (pg->num_clks--)
1502 		clk_put(pg->clks[pg->num_clks]);
1503 
1504 	kfree(pg->clks);
1505 
1506 	set_bit(pg->id, pmc->powergates_available);
1507 
1508 	kfree(pg);
1509 }
1510 
tegra_powergate_remove_all(struct device_node * parent)1511 static void tegra_powergate_remove_all(struct device_node *parent)
1512 {
1513 	struct generic_pm_domain *genpd;
1514 	struct device_node *np, *child;
1515 
1516 	np = of_get_child_by_name(parent, "powergates");
1517 	if (!np)
1518 		return;
1519 
1520 	for_each_child_of_node(np, child) {
1521 		of_genpd_del_provider(child);
1522 
1523 		genpd = of_genpd_remove_last(child);
1524 		if (IS_ERR(genpd))
1525 			continue;
1526 
1527 		tegra_powergate_remove(genpd);
1528 	}
1529 
1530 	of_node_put(np);
1531 
1532 	np = of_get_child_by_name(parent, "core-domain");
1533 	if (np) {
1534 		of_genpd_del_provider(np);
1535 		of_genpd_remove_last(np);
1536 	}
1537 }
1538 
1539 static const struct tegra_io_pad_soc *
tegra_io_pad_find(struct tegra_pmc * pmc,enum tegra_io_pad id)1540 tegra_io_pad_find(struct tegra_pmc *pmc, enum tegra_io_pad id)
1541 {
1542 	unsigned int i;
1543 
1544 	for (i = 0; i < pmc->soc->num_io_pads; i++)
1545 		if (pmc->soc->io_pads[i].id == id)
1546 			return &pmc->soc->io_pads[i];
1547 
1548 	return NULL;
1549 }
1550 
tegra_io_pad_prepare(struct tegra_pmc * pmc,const struct tegra_io_pad_soc * pad,unsigned long * request,unsigned long * status,u32 * mask)1551 static int tegra_io_pad_prepare(struct tegra_pmc *pmc,
1552 				const struct tegra_io_pad_soc *pad,
1553 				unsigned long *request,
1554 				unsigned long *status,
1555 				u32 *mask)
1556 {
1557 	unsigned long rate, value;
1558 
1559 	if (pad->dpd == UINT_MAX)
1560 		return -EINVAL;
1561 
1562 	*request = pad->request;
1563 	*status = pad->status;
1564 	*mask = BIT(pad->dpd);
1565 
1566 	if (pmc->clk) {
1567 		rate = pmc->rate;
1568 		if (!rate) {
1569 			dev_err(pmc->dev, "failed to get clock rate\n");
1570 			return -ENODEV;
1571 		}
1572 
1573 		tegra_pmc_writel(pmc, DPD_SAMPLE_ENABLE, DPD_SAMPLE);
1574 
1575 		/* must be at least 200 ns, in APB (PCLK) clock cycles */
1576 		value = DIV_ROUND_UP(1000000000, rate);
1577 		value = DIV_ROUND_UP(200, value);
1578 		tegra_pmc_writel(pmc, value, SEL_DPD_TIM);
1579 	}
1580 
1581 	return 0;
1582 }
1583 
tegra_io_pad_poll(struct tegra_pmc * pmc,unsigned long offset,u32 mask,u32 val,unsigned long timeout)1584 static int tegra_io_pad_poll(struct tegra_pmc *pmc, unsigned long offset,
1585 			     u32 mask, u32 val, unsigned long timeout)
1586 {
1587 	u32 value;
1588 
1589 	timeout = jiffies + msecs_to_jiffies(timeout);
1590 
1591 	while (time_after(timeout, jiffies)) {
1592 		value = tegra_pmc_readl(pmc, offset);
1593 		if ((value & mask) == val)
1594 			return 0;
1595 
1596 		usleep_range(250, 1000);
1597 	}
1598 
1599 	return -ETIMEDOUT;
1600 }
1601 
tegra_io_pad_unprepare(struct tegra_pmc * pmc)1602 static void tegra_io_pad_unprepare(struct tegra_pmc *pmc)
1603 {
1604 	if (pmc->clk)
1605 		tegra_pmc_writel(pmc, DPD_SAMPLE_DISABLE, DPD_SAMPLE);
1606 }
1607 
1608 /**
1609  * tegra_io_pad_power_enable() - enable power to I/O pad
1610  * @id: Tegra I/O pad ID for which to enable power
1611  *
1612  * Returns: 0 on success or a negative error code on failure.
1613  */
tegra_io_pad_power_enable(enum tegra_io_pad id)1614 int tegra_io_pad_power_enable(enum tegra_io_pad id)
1615 {
1616 	const struct tegra_io_pad_soc *pad;
1617 	unsigned long request, status;
1618 	u32 mask;
1619 	int err;
1620 
1621 	pad = tegra_io_pad_find(pmc, id);
1622 	if (!pad) {
1623 		dev_err(pmc->dev, "invalid I/O pad ID %u\n", id);
1624 		return -ENOENT;
1625 	}
1626 
1627 	mutex_lock(&pmc->powergates_lock);
1628 
1629 	err = tegra_io_pad_prepare(pmc, pad, &request, &status, &mask);
1630 	if (err < 0) {
1631 		dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err);
1632 		goto unlock;
1633 	}
1634 
1635 	tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_OFF | mask, request);
1636 
1637 	err = tegra_io_pad_poll(pmc, status, mask, 0, 250);
1638 	if (err < 0) {
1639 		dev_err(pmc->dev, "failed to enable I/O pad: %d\n", err);
1640 		goto unlock;
1641 	}
1642 
1643 	tegra_io_pad_unprepare(pmc);
1644 
1645 unlock:
1646 	mutex_unlock(&pmc->powergates_lock);
1647 	return err;
1648 }
1649 EXPORT_SYMBOL(tegra_io_pad_power_enable);
1650 
1651 /**
1652  * tegra_io_pad_power_disable() - disable power to I/O pad
1653  * @id: Tegra I/O pad ID for which to disable power
1654  *
1655  * Returns: 0 on success or a negative error code on failure.
1656  */
tegra_io_pad_power_disable(enum tegra_io_pad id)1657 int tegra_io_pad_power_disable(enum tegra_io_pad id)
1658 {
1659 	const struct tegra_io_pad_soc *pad;
1660 	unsigned long request, status;
1661 	u32 mask;
1662 	int err;
1663 
1664 	pad = tegra_io_pad_find(pmc, id);
1665 	if (!pad) {
1666 		dev_err(pmc->dev, "invalid I/O pad ID %u\n", id);
1667 		return -ENOENT;
1668 	}
1669 
1670 	mutex_lock(&pmc->powergates_lock);
1671 
1672 	err = tegra_io_pad_prepare(pmc, pad, &request, &status, &mask);
1673 	if (err < 0) {
1674 		dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err);
1675 		goto unlock;
1676 	}
1677 
1678 	tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_ON | mask, request);
1679 
1680 	err = tegra_io_pad_poll(pmc, status, mask, mask, 250);
1681 	if (err < 0) {
1682 		dev_err(pmc->dev, "failed to disable I/O pad: %d\n", err);
1683 		goto unlock;
1684 	}
1685 
1686 	tegra_io_pad_unprepare(pmc);
1687 
1688 unlock:
1689 	mutex_unlock(&pmc->powergates_lock);
1690 	return err;
1691 }
1692 EXPORT_SYMBOL(tegra_io_pad_power_disable);
1693 
tegra_io_pad_is_powered(struct tegra_pmc * pmc,enum tegra_io_pad id)1694 static int tegra_io_pad_is_powered(struct tegra_pmc *pmc, enum tegra_io_pad id)
1695 {
1696 	const struct tegra_io_pad_soc *pad;
1697 	unsigned long status;
1698 	u32 mask, value;
1699 
1700 	pad = tegra_io_pad_find(pmc, id);
1701 	if (!pad) {
1702 		dev_err(pmc->dev, "invalid I/O pad ID %u\n", id);
1703 		return -ENOENT;
1704 	}
1705 
1706 	if (pad->dpd == UINT_MAX)
1707 		return -EINVAL;
1708 
1709 	status = pad->status;
1710 	mask = BIT(pad->dpd);
1711 
1712 	value = tegra_pmc_readl(pmc, status);
1713 
1714 	return !(value & mask);
1715 }
1716 
tegra_io_pad_set_voltage(struct tegra_pmc * pmc,enum tegra_io_pad id,int voltage)1717 static int tegra_io_pad_set_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id,
1718 				    int voltage)
1719 {
1720 	const struct tegra_io_pad_soc *pad;
1721 	u32 value;
1722 
1723 	pad = tegra_io_pad_find(pmc, id);
1724 	if (!pad)
1725 		return -ENOENT;
1726 
1727 	if (pad->voltage == UINT_MAX)
1728 		return -ENOTSUPP;
1729 
1730 	mutex_lock(&pmc->powergates_lock);
1731 
1732 	if (pmc->soc->has_impl_33v_pwr) {
1733 		value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR);
1734 
1735 		if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8)
1736 			value &= ~BIT(pad->voltage);
1737 		else
1738 			value |= BIT(pad->voltage);
1739 
1740 		tegra_pmc_writel(pmc, value, PMC_IMPL_E_33V_PWR);
1741 	} else {
1742 		/* write-enable PMC_PWR_DET_VALUE[pad->voltage] */
1743 		value = tegra_pmc_readl(pmc, PMC_PWR_DET);
1744 		value |= BIT(pad->voltage);
1745 		tegra_pmc_writel(pmc, value, PMC_PWR_DET);
1746 
1747 		/* update I/O voltage */
1748 		value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE);
1749 
1750 		if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8)
1751 			value &= ~BIT(pad->voltage);
1752 		else
1753 			value |= BIT(pad->voltage);
1754 
1755 		tegra_pmc_writel(pmc, value, PMC_PWR_DET_VALUE);
1756 	}
1757 
1758 	mutex_unlock(&pmc->powergates_lock);
1759 
1760 	usleep_range(100, 250);
1761 
1762 	return 0;
1763 }
1764 
tegra_io_pad_get_voltage(struct tegra_pmc * pmc,enum tegra_io_pad id)1765 static int tegra_io_pad_get_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id)
1766 {
1767 	const struct tegra_io_pad_soc *pad;
1768 	u32 value;
1769 
1770 	pad = tegra_io_pad_find(pmc, id);
1771 	if (!pad)
1772 		return -ENOENT;
1773 
1774 	if (pad->voltage == UINT_MAX)
1775 		return -ENOTSUPP;
1776 
1777 	if (pmc->soc->has_impl_33v_pwr)
1778 		value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR);
1779 	else
1780 		value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE);
1781 
1782 	if ((value & BIT(pad->voltage)) == 0)
1783 		return TEGRA_IO_PAD_VOLTAGE_1V8;
1784 
1785 	return TEGRA_IO_PAD_VOLTAGE_3V3;
1786 }
1787 
1788 /**
1789  * tegra_io_rail_power_on() - enable power to I/O rail
1790  * @id: Tegra I/O pad ID for which to enable power
1791  *
1792  * See also: tegra_io_pad_power_enable()
1793  */
tegra_io_rail_power_on(unsigned int id)1794 int tegra_io_rail_power_on(unsigned int id)
1795 {
1796 	return tegra_io_pad_power_enable(id);
1797 }
1798 EXPORT_SYMBOL(tegra_io_rail_power_on);
1799 
1800 /**
1801  * tegra_io_rail_power_off() - disable power to I/O rail
1802  * @id: Tegra I/O pad ID for which to disable power
1803  *
1804  * See also: tegra_io_pad_power_disable()
1805  */
tegra_io_rail_power_off(unsigned int id)1806 int tegra_io_rail_power_off(unsigned int id)
1807 {
1808 	return tegra_io_pad_power_disable(id);
1809 }
1810 EXPORT_SYMBOL(tegra_io_rail_power_off);
1811 
1812 #ifdef CONFIG_PM_SLEEP
tegra_pmc_get_suspend_mode(void)1813 enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void)
1814 {
1815 	return pmc->suspend_mode;
1816 }
1817 
tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode)1818 void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode)
1819 {
1820 	if (mode < TEGRA_SUSPEND_NONE || mode >= TEGRA_MAX_SUSPEND_MODE)
1821 		return;
1822 
1823 	pmc->suspend_mode = mode;
1824 }
1825 
tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode)1826 void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode)
1827 {
1828 	unsigned long long rate = 0;
1829 	u64 ticks;
1830 	u32 value;
1831 
1832 	switch (mode) {
1833 	case TEGRA_SUSPEND_LP1:
1834 		rate = 32768;
1835 		break;
1836 
1837 	case TEGRA_SUSPEND_LP2:
1838 		rate = pmc->rate;
1839 		break;
1840 
1841 	default:
1842 		break;
1843 	}
1844 
1845 	if (WARN_ON_ONCE(rate == 0))
1846 		rate = 100000000;
1847 
1848 	ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1;
1849 	do_div(ticks, USEC_PER_SEC);
1850 	tegra_pmc_writel(pmc, ticks, PMC_CPUPWRGOOD_TIMER);
1851 
1852 	ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1;
1853 	do_div(ticks, USEC_PER_SEC);
1854 	tegra_pmc_writel(pmc, ticks, PMC_CPUPWROFF_TIMER);
1855 
1856 	value = tegra_pmc_readl(pmc, PMC_CNTRL);
1857 	value &= ~PMC_CNTRL_SIDE_EFFECT_LP0;
1858 	value |= PMC_CNTRL_CPU_PWRREQ_OE;
1859 	tegra_pmc_writel(pmc, value, PMC_CNTRL);
1860 }
1861 #endif
1862 
tegra_pmc_parse_dt(struct tegra_pmc * pmc,struct device_node * np)1863 static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np)
1864 {
1865 	u32 value, values[2];
1866 
1867 	if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) {
1868 		pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1869 	} else {
1870 		switch (value) {
1871 		case 0:
1872 			pmc->suspend_mode = TEGRA_SUSPEND_LP0;
1873 			break;
1874 
1875 		case 1:
1876 			pmc->suspend_mode = TEGRA_SUSPEND_LP1;
1877 			break;
1878 
1879 		case 2:
1880 			pmc->suspend_mode = TEGRA_SUSPEND_LP2;
1881 			break;
1882 
1883 		default:
1884 			pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1885 			break;
1886 		}
1887 	}
1888 
1889 	pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode);
1890 
1891 	if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value))
1892 		pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1893 
1894 	pmc->cpu_good_time = value;
1895 
1896 	if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value))
1897 		pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1898 
1899 	pmc->cpu_off_time = value;
1900 
1901 	if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time",
1902 				       values, ARRAY_SIZE(values)))
1903 		pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1904 
1905 	pmc->core_osc_time = values[0];
1906 	pmc->core_pmu_time = values[1];
1907 
1908 	if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value))
1909 		pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1910 
1911 	pmc->core_off_time = value;
1912 
1913 	pmc->corereq_high = of_property_read_bool(np,
1914 				"nvidia,core-power-req-active-high");
1915 
1916 	pmc->sysclkreq_high = of_property_read_bool(np,
1917 				"nvidia,sys-clock-req-active-high");
1918 
1919 	pmc->combined_req = of_property_read_bool(np,
1920 				"nvidia,combined-power-req");
1921 
1922 	pmc->cpu_pwr_good_en = of_property_read_bool(np,
1923 				"nvidia,cpu-pwr-good-en");
1924 
1925 	if (of_property_read_u32_array(np, "nvidia,lp0-vec", values,
1926 				       ARRAY_SIZE(values)))
1927 		if (pmc->suspend_mode == TEGRA_SUSPEND_LP0)
1928 			pmc->suspend_mode = TEGRA_SUSPEND_LP1;
1929 
1930 	pmc->lp0_vec_phys = values[0];
1931 	pmc->lp0_vec_size = values[1];
1932 
1933 	return 0;
1934 }
1935 
tegra_pmc_init(struct tegra_pmc * pmc)1936 static int tegra_pmc_init(struct tegra_pmc *pmc)
1937 {
1938 	if (pmc->soc->max_wake_events > 0) {
1939 		pmc->wake_type_level_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL);
1940 		if (!pmc->wake_type_level_map)
1941 			return -ENOMEM;
1942 
1943 		pmc->wake_type_dual_edge_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL);
1944 		if (!pmc->wake_type_dual_edge_map)
1945 			return -ENOMEM;
1946 
1947 		pmc->wake_sw_status_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL);
1948 		if (!pmc->wake_sw_status_map)
1949 			return -ENOMEM;
1950 
1951 		pmc->wake_cntrl_level_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL);
1952 		if (!pmc->wake_cntrl_level_map)
1953 			return -ENOMEM;
1954 	}
1955 
1956 	if (pmc->soc->init)
1957 		pmc->soc->init(pmc);
1958 
1959 	return 0;
1960 }
1961 
tegra_pmc_init_tsense_reset(struct tegra_pmc * pmc)1962 static void tegra_pmc_init_tsense_reset(struct tegra_pmc *pmc)
1963 {
1964 	static const char disabled[] = "emergency thermal reset disabled";
1965 	u32 pmu_addr, ctrl_id, reg_addr, reg_data, pinmux;
1966 	struct device *dev = pmc->dev;
1967 	struct device_node *np;
1968 	u32 value, checksum;
1969 
1970 	if (!pmc->soc->has_tsense_reset)
1971 		return;
1972 
1973 	np = of_get_child_by_name(pmc->dev->of_node, "i2c-thermtrip");
1974 	if (!np) {
1975 		dev_warn(dev, "i2c-thermtrip node not found, %s.\n", disabled);
1976 		return;
1977 	}
1978 
1979 	if (of_property_read_u32(np, "nvidia,i2c-controller-id", &ctrl_id)) {
1980 		dev_err(dev, "I2C controller ID missing, %s.\n", disabled);
1981 		goto out;
1982 	}
1983 
1984 	if (of_property_read_u32(np, "nvidia,bus-addr", &pmu_addr)) {
1985 		dev_err(dev, "nvidia,bus-addr missing, %s.\n", disabled);
1986 		goto out;
1987 	}
1988 
1989 	if (of_property_read_u32(np, "nvidia,reg-addr", &reg_addr)) {
1990 		dev_err(dev, "nvidia,reg-addr missing, %s.\n", disabled);
1991 		goto out;
1992 	}
1993 
1994 	if (of_property_read_u32(np, "nvidia,reg-data", &reg_data)) {
1995 		dev_err(dev, "nvidia,reg-data missing, %s.\n", disabled);
1996 		goto out;
1997 	}
1998 
1999 	if (of_property_read_u32(np, "nvidia,pinmux-id", &pinmux))
2000 		pinmux = 0;
2001 
2002 	value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL);
2003 	value |= PMC_SENSOR_CTRL_SCRATCH_WRITE;
2004 	tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL);
2005 
2006 	value = (reg_data << PMC_SCRATCH54_DATA_SHIFT) |
2007 		(reg_addr << PMC_SCRATCH54_ADDR_SHIFT);
2008 	tegra_pmc_writel(pmc, value, PMC_SCRATCH54);
2009 
2010 	value = PMC_SCRATCH55_RESET_TEGRA;
2011 	value |= ctrl_id << PMC_SCRATCH55_CNTRL_ID_SHIFT;
2012 	value |= pinmux << PMC_SCRATCH55_PINMUX_SHIFT;
2013 	value |= pmu_addr << PMC_SCRATCH55_I2CSLV1_SHIFT;
2014 
2015 	/*
2016 	 * Calculate checksum of SCRATCH54, SCRATCH55 fields. Bits 23:16 will
2017 	 * contain the checksum and are currently zero, so they are not added.
2018 	 */
2019 	checksum = reg_addr + reg_data + (value & 0xff) + ((value >> 8) & 0xff)
2020 		+ ((value >> 24) & 0xff);
2021 	checksum &= 0xff;
2022 	checksum = 0x100 - checksum;
2023 
2024 	value |= checksum << PMC_SCRATCH55_CHECKSUM_SHIFT;
2025 
2026 	tegra_pmc_writel(pmc, value, PMC_SCRATCH55);
2027 
2028 	value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL);
2029 	value |= PMC_SENSOR_CTRL_ENABLE_RST;
2030 	tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL);
2031 
2032 	dev_info(pmc->dev, "emergency thermal reset enabled\n");
2033 
2034 out:
2035 	of_node_put(np);
2036 }
2037 
tegra_io_pad_pinctrl_get_groups_count(struct pinctrl_dev * pctl_dev)2038 static int tegra_io_pad_pinctrl_get_groups_count(struct pinctrl_dev *pctl_dev)
2039 {
2040 	struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
2041 
2042 	return pmc->soc->num_io_pads;
2043 }
2044 
tegra_io_pad_pinctrl_get_group_name(struct pinctrl_dev * pctl,unsigned int group)2045 static const char *tegra_io_pad_pinctrl_get_group_name(struct pinctrl_dev *pctl,
2046 						       unsigned int group)
2047 {
2048 	struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl);
2049 
2050 	return pmc->soc->io_pads[group].name;
2051 }
2052 
tegra_io_pad_pinctrl_get_group_pins(struct pinctrl_dev * pctl_dev,unsigned int group,const unsigned int ** pins,unsigned int * num_pins)2053 static int tegra_io_pad_pinctrl_get_group_pins(struct pinctrl_dev *pctl_dev,
2054 					       unsigned int group,
2055 					       const unsigned int **pins,
2056 					       unsigned int *num_pins)
2057 {
2058 	struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
2059 
2060 	*pins = &pmc->soc->io_pads[group].id;
2061 	*num_pins = 1;
2062 
2063 	return 0;
2064 }
2065 
2066 static const struct pinctrl_ops tegra_io_pad_pinctrl_ops = {
2067 	.get_groups_count = tegra_io_pad_pinctrl_get_groups_count,
2068 	.get_group_name = tegra_io_pad_pinctrl_get_group_name,
2069 	.get_group_pins = tegra_io_pad_pinctrl_get_group_pins,
2070 	.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
2071 	.dt_free_map = pinconf_generic_dt_free_map,
2072 };
2073 
tegra_io_pad_pinconf_get(struct pinctrl_dev * pctl_dev,unsigned int pin,unsigned long * config)2074 static int tegra_io_pad_pinconf_get(struct pinctrl_dev *pctl_dev,
2075 				    unsigned int pin, unsigned long *config)
2076 {
2077 	enum pin_config_param param = pinconf_to_config_param(*config);
2078 	struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
2079 	const struct tegra_io_pad_soc *pad;
2080 	int ret;
2081 	u32 arg;
2082 
2083 	pad = tegra_io_pad_find(pmc, pin);
2084 	if (!pad)
2085 		return -EINVAL;
2086 
2087 	switch (param) {
2088 	case PIN_CONFIG_POWER_SOURCE:
2089 		ret = tegra_io_pad_get_voltage(pmc, pad->id);
2090 		if (ret < 0)
2091 			return ret;
2092 
2093 		arg = ret;
2094 		break;
2095 
2096 	case PIN_CONFIG_MODE_LOW_POWER:
2097 		ret = tegra_io_pad_is_powered(pmc, pad->id);
2098 		if (ret < 0)
2099 			return ret;
2100 
2101 		arg = !ret;
2102 		break;
2103 
2104 	default:
2105 		return -EINVAL;
2106 	}
2107 
2108 	*config = pinconf_to_config_packed(param, arg);
2109 
2110 	return 0;
2111 }
2112 
tegra_io_pad_pinconf_set(struct pinctrl_dev * pctl_dev,unsigned int pin,unsigned long * configs,unsigned int num_configs)2113 static int tegra_io_pad_pinconf_set(struct pinctrl_dev *pctl_dev,
2114 				    unsigned int pin, unsigned long *configs,
2115 				    unsigned int num_configs)
2116 {
2117 	struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
2118 	const struct tegra_io_pad_soc *pad;
2119 	enum pin_config_param param;
2120 	unsigned int i;
2121 	int err;
2122 	u32 arg;
2123 
2124 	pad = tegra_io_pad_find(pmc, pin);
2125 	if (!pad)
2126 		return -EINVAL;
2127 
2128 	for (i = 0; i < num_configs; ++i) {
2129 		param = pinconf_to_config_param(configs[i]);
2130 		arg = pinconf_to_config_argument(configs[i]);
2131 
2132 		switch (param) {
2133 		case PIN_CONFIG_MODE_LOW_POWER:
2134 			if (arg)
2135 				err = tegra_io_pad_power_disable(pad->id);
2136 			else
2137 				err = tegra_io_pad_power_enable(pad->id);
2138 			if (err)
2139 				return err;
2140 			break;
2141 		case PIN_CONFIG_POWER_SOURCE:
2142 			if (arg != TEGRA_IO_PAD_VOLTAGE_1V8 &&
2143 			    arg != TEGRA_IO_PAD_VOLTAGE_3V3)
2144 				return -EINVAL;
2145 			err = tegra_io_pad_set_voltage(pmc, pad->id, arg);
2146 			if (err)
2147 				return err;
2148 			break;
2149 		default:
2150 			return -EINVAL;
2151 		}
2152 	}
2153 
2154 	return 0;
2155 }
2156 
2157 static const struct pinconf_ops tegra_io_pad_pinconf_ops = {
2158 	.pin_config_get = tegra_io_pad_pinconf_get,
2159 	.pin_config_set = tegra_io_pad_pinconf_set,
2160 	.is_generic = true,
2161 };
2162 
2163 static struct pinctrl_desc tegra_pmc_pctl_desc = {
2164 	.pctlops = &tegra_io_pad_pinctrl_ops,
2165 	.confops = &tegra_io_pad_pinconf_ops,
2166 };
2167 
tegra_pmc_pinctrl_init(struct tegra_pmc * pmc)2168 static int tegra_pmc_pinctrl_init(struct tegra_pmc *pmc)
2169 {
2170 	int err;
2171 
2172 	if (!pmc->soc->num_pin_descs)
2173 		return 0;
2174 
2175 	tegra_pmc_pctl_desc.name = dev_name(pmc->dev);
2176 	tegra_pmc_pctl_desc.pins = pmc->soc->pin_descs;
2177 	tegra_pmc_pctl_desc.npins = pmc->soc->num_pin_descs;
2178 
2179 	pmc->pctl_dev = devm_pinctrl_register(pmc->dev, &tegra_pmc_pctl_desc,
2180 					      pmc);
2181 	if (IS_ERR(pmc->pctl_dev)) {
2182 		err = PTR_ERR(pmc->pctl_dev);
2183 		dev_err(pmc->dev, "failed to register pin controller: %d\n",
2184 			err);
2185 		return err;
2186 	}
2187 
2188 	return 0;
2189 }
2190 
reset_reason_show(struct device * dev,struct device_attribute * attr,char * buf)2191 static ssize_t reset_reason_show(struct device *dev,
2192 				 struct device_attribute *attr, char *buf)
2193 {
2194 	u32 value;
2195 
2196 	value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status);
2197 	value &= pmc->soc->regs->rst_source_mask;
2198 	value >>= pmc->soc->regs->rst_source_shift;
2199 
2200 	if (WARN_ON(value >= pmc->soc->num_reset_sources))
2201 		return sprintf(buf, "%s\n", "UNKNOWN");
2202 
2203 	return sprintf(buf, "%s\n", pmc->soc->reset_sources[value]);
2204 }
2205 
2206 static DEVICE_ATTR_RO(reset_reason);
2207 
reset_level_show(struct device * dev,struct device_attribute * attr,char * buf)2208 static ssize_t reset_level_show(struct device *dev,
2209 				struct device_attribute *attr, char *buf)
2210 {
2211 	u32 value;
2212 
2213 	value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status);
2214 	value &= pmc->soc->regs->rst_level_mask;
2215 	value >>= pmc->soc->regs->rst_level_shift;
2216 
2217 	if (WARN_ON(value >= pmc->soc->num_reset_levels))
2218 		return sprintf(buf, "%s\n", "UNKNOWN");
2219 
2220 	return sprintf(buf, "%s\n", pmc->soc->reset_levels[value]);
2221 }
2222 
2223 static DEVICE_ATTR_RO(reset_level);
2224 
tegra_pmc_reset_sysfs_init(struct tegra_pmc * pmc)2225 static void tegra_pmc_reset_sysfs_init(struct tegra_pmc *pmc)
2226 {
2227 	struct device *dev = pmc->dev;
2228 	int err = 0;
2229 
2230 	if (pmc->soc->reset_sources) {
2231 		err = device_create_file(dev, &dev_attr_reset_reason);
2232 		if (err < 0)
2233 			dev_warn(dev,
2234 				 "failed to create attr \"reset_reason\": %d\n",
2235 				 err);
2236 	}
2237 
2238 	if (pmc->soc->reset_levels) {
2239 		err = device_create_file(dev, &dev_attr_reset_level);
2240 		if (err < 0)
2241 			dev_warn(dev,
2242 				 "failed to create attr \"reset_level\": %d\n",
2243 				 err);
2244 	}
2245 }
2246 
tegra_pmc_irq_translate(struct irq_domain * domain,struct irq_fwspec * fwspec,unsigned long * hwirq,unsigned int * type)2247 static int tegra_pmc_irq_translate(struct irq_domain *domain,
2248 				   struct irq_fwspec *fwspec,
2249 				   unsigned long *hwirq,
2250 				   unsigned int *type)
2251 {
2252 	if (WARN_ON(fwspec->param_count < 2))
2253 		return -EINVAL;
2254 
2255 	*hwirq = fwspec->param[0];
2256 	*type = fwspec->param[1];
2257 
2258 	return 0;
2259 }
2260 
tegra_pmc_irq_alloc(struct irq_domain * domain,unsigned int virq,unsigned int num_irqs,void * data)2261 static int tegra_pmc_irq_alloc(struct irq_domain *domain, unsigned int virq,
2262 			       unsigned int num_irqs, void *data)
2263 {
2264 	struct tegra_pmc *pmc = domain->host_data;
2265 	const struct tegra_pmc_soc *soc = pmc->soc;
2266 	struct irq_fwspec *fwspec = data;
2267 	unsigned int i;
2268 	int err = 0;
2269 
2270 	if (WARN_ON(num_irqs > 1))
2271 		return -EINVAL;
2272 
2273 	for (i = 0; i < soc->num_wake_events; i++) {
2274 		const struct tegra_wake_event *event = &soc->wake_events[i];
2275 
2276 		/* IRQ and simple wake events */
2277 		if (fwspec->param_count == 2) {
2278 			struct irq_fwspec spec;
2279 
2280 			if (event->id != fwspec->param[0])
2281 				continue;
2282 
2283 			err = irq_domain_set_hwirq_and_chip(domain, virq,
2284 							    event->id,
2285 							    &pmc->irq, pmc);
2286 			if (err < 0)
2287 				break;
2288 
2289 			/* simple hierarchies stop at the PMC level */
2290 			if (event->irq == 0) {
2291 				err = irq_domain_disconnect_hierarchy(domain->parent, virq);
2292 				break;
2293 			}
2294 
2295 			spec.fwnode = &pmc->dev->of_node->fwnode;
2296 			spec.param_count = 3;
2297 			spec.param[0] = GIC_SPI;
2298 			spec.param[1] = event->irq;
2299 			spec.param[2] = fwspec->param[1];
2300 
2301 			err = irq_domain_alloc_irqs_parent(domain, virq,
2302 							   num_irqs, &spec);
2303 
2304 			break;
2305 		}
2306 
2307 		/* GPIO wake events */
2308 		if (fwspec->param_count == 3) {
2309 			if (event->gpio.instance != fwspec->param[0] ||
2310 			    event->gpio.pin != fwspec->param[1])
2311 				continue;
2312 
2313 			err = irq_domain_set_hwirq_and_chip(domain, virq,
2314 							    event->id,
2315 							    &pmc->irq, pmc);
2316 
2317 			/* GPIO hierarchies stop at the PMC level */
2318 			if (!err && domain->parent)
2319 				err = irq_domain_disconnect_hierarchy(domain->parent,
2320 								      virq);
2321 			break;
2322 		}
2323 	}
2324 
2325 	/* If there is no wake-up event, there is no PMC mapping */
2326 	if (i == soc->num_wake_events)
2327 		err = irq_domain_disconnect_hierarchy(domain, virq);
2328 
2329 	return err;
2330 }
2331 
2332 static const struct irq_domain_ops tegra_pmc_irq_domain_ops = {
2333 	.translate = tegra_pmc_irq_translate,
2334 	.alloc = tegra_pmc_irq_alloc,
2335 };
2336 
tegra210_pmc_irq_set_wake(struct irq_data * data,unsigned int on)2337 static int tegra210_pmc_irq_set_wake(struct irq_data *data, unsigned int on)
2338 {
2339 	struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
2340 	unsigned int offset, bit;
2341 	u32 value;
2342 
2343 	offset = data->hwirq / 32;
2344 	bit = data->hwirq % 32;
2345 
2346 	/* clear wake status */
2347 	tegra_pmc_writel(pmc, 0, PMC_SW_WAKE_STATUS);
2348 	tegra_pmc_writel(pmc, 0, PMC_SW_WAKE2_STATUS);
2349 
2350 	tegra_pmc_writel(pmc, 0, PMC_WAKE_STATUS);
2351 	tegra_pmc_writel(pmc, 0, PMC_WAKE2_STATUS);
2352 
2353 	/* enable PMC wake */
2354 	if (data->hwirq >= 32)
2355 		offset = PMC_WAKE2_MASK;
2356 	else
2357 		offset = PMC_WAKE_MASK;
2358 
2359 	value = tegra_pmc_readl(pmc, offset);
2360 
2361 	if (on)
2362 		value |= BIT(bit);
2363 	else
2364 		value &= ~BIT(bit);
2365 
2366 	tegra_pmc_writel(pmc, value, offset);
2367 
2368 	return 0;
2369 }
2370 
tegra210_pmc_irq_set_type(struct irq_data * data,unsigned int type)2371 static int tegra210_pmc_irq_set_type(struct irq_data *data, unsigned int type)
2372 {
2373 	struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
2374 	unsigned int offset, bit;
2375 	u32 value;
2376 
2377 	offset = data->hwirq / 32;
2378 	bit = data->hwirq % 32;
2379 
2380 	if (data->hwirq >= 32)
2381 		offset = PMC_WAKE2_LEVEL;
2382 	else
2383 		offset = PMC_WAKE_LEVEL;
2384 
2385 	value = tegra_pmc_readl(pmc, offset);
2386 
2387 	switch (type) {
2388 	case IRQ_TYPE_EDGE_RISING:
2389 	case IRQ_TYPE_LEVEL_HIGH:
2390 		value |= BIT(bit);
2391 		break;
2392 
2393 	case IRQ_TYPE_EDGE_FALLING:
2394 	case IRQ_TYPE_LEVEL_LOW:
2395 		value &= ~BIT(bit);
2396 		break;
2397 
2398 	case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING:
2399 		value ^= BIT(bit);
2400 		break;
2401 
2402 	default:
2403 		return -EINVAL;
2404 	}
2405 
2406 	tegra_pmc_writel(pmc, value, offset);
2407 
2408 	return 0;
2409 }
2410 
tegra186_pmc_set_wake_filters(struct tegra_pmc * pmc)2411 static void tegra186_pmc_set_wake_filters(struct tegra_pmc *pmc)
2412 {
2413 	u32 value;
2414 
2415 	/* SW Wake (wake83) needs SR_CAPTURE filter to be enabled */
2416 	value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(SW_WAKE_ID));
2417 	value |= WAKE_AOWAKE_CNTRL_SR_CAPTURE_EN;
2418 	writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(SW_WAKE_ID));
2419 	dev_dbg(pmc->dev, "WAKE_AOWAKE_CNTRL_83 = 0x%x\n", value);
2420 }
2421 
tegra186_pmc_irq_set_wake(struct irq_data * data,unsigned int on)2422 static int tegra186_pmc_irq_set_wake(struct irq_data *data, unsigned int on)
2423 {
2424 	struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
2425 	unsigned int offset, bit;
2426 	u32 value;
2427 
2428 	offset = data->hwirq / 32;
2429 	bit = data->hwirq % 32;
2430 
2431 	/* clear wake status */
2432 	writel(0x1, pmc->wake + WAKE_AOWAKE_STATUS_W(data->hwirq));
2433 
2434 	/* route wake to tier 2 */
2435 	value = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset));
2436 
2437 	if (!on)
2438 		value &= ~(1 << bit);
2439 	else
2440 		value |= 1 << bit;
2441 
2442 	writel(value, pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset));
2443 
2444 	/* enable wakeup event */
2445 	writel(!!on, pmc->wake + WAKE_AOWAKE_MASK_W(data->hwirq));
2446 
2447 	return 0;
2448 }
2449 
tegra186_pmc_irq_set_type(struct irq_data * data,unsigned int type)2450 static int tegra186_pmc_irq_set_type(struct irq_data *data, unsigned int type)
2451 {
2452 	struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
2453 	u32 value;
2454 
2455 	value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq));
2456 
2457 	switch (type) {
2458 	case IRQ_TYPE_EDGE_RISING:
2459 	case IRQ_TYPE_LEVEL_HIGH:
2460 		value |= WAKE_AOWAKE_CNTRL_LEVEL;
2461 		set_bit(data->hwirq, pmc->wake_type_level_map);
2462 		clear_bit(data->hwirq, pmc->wake_type_dual_edge_map);
2463 		break;
2464 
2465 	case IRQ_TYPE_EDGE_FALLING:
2466 	case IRQ_TYPE_LEVEL_LOW:
2467 		value &= ~WAKE_AOWAKE_CNTRL_LEVEL;
2468 		clear_bit(data->hwirq, pmc->wake_type_level_map);
2469 		clear_bit(data->hwirq, pmc->wake_type_dual_edge_map);
2470 		break;
2471 
2472 	case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING:
2473 		value ^= WAKE_AOWAKE_CNTRL_LEVEL;
2474 		clear_bit(data->hwirq, pmc->wake_type_level_map);
2475 		set_bit(data->hwirq, pmc->wake_type_dual_edge_map);
2476 		break;
2477 
2478 	default:
2479 		return -EINVAL;
2480 	}
2481 
2482 	writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq));
2483 
2484 	return 0;
2485 }
2486 
tegra_irq_mask_parent(struct irq_data * data)2487 static void tegra_irq_mask_parent(struct irq_data *data)
2488 {
2489 	if (data->parent_data)
2490 		irq_chip_mask_parent(data);
2491 }
2492 
tegra_irq_unmask_parent(struct irq_data * data)2493 static void tegra_irq_unmask_parent(struct irq_data *data)
2494 {
2495 	if (data->parent_data)
2496 		irq_chip_unmask_parent(data);
2497 }
2498 
tegra_irq_eoi_parent(struct irq_data * data)2499 static void tegra_irq_eoi_parent(struct irq_data *data)
2500 {
2501 	if (data->parent_data)
2502 		irq_chip_eoi_parent(data);
2503 }
2504 
tegra_irq_set_affinity_parent(struct irq_data * data,const struct cpumask * dest,bool force)2505 static int tegra_irq_set_affinity_parent(struct irq_data *data,
2506 					 const struct cpumask *dest,
2507 					 bool force)
2508 {
2509 	if (data->parent_data)
2510 		return irq_chip_set_affinity_parent(data, dest, force);
2511 
2512 	return -EINVAL;
2513 }
2514 
tegra_pmc_irq_init(struct tegra_pmc * pmc)2515 static int tegra_pmc_irq_init(struct tegra_pmc *pmc)
2516 {
2517 	struct irq_domain *parent = NULL;
2518 	struct device_node *np;
2519 
2520 	np = of_irq_find_parent(pmc->dev->of_node);
2521 	if (np) {
2522 		parent = irq_find_host(np);
2523 		of_node_put(np);
2524 	}
2525 
2526 	if (!parent)
2527 		return 0;
2528 
2529 	pmc->irq.name = dev_name(pmc->dev);
2530 	pmc->irq.irq_mask = tegra_irq_mask_parent;
2531 	pmc->irq.irq_unmask = tegra_irq_unmask_parent;
2532 	pmc->irq.irq_eoi = tegra_irq_eoi_parent;
2533 	pmc->irq.irq_set_affinity = tegra_irq_set_affinity_parent;
2534 	pmc->irq.irq_set_type = pmc->soc->irq_set_type;
2535 	pmc->irq.irq_set_wake = pmc->soc->irq_set_wake;
2536 
2537 	pmc->domain = irq_domain_add_hierarchy(parent, 0, 96, pmc->dev->of_node,
2538 					       &tegra_pmc_irq_domain_ops, pmc);
2539 	if (!pmc->domain) {
2540 		dev_err(pmc->dev, "failed to allocate domain\n");
2541 		return -ENOMEM;
2542 	}
2543 
2544 	return 0;
2545 }
2546 
tegra_pmc_clk_notify_cb(struct notifier_block * nb,unsigned long action,void * ptr)2547 static int tegra_pmc_clk_notify_cb(struct notifier_block *nb,
2548 				   unsigned long action, void *ptr)
2549 {
2550 	struct tegra_pmc *pmc = container_of(nb, struct tegra_pmc, clk_nb);
2551 	struct clk_notifier_data *data = ptr;
2552 
2553 	switch (action) {
2554 	case PRE_RATE_CHANGE:
2555 		mutex_lock(&pmc->powergates_lock);
2556 		break;
2557 
2558 	case POST_RATE_CHANGE:
2559 		pmc->rate = data->new_rate;
2560 		fallthrough;
2561 
2562 	case ABORT_RATE_CHANGE:
2563 		mutex_unlock(&pmc->powergates_lock);
2564 		break;
2565 
2566 	default:
2567 		WARN_ON_ONCE(1);
2568 		return notifier_from_errno(-EINVAL);
2569 	}
2570 
2571 	return NOTIFY_OK;
2572 }
2573 
pmc_clk_fence_udelay(u32 offset)2574 static void pmc_clk_fence_udelay(u32 offset)
2575 {
2576 	tegra_pmc_readl(pmc, offset);
2577 	/* pmc clk propagation delay 2 us */
2578 	udelay(2);
2579 }
2580 
pmc_clk_mux_get_parent(struct clk_hw * hw)2581 static u8 pmc_clk_mux_get_parent(struct clk_hw *hw)
2582 {
2583 	struct pmc_clk *clk = to_pmc_clk(hw);
2584 	u32 val;
2585 
2586 	val = tegra_pmc_readl(pmc, clk->offs) >> clk->mux_shift;
2587 	val &= PMC_CLK_OUT_MUX_MASK;
2588 
2589 	return val;
2590 }
2591 
pmc_clk_mux_set_parent(struct clk_hw * hw,u8 index)2592 static int pmc_clk_mux_set_parent(struct clk_hw *hw, u8 index)
2593 {
2594 	struct pmc_clk *clk = to_pmc_clk(hw);
2595 	u32 val;
2596 
2597 	val = tegra_pmc_readl(pmc, clk->offs);
2598 	val &= ~(PMC_CLK_OUT_MUX_MASK << clk->mux_shift);
2599 	val |= index << clk->mux_shift;
2600 	tegra_pmc_writel(pmc, val, clk->offs);
2601 	pmc_clk_fence_udelay(clk->offs);
2602 
2603 	return 0;
2604 }
2605 
pmc_clk_is_enabled(struct clk_hw * hw)2606 static int pmc_clk_is_enabled(struct clk_hw *hw)
2607 {
2608 	struct pmc_clk *clk = to_pmc_clk(hw);
2609 	u32 val;
2610 
2611 	val = tegra_pmc_readl(pmc, clk->offs) & BIT(clk->force_en_shift);
2612 
2613 	return val ? 1 : 0;
2614 }
2615 
pmc_clk_set_state(unsigned long offs,u32 shift,int state)2616 static void pmc_clk_set_state(unsigned long offs, u32 shift, int state)
2617 {
2618 	u32 val;
2619 
2620 	val = tegra_pmc_readl(pmc, offs);
2621 	val = state ? (val | BIT(shift)) : (val & ~BIT(shift));
2622 	tegra_pmc_writel(pmc, val, offs);
2623 	pmc_clk_fence_udelay(offs);
2624 }
2625 
pmc_clk_enable(struct clk_hw * hw)2626 static int pmc_clk_enable(struct clk_hw *hw)
2627 {
2628 	struct pmc_clk *clk = to_pmc_clk(hw);
2629 
2630 	pmc_clk_set_state(clk->offs, clk->force_en_shift, 1);
2631 
2632 	return 0;
2633 }
2634 
pmc_clk_disable(struct clk_hw * hw)2635 static void pmc_clk_disable(struct clk_hw *hw)
2636 {
2637 	struct pmc_clk *clk = to_pmc_clk(hw);
2638 
2639 	pmc_clk_set_state(clk->offs, clk->force_en_shift, 0);
2640 }
2641 
2642 static const struct clk_ops pmc_clk_ops = {
2643 	.get_parent = pmc_clk_mux_get_parent,
2644 	.set_parent = pmc_clk_mux_set_parent,
2645 	.determine_rate = __clk_mux_determine_rate,
2646 	.is_enabled = pmc_clk_is_enabled,
2647 	.enable = pmc_clk_enable,
2648 	.disable = pmc_clk_disable,
2649 };
2650 
2651 static struct clk *
tegra_pmc_clk_out_register(struct tegra_pmc * pmc,const struct pmc_clk_init_data * data,unsigned long offset)2652 tegra_pmc_clk_out_register(struct tegra_pmc *pmc,
2653 			   const struct pmc_clk_init_data *data,
2654 			   unsigned long offset)
2655 {
2656 	struct clk_init_data init;
2657 	struct pmc_clk *pmc_clk;
2658 
2659 	pmc_clk = devm_kzalloc(pmc->dev, sizeof(*pmc_clk), GFP_KERNEL);
2660 	if (!pmc_clk)
2661 		return ERR_PTR(-ENOMEM);
2662 
2663 	init.name = data->name;
2664 	init.ops = &pmc_clk_ops;
2665 	init.parent_names = data->parents;
2666 	init.num_parents = data->num_parents;
2667 	init.flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT |
2668 		     CLK_SET_PARENT_GATE;
2669 
2670 	pmc_clk->hw.init = &init;
2671 	pmc_clk->offs = offset;
2672 	pmc_clk->mux_shift = data->mux_shift;
2673 	pmc_clk->force_en_shift = data->force_en_shift;
2674 
2675 	return clk_register(NULL, &pmc_clk->hw);
2676 }
2677 
pmc_clk_gate_is_enabled(struct clk_hw * hw)2678 static int pmc_clk_gate_is_enabled(struct clk_hw *hw)
2679 {
2680 	struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
2681 
2682 	return tegra_pmc_readl(pmc, gate->offs) & BIT(gate->shift) ? 1 : 0;
2683 }
2684 
pmc_clk_gate_enable(struct clk_hw * hw)2685 static int pmc_clk_gate_enable(struct clk_hw *hw)
2686 {
2687 	struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
2688 
2689 	pmc_clk_set_state(gate->offs, gate->shift, 1);
2690 
2691 	return 0;
2692 }
2693 
pmc_clk_gate_disable(struct clk_hw * hw)2694 static void pmc_clk_gate_disable(struct clk_hw *hw)
2695 {
2696 	struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
2697 
2698 	pmc_clk_set_state(gate->offs, gate->shift, 0);
2699 }
2700 
2701 static const struct clk_ops pmc_clk_gate_ops = {
2702 	.is_enabled = pmc_clk_gate_is_enabled,
2703 	.enable = pmc_clk_gate_enable,
2704 	.disable = pmc_clk_gate_disable,
2705 };
2706 
2707 static struct clk *
tegra_pmc_clk_gate_register(struct tegra_pmc * pmc,const char * name,const char * parent_name,unsigned long offset,u32 shift)2708 tegra_pmc_clk_gate_register(struct tegra_pmc *pmc, const char *name,
2709 			    const char *parent_name, unsigned long offset,
2710 			    u32 shift)
2711 {
2712 	struct clk_init_data init;
2713 	struct pmc_clk_gate *gate;
2714 
2715 	gate = devm_kzalloc(pmc->dev, sizeof(*gate), GFP_KERNEL);
2716 	if (!gate)
2717 		return ERR_PTR(-ENOMEM);
2718 
2719 	init.name = name;
2720 	init.ops = &pmc_clk_gate_ops;
2721 	init.parent_names = &parent_name;
2722 	init.num_parents = 1;
2723 	init.flags = 0;
2724 
2725 	gate->hw.init = &init;
2726 	gate->offs = offset;
2727 	gate->shift = shift;
2728 
2729 	return clk_register(NULL, &gate->hw);
2730 }
2731 
tegra_pmc_clock_register(struct tegra_pmc * pmc,struct device_node * np)2732 static void tegra_pmc_clock_register(struct tegra_pmc *pmc,
2733 				     struct device_node *np)
2734 {
2735 	struct clk *clk;
2736 	struct clk_onecell_data *clk_data;
2737 	unsigned int num_clks;
2738 	int i, err;
2739 
2740 	num_clks = pmc->soc->num_pmc_clks;
2741 	if (pmc->soc->has_blink_output)
2742 		num_clks += 1;
2743 
2744 	if (!num_clks)
2745 		return;
2746 
2747 	clk_data = devm_kmalloc(pmc->dev, sizeof(*clk_data), GFP_KERNEL);
2748 	if (!clk_data)
2749 		return;
2750 
2751 	clk_data->clks = devm_kcalloc(pmc->dev, TEGRA_PMC_CLK_MAX,
2752 				      sizeof(*clk_data->clks), GFP_KERNEL);
2753 	if (!clk_data->clks)
2754 		return;
2755 
2756 	clk_data->clk_num = TEGRA_PMC_CLK_MAX;
2757 
2758 	for (i = 0; i < TEGRA_PMC_CLK_MAX; i++)
2759 		clk_data->clks[i] = ERR_PTR(-ENOENT);
2760 
2761 	for (i = 0; i < pmc->soc->num_pmc_clks; i++) {
2762 		const struct pmc_clk_init_data *data;
2763 
2764 		data = pmc->soc->pmc_clks_data + i;
2765 
2766 		clk = tegra_pmc_clk_out_register(pmc, data, PMC_CLK_OUT_CNTRL);
2767 		if (IS_ERR(clk)) {
2768 			dev_warn(pmc->dev, "unable to register clock %s: %d\n",
2769 				 data->name, PTR_ERR_OR_ZERO(clk));
2770 			return;
2771 		}
2772 
2773 		err = clk_register_clkdev(clk, data->name, NULL);
2774 		if (err) {
2775 			dev_warn(pmc->dev,
2776 				 "unable to register %s clock lookup: %d\n",
2777 				 data->name, err);
2778 			return;
2779 		}
2780 
2781 		clk_data->clks[data->clk_id] = clk;
2782 	}
2783 
2784 	if (pmc->soc->has_blink_output) {
2785 		tegra_pmc_writel(pmc, 0x0, PMC_BLINK_TIMER);
2786 		clk = tegra_pmc_clk_gate_register(pmc,
2787 						  "pmc_blink_override",
2788 						  "clk_32k",
2789 						  PMC_DPD_PADS_ORIDE,
2790 						  PMC_DPD_PADS_ORIDE_BLINK);
2791 		if (IS_ERR(clk)) {
2792 			dev_warn(pmc->dev,
2793 				 "unable to register pmc_blink_override: %d\n",
2794 				 PTR_ERR_OR_ZERO(clk));
2795 			return;
2796 		}
2797 
2798 		clk = tegra_pmc_clk_gate_register(pmc, "pmc_blink",
2799 						  "pmc_blink_override",
2800 						  PMC_CNTRL,
2801 						  PMC_CNTRL_BLINK_EN);
2802 		if (IS_ERR(clk)) {
2803 			dev_warn(pmc->dev,
2804 				 "unable to register pmc_blink: %d\n",
2805 				 PTR_ERR_OR_ZERO(clk));
2806 			return;
2807 		}
2808 
2809 		err = clk_register_clkdev(clk, "pmc_blink", NULL);
2810 		if (err) {
2811 			dev_warn(pmc->dev,
2812 				 "unable to register pmc_blink lookup: %d\n",
2813 				 err);
2814 			return;
2815 		}
2816 
2817 		clk_data->clks[TEGRA_PMC_CLK_BLINK] = clk;
2818 	}
2819 
2820 	err = of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
2821 	if (err)
2822 		dev_warn(pmc->dev, "failed to add pmc clock provider: %d\n",
2823 			 err);
2824 }
2825 
2826 static const struct regmap_range pmc_usb_sleepwalk_ranges[] = {
2827 	regmap_reg_range(PMC_USB_DEBOUNCE_DEL, PMC_USB_AO),
2828 	regmap_reg_range(PMC_UTMIP_UHSIC_TRIGGERS, PMC_UTMIP_UHSIC_SAVED_STATE),
2829 	regmap_reg_range(PMC_UTMIP_TERM_PAD_CFG, PMC_UTMIP_UHSIC_FAKE),
2830 	regmap_reg_range(PMC_UTMIP_UHSIC_LINE_WAKEUP, PMC_UTMIP_UHSIC_LINE_WAKEUP),
2831 	regmap_reg_range(PMC_UTMIP_BIAS_MASTER_CNTRL, PMC_UTMIP_MASTER_CONFIG),
2832 	regmap_reg_range(PMC_UTMIP_UHSIC2_TRIGGERS, PMC_UTMIP_MASTER2_CONFIG),
2833 	regmap_reg_range(PMC_UTMIP_PAD_CFG0, PMC_UTMIP_UHSIC_SLEEP_CFG1),
2834 	regmap_reg_range(PMC_UTMIP_SLEEPWALK_P3, PMC_UTMIP_SLEEPWALK_P3),
2835 };
2836 
2837 static const struct regmap_access_table pmc_usb_sleepwalk_table = {
2838 	.yes_ranges = pmc_usb_sleepwalk_ranges,
2839 	.n_yes_ranges = ARRAY_SIZE(pmc_usb_sleepwalk_ranges),
2840 };
2841 
tegra_pmc_regmap_readl(void * context,unsigned int offset,unsigned int * value)2842 static int tegra_pmc_regmap_readl(void *context, unsigned int offset, unsigned int *value)
2843 {
2844 	struct tegra_pmc *pmc = context;
2845 
2846 	*value = tegra_pmc_readl(pmc, offset);
2847 	return 0;
2848 }
2849 
tegra_pmc_regmap_writel(void * context,unsigned int offset,unsigned int value)2850 static int tegra_pmc_regmap_writel(void *context, unsigned int offset, unsigned int value)
2851 {
2852 	struct tegra_pmc *pmc = context;
2853 
2854 	tegra_pmc_writel(pmc, value, offset);
2855 	return 0;
2856 }
2857 
2858 static const struct regmap_config usb_sleepwalk_regmap_config = {
2859 	.name = "usb_sleepwalk",
2860 	.reg_bits = 32,
2861 	.val_bits = 32,
2862 	.reg_stride = 4,
2863 	.fast_io = true,
2864 	.rd_table = &pmc_usb_sleepwalk_table,
2865 	.wr_table = &pmc_usb_sleepwalk_table,
2866 	.reg_read = tegra_pmc_regmap_readl,
2867 	.reg_write = tegra_pmc_regmap_writel,
2868 };
2869 
tegra_pmc_regmap_init(struct tegra_pmc * pmc)2870 static int tegra_pmc_regmap_init(struct tegra_pmc *pmc)
2871 {
2872 	struct regmap *regmap;
2873 	int err;
2874 
2875 	if (pmc->soc->has_usb_sleepwalk) {
2876 		regmap = devm_regmap_init(pmc->dev, NULL, pmc, &usb_sleepwalk_regmap_config);
2877 		if (IS_ERR(regmap)) {
2878 			err = PTR_ERR(regmap);
2879 			dev_err(pmc->dev, "failed to allocate register map (%d)\n", err);
2880 			return err;
2881 		}
2882 	}
2883 
2884 	return 0;
2885 }
2886 
tegra_pmc_reset_suspend_mode(void * data)2887 static void tegra_pmc_reset_suspend_mode(void *data)
2888 {
2889 	pmc->suspend_mode = TEGRA_SUSPEND_NOT_READY;
2890 }
2891 
tegra_pmc_probe(struct platform_device * pdev)2892 static int tegra_pmc_probe(struct platform_device *pdev)
2893 {
2894 	void __iomem *base;
2895 	struct resource *res;
2896 	int err;
2897 
2898 	/*
2899 	 * Early initialisation should have configured an initial
2900 	 * register mapping and setup the soc data pointer. If these
2901 	 * are not valid then something went badly wrong!
2902 	 */
2903 	if (WARN_ON(!pmc->base || !pmc->soc))
2904 		return -ENODEV;
2905 
2906 	err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node);
2907 	if (err < 0)
2908 		return err;
2909 
2910 	err = devm_add_action_or_reset(&pdev->dev, tegra_pmc_reset_suspend_mode,
2911 				       NULL);
2912 	if (err)
2913 		return err;
2914 
2915 	/* take over the memory region from the early initialization */
2916 	base = devm_platform_ioremap_resource(pdev, 0);
2917 	if (IS_ERR(base))
2918 		return PTR_ERR(base);
2919 
2920 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "wake");
2921 	if (res) {
2922 		pmc->wake = devm_ioremap_resource(&pdev->dev, res);
2923 		if (IS_ERR(pmc->wake))
2924 			return PTR_ERR(pmc->wake);
2925 	} else {
2926 		pmc->wake = base;
2927 	}
2928 
2929 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "aotag");
2930 	if (res) {
2931 		pmc->aotag = devm_ioremap_resource(&pdev->dev, res);
2932 		if (IS_ERR(pmc->aotag))
2933 			return PTR_ERR(pmc->aotag);
2934 	} else {
2935 		pmc->aotag = base;
2936 	}
2937 
2938 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "scratch");
2939 	if (res) {
2940 		pmc->scratch = devm_ioremap_resource(&pdev->dev, res);
2941 		if (IS_ERR(pmc->scratch))
2942 			return PTR_ERR(pmc->scratch);
2943 	} else {
2944 		pmc->scratch = base;
2945 	}
2946 
2947 	pmc->clk = devm_clk_get_optional(&pdev->dev, "pclk");
2948 	if (IS_ERR(pmc->clk))
2949 		return dev_err_probe(&pdev->dev, PTR_ERR(pmc->clk),
2950 				     "failed to get pclk\n");
2951 
2952 	/*
2953 	 * PMC should be last resort for restarting since it soft-resets
2954 	 * CPU without resetting everything else.
2955 	 */
2956 	err = devm_register_reboot_notifier(&pdev->dev,
2957 					    &tegra_pmc_reboot_notifier);
2958 	if (err) {
2959 		dev_err(&pdev->dev, "unable to register reboot notifier, %d\n",
2960 			err);
2961 		return err;
2962 	}
2963 
2964 	err = devm_register_sys_off_handler(&pdev->dev,
2965 					    SYS_OFF_MODE_RESTART,
2966 					    SYS_OFF_PRIO_LOW,
2967 					    tegra_pmc_restart_handler, NULL);
2968 	if (err) {
2969 		dev_err(&pdev->dev, "failed to register sys-off handler: %d\n",
2970 			err);
2971 		return err;
2972 	}
2973 
2974 	/*
2975 	 * PMC should be primary power-off method if it soft-resets CPU,
2976 	 * asking bootloader to shutdown hardware.
2977 	 */
2978 	err = devm_register_sys_off_handler(&pdev->dev,
2979 					    SYS_OFF_MODE_POWER_OFF,
2980 					    SYS_OFF_PRIO_FIRMWARE,
2981 					    tegra_pmc_power_off_handler, NULL);
2982 	if (err) {
2983 		dev_err(&pdev->dev, "failed to register sys-off handler: %d\n",
2984 			err);
2985 		return err;
2986 	}
2987 
2988 	/*
2989 	 * PCLK clock rate can't be retrieved using CLK API because it
2990 	 * causes lockup if CPU enters LP2 idle state from some other
2991 	 * CLK notifier, hence we're caching the rate's value locally.
2992 	 */
2993 	if (pmc->clk) {
2994 		pmc->clk_nb.notifier_call = tegra_pmc_clk_notify_cb;
2995 		err = devm_clk_notifier_register(&pdev->dev, pmc->clk,
2996 						 &pmc->clk_nb);
2997 		if (err) {
2998 			dev_err(&pdev->dev,
2999 				"failed to register clk notifier\n");
3000 			return err;
3001 		}
3002 
3003 		pmc->rate = clk_get_rate(pmc->clk);
3004 	}
3005 
3006 	pmc->dev = &pdev->dev;
3007 
3008 	err = tegra_pmc_init(pmc);
3009 	if (err < 0) {
3010 		dev_err(&pdev->dev, "failed to initialize PMC: %d\n", err);
3011 		return err;
3012 	}
3013 
3014 	tegra_pmc_init_tsense_reset(pmc);
3015 
3016 	tegra_pmc_reset_sysfs_init(pmc);
3017 
3018 	err = tegra_pmc_pinctrl_init(pmc);
3019 	if (err)
3020 		goto cleanup_sysfs;
3021 
3022 	err = tegra_pmc_regmap_init(pmc);
3023 	if (err < 0)
3024 		goto cleanup_sysfs;
3025 
3026 	err = tegra_powergate_init(pmc, pdev->dev.of_node);
3027 	if (err < 0)
3028 		goto cleanup_powergates;
3029 
3030 	err = tegra_pmc_irq_init(pmc);
3031 	if (err < 0)
3032 		goto cleanup_powergates;
3033 
3034 	mutex_lock(&pmc->powergates_lock);
3035 	iounmap(pmc->base);
3036 	pmc->base = base;
3037 	mutex_unlock(&pmc->powergates_lock);
3038 
3039 	tegra_pmc_clock_register(pmc, pdev->dev.of_node);
3040 	platform_set_drvdata(pdev, pmc);
3041 	tegra_pm_init_suspend();
3042 
3043 	/* Some wakes require specific filter configuration */
3044 	if (pmc->soc->set_wake_filters)
3045 		pmc->soc->set_wake_filters(pmc);
3046 
3047 	debugfs_create_file("powergate", 0444, NULL, NULL, &powergate_fops);
3048 
3049 	return 0;
3050 
3051 cleanup_powergates:
3052 	tegra_powergate_remove_all(pdev->dev.of_node);
3053 cleanup_sysfs:
3054 	device_remove_file(&pdev->dev, &dev_attr_reset_reason);
3055 	device_remove_file(&pdev->dev, &dev_attr_reset_level);
3056 
3057 	return err;
3058 }
3059 
3060 /*
3061  * Ensures that sufficient time is passed for a register write to
3062  * serialize into the 32KHz domain.
3063  */
wke_32kwritel(struct tegra_pmc * pmc,u32 value,unsigned int offset)3064 static void wke_32kwritel(struct tegra_pmc *pmc, u32 value, unsigned int offset)
3065 {
3066 	writel(value, pmc->wake + offset);
3067 	udelay(130);
3068 }
3069 
wke_write_wake_level(struct tegra_pmc * pmc,int wake,int level)3070 static void wke_write_wake_level(struct tegra_pmc *pmc, int wake, int level)
3071 {
3072 	unsigned int offset = WAKE_AOWAKE_CNTRL(wake);
3073 	u32 value;
3074 
3075 	value = readl(pmc->wake + offset);
3076 	if (level)
3077 		value |= WAKE_AOWAKE_CNTRL_LEVEL;
3078 	else
3079 		value &= ~WAKE_AOWAKE_CNTRL_LEVEL;
3080 
3081 	writel(value, pmc->wake + offset);
3082 }
3083 
wke_write_wake_levels(struct tegra_pmc * pmc)3084 static void wke_write_wake_levels(struct tegra_pmc *pmc)
3085 {
3086 	unsigned int i;
3087 
3088 	for (i = 0; i < pmc->soc->max_wake_events; i++)
3089 		wke_write_wake_level(pmc, i, test_bit(i, pmc->wake_cntrl_level_map));
3090 }
3091 
wke_clear_sw_wake_status(struct tegra_pmc * pmc)3092 static void wke_clear_sw_wake_status(struct tegra_pmc *pmc)
3093 {
3094 	wke_32kwritel(pmc, 1, WAKE_AOWAKE_SW_STATUS_W_0);
3095 }
3096 
wke_read_sw_wake_status(struct tegra_pmc * pmc)3097 static void wke_read_sw_wake_status(struct tegra_pmc *pmc)
3098 {
3099 	unsigned long status;
3100 	unsigned int wake, i;
3101 
3102 	for (i = 0; i < pmc->soc->max_wake_events; i++)
3103 		wke_write_wake_level(pmc, i, 0);
3104 
3105 	wke_clear_sw_wake_status(pmc);
3106 
3107 	wke_32kwritel(pmc, 1, WAKE_LATCH_SW);
3108 
3109 	/*
3110 	 * WAKE_AOWAKE_SW_STATUS is edge triggered, so in order to
3111 	 * obtain the current status of the input wake signals, change
3112 	 * the polarity of the wake level from 0->1 while latching to force
3113 	 * a positive edge if the sampled signal is '1'.
3114 	 */
3115 	for (i = 0; i < pmc->soc->max_wake_events; i++)
3116 		wke_write_wake_level(pmc, i, 1);
3117 
3118 	/*
3119 	 * Wait for the update to be synced into the 32kHz domain,
3120 	 * and let enough time lapse, so that the wake signals have time to
3121 	 * be sampled.
3122 	 */
3123 	udelay(300);
3124 
3125 	wke_32kwritel(pmc, 0, WAKE_LATCH_SW);
3126 
3127 	bitmap_zero(pmc->wake_sw_status_map, pmc->soc->max_wake_events);
3128 
3129 	for (i = 0; i < pmc->soc->max_wake_vectors; i++) {
3130 		status = readl(pmc->wake + WAKE_AOWAKE_SW_STATUS(i));
3131 
3132 		for_each_set_bit(wake, &status, 32)
3133 			set_bit(wake + (i * 32), pmc->wake_sw_status_map);
3134 	}
3135 }
3136 
wke_clear_wake_status(struct tegra_pmc * pmc)3137 static void wke_clear_wake_status(struct tegra_pmc *pmc)
3138 {
3139 	unsigned long status;
3140 	unsigned int i, wake;
3141 	u32 mask;
3142 
3143 	for (i = 0; i < pmc->soc->max_wake_vectors; i++) {
3144 		mask = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(i));
3145 		status = readl(pmc->wake + WAKE_AOWAKE_STATUS_R(i)) & mask;
3146 
3147 		for_each_set_bit(wake, &status, 32)
3148 			wke_32kwritel(pmc, 0x1, WAKE_AOWAKE_STATUS_W((i * 32) + wake));
3149 	}
3150 }
3151 
3152 /* translate sc7 wake sources back into IRQs to catch edge triggered wakeups */
tegra186_pmc_process_wake_events(struct tegra_pmc * pmc,unsigned int index,unsigned long status)3153 static void tegra186_pmc_process_wake_events(struct tegra_pmc *pmc, unsigned int index,
3154 					     unsigned long status)
3155 {
3156 	unsigned int wake;
3157 
3158 	dev_dbg(pmc->dev, "Wake[%d:%d]  status=%#lx\n", (index * 32) + 31, index * 32, status);
3159 
3160 	for_each_set_bit(wake, &status, 32) {
3161 		irq_hw_number_t hwirq = wake + 32 * index;
3162 		struct irq_desc *desc;
3163 		unsigned int irq;
3164 
3165 		irq = irq_find_mapping(pmc->domain, hwirq);
3166 
3167 		desc = irq_to_desc(irq);
3168 		if (!desc || !desc->action || !desc->action->name) {
3169 			dev_dbg(pmc->dev, "Resume caused by WAKE%ld, IRQ %d\n", hwirq, irq);
3170 			continue;
3171 		}
3172 
3173 		dev_dbg(pmc->dev, "Resume caused by WAKE%ld, %s\n", hwirq, desc->action->name);
3174 		generic_handle_irq(irq);
3175 	}
3176 }
3177 
tegra186_pmc_wake_syscore_resume(void)3178 static void tegra186_pmc_wake_syscore_resume(void)
3179 {
3180 	u32 status, mask;
3181 	unsigned int i;
3182 
3183 	for (i = 0; i < pmc->soc->max_wake_vectors; i++) {
3184 		mask = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(i));
3185 		status = readl(pmc->wake + WAKE_AOWAKE_STATUS_R(i)) & mask;
3186 
3187 		tegra186_pmc_process_wake_events(pmc, i, status);
3188 	}
3189 }
3190 
tegra186_pmc_wake_syscore_suspend(void)3191 static int tegra186_pmc_wake_syscore_suspend(void)
3192 {
3193 	wke_read_sw_wake_status(pmc);
3194 
3195 	/* flip the wakeup trigger for dual-edge triggered pads
3196 	 * which are currently asserting as wakeups
3197 	 */
3198 	bitmap_andnot(pmc->wake_cntrl_level_map, pmc->wake_type_dual_edge_map,
3199 		      pmc->wake_sw_status_map, pmc->soc->max_wake_events);
3200 	bitmap_or(pmc->wake_cntrl_level_map, pmc->wake_cntrl_level_map,
3201 		  pmc->wake_type_level_map, pmc->soc->max_wake_events);
3202 
3203 	/* Clear PMC Wake Status registers while going to suspend */
3204 	wke_clear_wake_status(pmc);
3205 	wke_write_wake_levels(pmc);
3206 
3207 	return 0;
3208 }
3209 
3210 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)
tegra_pmc_suspend(struct device * dev)3211 static int tegra_pmc_suspend(struct device *dev)
3212 {
3213 	struct tegra_pmc *pmc = dev_get_drvdata(dev);
3214 
3215 	tegra_pmc_writel(pmc, virt_to_phys(tegra_resume), PMC_SCRATCH41);
3216 
3217 	return 0;
3218 }
3219 
tegra_pmc_resume(struct device * dev)3220 static int tegra_pmc_resume(struct device *dev)
3221 {
3222 	struct tegra_pmc *pmc = dev_get_drvdata(dev);
3223 
3224 	tegra_pmc_writel(pmc, 0x0, PMC_SCRATCH41);
3225 
3226 	return 0;
3227 }
3228 
3229 static SIMPLE_DEV_PM_OPS(tegra_pmc_pm_ops, tegra_pmc_suspend, tegra_pmc_resume);
3230 
3231 #endif
3232 
3233 static const char * const tegra20_powergates[] = {
3234 	[TEGRA_POWERGATE_CPU] = "cpu",
3235 	[TEGRA_POWERGATE_3D] = "td",
3236 	[TEGRA_POWERGATE_VENC] = "venc",
3237 	[TEGRA_POWERGATE_VDEC] = "vdec",
3238 	[TEGRA_POWERGATE_PCIE] = "pcie",
3239 	[TEGRA_POWERGATE_L2] = "l2",
3240 	[TEGRA_POWERGATE_MPE] = "mpe",
3241 };
3242 
3243 static const struct tegra_pmc_regs tegra20_pmc_regs = {
3244 	.scratch0 = 0x50,
3245 	.rst_status = 0x1b4,
3246 	.rst_source_shift = 0x0,
3247 	.rst_source_mask = 0x7,
3248 	.rst_level_shift = 0x0,
3249 	.rst_level_mask = 0x0,
3250 };
3251 
tegra20_pmc_init(struct tegra_pmc * pmc)3252 static void tegra20_pmc_init(struct tegra_pmc *pmc)
3253 {
3254 	u32 value, osc, pmu, off;
3255 
3256 	/* Always enable CPU power request */
3257 	value = tegra_pmc_readl(pmc, PMC_CNTRL);
3258 	value |= PMC_CNTRL_CPU_PWRREQ_OE;
3259 	tegra_pmc_writel(pmc, value, PMC_CNTRL);
3260 
3261 	value = tegra_pmc_readl(pmc, PMC_CNTRL);
3262 
3263 	if (pmc->sysclkreq_high)
3264 		value &= ~PMC_CNTRL_SYSCLK_POLARITY;
3265 	else
3266 		value |= PMC_CNTRL_SYSCLK_POLARITY;
3267 
3268 	if (pmc->corereq_high)
3269 		value &= ~PMC_CNTRL_PWRREQ_POLARITY;
3270 	else
3271 		value |= PMC_CNTRL_PWRREQ_POLARITY;
3272 
3273 	/* configure the output polarity while the request is tristated */
3274 	tegra_pmc_writel(pmc, value, PMC_CNTRL);
3275 
3276 	/* now enable the request */
3277 	value = tegra_pmc_readl(pmc, PMC_CNTRL);
3278 	value |= PMC_CNTRL_SYSCLK_OE;
3279 	tegra_pmc_writel(pmc, value, PMC_CNTRL);
3280 
3281 	/* program core timings which are applicable only for suspend state */
3282 	if (pmc->suspend_mode != TEGRA_SUSPEND_NONE) {
3283 		osc = DIV_ROUND_UP(pmc->core_osc_time * 8192, 1000000);
3284 		pmu = DIV_ROUND_UP(pmc->core_pmu_time * 32768, 1000000);
3285 		off = DIV_ROUND_UP(pmc->core_off_time * 32768, 1000000);
3286 		tegra_pmc_writel(pmc, ((osc << 8) & 0xff00) | (pmu & 0xff),
3287 				 PMC_COREPWRGOOD_TIMER);
3288 		tegra_pmc_writel(pmc, off, PMC_COREPWROFF_TIMER);
3289 	}
3290 }
3291 
tegra20_pmc_setup_irq_polarity(struct tegra_pmc * pmc,struct device_node * np,bool invert)3292 static void tegra20_pmc_setup_irq_polarity(struct tegra_pmc *pmc,
3293 					   struct device_node *np,
3294 					   bool invert)
3295 {
3296 	u32 value;
3297 
3298 	value = tegra_pmc_readl(pmc, PMC_CNTRL);
3299 
3300 	if (invert)
3301 		value |= PMC_CNTRL_INTR_POLARITY;
3302 	else
3303 		value &= ~PMC_CNTRL_INTR_POLARITY;
3304 
3305 	tegra_pmc_writel(pmc, value, PMC_CNTRL);
3306 }
3307 
3308 static const struct tegra_pmc_soc tegra20_pmc_soc = {
3309 	.supports_core_domain = true,
3310 	.num_powergates = ARRAY_SIZE(tegra20_powergates),
3311 	.powergates = tegra20_powergates,
3312 	.num_cpu_powergates = 0,
3313 	.cpu_powergates = NULL,
3314 	.has_tsense_reset = false,
3315 	.has_gpu_clamps = false,
3316 	.needs_mbist_war = false,
3317 	.has_impl_33v_pwr = false,
3318 	.maybe_tz_only = false,
3319 	.num_io_pads = 0,
3320 	.io_pads = NULL,
3321 	.num_pin_descs = 0,
3322 	.pin_descs = NULL,
3323 	.regs = &tegra20_pmc_regs,
3324 	.init = tegra20_pmc_init,
3325 	.setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
3326 	.powergate_set = tegra20_powergate_set,
3327 	.reset_sources = NULL,
3328 	.num_reset_sources = 0,
3329 	.reset_levels = NULL,
3330 	.num_reset_levels = 0,
3331 	.pmc_clks_data = NULL,
3332 	.num_pmc_clks = 0,
3333 	.has_blink_output = true,
3334 	.has_usb_sleepwalk = true,
3335 };
3336 
3337 static const char * const tegra30_powergates[] = {
3338 	[TEGRA_POWERGATE_CPU] = "cpu0",
3339 	[TEGRA_POWERGATE_3D] = "td",
3340 	[TEGRA_POWERGATE_VENC] = "venc",
3341 	[TEGRA_POWERGATE_VDEC] = "vdec",
3342 	[TEGRA_POWERGATE_PCIE] = "pcie",
3343 	[TEGRA_POWERGATE_L2] = "l2",
3344 	[TEGRA_POWERGATE_MPE] = "mpe",
3345 	[TEGRA_POWERGATE_HEG] = "heg",
3346 	[TEGRA_POWERGATE_SATA] = "sata",
3347 	[TEGRA_POWERGATE_CPU1] = "cpu1",
3348 	[TEGRA_POWERGATE_CPU2] = "cpu2",
3349 	[TEGRA_POWERGATE_CPU3] = "cpu3",
3350 	[TEGRA_POWERGATE_CELP] = "celp",
3351 	[TEGRA_POWERGATE_3D1] = "td2",
3352 };
3353 
3354 static const u8 tegra30_cpu_powergates[] = {
3355 	TEGRA_POWERGATE_CPU,
3356 	TEGRA_POWERGATE_CPU1,
3357 	TEGRA_POWERGATE_CPU2,
3358 	TEGRA_POWERGATE_CPU3,
3359 };
3360 
3361 static const char * const tegra30_reset_sources[] = {
3362 	"POWER_ON_RESET",
3363 	"WATCHDOG",
3364 	"SENSOR",
3365 	"SW_MAIN",
3366 	"LP0"
3367 };
3368 
3369 static const struct tegra_pmc_soc tegra30_pmc_soc = {
3370 	.supports_core_domain = true,
3371 	.num_powergates = ARRAY_SIZE(tegra30_powergates),
3372 	.powergates = tegra30_powergates,
3373 	.num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates),
3374 	.cpu_powergates = tegra30_cpu_powergates,
3375 	.has_tsense_reset = true,
3376 	.has_gpu_clamps = false,
3377 	.needs_mbist_war = false,
3378 	.has_impl_33v_pwr = false,
3379 	.maybe_tz_only = false,
3380 	.num_io_pads = 0,
3381 	.io_pads = NULL,
3382 	.num_pin_descs = 0,
3383 	.pin_descs = NULL,
3384 	.regs = &tegra20_pmc_regs,
3385 	.init = tegra20_pmc_init,
3386 	.setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
3387 	.powergate_set = tegra20_powergate_set,
3388 	.reset_sources = tegra30_reset_sources,
3389 	.num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
3390 	.reset_levels = NULL,
3391 	.num_reset_levels = 0,
3392 	.pmc_clks_data = tegra_pmc_clks_data,
3393 	.num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
3394 	.has_blink_output = true,
3395 	.has_usb_sleepwalk = true,
3396 };
3397 
3398 static const char * const tegra114_powergates[] = {
3399 	[TEGRA_POWERGATE_CPU] = "crail",
3400 	[TEGRA_POWERGATE_3D] = "td",
3401 	[TEGRA_POWERGATE_VENC] = "venc",
3402 	[TEGRA_POWERGATE_VDEC] = "vdec",
3403 	[TEGRA_POWERGATE_MPE] = "mpe",
3404 	[TEGRA_POWERGATE_HEG] = "heg",
3405 	[TEGRA_POWERGATE_CPU1] = "cpu1",
3406 	[TEGRA_POWERGATE_CPU2] = "cpu2",
3407 	[TEGRA_POWERGATE_CPU3] = "cpu3",
3408 	[TEGRA_POWERGATE_CELP] = "celp",
3409 	[TEGRA_POWERGATE_CPU0] = "cpu0",
3410 	[TEGRA_POWERGATE_C0NC] = "c0nc",
3411 	[TEGRA_POWERGATE_C1NC] = "c1nc",
3412 	[TEGRA_POWERGATE_DIS] = "dis",
3413 	[TEGRA_POWERGATE_DISB] = "disb",
3414 	[TEGRA_POWERGATE_XUSBA] = "xusba",
3415 	[TEGRA_POWERGATE_XUSBB] = "xusbb",
3416 	[TEGRA_POWERGATE_XUSBC] = "xusbc",
3417 };
3418 
3419 static const u8 tegra114_cpu_powergates[] = {
3420 	TEGRA_POWERGATE_CPU0,
3421 	TEGRA_POWERGATE_CPU1,
3422 	TEGRA_POWERGATE_CPU2,
3423 	TEGRA_POWERGATE_CPU3,
3424 };
3425 
3426 static const struct tegra_pmc_soc tegra114_pmc_soc = {
3427 	.supports_core_domain = false,
3428 	.num_powergates = ARRAY_SIZE(tegra114_powergates),
3429 	.powergates = tegra114_powergates,
3430 	.num_cpu_powergates = ARRAY_SIZE(tegra114_cpu_powergates),
3431 	.cpu_powergates = tegra114_cpu_powergates,
3432 	.has_tsense_reset = true,
3433 	.has_gpu_clamps = false,
3434 	.needs_mbist_war = false,
3435 	.has_impl_33v_pwr = false,
3436 	.maybe_tz_only = false,
3437 	.num_io_pads = 0,
3438 	.io_pads = NULL,
3439 	.num_pin_descs = 0,
3440 	.pin_descs = NULL,
3441 	.regs = &tegra20_pmc_regs,
3442 	.init = tegra20_pmc_init,
3443 	.setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
3444 	.powergate_set = tegra114_powergate_set,
3445 	.reset_sources = tegra30_reset_sources,
3446 	.num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
3447 	.reset_levels = NULL,
3448 	.num_reset_levels = 0,
3449 	.pmc_clks_data = tegra_pmc_clks_data,
3450 	.num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
3451 	.has_blink_output = true,
3452 	.has_usb_sleepwalk = true,
3453 };
3454 
3455 static const char * const tegra124_powergates[] = {
3456 	[TEGRA_POWERGATE_CPU] = "crail",
3457 	[TEGRA_POWERGATE_3D] = "3d",
3458 	[TEGRA_POWERGATE_VENC] = "venc",
3459 	[TEGRA_POWERGATE_PCIE] = "pcie",
3460 	[TEGRA_POWERGATE_VDEC] = "vdec",
3461 	[TEGRA_POWERGATE_MPE] = "mpe",
3462 	[TEGRA_POWERGATE_HEG] = "heg",
3463 	[TEGRA_POWERGATE_SATA] = "sata",
3464 	[TEGRA_POWERGATE_CPU1] = "cpu1",
3465 	[TEGRA_POWERGATE_CPU2] = "cpu2",
3466 	[TEGRA_POWERGATE_CPU3] = "cpu3",
3467 	[TEGRA_POWERGATE_CELP] = "celp",
3468 	[TEGRA_POWERGATE_CPU0] = "cpu0",
3469 	[TEGRA_POWERGATE_C0NC] = "c0nc",
3470 	[TEGRA_POWERGATE_C1NC] = "c1nc",
3471 	[TEGRA_POWERGATE_SOR] = "sor",
3472 	[TEGRA_POWERGATE_DIS] = "dis",
3473 	[TEGRA_POWERGATE_DISB] = "disb",
3474 	[TEGRA_POWERGATE_XUSBA] = "xusba",
3475 	[TEGRA_POWERGATE_XUSBB] = "xusbb",
3476 	[TEGRA_POWERGATE_XUSBC] = "xusbc",
3477 	[TEGRA_POWERGATE_VIC] = "vic",
3478 	[TEGRA_POWERGATE_IRAM] = "iram",
3479 };
3480 
3481 static const u8 tegra124_cpu_powergates[] = {
3482 	TEGRA_POWERGATE_CPU0,
3483 	TEGRA_POWERGATE_CPU1,
3484 	TEGRA_POWERGATE_CPU2,
3485 	TEGRA_POWERGATE_CPU3,
3486 };
3487 
3488 #define TEGRA_IO_PAD(_id, _dpd, _request, _status, _voltage, _name)	\
3489 	((struct tegra_io_pad_soc) {					\
3490 		.id		= (_id),				\
3491 		.dpd		= (_dpd),				\
3492 		.request	= (_request),				\
3493 		.status		= (_status),				\
3494 		.voltage	= (_voltage),				\
3495 		.name		= (_name),				\
3496 	})
3497 
3498 #define TEGRA_IO_PIN_DESC(_id, _name)	\
3499 	((struct pinctrl_pin_desc) {	\
3500 		.number	= (_id),	\
3501 		.name	= (_name),	\
3502 	})
3503 
3504 static const struct tegra_io_pad_soc tegra124_io_pads[] = {
3505 	TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO, 17, 0x1b8, 0x1bc, UINT_MAX, "audio"),
3506 	TEGRA_IO_PAD(TEGRA_IO_PAD_BB, 15, 0x1b8, 0x1bc, UINT_MAX, "bb"),
3507 	TEGRA_IO_PAD(TEGRA_IO_PAD_CAM, 4, 0x1c0, 0x1c4, UINT_MAX, "cam"),
3508 	TEGRA_IO_PAD(TEGRA_IO_PAD_COMP, 22, 0x1b8, 0x1bc, UINT_MAX, "comp"),
3509 	TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0x1b8, 0x1bc, UINT_MAX, "csia"),
3510 	TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0x1b8, 0x1bc, UINT_MAX, "csib"),
3511 	TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 12, 0x1c0, 0x1c4, UINT_MAX, "csie"),
3512 	TEGRA_IO_PAD(TEGRA_IO_PAD_DSI, 2, 0x1b8, 0x1bc, UINT_MAX, "dsi"),
3513 	TEGRA_IO_PAD(TEGRA_IO_PAD_DSIB, 7, 0x1c0, 0x1c4, UINT_MAX, "dsib"),
3514 	TEGRA_IO_PAD(TEGRA_IO_PAD_DSIC, 8, 0x1c0, 0x1c4, UINT_MAX, "dsic"),
3515 	TEGRA_IO_PAD(TEGRA_IO_PAD_DSID, 9, 0x1c0, 0x1c4, UINT_MAX, "dsid"),
3516 	TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI, 28, 0x1b8, 0x1bc, UINT_MAX, "hdmi"),
3517 	TEGRA_IO_PAD(TEGRA_IO_PAD_HSIC, 19, 0x1b8, 0x1bc, UINT_MAX, "hsic"),
3518 	TEGRA_IO_PAD(TEGRA_IO_PAD_HV, 6, 0x1c0, 0x1c4, UINT_MAX, "hv"),
3519 	TEGRA_IO_PAD(TEGRA_IO_PAD_LVDS, 25, 0x1c0, 0x1c4, UINT_MAX, "lvds"),
3520 	TEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x1b8, 0x1bc, UINT_MAX, "mipi-bias"),
3521 	TEGRA_IO_PAD(TEGRA_IO_PAD_NAND, 13, 0x1b8, 0x1bc, UINT_MAX, "nand"),
3522 	TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_BIAS, 4, 0x1b8, 0x1bc, UINT_MAX, "pex-bias"),
3523 	TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 5, 0x1b8, 0x1bc, UINT_MAX, "pex-clk1"),
3524 	TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x1b8, 0x1bc, UINT_MAX, "pex-clk2"),
3525 	TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, 0, 0x1c0, 0x1c4, UINT_MAX, "pex-cntrl"),
3526 	TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1, 1, 0x1c0, 0x1c4, UINT_MAX, "sdmmc1"),
3527 	TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3, 2, 0x1c0, 0x1c4, UINT_MAX, "sdmmc3"),
3528 	TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC4, 3, 0x1c0, 0x1c4, UINT_MAX, "sdmmc4"),
3529 	TEGRA_IO_PAD(TEGRA_IO_PAD_SYS_DDC, 26, 0x1c0, 0x1c4, UINT_MAX, "sys_ddc"),
3530 	TEGRA_IO_PAD(TEGRA_IO_PAD_UART, 14, 0x1b8, 0x1bc, UINT_MAX, "uart"),
3531 	TEGRA_IO_PAD(TEGRA_IO_PAD_USB0, 9, 0x1b8, 0x1bc, UINT_MAX, "usb0"),
3532 	TEGRA_IO_PAD(TEGRA_IO_PAD_USB1, 10, 0x1b8, 0x1bc, UINT_MAX, "usb1"),
3533 	TEGRA_IO_PAD(TEGRA_IO_PAD_USB2, 11, 0x1b8, 0x1bc, UINT_MAX, "usb2"),
3534 	TEGRA_IO_PAD(TEGRA_IO_PAD_USB_BIAS, 12, 0x1b8, 0x1bc, UINT_MAX, "usb_bias"),
3535 };
3536 
3537 static const struct pinctrl_pin_desc tegra124_pin_descs[] = {
3538 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO, "audio"),
3539 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_BB, "bb"),
3540 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CAM, "cam"),
3541 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_COMP, "comp"),
3542 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"),
3543 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"),
3544 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"),
3545 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSI, "dsi"),
3546 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIB, "dsib"),
3547 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIC, "dsic"),
3548 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSID, "dsid"),
3549 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI, "hdmi"),
3550 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HSIC, "hsic"),
3551 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HV, "hv"),
3552 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_LVDS, "lvds"),
3553 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_MIPI_BIAS, "mipi-bias"),
3554 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_NAND, "nand"),
3555 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_BIAS, "pex-bias"),
3556 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK1, "pex-clk1"),
3557 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"),
3558 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CNTRL, "pex-cntrl"),
3559 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1, "sdmmc1"),
3560 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3, "sdmmc3"),
3561 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC4, "sdmmc4"),
3562 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SYS_DDC, "sys_ddc"),
3563 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART, "uart"),
3564 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB0, "usb0"),
3565 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB1, "usb1"),
3566 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB2, "usb2"),
3567 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB_BIAS, "usb_bias"),
3568 };
3569 
3570 static const struct tegra_pmc_soc tegra124_pmc_soc = {
3571 	.supports_core_domain = false,
3572 	.num_powergates = ARRAY_SIZE(tegra124_powergates),
3573 	.powergates = tegra124_powergates,
3574 	.num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates),
3575 	.cpu_powergates = tegra124_cpu_powergates,
3576 	.has_tsense_reset = true,
3577 	.has_gpu_clamps = true,
3578 	.needs_mbist_war = false,
3579 	.has_impl_33v_pwr = false,
3580 	.maybe_tz_only = false,
3581 	.num_io_pads = ARRAY_SIZE(tegra124_io_pads),
3582 	.io_pads = tegra124_io_pads,
3583 	.num_pin_descs = ARRAY_SIZE(tegra124_pin_descs),
3584 	.pin_descs = tegra124_pin_descs,
3585 	.regs = &tegra20_pmc_regs,
3586 	.init = tegra20_pmc_init,
3587 	.setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
3588 	.powergate_set = tegra114_powergate_set,
3589 	.reset_sources = tegra30_reset_sources,
3590 	.num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
3591 	.reset_levels = NULL,
3592 	.num_reset_levels = 0,
3593 	.pmc_clks_data = tegra_pmc_clks_data,
3594 	.num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
3595 	.has_blink_output = true,
3596 	.has_usb_sleepwalk = true,
3597 };
3598 
3599 static const char * const tegra210_powergates[] = {
3600 	[TEGRA_POWERGATE_CPU] = "crail",
3601 	[TEGRA_POWERGATE_3D] = "3d",
3602 	[TEGRA_POWERGATE_VENC] = "venc",
3603 	[TEGRA_POWERGATE_PCIE] = "pcie",
3604 	[TEGRA_POWERGATE_MPE] = "mpe",
3605 	[TEGRA_POWERGATE_SATA] = "sata",
3606 	[TEGRA_POWERGATE_CPU1] = "cpu1",
3607 	[TEGRA_POWERGATE_CPU2] = "cpu2",
3608 	[TEGRA_POWERGATE_CPU3] = "cpu3",
3609 	[TEGRA_POWERGATE_CPU0] = "cpu0",
3610 	[TEGRA_POWERGATE_C0NC] = "c0nc",
3611 	[TEGRA_POWERGATE_SOR] = "sor",
3612 	[TEGRA_POWERGATE_DIS] = "dis",
3613 	[TEGRA_POWERGATE_DISB] = "disb",
3614 	[TEGRA_POWERGATE_XUSBA] = "xusba",
3615 	[TEGRA_POWERGATE_XUSBB] = "xusbb",
3616 	[TEGRA_POWERGATE_XUSBC] = "xusbc",
3617 	[TEGRA_POWERGATE_VIC] = "vic",
3618 	[TEGRA_POWERGATE_IRAM] = "iram",
3619 	[TEGRA_POWERGATE_NVDEC] = "nvdec",
3620 	[TEGRA_POWERGATE_NVJPG] = "nvjpg",
3621 	[TEGRA_POWERGATE_AUD] = "aud",
3622 	[TEGRA_POWERGATE_DFD] = "dfd",
3623 	[TEGRA_POWERGATE_VE2] = "ve2",
3624 };
3625 
3626 static const u8 tegra210_cpu_powergates[] = {
3627 	TEGRA_POWERGATE_CPU0,
3628 	TEGRA_POWERGATE_CPU1,
3629 	TEGRA_POWERGATE_CPU2,
3630 	TEGRA_POWERGATE_CPU3,
3631 };
3632 
3633 static const struct tegra_io_pad_soc tegra210_io_pads[] = {
3634 	TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO, 17, 0x1b8, 0x1bc, 5, "audio"),
3635 	TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, 29, 0x1c0, 0x1c4, 18, "audio-hv"),
3636 	TEGRA_IO_PAD(TEGRA_IO_PAD_CAM, 4, 0x1c0, 0x1c4, 10, "cam"),
3637 	TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0x1b8, 0x1bc, UINT_MAX, "csia"),
3638 	TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0x1b8, 0x1bc, UINT_MAX, "csib"),
3639 	TEGRA_IO_PAD(TEGRA_IO_PAD_CSIC, 10, 0x1c0, 0x1c4, UINT_MAX, "csic"),
3640 	TEGRA_IO_PAD(TEGRA_IO_PAD_CSID, 11, 0x1c0, 0x1c4, UINT_MAX, "csid"),
3641 	TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 12, 0x1c0, 0x1c4, UINT_MAX, "csie"),
3642 	TEGRA_IO_PAD(TEGRA_IO_PAD_CSIF, 13, 0x1c0, 0x1c4, UINT_MAX, "csif"),
3643 	TEGRA_IO_PAD(TEGRA_IO_PAD_DBG, 25, 0x1b8, 0x1bc, 19, "dbg"),
3644 	TEGRA_IO_PAD(TEGRA_IO_PAD_DEBUG_NONAO, 26, 0x1b8, 0x1bc, UINT_MAX, "debug-nonao"),
3645 	TEGRA_IO_PAD(TEGRA_IO_PAD_DMIC, 18, 0x1c0, 0x1c4, 20, "dmic"),
3646 	TEGRA_IO_PAD(TEGRA_IO_PAD_DP, 19, 0x1c0, 0x1c4, UINT_MAX, "dp"),
3647 	TEGRA_IO_PAD(TEGRA_IO_PAD_DSI, 2, 0x1b8, 0x1bc, UINT_MAX, "dsi"),
3648 	TEGRA_IO_PAD(TEGRA_IO_PAD_DSIB, 7, 0x1c0, 0x1c4, UINT_MAX, "dsib"),
3649 	TEGRA_IO_PAD(TEGRA_IO_PAD_DSIC, 8, 0x1c0, 0x1c4, UINT_MAX, "dsic"),
3650 	TEGRA_IO_PAD(TEGRA_IO_PAD_DSID, 9, 0x1c0, 0x1c4, UINT_MAX, "dsid"),
3651 	TEGRA_IO_PAD(TEGRA_IO_PAD_EMMC, 3, 0x1c0, 0x1c4, UINT_MAX, "emmc"),
3652 	TEGRA_IO_PAD(TEGRA_IO_PAD_EMMC2, 5, 0x1c0, 0x1c4, UINT_MAX, "emmc2"),
3653 	TEGRA_IO_PAD(TEGRA_IO_PAD_GPIO, 27, 0x1b8, 0x1bc, 21, "gpio"),
3654 	TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI, 28, 0x1b8, 0x1bc, UINT_MAX, "hdmi"),
3655 	TEGRA_IO_PAD(TEGRA_IO_PAD_HSIC, 19, 0x1b8, 0x1bc, UINT_MAX, "hsic"),
3656 	TEGRA_IO_PAD(TEGRA_IO_PAD_LVDS, 25, 0x1c0, 0x1c4, UINT_MAX, "lvds"),
3657 	TEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x1b8, 0x1bc, UINT_MAX, "mipi-bias"),
3658 	TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_BIAS, 4, 0x1b8, 0x1bc, UINT_MAX, "pex-bias"),
3659 	TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 5, 0x1b8, 0x1bc, UINT_MAX, "pex-clk1"),
3660 	TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x1b8, 0x1bc, UINT_MAX, "pex-clk2"),
3661 	TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, UINT_MAX, UINT_MAX, UINT_MAX, 11, "pex-cntrl"),
3662 	TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1, 1, 0x1c0, 0x1c4, 12, "sdmmc1"),
3663 	TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3, 2, 0x1c0, 0x1c4, 13, "sdmmc3"),
3664 	TEGRA_IO_PAD(TEGRA_IO_PAD_SPI, 14, 0x1c0, 0x1c4, 22, "spi"),
3665 	TEGRA_IO_PAD(TEGRA_IO_PAD_SPI_HV, 15, 0x1c0, 0x1c4, 23, "spi-hv"),
3666 	TEGRA_IO_PAD(TEGRA_IO_PAD_UART, 14, 0x1b8, 0x1bc, 2, "uart"),
3667 	TEGRA_IO_PAD(TEGRA_IO_PAD_USB0, 9, 0x1b8, 0x1bc, UINT_MAX, "usb0"),
3668 	TEGRA_IO_PAD(TEGRA_IO_PAD_USB1, 10, 0x1b8, 0x1bc, UINT_MAX, "usb1"),
3669 	TEGRA_IO_PAD(TEGRA_IO_PAD_USB2, 11, 0x1b8, 0x1bc, UINT_MAX, "usb2"),
3670 	TEGRA_IO_PAD(TEGRA_IO_PAD_USB3, 18, 0x1b8, 0x1bc, UINT_MAX, "usb3"),
3671 	TEGRA_IO_PAD(TEGRA_IO_PAD_USB_BIAS, 12, 0x1b8, 0x1bc, UINT_MAX, "usb-bias"),
3672 };
3673 
3674 static const struct pinctrl_pin_desc tegra210_pin_descs[] = {
3675 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO, "audio"),
3676 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO_HV, "audio-hv"),
3677 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CAM, "cam"),
3678 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"),
3679 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"),
3680 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIC, "csic"),
3681 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSID, "csid"),
3682 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"),
3683 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIF, "csif"),
3684 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DBG, "dbg"),
3685 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DEBUG_NONAO, "debug-nonao"),
3686 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DMIC, "dmic"),
3687 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DP, "dp"),
3688 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSI, "dsi"),
3689 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIB, "dsib"),
3690 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIC, "dsic"),
3691 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSID, "dsid"),
3692 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EMMC, "emmc"),
3693 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EMMC2, "emmc2"),
3694 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_GPIO, "gpio"),
3695 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI, "hdmi"),
3696 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HSIC, "hsic"),
3697 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_LVDS, "lvds"),
3698 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_MIPI_BIAS, "mipi-bias"),
3699 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_BIAS, "pex-bias"),
3700 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK1, "pex-clk1"),
3701 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"),
3702 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CNTRL, "pex-cntrl"),
3703 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1, "sdmmc1"),
3704 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3, "sdmmc3"),
3705 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SPI, "spi"),
3706 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SPI_HV, "spi-hv"),
3707 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART, "uart"),
3708 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB0, "usb0"),
3709 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB1, "usb1"),
3710 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB2, "usb2"),
3711 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB3, "usb3"),
3712 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB_BIAS, "usb-bias"),
3713 };
3714 
3715 static const char * const tegra210_reset_sources[] = {
3716 	"POWER_ON_RESET",
3717 	"WATCHDOG",
3718 	"SENSOR",
3719 	"SW_MAIN",
3720 	"LP0",
3721 	"AOTAG"
3722 };
3723 
3724 static const struct tegra_wake_event tegra210_wake_events[] = {
3725 	TEGRA_WAKE_IRQ("rtc", 16, 2),
3726 	TEGRA_WAKE_IRQ("pmu", 51, 86),
3727 };
3728 
3729 static const struct tegra_pmc_soc tegra210_pmc_soc = {
3730 	.supports_core_domain = false,
3731 	.num_powergates = ARRAY_SIZE(tegra210_powergates),
3732 	.powergates = tegra210_powergates,
3733 	.num_cpu_powergates = ARRAY_SIZE(tegra210_cpu_powergates),
3734 	.cpu_powergates = tegra210_cpu_powergates,
3735 	.has_tsense_reset = true,
3736 	.has_gpu_clamps = true,
3737 	.needs_mbist_war = true,
3738 	.has_impl_33v_pwr = false,
3739 	.maybe_tz_only = true,
3740 	.num_io_pads = ARRAY_SIZE(tegra210_io_pads),
3741 	.io_pads = tegra210_io_pads,
3742 	.num_pin_descs = ARRAY_SIZE(tegra210_pin_descs),
3743 	.pin_descs = tegra210_pin_descs,
3744 	.regs = &tegra20_pmc_regs,
3745 	.init = tegra20_pmc_init,
3746 	.setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
3747 	.powergate_set = tegra114_powergate_set,
3748 	.irq_set_wake = tegra210_pmc_irq_set_wake,
3749 	.irq_set_type = tegra210_pmc_irq_set_type,
3750 	.reset_sources = tegra210_reset_sources,
3751 	.num_reset_sources = ARRAY_SIZE(tegra210_reset_sources),
3752 	.reset_levels = NULL,
3753 	.num_reset_levels = 0,
3754 	.num_wake_events = ARRAY_SIZE(tegra210_wake_events),
3755 	.wake_events = tegra210_wake_events,
3756 	.pmc_clks_data = tegra_pmc_clks_data,
3757 	.num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
3758 	.has_blink_output = true,
3759 	.has_usb_sleepwalk = true,
3760 };
3761 
3762 static const struct tegra_io_pad_soc tegra186_io_pads[] = {
3763 	TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0x74, 0x78, UINT_MAX, "csia"),
3764 	TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0x74, 0x78, UINT_MAX, "csib"),
3765 	TEGRA_IO_PAD(TEGRA_IO_PAD_DSI, 2, 0x74, 0x78, UINT_MAX, "dsi"),
3766 	TEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x74, 0x78, UINT_MAX, "mipi-bias"),
3767 	TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, 0x74, 0x78, UINT_MAX, "pex-clk-bias"),
3768 	TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK3, 5, 0x74, 0x78, UINT_MAX, "pex-clk3"),
3769 	TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x74, 0x78, UINT_MAX, "pex-clk2"),
3770 	TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 7, 0x74, 0x78, UINT_MAX, "pex-clk1"),
3771 	TEGRA_IO_PAD(TEGRA_IO_PAD_USB0, 9, 0x74, 0x78, UINT_MAX, "usb0"),
3772 	TEGRA_IO_PAD(TEGRA_IO_PAD_USB1, 10, 0x74, 0x78, UINT_MAX, "usb1"),
3773 	TEGRA_IO_PAD(TEGRA_IO_PAD_USB2, 11, 0x74, 0x78, UINT_MAX, "usb2"),
3774 	TEGRA_IO_PAD(TEGRA_IO_PAD_USB_BIAS, 12, 0x74, 0x78, UINT_MAX, "usb-bias"),
3775 	TEGRA_IO_PAD(TEGRA_IO_PAD_UART, 14, 0x74, 0x78, UINT_MAX, "uart"),
3776 	TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO, 17, 0x74, 0x78, UINT_MAX, "audio"),
3777 	TEGRA_IO_PAD(TEGRA_IO_PAD_HSIC, 19, 0x74, 0x78, UINT_MAX, "hsic"),
3778 	TEGRA_IO_PAD(TEGRA_IO_PAD_DBG, 25, 0x74, 0x78, UINT_MAX, "dbg"),
3779 	TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP0, 28, 0x74, 0x78, UINT_MAX, "hdmi-dp0"),
3780 	TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP1, 29, 0x74, 0x78, UINT_MAX, "hdmi-dp1"),
3781 	TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, 0, 0x7c, 0x80, UINT_MAX, "pex-cntrl"),
3782 	TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC2_HV, 2, 0x7c, 0x80, 5, "sdmmc2-hv"),
3783 	TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC4, 4, 0x7c, 0x80, UINT_MAX, "sdmmc4"),
3784 	TEGRA_IO_PAD(TEGRA_IO_PAD_CAM, 6, 0x7c, 0x80, UINT_MAX, "cam"),
3785 	TEGRA_IO_PAD(TEGRA_IO_PAD_DSIB, 8, 0x7c, 0x80, UINT_MAX, "dsib"),
3786 	TEGRA_IO_PAD(TEGRA_IO_PAD_DSIC, 9, 0x7c, 0x80, UINT_MAX, "dsic"),
3787 	TEGRA_IO_PAD(TEGRA_IO_PAD_DSID, 10, 0x7c, 0x80, UINT_MAX, "dsid"),
3788 	TEGRA_IO_PAD(TEGRA_IO_PAD_CSIC, 11, 0x7c, 0x80, UINT_MAX, "csic"),
3789 	TEGRA_IO_PAD(TEGRA_IO_PAD_CSID, 12, 0x7c, 0x80, UINT_MAX, "csid"),
3790 	TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 13, 0x7c, 0x80, UINT_MAX, "csie"),
3791 	TEGRA_IO_PAD(TEGRA_IO_PAD_CSIF, 14, 0x7c, 0x80, UINT_MAX, "csif"),
3792 	TEGRA_IO_PAD(TEGRA_IO_PAD_SPI, 15, 0x7c, 0x80, UINT_MAX, "spi"),
3793 	TEGRA_IO_PAD(TEGRA_IO_PAD_UFS, 17, 0x7c, 0x80, UINT_MAX, "ufs"),
3794 	TEGRA_IO_PAD(TEGRA_IO_PAD_DMIC_HV, 20, 0x7c, 0x80, 2, "dmic-hv"),
3795 	TEGRA_IO_PAD(TEGRA_IO_PAD_EDP, 21, 0x7c, 0x80, UINT_MAX, "edp"),
3796 	TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1_HV, 23, 0x7c, 0x80, 4, "sdmmc1-hv"),
3797 	TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3_HV, 24, 0x7c, 0x80, 6, "sdmmc3-hv"),
3798 	TEGRA_IO_PAD(TEGRA_IO_PAD_CONN, 28, 0x7c, 0x80, UINT_MAX, "conn"),
3799 	TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, 29, 0x7c, 0x80, 1, "audio-hv"),
3800 	TEGRA_IO_PAD(TEGRA_IO_PAD_AO_HV, UINT_MAX, UINT_MAX, UINT_MAX, 0, "ao-hv"),
3801 };
3802 
3803 static const struct pinctrl_pin_desc tegra186_pin_descs[] = {
3804 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"),
3805 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"),
3806 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSI, "dsi"),
3807 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_MIPI_BIAS, "mipi-bias"),
3808 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK_BIAS, "pex-clk-bias"),
3809 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK3, "pex-clk3"),
3810 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"),
3811 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK1, "pex-clk1"),
3812 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB0, "usb0"),
3813 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB1, "usb1"),
3814 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB2, "usb2"),
3815 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB_BIAS, "usb-bias"),
3816 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART, "uart"),
3817 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO, "audio"),
3818 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HSIC, "hsic"),
3819 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DBG, "dbg"),
3820 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP0, "hdmi-dp0"),
3821 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP1, "hdmi-dp1"),
3822 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CNTRL, "pex-cntrl"),
3823 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC2_HV, "sdmmc2-hv"),
3824 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC4, "sdmmc4"),
3825 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CAM, "cam"),
3826 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIB, "dsib"),
3827 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIC, "dsic"),
3828 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSID, "dsid"),
3829 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIC, "csic"),
3830 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSID, "csid"),
3831 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"),
3832 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIF, "csif"),
3833 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SPI, "spi"),
3834 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UFS, "ufs"),
3835 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DMIC_HV, "dmic-hv"),
3836 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EDP, "edp"),
3837 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1_HV, "sdmmc1-hv"),
3838 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3_HV, "sdmmc3-hv"),
3839 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CONN, "conn"),
3840 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO_HV, "audio-hv"),
3841 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AO_HV, "ao-hv"),
3842 };
3843 
3844 static const struct tegra_pmc_regs tegra186_pmc_regs = {
3845 	.scratch0 = 0x2000,
3846 	.rst_status = 0x70,
3847 	.rst_source_shift = 0x2,
3848 	.rst_source_mask = 0x3c,
3849 	.rst_level_shift = 0x0,
3850 	.rst_level_mask = 0x3,
3851 };
3852 
tegra186_pmc_init(struct tegra_pmc * pmc)3853 static void tegra186_pmc_init(struct tegra_pmc *pmc)
3854 {
3855 	pmc->syscore.suspend = tegra186_pmc_wake_syscore_suspend;
3856 	pmc->syscore.resume = tegra186_pmc_wake_syscore_resume;
3857 
3858 	register_syscore_ops(&pmc->syscore);
3859 }
3860 
tegra186_pmc_setup_irq_polarity(struct tegra_pmc * pmc,struct device_node * np,bool invert)3861 static void tegra186_pmc_setup_irq_polarity(struct tegra_pmc *pmc,
3862 					    struct device_node *np,
3863 					    bool invert)
3864 {
3865 	struct resource regs;
3866 	void __iomem *wake;
3867 	u32 value;
3868 	int index;
3869 
3870 	index = of_property_match_string(np, "reg-names", "wake");
3871 	if (index < 0) {
3872 		dev_err(pmc->dev, "failed to find PMC wake registers\n");
3873 		return;
3874 	}
3875 
3876 	of_address_to_resource(np, index, &regs);
3877 
3878 	wake = ioremap(regs.start, resource_size(&regs));
3879 	if (!wake) {
3880 		dev_err(pmc->dev, "failed to map PMC wake registers\n");
3881 		return;
3882 	}
3883 
3884 	value = readl(wake + WAKE_AOWAKE_CTRL);
3885 
3886 	if (invert)
3887 		value |= WAKE_AOWAKE_CTRL_INTR_POLARITY;
3888 	else
3889 		value &= ~WAKE_AOWAKE_CTRL_INTR_POLARITY;
3890 
3891 	writel(value, wake + WAKE_AOWAKE_CTRL);
3892 
3893 	iounmap(wake);
3894 }
3895 
3896 static const char * const tegra186_reset_sources[] = {
3897 	"SYS_RESET",
3898 	"AOWDT",
3899 	"MCCPLEXWDT",
3900 	"BPMPWDT",
3901 	"SCEWDT",
3902 	"SPEWDT",
3903 	"APEWDT",
3904 	"BCCPLEXWDT",
3905 	"SENSOR",
3906 	"AOTAG",
3907 	"VFSENSOR",
3908 	"SWREST",
3909 	"SC7",
3910 	"HSM",
3911 	"CORESIGHT"
3912 };
3913 
3914 static const char * const tegra186_reset_levels[] = {
3915 	"L0", "L1", "L2", "WARM"
3916 };
3917 
3918 static const struct tegra_wake_event tegra186_wake_events[] = {
3919 	TEGRA_WAKE_IRQ("pmu", 24, 209),
3920 	TEGRA_WAKE_GPIO("power", 29, 1, TEGRA186_AON_GPIO(FF, 0)),
3921 	TEGRA_WAKE_IRQ("rtc", 73, 10),
3922 };
3923 
3924 static const struct tegra_pmc_soc tegra186_pmc_soc = {
3925 	.supports_core_domain = false,
3926 	.num_powergates = 0,
3927 	.powergates = NULL,
3928 	.num_cpu_powergates = 0,
3929 	.cpu_powergates = NULL,
3930 	.has_tsense_reset = false,
3931 	.has_gpu_clamps = false,
3932 	.needs_mbist_war = false,
3933 	.has_impl_33v_pwr = true,
3934 	.maybe_tz_only = false,
3935 	.num_io_pads = ARRAY_SIZE(tegra186_io_pads),
3936 	.io_pads = tegra186_io_pads,
3937 	.num_pin_descs = ARRAY_SIZE(tegra186_pin_descs),
3938 	.pin_descs = tegra186_pin_descs,
3939 	.regs = &tegra186_pmc_regs,
3940 	.init = tegra186_pmc_init,
3941 	.setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
3942 	.set_wake_filters = tegra186_pmc_set_wake_filters,
3943 	.irq_set_wake = tegra186_pmc_irq_set_wake,
3944 	.irq_set_type = tegra186_pmc_irq_set_type,
3945 	.reset_sources = tegra186_reset_sources,
3946 	.num_reset_sources = ARRAY_SIZE(tegra186_reset_sources),
3947 	.reset_levels = tegra186_reset_levels,
3948 	.num_reset_levels = ARRAY_SIZE(tegra186_reset_levels),
3949 	.num_wake_events = ARRAY_SIZE(tegra186_wake_events),
3950 	.wake_events = tegra186_wake_events,
3951 	.max_wake_events = 96,
3952 	.max_wake_vectors = 3,
3953 	.pmc_clks_data = NULL,
3954 	.num_pmc_clks = 0,
3955 	.has_blink_output = false,
3956 	.has_usb_sleepwalk = false,
3957 };
3958 
3959 static const struct tegra_io_pad_soc tegra194_io_pads[] = {
3960 	TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0x74, 0x78, UINT_MAX, "csia"),
3961 	TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0x74, 0x78, UINT_MAX, "csib"),
3962 	TEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x74, 0x78, UINT_MAX, "mipi-bias"),
3963 	TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, 0x74, 0x78, UINT_MAX, "pex-clk-bias"),
3964 	TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK3, 5, 0x74, 0x78, UINT_MAX, "pex-clk3"),
3965 	TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x74, 0x78, UINT_MAX, "pex-clk2"),
3966 	TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 7, 0x74, 0x78, UINT_MAX, "pex-clk1"),
3967 	TEGRA_IO_PAD(TEGRA_IO_PAD_EQOS, 8, 0x74, 0x78, UINT_MAX, "eqos"),
3968 	TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_2_BIAS, 9, 0x74, 0x78, UINT_MAX, "pex-clk-2-bias"),
3969 	TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_2, 10, 0x74, 0x78, UINT_MAX, "pex-clk-2"),
3970 	TEGRA_IO_PAD(TEGRA_IO_PAD_DAP3, 11, 0x74, 0x78, UINT_MAX, "dap3"),
3971 	TEGRA_IO_PAD(TEGRA_IO_PAD_DAP5, 12, 0x74, 0x78, UINT_MAX, "dap5"),
3972 	TEGRA_IO_PAD(TEGRA_IO_PAD_UART, 14, 0x74, 0x78, UINT_MAX, "uart"),
3973 	TEGRA_IO_PAD(TEGRA_IO_PAD_PWR_CTL, 15, 0x74, 0x78, UINT_MAX, "pwr-ctl"),
3974 	TEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO53, 16, 0x74, 0x78, UINT_MAX, "soc-gpio53"),
3975 	TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO, 17, 0x74, 0x78, UINT_MAX, "audio"),
3976 	TEGRA_IO_PAD(TEGRA_IO_PAD_GP_PWM2, 18, 0x74, 0x78, UINT_MAX, "gp-pwm2"),
3977 	TEGRA_IO_PAD(TEGRA_IO_PAD_GP_PWM3, 19, 0x74, 0x78, UINT_MAX, "gp-pwm3"),
3978 	TEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO12, 20, 0x74, 0x78, UINT_MAX, "soc-gpio12"),
3979 	TEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO13, 21, 0x74, 0x78, UINT_MAX, "soc-gpio13"),
3980 	TEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO10, 22, 0x74, 0x78, UINT_MAX, "soc-gpio10"),
3981 	TEGRA_IO_PAD(TEGRA_IO_PAD_UART4, 23, 0x74, 0x78, UINT_MAX, "uart4"),
3982 	TEGRA_IO_PAD(TEGRA_IO_PAD_UART5, 24, 0x74, 0x78, UINT_MAX, "uart5"),
3983 	TEGRA_IO_PAD(TEGRA_IO_PAD_DBG, 25, 0x74, 0x78, UINT_MAX, "dbg"),
3984 	TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP3, 26, 0x74, 0x78, UINT_MAX, "hdmi-dp3"),
3985 	TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP2, 27, 0x74, 0x78, UINT_MAX, "hdmi-dp2"),
3986 	TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP0, 28, 0x74, 0x78, UINT_MAX, "hdmi-dp0"),
3987 	TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP1, 29, 0x74, 0x78, UINT_MAX, "hdmi-dp1"),
3988 	TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, 0, 0x7c, 0x80, UINT_MAX, "pex-cntrl"),
3989 	TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CTL2, 1, 0x7c, 0x80, UINT_MAX, "pex-ctl2"),
3990 	TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_L0_RST, 2, 0x7c, 0x80, UINT_MAX, "pex-l0-rst"),
3991 	TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_L1_RST, 3, 0x7c, 0x80, UINT_MAX, "pex-l1-rst"),
3992 	TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC4, 4, 0x7c, 0x80, UINT_MAX, "sdmmc4"),
3993 	TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_L5_RST, 5, 0x7c, 0x80, UINT_MAX, "pex-l5-rst"),
3994 	TEGRA_IO_PAD(TEGRA_IO_PAD_CAM, 6, 0x7c, 0x80, UINT_MAX, "cam"),
3995 	TEGRA_IO_PAD(TEGRA_IO_PAD_CSIC, 11, 0x7c, 0x80, UINT_MAX, "csic"),
3996 	TEGRA_IO_PAD(TEGRA_IO_PAD_CSID, 12, 0x7c, 0x80, UINT_MAX, "csid"),
3997 	TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 13, 0x7c, 0x80, UINT_MAX, "csie"),
3998 	TEGRA_IO_PAD(TEGRA_IO_PAD_CSIF, 14, 0x7c, 0x80, UINT_MAX, "csif"),
3999 	TEGRA_IO_PAD(TEGRA_IO_PAD_SPI, 15, 0x7c, 0x80, UINT_MAX, "spi"),
4000 	TEGRA_IO_PAD(TEGRA_IO_PAD_UFS, 17, 0x7c, 0x80, UINT_MAX, "ufs"),
4001 	TEGRA_IO_PAD(TEGRA_IO_PAD_CSIG, 18, 0x7c, 0x80, UINT_MAX, "csig"),
4002 	TEGRA_IO_PAD(TEGRA_IO_PAD_CSIH, 19, 0x7c, 0x80, UINT_MAX, "csih"),
4003 	TEGRA_IO_PAD(TEGRA_IO_PAD_EDP, 21, 0x7c, 0x80, UINT_MAX, "edp"),
4004 	TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1_HV, 23, 0x7c, 0x80, 4, "sdmmc1-hv"),
4005 	TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3_HV, 24, 0x7c, 0x80, 6, "sdmmc3-hv"),
4006 	TEGRA_IO_PAD(TEGRA_IO_PAD_CONN, 28, 0x7c, 0x80, UINT_MAX, "conn"),
4007 	TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, 29, 0x7c, 0x80, 1, "audio-hv"),
4008 	TEGRA_IO_PAD(TEGRA_IO_PAD_AO_HV, UINT_MAX, UINT_MAX, UINT_MAX, 0, "ao-hv"),
4009 };
4010 
4011 static const struct pinctrl_pin_desc tegra194_pin_descs[] = {
4012 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"),
4013 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"),
4014 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_MIPI_BIAS, "mipi-bias"),
4015 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK_BIAS, "pex-clk-bias"),
4016 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK3, "pex-clk3"),
4017 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"),
4018 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK1, "pex-clk1"),
4019 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EQOS, "eqos"),
4020 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK_2_BIAS, "pex-clk-2-bias"),
4021 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK_2, "pex-clk-2"),
4022 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DAP3, "dap3"),
4023 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DAP5, "dap5"),
4024 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART, "uart"),
4025 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PWR_CTL, "pwr-ctl"),
4026 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SOC_GPIO53, "soc-gpio53"),
4027 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO, "audio"),
4028 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_GP_PWM2, "gp-pwm2"),
4029 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_GP_PWM3, "gp-pwm3"),
4030 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SOC_GPIO12, "soc-gpio12"),
4031 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SOC_GPIO13, "soc-gpio13"),
4032 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SOC_GPIO10, "soc-gpio10"),
4033 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART4, "uart4"),
4034 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART5, "uart5"),
4035 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DBG, "dbg"),
4036 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP3, "hdmi-dp3"),
4037 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP2, "hdmi-dp2"),
4038 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP0, "hdmi-dp0"),
4039 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP1, "hdmi-dp1"),
4040 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CNTRL, "pex-cntrl"),
4041 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CTL2, "pex-ctl2"),
4042 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_L0_RST, "pex-l0-rst"),
4043 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_L1_RST, "pex-l1-rst"),
4044 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC4, "sdmmc4"),
4045 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_L5_RST, "pex-l5-rst"),
4046 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CAM, "cam"),
4047 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIC, "csic"),
4048 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSID, "csid"),
4049 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"),
4050 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIF, "csif"),
4051 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SPI, "spi"),
4052 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UFS, "ufs"),
4053 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIG, "csig"),
4054 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIH, "csih"),
4055 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EDP, "edp"),
4056 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1_HV, "sdmmc1-hv"),
4057 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3_HV, "sdmmc3-hv"),
4058 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CONN, "conn"),
4059 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO_HV, "audio-hv"),
4060 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AO_HV, "ao-hv"),
4061 };
4062 
4063 static const struct tegra_pmc_regs tegra194_pmc_regs = {
4064 	.scratch0 = 0x2000,
4065 	.rst_status = 0x70,
4066 	.rst_source_shift = 0x2,
4067 	.rst_source_mask = 0x7c,
4068 	.rst_level_shift = 0x0,
4069 	.rst_level_mask = 0x3,
4070 };
4071 
4072 static const char * const tegra194_reset_sources[] = {
4073 	"SYS_RESET_N",
4074 	"AOWDT",
4075 	"BCCPLEXWDT",
4076 	"BPMPWDT",
4077 	"SCEWDT",
4078 	"SPEWDT",
4079 	"APEWDT",
4080 	"LCCPLEXWDT",
4081 	"SENSOR",
4082 	"AOTAG",
4083 	"VFSENSOR",
4084 	"MAINSWRST",
4085 	"SC7",
4086 	"HSM",
4087 	"CSITE",
4088 	"RCEWDT",
4089 	"PVA0WDT",
4090 	"PVA1WDT",
4091 	"L1A_ASYNC",
4092 	"BPMPBOOT",
4093 	"FUSECRC",
4094 };
4095 
4096 static const struct tegra_wake_event tegra194_wake_events[] = {
4097 	TEGRA_WAKE_IRQ("pmu", 24, 209),
4098 	TEGRA_WAKE_GPIO("power", 29, 1, TEGRA194_AON_GPIO(EE, 4)),
4099 	TEGRA_WAKE_IRQ("rtc", 73, 10),
4100 	TEGRA_WAKE_SIMPLE("usb3-port-0", 76),
4101 	TEGRA_WAKE_SIMPLE("usb3-port-1", 77),
4102 	TEGRA_WAKE_SIMPLE("usb3-port-2-3", 78),
4103 	TEGRA_WAKE_SIMPLE("usb2-port-0", 79),
4104 	TEGRA_WAKE_SIMPLE("usb2-port-1", 80),
4105 	TEGRA_WAKE_SIMPLE("usb2-port-2", 81),
4106 	TEGRA_WAKE_SIMPLE("usb2-port-3", 82),
4107 };
4108 
4109 static const struct tegra_pmc_soc tegra194_pmc_soc = {
4110 	.supports_core_domain = false,
4111 	.num_powergates = 0,
4112 	.powergates = NULL,
4113 	.num_cpu_powergates = 0,
4114 	.cpu_powergates = NULL,
4115 	.has_tsense_reset = false,
4116 	.has_gpu_clamps = false,
4117 	.needs_mbist_war = false,
4118 	.has_impl_33v_pwr = true,
4119 	.maybe_tz_only = false,
4120 	.num_io_pads = ARRAY_SIZE(tegra194_io_pads),
4121 	.io_pads = tegra194_io_pads,
4122 	.num_pin_descs = ARRAY_SIZE(tegra194_pin_descs),
4123 	.pin_descs = tegra194_pin_descs,
4124 	.regs = &tegra194_pmc_regs,
4125 	.init = tegra186_pmc_init,
4126 	.setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
4127 	.set_wake_filters = tegra186_pmc_set_wake_filters,
4128 	.irq_set_wake = tegra186_pmc_irq_set_wake,
4129 	.irq_set_type = tegra186_pmc_irq_set_type,
4130 	.reset_sources = tegra194_reset_sources,
4131 	.num_reset_sources = ARRAY_SIZE(tegra194_reset_sources),
4132 	.reset_levels = tegra186_reset_levels,
4133 	.num_reset_levels = ARRAY_SIZE(tegra186_reset_levels),
4134 	.num_wake_events = ARRAY_SIZE(tegra194_wake_events),
4135 	.wake_events = tegra194_wake_events,
4136 	.max_wake_events = 96,
4137 	.max_wake_vectors = 3,
4138 	.pmc_clks_data = NULL,
4139 	.num_pmc_clks = 0,
4140 	.has_blink_output = false,
4141 	.has_usb_sleepwalk = false,
4142 };
4143 
4144 static const struct tegra_io_pad_soc tegra234_io_pads[] = {
4145 	TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0xe0c0, 0xe0c4, UINT_MAX, "csia"),
4146 	TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0xe0c0, 0xe0c4, UINT_MAX, "csib"),
4147 	TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP0, 0, 0xe0d0, 0xe0d4, UINT_MAX, "hdmi-dp0"),
4148 	TEGRA_IO_PAD(TEGRA_IO_PAD_CSIC, 2, 0xe0c0, 0xe0c4, UINT_MAX, "csic"),
4149 	TEGRA_IO_PAD(TEGRA_IO_PAD_CSID, 3, 0xe0c0, 0xe0c4, UINT_MAX, "csid"),
4150 	TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 4, 0xe0c0, 0xe0c4, UINT_MAX, "csie"),
4151 	TEGRA_IO_PAD(TEGRA_IO_PAD_CSIF, 5, 0xe0c0, 0xe0c4, UINT_MAX, "csif"),
4152 	TEGRA_IO_PAD(TEGRA_IO_PAD_UFS, 0, 0xe064, 0xe068, UINT_MAX, "ufs"),
4153 	TEGRA_IO_PAD(TEGRA_IO_PAD_EDP, 1, 0xe05c, 0xe060, UINT_MAX, "edp"),
4154 	TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1_HV, 0, 0xe054, 0xe058, 4, "sdmmc1-hv"),
4155 	TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3_HV, UINT_MAX, UINT_MAX, UINT_MAX, 6, "sdmmc3-hv"),
4156 	TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, UINT_MAX, UINT_MAX, UINT_MAX, 1, "audio-hv"),
4157 	TEGRA_IO_PAD(TEGRA_IO_PAD_AO_HV, UINT_MAX, UINT_MAX, UINT_MAX, 0, "ao-hv"),
4158 	TEGRA_IO_PAD(TEGRA_IO_PAD_CSIG, 6, 0xe0c0, 0xe0c4, UINT_MAX, "csig"),
4159 	TEGRA_IO_PAD(TEGRA_IO_PAD_CSIH, 7, 0xe0c0, 0xe0c4, UINT_MAX, "csih"),
4160 };
4161 
4162 static const struct pinctrl_pin_desc tegra234_pin_descs[] = {
4163 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"),
4164 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"),
4165 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP0, "hdmi-dp0"),
4166 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIC, "csic"),
4167 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSID, "csid"),
4168 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"),
4169 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIF, "csif"),
4170 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UFS, "ufs"),
4171 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EDP, "edp"),
4172 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1_HV, "sdmmc1-hv"),
4173 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3_HV, "sdmmc3-hv"),
4174 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO_HV, "audio-hv"),
4175 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AO_HV, "ao-hv"),
4176 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIG, "csig"),
4177 	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIH, "csih"),
4178 };
4179 
4180 static const struct tegra_pmc_regs tegra234_pmc_regs = {
4181 	.scratch0 = 0x2000,
4182 	.rst_status = 0x70,
4183 	.rst_source_shift = 0x2,
4184 	.rst_source_mask = 0xfc,
4185 	.rst_level_shift = 0x0,
4186 	.rst_level_mask = 0x3,
4187 };
4188 
4189 static const char * const tegra234_reset_sources[] = {
4190 	"SYS_RESET_N",	/* 0x0 */
4191 	"AOWDT",
4192 	"BCCPLEXWDT",
4193 	"BPMPWDT",
4194 	"SCEWDT",
4195 	"SPEWDT",
4196 	"APEWDT",
4197 	"LCCPLEXWDT",
4198 	"SENSOR",	/* 0x8 */
4199 	NULL,
4200 	NULL,
4201 	"MAINSWRST",
4202 	"SC7",
4203 	"HSM",
4204 	NULL,
4205 	"RCEWDT",
4206 	NULL,		/* 0x10 */
4207 	NULL,
4208 	NULL,
4209 	"BPMPBOOT",
4210 	"FUSECRC",
4211 	"DCEWDT",
4212 	"PSCWDT",
4213 	"PSC",
4214 	"CSITE_SW",	/* 0x18 */
4215 	"POD",
4216 	"SCPM",
4217 	"VREFRO_POWERBAD",
4218 	"VMON",
4219 	"FMON",
4220 	"FSI_R5WDT",
4221 	"FSI_THERM",
4222 	"FSI_R52C0WDT",	/* 0x20 */
4223 	"FSI_R52C1WDT",
4224 	"FSI_R52C2WDT",
4225 	"FSI_R52C3WDT",
4226 	"FSI_FMON",
4227 	"FSI_VMON",	/* 0x25 */
4228 };
4229 
4230 static const struct tegra_wake_event tegra234_wake_events[] = {
4231 	TEGRA_WAKE_IRQ("pmu", 24, 209),
4232 	TEGRA_WAKE_GPIO("power", 29, 1, TEGRA234_AON_GPIO(EE, 4)),
4233 	TEGRA_WAKE_GPIO("mgbe", 56, 0, TEGRA234_MAIN_GPIO(Y, 3)),
4234 	TEGRA_WAKE_IRQ("rtc", 73, 10),
4235 	TEGRA_WAKE_IRQ("sw-wake", SW_WAKE_ID, 179),
4236 };
4237 
4238 static const struct tegra_pmc_soc tegra234_pmc_soc = {
4239 	.supports_core_domain = false,
4240 	.num_powergates = 0,
4241 	.powergates = NULL,
4242 	.num_cpu_powergates = 0,
4243 	.cpu_powergates = NULL,
4244 	.has_tsense_reset = false,
4245 	.has_gpu_clamps = false,
4246 	.needs_mbist_war = false,
4247 	.has_impl_33v_pwr = true,
4248 	.maybe_tz_only = false,
4249 	.num_io_pads = ARRAY_SIZE(tegra234_io_pads),
4250 	.io_pads = tegra234_io_pads,
4251 	.num_pin_descs = ARRAY_SIZE(tegra234_pin_descs),
4252 	.pin_descs = tegra234_pin_descs,
4253 	.regs = &tegra234_pmc_regs,
4254 	.init = tegra186_pmc_init,
4255 	.setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
4256 	.set_wake_filters = tegra186_pmc_set_wake_filters,
4257 	.irq_set_wake = tegra186_pmc_irq_set_wake,
4258 	.irq_set_type = tegra186_pmc_irq_set_type,
4259 	.reset_sources = tegra234_reset_sources,
4260 	.num_reset_sources = ARRAY_SIZE(tegra234_reset_sources),
4261 	.reset_levels = tegra186_reset_levels,
4262 	.num_reset_levels = ARRAY_SIZE(tegra186_reset_levels),
4263 	.num_wake_events = ARRAY_SIZE(tegra234_wake_events),
4264 	.wake_events = tegra234_wake_events,
4265 	.max_wake_events = 96,
4266 	.max_wake_vectors = 3,
4267 	.pmc_clks_data = NULL,
4268 	.num_pmc_clks = 0,
4269 	.has_blink_output = false,
4270 };
4271 
4272 static const struct of_device_id tegra_pmc_match[] = {
4273 	{ .compatible = "nvidia,tegra234-pmc", .data = &tegra234_pmc_soc },
4274 	{ .compatible = "nvidia,tegra194-pmc", .data = &tegra194_pmc_soc },
4275 	{ .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc },
4276 	{ .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc },
4277 	{ .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc },
4278 	{ .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc },
4279 	{ .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc },
4280 	{ .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc },
4281 	{ .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc },
4282 	{ }
4283 };
4284 
tegra_pmc_sync_state(struct device * dev)4285 static void tegra_pmc_sync_state(struct device *dev)
4286 {
4287 	int err;
4288 
4289 	/*
4290 	 * Newer device-trees have power domains, but we need to prepare all
4291 	 * device drivers with runtime PM and OPP support first, otherwise
4292 	 * state syncing is unsafe.
4293 	 */
4294 	if (!pmc->soc->supports_core_domain)
4295 		return;
4296 
4297 	/*
4298 	 * Older device-trees don't have core PD, and thus, there are
4299 	 * no dependencies that will block the state syncing. We shouldn't
4300 	 * mark the domain as synced in this case.
4301 	 */
4302 	if (!pmc->core_domain_registered)
4303 		return;
4304 
4305 	pmc->core_domain_state_synced = true;
4306 
4307 	/* this is a no-op if core regulator isn't used */
4308 	mutex_lock(&pmc->powergates_lock);
4309 	err = dev_pm_opp_sync_regulators(dev);
4310 	mutex_unlock(&pmc->powergates_lock);
4311 
4312 	if (err)
4313 		dev_err(dev, "failed to sync regulators: %d\n", err);
4314 }
4315 
4316 static struct platform_driver tegra_pmc_driver = {
4317 	.driver = {
4318 		.name = "tegra-pmc",
4319 		.suppress_bind_attrs = true,
4320 		.of_match_table = tegra_pmc_match,
4321 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)
4322 		.pm = &tegra_pmc_pm_ops,
4323 #endif
4324 		.sync_state = tegra_pmc_sync_state,
4325 	},
4326 	.probe = tegra_pmc_probe,
4327 };
4328 builtin_platform_driver(tegra_pmc_driver);
4329 
tegra_pmc_detect_tz_only(struct tegra_pmc * pmc)4330 static bool __init tegra_pmc_detect_tz_only(struct tegra_pmc *pmc)
4331 {
4332 	u32 value, saved;
4333 
4334 	saved = readl(pmc->base + pmc->soc->regs->scratch0);
4335 	value = saved ^ 0xffffffff;
4336 
4337 	if (value == 0xffffffff)
4338 		value = 0xdeadbeef;
4339 
4340 	/* write pattern and read it back */
4341 	writel(value, pmc->base + pmc->soc->regs->scratch0);
4342 	value = readl(pmc->base + pmc->soc->regs->scratch0);
4343 
4344 	/* if we read all-zeroes, access is restricted to TZ only */
4345 	if (value == 0) {
4346 		pr_info("access to PMC is restricted to TZ\n");
4347 		return true;
4348 	}
4349 
4350 	/* restore original value */
4351 	writel(saved, pmc->base + pmc->soc->regs->scratch0);
4352 
4353 	return false;
4354 }
4355 
4356 /*
4357  * Early initialization to allow access to registers in the very early boot
4358  * process.
4359  */
tegra_pmc_early_init(void)4360 static int __init tegra_pmc_early_init(void)
4361 {
4362 	const struct of_device_id *match;
4363 	struct device_node *np;
4364 	struct resource regs;
4365 	unsigned int i;
4366 	bool invert;
4367 
4368 	mutex_init(&pmc->powergates_lock);
4369 
4370 	np = of_find_matching_node_and_match(NULL, tegra_pmc_match, &match);
4371 	if (!np) {
4372 		/*
4373 		 * Fall back to legacy initialization for 32-bit ARM only. All
4374 		 * 64-bit ARM device tree files for Tegra are required to have
4375 		 * a PMC node.
4376 		 *
4377 		 * This is for backwards-compatibility with old device trees
4378 		 * that didn't contain a PMC node. Note that in this case the
4379 		 * SoC data can't be matched and therefore powergating is
4380 		 * disabled.
4381 		 */
4382 		if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) {
4383 			pr_warn("DT node not found, powergating disabled\n");
4384 
4385 			regs.start = 0x7000e400;
4386 			regs.end = 0x7000e7ff;
4387 			regs.flags = IORESOURCE_MEM;
4388 
4389 			pr_warn("Using memory region %pR\n", &regs);
4390 		} else {
4391 			/*
4392 			 * At this point we're not running on Tegra, so play
4393 			 * nice with multi-platform kernels.
4394 			 */
4395 			return 0;
4396 		}
4397 	} else {
4398 		/*
4399 		 * Extract information from the device tree if we've found a
4400 		 * matching node.
4401 		 */
4402 		if (of_address_to_resource(np, 0, &regs) < 0) {
4403 			pr_err("failed to get PMC registers\n");
4404 			of_node_put(np);
4405 			return -ENXIO;
4406 		}
4407 	}
4408 
4409 	pmc->base = ioremap(regs.start, resource_size(&regs));
4410 	if (!pmc->base) {
4411 		pr_err("failed to map PMC registers\n");
4412 		of_node_put(np);
4413 		return -ENXIO;
4414 	}
4415 
4416 	if (of_device_is_available(np)) {
4417 		pmc->soc = match->data;
4418 
4419 		if (pmc->soc->maybe_tz_only)
4420 			pmc->tz_only = tegra_pmc_detect_tz_only(pmc);
4421 
4422 		/* Create a bitmap of the available and valid partitions */
4423 		for (i = 0; i < pmc->soc->num_powergates; i++)
4424 			if (pmc->soc->powergates[i])
4425 				set_bit(i, pmc->powergates_available);
4426 
4427 		/*
4428 		 * Invert the interrupt polarity if a PMC device tree node
4429 		 * exists and contains the nvidia,invert-interrupt property.
4430 		 */
4431 		invert = of_property_read_bool(np, "nvidia,invert-interrupt");
4432 
4433 		pmc->soc->setup_irq_polarity(pmc, np, invert);
4434 
4435 		of_node_put(np);
4436 	}
4437 
4438 	return 0;
4439 }
4440 early_initcall(tegra_pmc_early_init);
4441