1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * QLogic Fibre Channel HBA Driver
4  * Copyright (c)  2003-2014 QLogic Corporation
5  */
6 
7 #ifndef __QLA_DMP27_H__
8 #define	__QLA_DMP27_H__
9 
10 #define IOBASE_ADDR	offsetof(struct device_reg_24xx, iobase_addr)
11 
12 struct __packed qla27xx_fwdt_template {
13 	__le32 template_type;
14 	__le32 entry_offset;
15 	__le32 template_size;
16 	uint32_t count;		/* borrow field for running/residual count */
17 
18 	__le32 entry_count;
19 	uint32_t template_version;
20 	__le32 capture_timestamp;
21 	uint32_t template_checksum;
22 
23 	uint32_t reserved_2;
24 	__le32 driver_info[3];
25 
26 	uint32_t saved_state[16];
27 
28 	uint32_t reserved_3[8];
29 	__le32 firmware_version[5];
30 };
31 
32 #define TEMPLATE_TYPE_FWDUMP		99
33 
34 #define ENTRY_TYPE_NOP			0
35 #define ENTRY_TYPE_TMP_END		255
36 #define ENTRY_TYPE_RD_IOB_T1		256
37 #define ENTRY_TYPE_WR_IOB_T1		257
38 #define ENTRY_TYPE_RD_IOB_T2		258
39 #define ENTRY_TYPE_WR_IOB_T2		259
40 #define ENTRY_TYPE_RD_PCI		260
41 #define ENTRY_TYPE_WR_PCI		261
42 #define ENTRY_TYPE_RD_RAM		262
43 #define ENTRY_TYPE_GET_QUEUE		263
44 #define ENTRY_TYPE_GET_FCE		264
45 #define ENTRY_TYPE_PSE_RISC		265
46 #define ENTRY_TYPE_RST_RISC		266
47 #define ENTRY_TYPE_DIS_INTR		267
48 #define ENTRY_TYPE_GET_HBUF		268
49 #define ENTRY_TYPE_SCRATCH		269
50 #define ENTRY_TYPE_RDREMREG		270
51 #define ENTRY_TYPE_WRREMREG		271
52 #define ENTRY_TYPE_RDREMRAM		272
53 #define ENTRY_TYPE_PCICFG		273
54 #define ENTRY_TYPE_GET_SHADOW		274
55 #define ENTRY_TYPE_WRITE_BUF		275
56 #define ENTRY_TYPE_CONDITIONAL		276
57 #define ENTRY_TYPE_RDPEPREG		277
58 #define ENTRY_TYPE_WRPEPREG		278
59 
60 #define CAPTURE_FLAG_PHYS_ONLY		BIT_0
61 #define CAPTURE_FLAG_PHYS_VIRT		BIT_1
62 
63 #define DRIVER_FLAG_SKIP_ENTRY		BIT_7
64 
65 struct __packed qla27xx_fwdt_entry {
66 	struct __packed {
67 		__le32 type;
68 		__le32 size;
69 		uint32_t reserved_1;
70 
71 		uint8_t  capture_flags;
72 		uint8_t  reserved_2[2];
73 		uint8_t  driver_flags;
74 	} hdr;
75 	union __packed {
76 		struct __packed {
77 		} t0;
78 
79 		struct __packed {
80 		} t255;
81 
82 		struct __packed {
83 			__le32 base_addr;
84 			uint8_t  reg_width;
85 			__le16 reg_count;
86 			uint8_t  pci_offset;
87 		} t256;
88 
89 		struct __packed {
90 			__le32 base_addr;
91 			__le32 write_data;
92 			uint8_t  pci_offset;
93 			uint8_t  reserved[3];
94 		} t257;
95 
96 		struct __packed {
97 			__le32 base_addr;
98 			uint8_t  reg_width;
99 			__le16 reg_count;
100 			uint8_t  pci_offset;
101 			uint8_t  banksel_offset;
102 			uint8_t  reserved[3];
103 			__le32 bank;
104 		} t258;
105 
106 		struct __packed {
107 			__le32 base_addr;
108 			__le32 write_data;
109 			uint8_t  reserved[2];
110 			uint8_t  pci_offset;
111 			uint8_t  banksel_offset;
112 			__le32 bank;
113 		} t259;
114 
115 		struct __packed {
116 			uint8_t pci_offset;
117 			uint8_t reserved[3];
118 		} t260;
119 
120 		struct __packed {
121 			uint8_t pci_offset;
122 			uint8_t reserved[3];
123 			__le32 write_data;
124 		} t261;
125 
126 		struct __packed {
127 			uint8_t  ram_area;
128 			uint8_t  reserved[3];
129 			__le32 start_addr;
130 			__le32 end_addr;
131 		} t262;
132 
133 		struct __packed {
134 			uint32_t num_queues;
135 			uint8_t  queue_type;
136 			uint8_t  reserved[3];
137 		} t263;
138 
139 		struct __packed {
140 			uint32_t fce_trace_size;
141 			uint64_t write_pointer;
142 			uint64_t base_pointer;
143 			uint32_t fce_enable_mb0;
144 			uint32_t fce_enable_mb2;
145 			uint32_t fce_enable_mb3;
146 			uint32_t fce_enable_mb4;
147 			uint32_t fce_enable_mb5;
148 			uint32_t fce_enable_mb6;
149 		} t264;
150 
151 		struct __packed {
152 		} t265;
153 
154 		struct __packed {
155 		} t266;
156 
157 		struct __packed {
158 			uint8_t  pci_offset;
159 			uint8_t  reserved[3];
160 			__le32 data;
161 		} t267;
162 
163 		struct __packed {
164 			uint8_t  buf_type;
165 			uint8_t  reserved[3];
166 			uint32_t buf_size;
167 			uint64_t start_addr;
168 		} t268;
169 
170 		struct __packed {
171 			uint32_t scratch_size;
172 		} t269;
173 
174 		struct __packed {
175 			__le32 addr;
176 			__le32 count;
177 		} t270;
178 
179 		struct __packed {
180 			__le32 addr;
181 			__le32 data;
182 		} t271;
183 
184 		struct __packed {
185 			__le32 addr;
186 			__le32 count;
187 		} t272;
188 
189 		struct __packed {
190 			__le32 addr;
191 			__le32 count;
192 		} t273;
193 
194 		struct __packed {
195 			uint32_t num_queues;
196 			uint8_t  queue_type;
197 			uint8_t  reserved[3];
198 		} t274;
199 
200 		struct __packed {
201 			__le32 length;
202 			uint8_t  buffer[];
203 		} t275;
204 
205 		struct __packed {
206 			__le32 cond1;
207 			__le32 cond2;
208 		} t276;
209 
210 		struct __packed {
211 			__le32 cmd_addr;
212 			__le32 wr_cmd_data;
213 			__le32 data_addr;
214 		} t277;
215 
216 		struct __packed {
217 			__le32 cmd_addr;
218 			__le32 wr_cmd_data;
219 			__le32 data_addr;
220 			__le32 wr_data;
221 		} t278;
222 	};
223 };
224 
225 #define T262_RAM_AREA_CRITICAL_RAM	1
226 #define T262_RAM_AREA_EXTERNAL_RAM	2
227 #define T262_RAM_AREA_SHARED_RAM	3
228 #define T262_RAM_AREA_DDR_RAM		4
229 #define T262_RAM_AREA_MISC		5
230 
231 #define T263_QUEUE_TYPE_REQ		1
232 #define T263_QUEUE_TYPE_RSP		2
233 #define T263_QUEUE_TYPE_ATIO		3
234 
235 #define T268_BUF_TYPE_EXTD_TRACE	1
236 #define T268_BUF_TYPE_EXCH_BUFOFF	2
237 #define T268_BUF_TYPE_EXTD_LOGIN	3
238 #define T268_BUF_TYPE_REQ_MIRROR	4
239 #define T268_BUF_TYPE_RSP_MIRROR	5
240 
241 #define T274_QUEUE_TYPE_REQ_SHAD	1
242 #define T274_QUEUE_TYPE_RSP_SHAD	2
243 #define T274_QUEUE_TYPE_ATIO_SHAD	3
244 
245 #endif
246