1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * AMD Platform Management Framework Driver
4  *
5  * Copyright (c) 2022, Advanced Micro Devices, Inc.
6  * All Rights Reserved.
7  *
8  * Author: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
9  */
10 
11 #ifndef PMF_H
12 #define PMF_H
13 
14 #include <linux/acpi.h>
15 #include <linux/platform_profile.h>
16 
17 /* APMF Functions */
18 #define APMF_FUNC_VERIFY_INTERFACE			0
19 #define APMF_FUNC_GET_SYS_PARAMS			1
20 #define APMF_FUNC_SBIOS_REQUESTS			2
21 #define APMF_FUNC_SBIOS_HEARTBEAT			4
22 #define APMF_FUNC_AUTO_MODE					5
23 #define APMF_FUNC_SET_FAN_IDX				7
24 #define APMF_FUNC_OS_POWER_SLIDER_UPDATE		8
25 #define APMF_FUNC_STATIC_SLIDER_GRANULAR       9
26 #define APMF_FUNC_DYN_SLIDER_AC				11
27 #define APMF_FUNC_DYN_SLIDER_DC				12
28 
29 /* Message Definitions */
30 #define SET_SPL				0x03 /* SPL: Sustained Power Limit */
31 #define SET_SPPT			0x05 /* SPPT: Slow Package Power Tracking */
32 #define SET_FPPT			0x07 /* FPPT: Fast Package Power Tracking */
33 #define GET_SPL				0x0B
34 #define GET_SPPT			0x0D
35 #define GET_FPPT			0x0F
36 #define SET_DRAM_ADDR_HIGH	0x14
37 #define SET_DRAM_ADDR_LOW	0x15
38 #define SET_TRANSFER_TABLE	0x16
39 #define SET_STT_MIN_LIMIT	0x18 /* STT: Skin Temperature Tracking */
40 #define SET_STT_LIMIT_APU	0x19
41 #define SET_STT_LIMIT_HS2	0x1A
42 #define SET_SPPT_APU_ONLY	0x1D
43 #define GET_SPPT_APU_ONLY	0x1E
44 #define GET_STT_MIN_LIMIT	0x1F
45 #define GET_STT_LIMIT_APU	0x20
46 #define GET_STT_LIMIT_HS2	0x21
47 
48 /* OS slider update notification */
49 #define DC_BEST_PERF		0
50 #define DC_BETTER_PERF		1
51 #define DC_BATTERY_SAVER	3
52 #define AC_BEST_PERF		4
53 #define AC_BETTER_PERF		5
54 #define AC_BETTER_BATTERY	6
55 
56 /* Fan Index for Auto Mode */
57 #define FAN_INDEX_AUTO		0xFFFFFFFF
58 
59 #define ARG_NONE 0
60 #define AVG_SAMPLE_SIZE 3
61 
62 /* AMD PMF BIOS interfaces */
63 struct apmf_verify_interface {
64 	u16 size;
65 	u16 version;
66 	u32 notification_mask;
67 	u32 supported_functions;
68 } __packed;
69 
70 struct apmf_system_params {
71 	u16 size;
72 	u32 valid_mask;
73 	u32 flags;
74 	u8 command_code;
75 	u32 heartbeat_int;
76 } __packed;
77 
78 struct apmf_sbios_req {
79 	u16 size;
80 	u32 pending_req;
81 	u8 rsd;
82 	u8 cql_event;
83 	u8 amt_event;
84 	u32 fppt;
85 	u32 sppt;
86 	u32 fppt_apu_only;
87 	u32 spl;
88 	u32 stt_min_limit;
89 	u8 skin_temp_apu;
90 	u8 skin_temp_hs2;
91 } __packed;
92 
93 struct apmf_fan_idx {
94 	u16 size;
95 	u8 fan_ctl_mode;
96 	u32 fan_ctl_idx;
97 } __packed;
98 
99 struct smu_pmf_metrics {
100 	u16 gfxclk_freq; /* in MHz */
101 	u16 socclk_freq; /* in MHz */
102 	u16 vclk_freq; /* in MHz */
103 	u16 dclk_freq; /* in MHz */
104 	u16 memclk_freq; /* in MHz */
105 	u16 spare;
106 	u16 gfx_activity; /* in Centi */
107 	u16 uvd_activity; /* in Centi */
108 	u16 voltage[2]; /* in mV */
109 	u16 currents[2]; /* in mA */
110 	u16 power[2];/* in mW */
111 	u16 core_freq[8]; /* in MHz */
112 	u16 core_power[8]; /* in mW */
113 	u16 core_temp[8]; /* in centi-Celsius */
114 	u16 l3_freq; /* in MHz */
115 	u16 l3_temp; /* in centi-Celsius */
116 	u16 gfx_temp; /* in centi-Celsius */
117 	u16 soc_temp; /* in centi-Celsius */
118 	u16 throttler_status;
119 	u16 current_socketpower; /* in mW */
120 	u16 stapm_orig_limit; /* in W */
121 	u16 stapm_cur_limit; /* in W */
122 	u32 apu_power; /* in mW */
123 	u32 dgpu_power; /* in mW */
124 	u16 vdd_tdc_val; /* in mA */
125 	u16 soc_tdc_val; /* in mA */
126 	u16 vdd_edc_val; /* in mA */
127 	u16 soc_edcv_al; /* in mA */
128 	u16 infra_cpu_maxfreq; /* in MHz */
129 	u16 infra_gfx_maxfreq; /* in MHz */
130 	u16 skin_temp; /* in centi-Celsius */
131 	u16 device_state;
132 } __packed;
133 
134 enum amd_stt_skin_temp {
135 	STT_TEMP_APU,
136 	STT_TEMP_HS2,
137 	STT_TEMP_COUNT,
138 };
139 
140 enum amd_slider_op {
141 	SLIDER_OP_GET,
142 	SLIDER_OP_SET,
143 };
144 
145 enum power_source {
146 	POWER_SOURCE_AC,
147 	POWER_SOURCE_DC,
148 	POWER_SOURCE_MAX,
149 };
150 
151 enum power_modes {
152 	POWER_MODE_PERFORMANCE,
153 	POWER_MODE_BALANCED_POWER,
154 	POWER_MODE_POWER_SAVER,
155 	POWER_MODE_MAX,
156 };
157 
158 struct amd_pmf_dev {
159 	void __iomem *regbase;
160 	void __iomem *smu_virt_addr;
161 	void *buf;
162 	u32 base_addr;
163 	u32 cpu_id;
164 	struct device *dev;
165 	struct mutex lock; /* protects the PMF interface */
166 	u32 supported_func;
167 	enum platform_profile_option current_profile;
168 	struct platform_profile_handler pprof;
169 	struct dentry *dbgfs_dir;
170 	int hb_interval; /* SBIOS heartbeat interval */
171 	struct delayed_work heart_beat;
172 	struct smu_pmf_metrics m_table;
173 	struct delayed_work work_buffer;
174 	ktime_t start_time;
175 	int socket_power_history[AVG_SAMPLE_SIZE];
176 	int socket_power_history_idx;
177 	bool amt_enabled;
178 	struct mutex update_mutex; /* protects race between ACPI handler and metrics thread */
179 	bool cnqf_enabled;
180 	bool cnqf_supported;
181 	struct notifier_block pwr_src_notifier;
182 };
183 
184 struct apmf_sps_prop_granular {
185 	u32 fppt;
186 	u32 sppt;
187 	u32 sppt_apu_only;
188 	u32 spl;
189 	u32 stt_min;
190 	u8 stt_skin_temp[STT_TEMP_COUNT];
191 	u32 fan_id;
192 } __packed;
193 
194 /* Static Slider */
195 struct apmf_static_slider_granular_output {
196 	u16 size;
197 	struct apmf_sps_prop_granular prop[POWER_SOURCE_MAX * POWER_MODE_MAX];
198 } __packed;
199 
200 struct amd_pmf_static_slider_granular {
201 	u16 size;
202 	struct apmf_sps_prop_granular prop[POWER_SOURCE_MAX][POWER_MODE_MAX];
203 };
204 
205 struct os_power_slider {
206 	u16 size;
207 	u8 slider_event;
208 } __packed;
209 
210 struct fan_table_control {
211 	bool manual;
212 	unsigned long fan_id;
213 };
214 
215 struct power_table_control {
216 	u32 spl;
217 	u32 sppt;
218 	u32 fppt;
219 	u32 sppt_apu_only;
220 	u32 stt_min;
221 	u32 stt_skin_temp[STT_TEMP_COUNT];
222 	u32 reserved[16];
223 };
224 
225 /* Auto Mode Layer */
226 enum auto_mode_transition_priority {
227 	AUTO_TRANSITION_TO_PERFORMANCE, /* Any other mode to Performance Mode */
228 	AUTO_TRANSITION_FROM_QUIET_TO_BALANCE, /* Quiet Mode to Balance Mode */
229 	AUTO_TRANSITION_TO_QUIET, /* Any other mode to Quiet Mode */
230 	AUTO_TRANSITION_FROM_PERFORMANCE_TO_BALANCE, /* Performance Mode to Balance Mode */
231 	AUTO_TRANSITION_MAX,
232 };
233 
234 enum auto_mode_mode {
235 	AUTO_QUIET,
236 	AUTO_BALANCE,
237 	AUTO_PERFORMANCE_ON_LAP,
238 	AUTO_PERFORMANCE,
239 	AUTO_MODE_MAX,
240 };
241 
242 struct auto_mode_trans_params {
243 	u32 time_constant; /* minimum time required to switch to next mode */
244 	u32 power_delta; /* delta power to shift mode */
245 	u32 power_threshold;
246 	u32 timer; /* elapsed time. if timer > TimeThreshold, it will move to next mode */
247 	u32 applied;
248 	enum auto_mode_mode target_mode;
249 	u32 shifting_up;
250 };
251 
252 struct auto_mode_mode_settings {
253 	struct power_table_control power_control;
254 	struct fan_table_control fan_control;
255 	u32 power_floor;
256 };
257 
258 struct auto_mode_mode_config {
259 	struct auto_mode_trans_params transition[AUTO_TRANSITION_MAX];
260 	struct auto_mode_mode_settings mode_set[AUTO_MODE_MAX];
261 	enum auto_mode_mode current_mode;
262 };
263 
264 struct apmf_auto_mode {
265 	u16 size;
266 	/* time constant */
267 	u32 balanced_to_perf;
268 	u32 perf_to_balanced;
269 	u32 quiet_to_balanced;
270 	u32 balanced_to_quiet;
271 	/* power floor */
272 	u32 pfloor_perf;
273 	u32 pfloor_balanced;
274 	u32 pfloor_quiet;
275 	/* Power delta for mode change */
276 	u32 pd_balanced_to_perf;
277 	u32 pd_perf_to_balanced;
278 	u32 pd_quiet_to_balanced;
279 	u32 pd_balanced_to_quiet;
280 	/* skin temperature limits */
281 	u8 stt_apu_perf_on_lap; /* CQL ON */
282 	u8 stt_hs2_perf_on_lap; /* CQL ON */
283 	u8 stt_apu_perf;
284 	u8 stt_hs2_perf;
285 	u8 stt_apu_balanced;
286 	u8 stt_hs2_balanced;
287 	u8 stt_apu_quiet;
288 	u8 stt_hs2_quiet;
289 	u32 stt_min_limit_perf_on_lap; /* CQL ON */
290 	u32 stt_min_limit_perf;
291 	u32 stt_min_limit_balanced;
292 	u32 stt_min_limit_quiet;
293 	/* SPL based */
294 	u32 fppt_perf_on_lap; /* CQL ON */
295 	u32 sppt_perf_on_lap; /* CQL ON */
296 	u32 spl_perf_on_lap; /* CQL ON */
297 	u32 sppt_apu_only_perf_on_lap; /* CQL ON */
298 	u32 fppt_perf;
299 	u32 sppt_perf;
300 	u32 spl_perf;
301 	u32 sppt_apu_only_perf;
302 	u32 fppt_balanced;
303 	u32 sppt_balanced;
304 	u32 spl_balanced;
305 	u32 sppt_apu_only_balanced;
306 	u32 fppt_quiet;
307 	u32 sppt_quiet;
308 	u32 spl_quiet;
309 	u32 sppt_apu_only_quiet;
310 	/* Fan ID */
311 	u32 fan_id_perf;
312 	u32 fan_id_balanced;
313 	u32 fan_id_quiet;
314 } __packed;
315 
316 /* CnQF Layer */
317 enum cnqf_trans_priority {
318 	CNQF_TRANSITION_TO_TURBO, /* Any other mode to Turbo Mode */
319 	CNQF_TRANSITION_FROM_BALANCE_TO_PERFORMANCE, /* quiet/balance to Performance Mode */
320 	CNQF_TRANSITION_FROM_QUIET_TO_BALANCE, /* Quiet Mode to Balance Mode */
321 	CNQF_TRANSITION_TO_QUIET, /* Any other mode to Quiet Mode */
322 	CNQF_TRANSITION_FROM_PERFORMANCE_TO_BALANCE, /* Performance/Turbo to Balance Mode */
323 	CNQF_TRANSITION_FROM_TURBO_TO_PERFORMANCE, /* Turbo mode to Performance Mode */
324 	CNQF_TRANSITION_MAX,
325 };
326 
327 enum cnqf_mode {
328 	CNQF_MODE_QUIET,
329 	CNQF_MODE_BALANCE,
330 	CNQF_MODE_PERFORMANCE,
331 	CNQF_MODE_TURBO,
332 	CNQF_MODE_MAX,
333 };
334 
335 enum apmf_cnqf_pos {
336 	APMF_CNQF_TURBO,
337 	APMF_CNQF_PERFORMANCE,
338 	APMF_CNQF_BALANCE,
339 	APMF_CNQF_QUIET,
340 	APMF_CNQF_MAX,
341 };
342 
343 struct cnqf_mode_settings {
344 	struct power_table_control power_control;
345 	struct fan_table_control fan_control;
346 	u32 power_floor;
347 };
348 
349 struct cnqf_tran_params {
350 	u32 time_constant; /* minimum time required to switch to next mode */
351 	u32 power_threshold;
352 	u32 timer; /* elapsed time. if timer > timethreshold, it will move to next mode */
353 	u32 total_power;
354 	u32 count;
355 	bool priority;
356 	bool shifting_up;
357 	enum cnqf_mode target_mode;
358 };
359 
360 struct cnqf_config {
361 	struct cnqf_tran_params trans_param[POWER_SOURCE_MAX][CNQF_TRANSITION_MAX];
362 	struct cnqf_mode_settings mode_set[POWER_SOURCE_MAX][CNQF_MODE_MAX];
363 	struct power_table_control defaults;
364 	enum cnqf_mode current_mode;
365 	u32 power_src;
366 	u32 avg_power;
367 };
368 
369 struct apmf_cnqf_power_set {
370 	u32 pfloor;
371 	u32 fppt;
372 	u32 sppt;
373 	u32 sppt_apu_only;
374 	u32 spl;
375 	u32 stt_min_limit;
376 	u8 stt_skintemp[STT_TEMP_COUNT];
377 	u32 fan_id;
378 } __packed;
379 
380 struct apmf_dyn_slider_output {
381 	u16 size;
382 	u16 flags;
383 	u32 t_perf_to_turbo;
384 	u32 t_balanced_to_perf;
385 	u32 t_quiet_to_balanced;
386 	u32 t_balanced_to_quiet;
387 	u32 t_perf_to_balanced;
388 	u32 t_turbo_to_perf;
389 	struct apmf_cnqf_power_set ps[APMF_CNQF_MAX];
390 } __packed;
391 
392 /* Core Layer */
393 int apmf_acpi_init(struct amd_pmf_dev *pmf_dev);
394 void apmf_acpi_deinit(struct amd_pmf_dev *pmf_dev);
395 int is_apmf_func_supported(struct amd_pmf_dev *pdev, unsigned long index);
396 int amd_pmf_send_cmd(struct amd_pmf_dev *dev, u8 message, bool get, u32 arg, u32 *data);
397 int amd_pmf_init_metrics_table(struct amd_pmf_dev *dev);
398 int amd_pmf_get_power_source(void);
399 int apmf_install_handler(struct amd_pmf_dev *pmf_dev);
400 int apmf_os_power_slider_update(struct amd_pmf_dev *dev, u8 flag);
401 
402 /* SPS Layer */
403 int amd_pmf_get_pprof_modes(struct amd_pmf_dev *pmf);
404 void amd_pmf_update_slider(struct amd_pmf_dev *dev, bool op, int idx,
405 			   struct amd_pmf_static_slider_granular *table);
406 int amd_pmf_init_sps(struct amd_pmf_dev *dev);
407 void amd_pmf_deinit_sps(struct amd_pmf_dev *dev);
408 int apmf_get_static_slider_granular(struct amd_pmf_dev *pdev,
409 				    struct apmf_static_slider_granular_output *output);
410 bool is_pprof_balanced(struct amd_pmf_dev *pmf);
411 int amd_pmf_power_slider_update_event(struct amd_pmf_dev *dev);
412 
413 
414 int apmf_update_fan_idx(struct amd_pmf_dev *pdev, bool manual, u32 idx);
415 int amd_pmf_set_sps_power_limits(struct amd_pmf_dev *pmf);
416 
417 /* Auto Mode Layer */
418 int apmf_get_auto_mode_def(struct amd_pmf_dev *pdev, struct apmf_auto_mode *data);
419 void amd_pmf_init_auto_mode(struct amd_pmf_dev *dev);
420 void amd_pmf_deinit_auto_mode(struct amd_pmf_dev *dev);
421 void amd_pmf_trans_automode(struct amd_pmf_dev *dev, int socket_power, ktime_t time_elapsed_ms);
422 int apmf_get_sbios_requests(struct amd_pmf_dev *pdev, struct apmf_sbios_req *req);
423 
424 void amd_pmf_update_2_cql(struct amd_pmf_dev *dev, bool is_cql_event);
425 int amd_pmf_reset_amt(struct amd_pmf_dev *dev);
426 void amd_pmf_handle_amt(struct amd_pmf_dev *dev);
427 
428 /* CnQF Layer */
429 int apmf_get_dyn_slider_def_ac(struct amd_pmf_dev *pdev, struct apmf_dyn_slider_output *data);
430 int apmf_get_dyn_slider_def_dc(struct amd_pmf_dev *pdev, struct apmf_dyn_slider_output *data);
431 int amd_pmf_init_cnqf(struct amd_pmf_dev *dev);
432 void amd_pmf_deinit_cnqf(struct amd_pmf_dev *dev);
433 int amd_pmf_trans_cnqf(struct amd_pmf_dev *dev, int socket_power, ktime_t time_lapsed_ms);
434 extern const struct attribute_group cnqf_feature_attribute_group;
435 
436 #endif /* PMF_H */
437