1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 
3 #include <linux/module.h>
4 #include <linux/of.h>
5 #include <linux/platform_device.h>
6 
7 #include "pinctrl-msm.h"
8 
9 static const char * const sm6125_tiles[] = {
10 	"south",
11 	"east",
12 	"west"
13 };
14 
15 enum {
16 	SOUTH,
17 	EAST,
18 	WEST
19 };
20 
21 #define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9)	\
22 	{						\
23 		.grp = PINCTRL_PINGROUP("gpio" #id, 	\
24 			gpio##id##_pins, 		\
25 			ARRAY_SIZE(gpio##id##_pins)),	\
26 		.funcs = (int[]){			\
27 			msm_mux_gpio, /* gpio mode */	\
28 			msm_mux_##f1,			\
29 			msm_mux_##f2,			\
30 			msm_mux_##f3,			\
31 			msm_mux_##f4,			\
32 			msm_mux_##f5,			\
33 			msm_mux_##f6,			\
34 			msm_mux_##f7,			\
35 			msm_mux_##f8,			\
36 			msm_mux_##f9			\
37 		},					\
38 		.nfuncs = 10,				\
39 		.ctl_reg = 0x1000 * id,		\
40 		.io_reg = 0x4 + 0x1000 * id,		\
41 		.intr_cfg_reg = 0x8 + 0x1000 * id,	\
42 		.intr_status_reg = 0xc + 0x1000 * id,	\
43 		.intr_target_reg = 0x8 + 0x1000 * id,	\
44 		.tile = _tile,			\
45 		.mux_bit = 2,			\
46 		.pull_bit = 0,			\
47 		.drv_bit = 6,			\
48 		.oe_bit = 9,			\
49 		.in_bit = 0,			\
50 		.out_bit = 1,			\
51 		.intr_enable_bit = 0,		\
52 		.intr_status_bit = 0,		\
53 		.intr_target_bit = 5,		\
54 		.intr_target_kpss_val = 3,	\
55 		.intr_raw_status_bit = 4,	\
56 		.intr_polarity_bit = 1,		\
57 		.intr_detection_bit = 2,	\
58 		.intr_detection_width = 2,	\
59 	}
60 
61 #define SDC_QDSD_PINGROUP(pg_name, _tile, ctl, pull, drv)	\
62 	{						\
63 		.grp = PINCTRL_PINGROUP(#pg_name, 	\
64 			pg_name##_pins, 		\
65 			ARRAY_SIZE(pg_name##_pins)),	\
66 		.ctl_reg = ctl,				\
67 		.io_reg = 0,				\
68 		.intr_cfg_reg = 0,			\
69 		.intr_status_reg = 0,			\
70 		.intr_target_reg = 0,			\
71 		.tile = _tile,				\
72 		.mux_bit = -1,				\
73 		.pull_bit = pull,			\
74 		.drv_bit = drv,				\
75 		.oe_bit = -1,				\
76 		.in_bit = -1,				\
77 		.out_bit = -1,				\
78 		.intr_enable_bit = -1,			\
79 		.intr_status_bit = -1,			\
80 		.intr_target_bit = -1,			\
81 		.intr_raw_status_bit = -1,		\
82 		.intr_polarity_bit = -1,		\
83 		.intr_detection_bit = -1,		\
84 		.intr_detection_width = -1,		\
85 	}
86 
87 #define UFS_RESET(pg_name, offset)				\
88 	{						\
89 		.grp = PINCTRL_PINGROUP(#pg_name, 	\
90 			pg_name##_pins, 		\
91 			ARRAY_SIZE(pg_name##_pins)),	\
92 		.ctl_reg = offset,			\
93 		.io_reg = offset + 0x4,			\
94 		.intr_cfg_reg = 0,			\
95 		.intr_status_reg = 0,			\
96 		.intr_target_reg = 0,			\
97 		.tile = WEST,				\
98 		.mux_bit = -1,				\
99 		.pull_bit = 3,				\
100 		.drv_bit = 0,				\
101 		.oe_bit = -1,				\
102 		.in_bit = -1,				\
103 		.out_bit = 0,				\
104 		.intr_enable_bit = -1,			\
105 		.intr_status_bit = -1,			\
106 		.intr_target_bit = -1,			\
107 		.intr_raw_status_bit = -1,		\
108 		.intr_polarity_bit = -1,		\
109 		.intr_detection_bit = -1,		\
110 		.intr_detection_width = -1,		\
111 	}
112 static const struct pinctrl_pin_desc sm6125_pins[] = {
113 	PINCTRL_PIN(0, "GPIO_0"),
114 	PINCTRL_PIN(1, "GPIO_1"),
115 	PINCTRL_PIN(2, "GPIO_2"),
116 	PINCTRL_PIN(3, "GPIO_3"),
117 	PINCTRL_PIN(4, "GPIO_4"),
118 	PINCTRL_PIN(5, "GPIO_5"),
119 	PINCTRL_PIN(6, "GPIO_6"),
120 	PINCTRL_PIN(7, "GPIO_7"),
121 	PINCTRL_PIN(8, "GPIO_8"),
122 	PINCTRL_PIN(9, "GPIO_9"),
123 	PINCTRL_PIN(10, "GPIO_10"),
124 	PINCTRL_PIN(11, "GPIO_11"),
125 	PINCTRL_PIN(12, "GPIO_12"),
126 	PINCTRL_PIN(13, "GPIO_13"),
127 	PINCTRL_PIN(14, "GPIO_14"),
128 	PINCTRL_PIN(15, "GPIO_15"),
129 	PINCTRL_PIN(16, "GPIO_16"),
130 	PINCTRL_PIN(17, "GPIO_17"),
131 	PINCTRL_PIN(18, "GPIO_18"),
132 	PINCTRL_PIN(19, "GPIO_19"),
133 	PINCTRL_PIN(20, "GPIO_20"),
134 	PINCTRL_PIN(21, "GPIO_21"),
135 	PINCTRL_PIN(22, "GPIO_22"),
136 	PINCTRL_PIN(23, "GPIO_23"),
137 	PINCTRL_PIN(24, "GPIO_24"),
138 	PINCTRL_PIN(25, "GPIO_25"),
139 	PINCTRL_PIN(26, "GPIO_26"),
140 	PINCTRL_PIN(27, "GPIO_27"),
141 	PINCTRL_PIN(28, "GPIO_28"),
142 	PINCTRL_PIN(29, "GPIO_29"),
143 	PINCTRL_PIN(30, "GPIO_30"),
144 	PINCTRL_PIN(31, "GPIO_31"),
145 	PINCTRL_PIN(32, "GPIO_32"),
146 	PINCTRL_PIN(33, "GPIO_33"),
147 	PINCTRL_PIN(34, "GPIO_34"),
148 	PINCTRL_PIN(35, "GPIO_35"),
149 	PINCTRL_PIN(36, "GPIO_36"),
150 	PINCTRL_PIN(37, "GPIO_37"),
151 	PINCTRL_PIN(38, "GPIO_38"),
152 	PINCTRL_PIN(39, "GPIO_39"),
153 	PINCTRL_PIN(40, "GPIO_40"),
154 	PINCTRL_PIN(41, "GPIO_41"),
155 	PINCTRL_PIN(42, "GPIO_42"),
156 	PINCTRL_PIN(43, "GPIO_43"),
157 	PINCTRL_PIN(44, "GPIO_44"),
158 	PINCTRL_PIN(45, "GPIO_45"),
159 	PINCTRL_PIN(46, "GPIO_46"),
160 	PINCTRL_PIN(47, "GPIO_47"),
161 	PINCTRL_PIN(48, "GPIO_48"),
162 	PINCTRL_PIN(49, "GPIO_49"),
163 	PINCTRL_PIN(50, "GPIO_50"),
164 	PINCTRL_PIN(51, "GPIO_51"),
165 	PINCTRL_PIN(52, "GPIO_52"),
166 	PINCTRL_PIN(53, "GPIO_53"),
167 	PINCTRL_PIN(54, "GPIO_54"),
168 	PINCTRL_PIN(55, "GPIO_55"),
169 	PINCTRL_PIN(56, "GPIO_56"),
170 	PINCTRL_PIN(57, "GPIO_57"),
171 	PINCTRL_PIN(58, "GPIO_58"),
172 	PINCTRL_PIN(59, "GPIO_59"),
173 	PINCTRL_PIN(60, "GPIO_60"),
174 	PINCTRL_PIN(61, "GPIO_61"),
175 	PINCTRL_PIN(62, "GPIO_62"),
176 	PINCTRL_PIN(63, "GPIO_63"),
177 	PINCTRL_PIN(64, "GPIO_64"),
178 	PINCTRL_PIN(65, "GPIO_65"),
179 	PINCTRL_PIN(66, "GPIO_66"),
180 	PINCTRL_PIN(67, "GPIO_67"),
181 	PINCTRL_PIN(68, "GPIO_68"),
182 	PINCTRL_PIN(69, "GPIO_69"),
183 	PINCTRL_PIN(70, "GPIO_70"),
184 	PINCTRL_PIN(71, "GPIO_71"),
185 	PINCTRL_PIN(72, "GPIO_72"),
186 	PINCTRL_PIN(73, "GPIO_73"),
187 	PINCTRL_PIN(74, "GPIO_74"),
188 	PINCTRL_PIN(75, "GPIO_75"),
189 	PINCTRL_PIN(76, "GPIO_76"),
190 	PINCTRL_PIN(77, "GPIO_77"),
191 	PINCTRL_PIN(78, "GPIO_78"),
192 	PINCTRL_PIN(79, "GPIO_79"),
193 	PINCTRL_PIN(80, "GPIO_80"),
194 	PINCTRL_PIN(81, "GPIO_81"),
195 	PINCTRL_PIN(82, "GPIO_82"),
196 	PINCTRL_PIN(83, "GPIO_83"),
197 	PINCTRL_PIN(84, "GPIO_84"),
198 	PINCTRL_PIN(85, "GPIO_85"),
199 	PINCTRL_PIN(86, "GPIO_86"),
200 	PINCTRL_PIN(87, "GPIO_87"),
201 	PINCTRL_PIN(88, "GPIO_88"),
202 	PINCTRL_PIN(89, "GPIO_89"),
203 	PINCTRL_PIN(90, "GPIO_90"),
204 	PINCTRL_PIN(91, "GPIO_91"),
205 	PINCTRL_PIN(92, "GPIO_92"),
206 	PINCTRL_PIN(93, "GPIO_93"),
207 	PINCTRL_PIN(94, "GPIO_94"),
208 	PINCTRL_PIN(95, "GPIO_95"),
209 	PINCTRL_PIN(96, "GPIO_96"),
210 	PINCTRL_PIN(97, "GPIO_97"),
211 	PINCTRL_PIN(98, "GPIO_98"),
212 	PINCTRL_PIN(99, "GPIO_99"),
213 	PINCTRL_PIN(100, "GPIO_100"),
214 	PINCTRL_PIN(101, "GPIO_101"),
215 	PINCTRL_PIN(102, "GPIO_102"),
216 	PINCTRL_PIN(103, "GPIO_103"),
217 	PINCTRL_PIN(104, "GPIO_104"),
218 	PINCTRL_PIN(105, "GPIO_105"),
219 	PINCTRL_PIN(106, "GPIO_106"),
220 	PINCTRL_PIN(107, "GPIO_107"),
221 	PINCTRL_PIN(108, "GPIO_108"),
222 	PINCTRL_PIN(109, "GPIO_109"),
223 	PINCTRL_PIN(110, "GPIO_110"),
224 	PINCTRL_PIN(111, "GPIO_111"),
225 	PINCTRL_PIN(112, "GPIO_112"),
226 	PINCTRL_PIN(113, "GPIO_113"),
227 	PINCTRL_PIN(114, "GPIO_114"),
228 	PINCTRL_PIN(115, "GPIO_115"),
229 	PINCTRL_PIN(116, "GPIO_116"),
230 	PINCTRL_PIN(117, "GPIO_117"),
231 	PINCTRL_PIN(118, "GPIO_118"),
232 	PINCTRL_PIN(119, "GPIO_119"),
233 	PINCTRL_PIN(120, "GPIO_120"),
234 	PINCTRL_PIN(121, "GPIO_121"),
235 	PINCTRL_PIN(122, "GPIO_122"),
236 	PINCTRL_PIN(123, "GPIO_123"),
237 	PINCTRL_PIN(124, "GPIO_124"),
238 	PINCTRL_PIN(125, "GPIO_125"),
239 	PINCTRL_PIN(126, "GPIO_126"),
240 	PINCTRL_PIN(127, "GPIO_127"),
241 	PINCTRL_PIN(128, "GPIO_128"),
242 	PINCTRL_PIN(129, "GPIO_129"),
243 	PINCTRL_PIN(130, "GPIO_130"),
244 	PINCTRL_PIN(131, "GPIO_131"),
245 	PINCTRL_PIN(132, "GPIO_132"),
246 	PINCTRL_PIN(133, "UFS_RESET"),
247 	PINCTRL_PIN(134, "SDC1_RCLK"),
248 	PINCTRL_PIN(135, "SDC1_CLK"),
249 	PINCTRL_PIN(136, "SDC1_CMD"),
250 	PINCTRL_PIN(137, "SDC1_DATA"),
251 	PINCTRL_PIN(138, "SDC2_CLK"),
252 	PINCTRL_PIN(139, "SDC2_CMD"),
253 	PINCTRL_PIN(140, "SDC2_DATA"),
254 };
255 
256 #define DECLARE_MSM_GPIO_PINS(pin) \
257 	static const unsigned int gpio##pin##_pins[] = { pin }
258 DECLARE_MSM_GPIO_PINS(0);
259 DECLARE_MSM_GPIO_PINS(1);
260 DECLARE_MSM_GPIO_PINS(2);
261 DECLARE_MSM_GPIO_PINS(3);
262 DECLARE_MSM_GPIO_PINS(4);
263 DECLARE_MSM_GPIO_PINS(5);
264 DECLARE_MSM_GPIO_PINS(6);
265 DECLARE_MSM_GPIO_PINS(7);
266 DECLARE_MSM_GPIO_PINS(8);
267 DECLARE_MSM_GPIO_PINS(9);
268 DECLARE_MSM_GPIO_PINS(10);
269 DECLARE_MSM_GPIO_PINS(11);
270 DECLARE_MSM_GPIO_PINS(12);
271 DECLARE_MSM_GPIO_PINS(13);
272 DECLARE_MSM_GPIO_PINS(14);
273 DECLARE_MSM_GPIO_PINS(15);
274 DECLARE_MSM_GPIO_PINS(16);
275 DECLARE_MSM_GPIO_PINS(17);
276 DECLARE_MSM_GPIO_PINS(18);
277 DECLARE_MSM_GPIO_PINS(19);
278 DECLARE_MSM_GPIO_PINS(20);
279 DECLARE_MSM_GPIO_PINS(21);
280 DECLARE_MSM_GPIO_PINS(22);
281 DECLARE_MSM_GPIO_PINS(23);
282 DECLARE_MSM_GPIO_PINS(24);
283 DECLARE_MSM_GPIO_PINS(25);
284 DECLARE_MSM_GPIO_PINS(26);
285 DECLARE_MSM_GPIO_PINS(27);
286 DECLARE_MSM_GPIO_PINS(28);
287 DECLARE_MSM_GPIO_PINS(29);
288 DECLARE_MSM_GPIO_PINS(30);
289 DECLARE_MSM_GPIO_PINS(31);
290 DECLARE_MSM_GPIO_PINS(32);
291 DECLARE_MSM_GPIO_PINS(33);
292 DECLARE_MSM_GPIO_PINS(34);
293 DECLARE_MSM_GPIO_PINS(35);
294 DECLARE_MSM_GPIO_PINS(36);
295 DECLARE_MSM_GPIO_PINS(37);
296 DECLARE_MSM_GPIO_PINS(38);
297 DECLARE_MSM_GPIO_PINS(39);
298 DECLARE_MSM_GPIO_PINS(40);
299 DECLARE_MSM_GPIO_PINS(41);
300 DECLARE_MSM_GPIO_PINS(42);
301 DECLARE_MSM_GPIO_PINS(43);
302 DECLARE_MSM_GPIO_PINS(44);
303 DECLARE_MSM_GPIO_PINS(45);
304 DECLARE_MSM_GPIO_PINS(46);
305 DECLARE_MSM_GPIO_PINS(47);
306 DECLARE_MSM_GPIO_PINS(48);
307 DECLARE_MSM_GPIO_PINS(49);
308 DECLARE_MSM_GPIO_PINS(50);
309 DECLARE_MSM_GPIO_PINS(51);
310 DECLARE_MSM_GPIO_PINS(52);
311 DECLARE_MSM_GPIO_PINS(53);
312 DECLARE_MSM_GPIO_PINS(54);
313 DECLARE_MSM_GPIO_PINS(55);
314 DECLARE_MSM_GPIO_PINS(56);
315 DECLARE_MSM_GPIO_PINS(57);
316 DECLARE_MSM_GPIO_PINS(58);
317 DECLARE_MSM_GPIO_PINS(59);
318 DECLARE_MSM_GPIO_PINS(60);
319 DECLARE_MSM_GPIO_PINS(61);
320 DECLARE_MSM_GPIO_PINS(62);
321 DECLARE_MSM_GPIO_PINS(63);
322 DECLARE_MSM_GPIO_PINS(64);
323 DECLARE_MSM_GPIO_PINS(65);
324 DECLARE_MSM_GPIO_PINS(66);
325 DECLARE_MSM_GPIO_PINS(67);
326 DECLARE_MSM_GPIO_PINS(68);
327 DECLARE_MSM_GPIO_PINS(69);
328 DECLARE_MSM_GPIO_PINS(70);
329 DECLARE_MSM_GPIO_PINS(71);
330 DECLARE_MSM_GPIO_PINS(72);
331 DECLARE_MSM_GPIO_PINS(73);
332 DECLARE_MSM_GPIO_PINS(74);
333 DECLARE_MSM_GPIO_PINS(75);
334 DECLARE_MSM_GPIO_PINS(76);
335 DECLARE_MSM_GPIO_PINS(77);
336 DECLARE_MSM_GPIO_PINS(78);
337 DECLARE_MSM_GPIO_PINS(79);
338 DECLARE_MSM_GPIO_PINS(80);
339 DECLARE_MSM_GPIO_PINS(81);
340 DECLARE_MSM_GPIO_PINS(82);
341 DECLARE_MSM_GPIO_PINS(83);
342 DECLARE_MSM_GPIO_PINS(84);
343 DECLARE_MSM_GPIO_PINS(85);
344 DECLARE_MSM_GPIO_PINS(86);
345 DECLARE_MSM_GPIO_PINS(87);
346 DECLARE_MSM_GPIO_PINS(88);
347 DECLARE_MSM_GPIO_PINS(89);
348 DECLARE_MSM_GPIO_PINS(90);
349 DECLARE_MSM_GPIO_PINS(91);
350 DECLARE_MSM_GPIO_PINS(92);
351 DECLARE_MSM_GPIO_PINS(93);
352 DECLARE_MSM_GPIO_PINS(94);
353 DECLARE_MSM_GPIO_PINS(95);
354 DECLARE_MSM_GPIO_PINS(96);
355 DECLARE_MSM_GPIO_PINS(97);
356 DECLARE_MSM_GPIO_PINS(98);
357 DECLARE_MSM_GPIO_PINS(99);
358 DECLARE_MSM_GPIO_PINS(100);
359 DECLARE_MSM_GPIO_PINS(101);
360 DECLARE_MSM_GPIO_PINS(102);
361 DECLARE_MSM_GPIO_PINS(103);
362 DECLARE_MSM_GPIO_PINS(104);
363 DECLARE_MSM_GPIO_PINS(105);
364 DECLARE_MSM_GPIO_PINS(106);
365 DECLARE_MSM_GPIO_PINS(107);
366 DECLARE_MSM_GPIO_PINS(108);
367 DECLARE_MSM_GPIO_PINS(109);
368 DECLARE_MSM_GPIO_PINS(110);
369 DECLARE_MSM_GPIO_PINS(111);
370 DECLARE_MSM_GPIO_PINS(112);
371 DECLARE_MSM_GPIO_PINS(113);
372 DECLARE_MSM_GPIO_PINS(114);
373 DECLARE_MSM_GPIO_PINS(115);
374 DECLARE_MSM_GPIO_PINS(116);
375 DECLARE_MSM_GPIO_PINS(117);
376 DECLARE_MSM_GPIO_PINS(118);
377 DECLARE_MSM_GPIO_PINS(119);
378 DECLARE_MSM_GPIO_PINS(120);
379 DECLARE_MSM_GPIO_PINS(121);
380 DECLARE_MSM_GPIO_PINS(122);
381 DECLARE_MSM_GPIO_PINS(123);
382 DECLARE_MSM_GPIO_PINS(124);
383 DECLARE_MSM_GPIO_PINS(125);
384 DECLARE_MSM_GPIO_PINS(126);
385 DECLARE_MSM_GPIO_PINS(127);
386 DECLARE_MSM_GPIO_PINS(128);
387 DECLARE_MSM_GPIO_PINS(129);
388 DECLARE_MSM_GPIO_PINS(130);
389 DECLARE_MSM_GPIO_PINS(131);
390 DECLARE_MSM_GPIO_PINS(132);
391 
392 static const unsigned int ufs_reset_pins[] = { 133 };
393 static const unsigned int sdc1_rclk_pins[] = { 134 };
394 static const unsigned int sdc1_clk_pins[] = { 135 };
395 static const unsigned int sdc1_cmd_pins[] = { 136 };
396 static const unsigned int sdc1_data_pins[] = { 137 };
397 static const unsigned int sdc2_clk_pins[] = { 138 };
398 static const unsigned int sdc2_cmd_pins[] = { 139 };
399 static const unsigned int sdc2_data_pins[] = { 140 };
400 
401 
402 enum sm6125_functions {
403 	msm_mux_qup00,
404 	msm_mux_gpio,
405 	msm_mux_qdss,
406 	msm_mux_qup01,
407 	msm_mux_qup02,
408 	msm_mux_ddr_pxi0,
409 	msm_mux_ddr_bist,
410 	msm_mux_atest_tsens2,
411 	msm_mux_vsense_trigger,
412 	msm_mux_atest_usb1,
413 	msm_mux_gp_pdm1,
414 	msm_mux_phase_flag,
415 	msm_mux_dbg_out,
416 	msm_mux_qup14,
417 	msm_mux_atest_usb11,
418 	msm_mux_ddr_pxi2,
419 	msm_mux_atest_usb10,
420 	msm_mux_jitter_bist,
421 	msm_mux_ddr_pxi3,
422 	msm_mux_pll_bypassnl,
423 	msm_mux_pll_bist,
424 	msm_mux_qup03,
425 	msm_mux_pll_reset,
426 	msm_mux_agera_pll,
427 	msm_mux_qdss_cti,
428 	msm_mux_qup04,
429 	msm_mux_wlan2_adc1,
430 	msm_mux_wlan2_adc0,
431 	msm_mux_wsa_clk,
432 	msm_mux_qup13,
433 	msm_mux_ter_mi2s,
434 	msm_mux_wsa_data,
435 	msm_mux_qup10,
436 	msm_mux_gcc_gp3,
437 	msm_mux_qup12,
438 	msm_mux_sd_write,
439 	msm_mux_qup11,
440 	msm_mux_cam_mclk,
441 	msm_mux_atest_tsens,
442 	msm_mux_cci_i2c,
443 	msm_mux_cci_timer2,
444 	msm_mux_cci_timer1,
445 	msm_mux_gcc_gp2,
446 	msm_mux_cci_async,
447 	msm_mux_cci_timer4,
448 	msm_mux_cci_timer0,
449 	msm_mux_gcc_gp1,
450 	msm_mux_cci_timer3,
451 	msm_mux_wlan1_adc1,
452 	msm_mux_wlan1_adc0,
453 	msm_mux_qlink_request,
454 	msm_mux_qlink_enable,
455 	msm_mux_pa_indicator,
456 	msm_mux_nav_pps,
457 	msm_mux_gps_tx,
458 	msm_mux_gp_pdm0,
459 	msm_mux_atest_usb13,
460 	msm_mux_ddr_pxi1,
461 	msm_mux_atest_usb12,
462 	msm_mux_cri_trng0,
463 	msm_mux_cri_trng,
464 	msm_mux_cri_trng1,
465 	msm_mux_gp_pdm2,
466 	msm_mux_sp_cmu,
467 	msm_mux_atest_usb2,
468 	msm_mux_atest_usb23,
469 	msm_mux_uim2_data,
470 	msm_mux_uim2_clk,
471 	msm_mux_uim2_reset,
472 	msm_mux_atest_usb22,
473 	msm_mux_uim2_present,
474 	msm_mux_atest_usb21,
475 	msm_mux_uim1_data,
476 	msm_mux_atest_usb20,
477 	msm_mux_uim1_clk,
478 	msm_mux_uim1_reset,
479 	msm_mux_uim1_present,
480 	msm_mux_mdp_vsync,
481 	msm_mux_copy_gp,
482 	msm_mux_tsense_pwm,
483 	msm_mux_mpm_pwr,
484 	msm_mux_tgu_ch3,
485 	msm_mux_mdp_vsync0,
486 	msm_mux_mdp_vsync1,
487 	msm_mux_mdp_vsync2,
488 	msm_mux_mdp_vsync3,
489 	msm_mux_mdp_vsync4,
490 	msm_mux_mdp_vsync5,
491 	msm_mux_tgu_ch0,
492 	msm_mux_tgu_ch1,
493 	msm_mux_atest_char1,
494 	msm_mux_vfr_1,
495 	msm_mux_tgu_ch2,
496 	msm_mux_atest_char0,
497 	msm_mux_atest_char2,
498 	msm_mux_atest_char3,
499 	msm_mux_ldo_en,
500 	msm_mux_ldo_update,
501 	msm_mux_prng_rosc,
502 	msm_mux_dp_hot,
503 	msm_mux_debug_hot,
504 	msm_mux_copy_phase,
505 	msm_mux_usb_phy,
506 	msm_mux_atest_char,
507 	msm_mux_unused1,
508 	msm_mux_qua_mi2s,
509 	msm_mux_mss_lte,
510 	msm_mux_swr_tx,
511 	msm_mux_aud_sb,
512 	msm_mux_unused2,
513 	msm_mux_swr_rx,
514 	msm_mux_edp_hot,
515 	msm_mux_audio_ref,
516 	msm_mux_pri_mi2s,
517 	msm_mux_pri_mi2s_ws,
518 	msm_mux_adsp_ext,
519 	msm_mux_edp_lcd,
520 	msm_mux_mclk2,
521 	msm_mux_m_voc,
522 	msm_mux_mclk1,
523 	msm_mux_qca_sb,
524 	msm_mux_qui_mi2s,
525 	msm_mux_dmic0_clk,
526 	msm_mux_sec_mi2s,
527 	msm_mux_dmic0_data,
528 	msm_mux_dmic1_clk,
529 	msm_mux_dmic1_data,
530 	msm_mux__,
531 };
532 
533 static const char * const qup00_groups[] = {
534 	"gpio0", "gpio1", "gpio2", "gpio3",
535 };
536 static const char * const gpio_groups[] = {
537 	"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
538 	"gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
539 	"gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
540 	"gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
541 	"gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
542 	"gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
543 	"gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
544 	"gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
545 	"gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
546 	"gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
547 	"gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
548 	"gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
549 	"gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
550 	"gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
551 	"gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104",
552 	"gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
553 	"gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116",
554 	"gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
555 	"gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128",
556 	"gpio129", "gpio130", "gpio131", "gpio132",
557 };
558 static const char * const qdss_groups[] = {
559 	"gpio0", "gpio1", "gpio2", "gpio3", "gpio20", "gpio21", "gpio34", "gpio35",
560 	"gpio36", "gpio42", "gpio41", "gpio43", "gpio44", "gpio45", "gpio46",
561 	"gpio47", "gpio48", "gpio49", "gpio80", "gpio81", "gpio82", "gpio83",
562 	"gpio84", "gpio85", "gpio86", "gpio91", "gpio92", "gpio94", "gpio96",
563 	"gpio100", "gpio102", "gpio114", "gpio115", "gpio116", "gpio117", "gpio118",
564 };
565 static const char * const qup01_groups[] = {
566 	"gpio4", "gpio5",
567 };
568 static const char * const qup02_groups[] = {
569 	"gpio6", "gpio7", "gpio8", "gpio9",
570 };
571 static const char * const ddr_pxi0_groups[] = {
572 	"gpio6", "gpio7",
573 };
574 static const char * const ddr_bist_groups[] = {
575 	"gpio7", "gpio8", "gpio9", "gpio10",
576 };
577 static const char * const atest_tsens2_groups[] = {
578 	"gpio7",
579 };
580 static const char * const vsense_trigger_groups[] = {
581 	"gpio7",
582 };
583 static const char * const atest_usb1_groups[] = {
584 	"gpio7",
585 };
586 static const char * const gp_pdm1_groups[] = {
587 	"gpio8", "gpio65",
588 };
589 static const char * const phase_flag_groups[] = {
590 	"gpio8", "gpio9", "gpio23", "gpio24", "gpio25", "gpio26", "gpio28",
591 	"gpio29", "gpio30", "gpio53", "gpio54", "gpio55", "gpio56", "gpio57",
592 	"gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio80", "gpio81",
593 	"gpio82", "gpio83", "gpio84", "gpio88", "gpio89", "gpio91", "gpio93",
594 	"gpio98", "gpio129", "gpio130", "gpio131",
595 };
596 static const char * const dbg_out_groups[] = {
597 	"gpio9",
598 };
599 static const char * const qup14_groups[] = {
600 	"gpio10", "gpio11", "gpio12", "gpio13",
601 };
602 static const char * const atest_usb11_groups[] = {
603 	"gpio10",
604 };
605 static const char * const ddr_pxi2_groups[] = {
606 	"gpio10", "gpio11",
607 };
608 static const char * const atest_usb10_groups[] = {
609 	"gpio11",
610 };
611 static const char * const jitter_bist_groups[] = {
612 	"gpio12", "gpio31",
613 };
614 static const char * const ddr_pxi3_groups[] = {
615 	"gpio12", "gpio13",
616 };
617 static const char * const pll_bypassnl_groups[] = {
618 	"gpio13",
619 };
620 static const char * const pll_bist_groups[] = {
621 	"gpio13", "gpio32",
622 };
623 static const char * const qup03_groups[] = {
624 	"gpio14", "gpio15",
625 };
626 static const char * const pll_reset_groups[] = {
627 	"gpio14",
628 };
629 static const char * const agera_pll_groups[] = {
630 	"gpio14", "gpio33",
631 };
632 static const char * const qdss_cti_groups[] = {
633 	"gpio14", "gpio15", "gpio95", "gpio101", "gpio106", "gpio107",
634 	"gpio110", "gpio111",
635 };
636 static const char * const qup04_groups[] = {
637 	"gpio16", "gpio17",
638 };
639 static const char * const wlan2_adc1_groups[] = {
640 	"gpio16",
641 };
642 static const char * const wlan2_adc0_groups[] = {
643 	"gpio17",
644 };
645 static const char * const wsa_clk_groups[] = {
646 	"gpio18",
647 };
648 static const char * const qup13_groups[] = {
649 	"gpio18", "gpio19", "gpio20", "gpio21",
650 };
651 static const char * const ter_mi2s_groups[] = {
652 	"gpio18", "gpio19", "gpio20", "gpio21",
653 };
654 static const char * const wsa_data_groups[] = {
655 	"gpio19",
656 };
657 static const char * const qup10_groups[] = {
658 	"gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27",
659 };
660 static const char * const gcc_gp3_groups[] = {
661 	"gpio22", "gpio58",
662 };
663 static const char * const qup12_groups[] = {
664 	"gpio28", "gpio29",
665 };
666 static const char * const sd_write_groups[] = {
667 	"gpio29",
668 };
669 static const char * const qup11_groups[] = {
670 	"gpio30", "gpio31", "gpio32", "gpio33",
671 };
672 static const char * const cam_mclk_groups[] = {
673 	"gpio34", "gpio35", "gpio36", "gpio44",
674 };
675 static const char * const atest_tsens_groups[] = {
676 	"gpio34",
677 };
678 static const char * const cci_i2c_groups[] = {
679 	"gpio37", "gpio38", "gpio39", "gpio40",
680 };
681 static const char * const cci_timer2_groups[] = {
682 	"gpio42",
683 };
684 static const char * const cci_timer1_groups[] = {
685 	"gpio43",
686 };
687 static const char * const gcc_gp2_groups[] = {
688 	"gpio43", "gpio44",
689 };
690 static const char * const cci_async_groups[] = {
691 	"gpio44", "gpio47", "gpio48",
692 };
693 static const char * const cci_timer4_groups[] = {
694 	"gpio44",
695 };
696 static const char * const cci_timer0_groups[] = {
697 	"gpio45",
698 };
699 static const char * const gcc_gp1_groups[] = {
700 	"gpio45", "gpio46",
701 };
702 static const char * const cci_timer3_groups[] = {
703 	"gpio46",
704 };
705 static const char * const wlan1_adc1_groups[] = {
706 	"gpio47",
707 };
708 static const char * const wlan1_adc0_groups[] = {
709 	"gpio48",
710 };
711 static const char * const qlink_request_groups[] = {
712 	"gpio50",
713 };
714 static const char * const qlink_enable_groups[] = {
715 	"gpio51",
716 };
717 static const char * const pa_indicator_groups[] = {
718 	"gpio52",
719 };
720 static const char * const nav_pps_groups[] = {
721 	"gpio52", "gpio55", "gpio56", "gpio58",
722 	"gpio59",
723 };
724 static const char * const gps_tx_groups[] = {
725 	"gpio52", "gpio53", "gpio55", "gpio56", "gpio58", "gpio59",
726 };
727 static const char * const gp_pdm0_groups[] = {
728 	"gpio53", "gpio94",
729 };
730 static const char * const atest_usb13_groups[] = {
731 	"gpio53",
732 };
733 static const char * const ddr_pxi1_groups[] = {
734 	"gpio53", "gpio54",
735 };
736 static const char * const atest_usb12_groups[] = {
737 	"gpio54",
738 };
739 static const char * const cri_trng0_groups[] = {
740 	"gpio59",
741 };
742 static const char * const cri_trng_groups[] = {
743 	"gpio60",
744 };
745 static const char * const cri_trng1_groups[] = {
746 	"gpio61",
747 };
748 static const char * const gp_pdm2_groups[] = {
749 	"gpio62", "gpio78",
750 };
751 static const char * const sp_cmu_groups[] = {
752 	"gpio63",
753 };
754 static const char * const atest_usb2_groups[] = {
755 	"gpio66",
756 };
757 static const char * const atest_usb23_groups[] = {
758 	"gpio67",
759 };
760 static const char * const uim2_data_groups[] = {
761 	"gpio72",
762 };
763 static const char * const uim2_clk_groups[] = {
764 	"gpio73",
765 };
766 static const char * const uim2_reset_groups[] = {
767 	"gpio74",
768 };
769 static const char * const atest_usb22_groups[] = {
770 	"gpio74",
771 };
772 static const char * const uim2_present_groups[] = {
773 	"gpio75",
774 };
775 static const char * const atest_usb21_groups[] = {
776 	"gpio75",
777 };
778 static const char * const uim1_data_groups[] = {
779 	"gpio76",
780 };
781 static const char * const atest_usb20_groups[] = {
782 	"gpio76",
783 };
784 static const char * const uim1_clk_groups[] = {
785 	"gpio77",
786 };
787 static const char * const uim1_reset_groups[] = {
788 	"gpio78",
789 };
790 static const char * const uim1_present_groups[] = {
791 	"gpio79",
792 };
793 static const char * const mdp_vsync_groups[] = {
794 	"gpio80", "gpio81", "gpio82", "gpio89", "gpio96", "gpio97",
795 };
796 static const char * const copy_gp_groups[] = {
797 	"gpio85",
798 };
799 static const char * const tsense_pwm_groups[] = {
800 	"gpio87",
801 };
802 static const char * const mpm_pwr_groups[] = {
803 	"gpio88",
804 };
805 static const char * const tgu_ch3_groups[] = {
806 	"gpio88",
807 };
808 static const char * const mdp_vsync0_groups[] = {
809 	"gpio89",
810 };
811 static const char * const mdp_vsync1_groups[] = {
812 	"gpio89",
813 };
814 static const char * const mdp_vsync2_groups[] = {
815 	"gpio89",
816 };
817 static const char * const mdp_vsync3_groups[] = {
818 	"gpio89",
819 };
820 static const char * const mdp_vsync4_groups[] = {
821 	"gpio89",
822 };
823 static const char * const mdp_vsync5_groups[] = {
824 	"gpio89",
825 };
826 static const char * const tgu_ch0_groups[] = {
827 	"gpio89",
828 };
829 static const char * const tgu_ch1_groups[] = {
830 	"gpio90",
831 };
832 static const char * const atest_char1_groups[] = {
833 	"gpio90",
834 };
835 static const char * const vfr_1_groups[] = {
836 	"gpio91",
837 };
838 static const char * const tgu_ch2_groups[] = {
839 	"gpio91",
840 };
841 static const char * const atest_char0_groups[] = {
842 	"gpio92",
843 };
844 static const char * const atest_char2_groups[] = {
845 	"gpio93",
846 };
847 static const char * const atest_char3_groups[] = {
848 	"gpio94",
849 };
850 static const char * const ldo_en_groups[] = {
851 	"gpio96",
852 };
853 static const char * const ldo_update_groups[] = {
854 	"gpio97",
855 };
856 static const char * const prng_rosc_groups[] = {
857 	"gpio98", "gpio100",
858 };
859 static const char * const dp_hot_groups[] = {
860 	"gpio100",
861 };
862 static const char * const debug_hot_groups[] = {
863 	"gpio101",
864 };
865 static const char * const copy_phase_groups[] = {
866 	"gpio101",
867 };
868 static const char * const usb_phy_groups[] = {
869 	"gpio102",
870 };
871 static const char * const atest_char_groups[] = {
872 	"gpio102",
873 };
874 static const char * const unused1_groups[] = {
875 	"gpio104",
876 };
877 static const char * const qua_mi2s_groups[] = {
878 	"gpio104", "gpio106", "gpio107", "gpio108", "gpio110", "gpio111",
879 };
880 static const char * const mss_lte_groups[] = {
881 	"gpio105", "gpio109",
882 };
883 static const char * const swr_tx_groups[] = {
884 	"gpio106", "gpio107", "gpio108", "gpio109",
885 };
886 static const char * const aud_sb_groups[] = {
887 	"gpio106", "gpio107", "gpio108", "gpio109",
888 };
889 static const char * const unused2_groups[] = {
890 	"gpio109",
891 };
892 static const char * const swr_rx_groups[] = {
893 	"gpio110", "gpio111", "gpio112",
894 };
895 static const char * const edp_hot_groups[] = {
896 	"gpio111",
897 };
898 static const char * const audio_ref_groups[] = {
899 	"gpio112",
900 };
901 static const char * const pri_mi2s_groups[] = {
902 	"gpio113", "gpio115", "gpio116",
903 };
904 static const char * const pri_mi2s_ws_groups[] = {
905 	"gpio114",
906 };
907 static const char * const adsp_ext_groups[] = {
908 	"gpio116",
909 };
910 static const char * const edp_lcd_groups[] = {
911 	"gpio117",
912 };
913 static const char * const mclk2_groups[] = {
914 	"gpio118",
915 };
916 static const char * const m_voc_groups[] = {
917 	"gpio118",
918 };
919 static const char * const mclk1_groups[] = {
920 	"gpio119",
921 };
922 static const char * const qca_sb_groups[] = {
923 	"gpio121", "gpio122",
924 };
925 static const char * const qui_mi2s_groups[] = {
926 	"gpio121", "gpio122", "gpio123", "gpio124",
927 };
928 static const char * const dmic0_clk_groups[] = {
929 	"gpio125",
930 };
931 static const char * const sec_mi2s_groups[] = {
932 	"gpio125", "gpio126", "gpio127", "gpio128",
933 };
934 static const char * const dmic0_data_groups[] = {
935 	"gpio126",
936 };
937 static const char * const dmic1_clk_groups[] = {
938 	"gpio127",
939 };
940 static const char * const dmic1_data_groups[] = {
941 	"gpio128",
942 };
943 
944 static const struct pinfunction sm6125_functions[] = {
945 	MSM_PIN_FUNCTION(qup00),
946 	MSM_PIN_FUNCTION(gpio),
947 	MSM_PIN_FUNCTION(qdss),
948 	MSM_PIN_FUNCTION(qup01),
949 	MSM_PIN_FUNCTION(qup02),
950 	MSM_PIN_FUNCTION(ddr_pxi0),
951 	MSM_PIN_FUNCTION(ddr_bist),
952 	MSM_PIN_FUNCTION(atest_tsens2),
953 	MSM_PIN_FUNCTION(vsense_trigger),
954 	MSM_PIN_FUNCTION(atest_usb1),
955 	MSM_PIN_FUNCTION(gp_pdm1),
956 	MSM_PIN_FUNCTION(phase_flag),
957 	MSM_PIN_FUNCTION(dbg_out),
958 	MSM_PIN_FUNCTION(qup14),
959 	MSM_PIN_FUNCTION(atest_usb11),
960 	MSM_PIN_FUNCTION(ddr_pxi2),
961 	MSM_PIN_FUNCTION(atest_usb10),
962 	MSM_PIN_FUNCTION(jitter_bist),
963 	MSM_PIN_FUNCTION(ddr_pxi3),
964 	MSM_PIN_FUNCTION(pll_bypassnl),
965 	MSM_PIN_FUNCTION(pll_bist),
966 	MSM_PIN_FUNCTION(qup03),
967 	MSM_PIN_FUNCTION(pll_reset),
968 	MSM_PIN_FUNCTION(agera_pll),
969 	MSM_PIN_FUNCTION(qdss_cti),
970 	MSM_PIN_FUNCTION(qup04),
971 	MSM_PIN_FUNCTION(wlan2_adc1),
972 	MSM_PIN_FUNCTION(wlan2_adc0),
973 	MSM_PIN_FUNCTION(wsa_clk),
974 	MSM_PIN_FUNCTION(qup13),
975 	MSM_PIN_FUNCTION(ter_mi2s),
976 	MSM_PIN_FUNCTION(wsa_data),
977 	MSM_PIN_FUNCTION(qup10),
978 	MSM_PIN_FUNCTION(gcc_gp3),
979 	MSM_PIN_FUNCTION(qup12),
980 	MSM_PIN_FUNCTION(sd_write),
981 	MSM_PIN_FUNCTION(qup11),
982 	MSM_PIN_FUNCTION(cam_mclk),
983 	MSM_PIN_FUNCTION(atest_tsens),
984 	MSM_PIN_FUNCTION(cci_i2c),
985 	MSM_PIN_FUNCTION(cci_timer2),
986 	MSM_PIN_FUNCTION(cci_timer1),
987 	MSM_PIN_FUNCTION(gcc_gp2),
988 	MSM_PIN_FUNCTION(cci_async),
989 	MSM_PIN_FUNCTION(cci_timer4),
990 	MSM_PIN_FUNCTION(cci_timer0),
991 	MSM_PIN_FUNCTION(gcc_gp1),
992 	MSM_PIN_FUNCTION(cci_timer3),
993 	MSM_PIN_FUNCTION(wlan1_adc1),
994 	MSM_PIN_FUNCTION(wlan1_adc0),
995 	MSM_PIN_FUNCTION(qlink_request),
996 	MSM_PIN_FUNCTION(qlink_enable),
997 	MSM_PIN_FUNCTION(pa_indicator),
998 	MSM_PIN_FUNCTION(nav_pps),
999 	MSM_PIN_FUNCTION(gps_tx),
1000 	MSM_PIN_FUNCTION(gp_pdm0),
1001 	MSM_PIN_FUNCTION(atest_usb13),
1002 	MSM_PIN_FUNCTION(ddr_pxi1),
1003 	MSM_PIN_FUNCTION(atest_usb12),
1004 	MSM_PIN_FUNCTION(cri_trng0),
1005 	MSM_PIN_FUNCTION(cri_trng),
1006 	MSM_PIN_FUNCTION(cri_trng1),
1007 	MSM_PIN_FUNCTION(gp_pdm2),
1008 	MSM_PIN_FUNCTION(sp_cmu),
1009 	MSM_PIN_FUNCTION(atest_usb2),
1010 	MSM_PIN_FUNCTION(atest_usb23),
1011 	MSM_PIN_FUNCTION(uim2_data),
1012 	MSM_PIN_FUNCTION(uim2_clk),
1013 	MSM_PIN_FUNCTION(uim2_reset),
1014 	MSM_PIN_FUNCTION(atest_usb22),
1015 	MSM_PIN_FUNCTION(uim2_present),
1016 	MSM_PIN_FUNCTION(atest_usb21),
1017 	MSM_PIN_FUNCTION(uim1_data),
1018 	MSM_PIN_FUNCTION(atest_usb20),
1019 	MSM_PIN_FUNCTION(uim1_clk),
1020 	MSM_PIN_FUNCTION(uim1_reset),
1021 	MSM_PIN_FUNCTION(uim1_present),
1022 	MSM_PIN_FUNCTION(mdp_vsync),
1023 	MSM_PIN_FUNCTION(copy_gp),
1024 	MSM_PIN_FUNCTION(tsense_pwm),
1025 	MSM_PIN_FUNCTION(mpm_pwr),
1026 	MSM_PIN_FUNCTION(tgu_ch3),
1027 	MSM_PIN_FUNCTION(mdp_vsync0),
1028 	MSM_PIN_FUNCTION(mdp_vsync1),
1029 	MSM_PIN_FUNCTION(mdp_vsync2),
1030 	MSM_PIN_FUNCTION(mdp_vsync3),
1031 	MSM_PIN_FUNCTION(mdp_vsync4),
1032 	MSM_PIN_FUNCTION(mdp_vsync5),
1033 	MSM_PIN_FUNCTION(tgu_ch0),
1034 	MSM_PIN_FUNCTION(tgu_ch1),
1035 	MSM_PIN_FUNCTION(atest_char1),
1036 	MSM_PIN_FUNCTION(vfr_1),
1037 	MSM_PIN_FUNCTION(tgu_ch2),
1038 	MSM_PIN_FUNCTION(atest_char0),
1039 	MSM_PIN_FUNCTION(atest_char2),
1040 	MSM_PIN_FUNCTION(atest_char3),
1041 	MSM_PIN_FUNCTION(ldo_en),
1042 	MSM_PIN_FUNCTION(ldo_update),
1043 	MSM_PIN_FUNCTION(prng_rosc),
1044 	MSM_PIN_FUNCTION(dp_hot),
1045 	MSM_PIN_FUNCTION(debug_hot),
1046 	MSM_PIN_FUNCTION(copy_phase),
1047 	MSM_PIN_FUNCTION(usb_phy),
1048 	MSM_PIN_FUNCTION(atest_char),
1049 	MSM_PIN_FUNCTION(unused1),
1050 	MSM_PIN_FUNCTION(qua_mi2s),
1051 	MSM_PIN_FUNCTION(mss_lte),
1052 	MSM_PIN_FUNCTION(swr_tx),
1053 	MSM_PIN_FUNCTION(aud_sb),
1054 	MSM_PIN_FUNCTION(unused2),
1055 	MSM_PIN_FUNCTION(swr_rx),
1056 	MSM_PIN_FUNCTION(edp_hot),
1057 	MSM_PIN_FUNCTION(audio_ref),
1058 	MSM_PIN_FUNCTION(pri_mi2s),
1059 	MSM_PIN_FUNCTION(pri_mi2s_ws),
1060 	MSM_PIN_FUNCTION(adsp_ext),
1061 	MSM_PIN_FUNCTION(edp_lcd),
1062 	MSM_PIN_FUNCTION(mclk2),
1063 	MSM_PIN_FUNCTION(m_voc),
1064 	MSM_PIN_FUNCTION(mclk1),
1065 	MSM_PIN_FUNCTION(qca_sb),
1066 	MSM_PIN_FUNCTION(qui_mi2s),
1067 	MSM_PIN_FUNCTION(dmic0_clk),
1068 	MSM_PIN_FUNCTION(sec_mi2s),
1069 	MSM_PIN_FUNCTION(dmic0_data),
1070 	MSM_PIN_FUNCTION(dmic1_clk),
1071 	MSM_PIN_FUNCTION(dmic1_data),
1072 };
1073 
1074  /*
1075  * Every pin is maintained as a single group, and missing or non-existing pin
1076  * would be maintained as dummy group to synchronize pin group index with
1077  * pin descriptor registered with pinctrl core.
1078  * Clients would not be able to request these dummy pin groups.
1079  */
1080 static const struct msm_pingroup sm6125_groups[] = {
1081 	[0] = PINGROUP(0, WEST, qup00, _, qdss, _, _, _, _, _, _),
1082 	[1] = PINGROUP(1, WEST, qup00, _, qdss, _, _, _, _, _, _),
1083 	[2] = PINGROUP(2, WEST, qup00, _, qdss, _, _, _, _, _, _),
1084 	[3] = PINGROUP(3, WEST, qup00, _, qdss, _, _, _, _, _, _),
1085 	[4] = PINGROUP(4, WEST, qup01, _, _, _, _, _, _, _, _),
1086 	[5] = PINGROUP(5, WEST, qup01, _, _, _, _, _, _, _, _),
1087 	[6] = PINGROUP(6, WEST, qup02, ddr_pxi0, _, _, _, _, _, _, _),
1088 	[7] = PINGROUP(7, WEST, qup02, ddr_bist, atest_tsens2, vsense_trigger, atest_usb1, ddr_pxi0, _, _, _),
1089 	[8] = PINGROUP(8, WEST, qup02, gp_pdm1, ddr_bist, _, phase_flag, _, _, _, _),
1090 	[9] = PINGROUP(9, WEST, qup02, ddr_bist, dbg_out, phase_flag, _, _, _, _, _),
1091 	[10] = PINGROUP(10, EAST, qup14, ddr_bist, atest_usb11, ddr_pxi2, _, _, _, _, _),
1092 	[11] = PINGROUP(11, EAST, qup14, atest_usb10, ddr_pxi2, _, _, _, _, _, _),
1093 	[12] = PINGROUP(12, EAST, qup14, jitter_bist, ddr_pxi3, _, _, _, _, _, _),
1094 	[13] = PINGROUP(13, EAST, qup14, pll_bypassnl, pll_bist, _, ddr_pxi3, _, _, _, _),
1095 	[14] = PINGROUP(14, WEST, qup03, qup03, pll_reset, agera_pll, _, qdss_cti, _, _, _),
1096 	[15] = PINGROUP(15, WEST, qup03, qup03, qdss_cti, _, _, _, _, _, _),
1097 	[16] = PINGROUP(16, WEST, qup04, qup04, _, wlan2_adc1, _, _, _, _, _),
1098 	[17] = PINGROUP(17, WEST, qup04, qup04, _, wlan2_adc0, _, _, _, _, _),
1099 	[18] = PINGROUP(18, EAST, wsa_clk, qup13, ter_mi2s, _, _, _, _, _, _),
1100 	[19] = PINGROUP(19, EAST, wsa_data, qup13, ter_mi2s, _, _, _, _, _, _),
1101 	[20] = PINGROUP(20, EAST, qup13, ter_mi2s, qdss, _, _, _, _, _, _),
1102 	[21] = PINGROUP(21, EAST, qup13, ter_mi2s, _, qdss, _, _, _, _, _),
1103 	[22] = PINGROUP(22, WEST, qup10, gcc_gp3, _, _, _, _, _, _, _),
1104 	[23] = PINGROUP(23, WEST, qup10, _, phase_flag, _, _, _, _, _, _),
1105 	[24] = PINGROUP(24, WEST, qup10, _, phase_flag, _, _, _, _, _, _),
1106 	[25] = PINGROUP(25, WEST, qup10, _, phase_flag, _, _, _, _, _, _),
1107 	[26] = PINGROUP(26, WEST, qup10, _, phase_flag, _, _, _, _, _, _),
1108 	[27] = PINGROUP(27, WEST, qup10, _, _, _, _, _, _, _, _),
1109 	[28] = PINGROUP(28, WEST, qup12, _, phase_flag, _, _, _, _, _, _),
1110 	[29] = PINGROUP(29, WEST, qup12, sd_write, _, phase_flag, _, _, _, _, _),
1111 	[30] = PINGROUP(30, WEST, qup11, _, phase_flag, _, _, _, _, _, _),
1112 	[31] = PINGROUP(31, WEST, qup11, jitter_bist, _, _, _, _, _, _, _),
1113 	[32] = PINGROUP(32, WEST, qup11, pll_bist, _, _, _, _, _, _, _),
1114 	[33] = PINGROUP(33, WEST, qup11, agera_pll, _, _, _, _, _, _, _),
1115 	[34] = PINGROUP(34, SOUTH, cam_mclk, _, qdss, atest_tsens, _, _, _, _, _),
1116 	[35] = PINGROUP(35, SOUTH, cam_mclk, _, qdss, _, _, _, _, _, _),
1117 	[36] = PINGROUP(36, SOUTH, cam_mclk, _, qdss, _, _, _, _, _, _),
1118 	[37] = PINGROUP(37, SOUTH, cci_i2c, _, _, _, _, _, _, _, _),
1119 	[38] = PINGROUP(38, EAST, cci_i2c, _, _, _, _, _, _, _, _),
1120 	[39] = PINGROUP(39, EAST, cci_i2c, _, _, _, _, _, _, _, _),
1121 	[40] = PINGROUP(40, EAST, cci_i2c, _, _, _, _, _, _, _, _),
1122 	[41] = PINGROUP(41, EAST, _, qdss, _, _, _, _, _, _, _),
1123 	[42] = PINGROUP(42, EAST, cci_timer2, _, qdss, _, _, _, _, _, _),
1124 	[43] = PINGROUP(43, EAST, cci_timer1, _, gcc_gp2, _, qdss, _, _, _, _),
1125 	[44] = PINGROUP(44, SOUTH, cci_async, cci_timer4, _, gcc_gp2, _, qdss, cam_mclk, _, _),
1126 	[45] = PINGROUP(45, SOUTH, cci_timer0, _, gcc_gp1, qdss, _, _, _, _, _),
1127 	[46] = PINGROUP(46, SOUTH, cci_timer3, _, gcc_gp1, _, qdss, _, _, _, _),
1128 	[47] = PINGROUP(47, SOUTH, cci_async, _, qdss, wlan1_adc1, _, _, _, _, _),
1129 	[48] = PINGROUP(48, SOUTH, cci_async, _, qdss, wlan1_adc0, _, _, _, _, _),
1130 	[49] = PINGROUP(49, SOUTH, qdss, _, _, _, _, _, _, _, _),
1131 	[50] = PINGROUP(50, SOUTH, qlink_request, _, _, _, _, _, _, _, _),
1132 	[51] = PINGROUP(51, SOUTH, qlink_enable, _, _, _, _, _, _, _, _),
1133 	[52] = PINGROUP(52, SOUTH, pa_indicator, nav_pps, nav_pps, gps_tx, _, _, _, _, _),
1134 	[53] = PINGROUP(53, SOUTH, _, gps_tx, gp_pdm0, _, phase_flag, atest_usb13, ddr_pxi1, _, _),
1135 	[54] = PINGROUP(54, SOUTH, _, _, phase_flag, atest_usb12, ddr_pxi1, _, _, _, _),
1136 	[55] = PINGROUP(55, SOUTH, _, nav_pps, nav_pps, gps_tx, _, phase_flag, _, _, _),
1137 	[56] = PINGROUP(56, SOUTH, _, nav_pps, gps_tx, nav_pps, phase_flag, _, _, _, _),
1138 	[57] = PINGROUP(57, SOUTH, _, phase_flag, _, _, _, _, _, _, _),
1139 	[58] = PINGROUP(58, SOUTH, _, nav_pps, nav_pps, gps_tx, gcc_gp3, _, phase_flag, _, _),
1140 	[59] = PINGROUP(59, SOUTH, _, nav_pps, nav_pps, gps_tx, cri_trng0, _, phase_flag, _, _),
1141 	[60] = PINGROUP(60, SOUTH, _, cri_trng, _, phase_flag, _, _, _, _, _),
1142 	[61] = PINGROUP(61, SOUTH, _, cri_trng1, _, phase_flag, _, _, _, _, _),
1143 	[62] = PINGROUP(62, SOUTH, _, _, gp_pdm2, _, phase_flag, _, _, _, _),
1144 	[63] = PINGROUP(63, SOUTH, _, sp_cmu, _, _, _, _, _, _, _),
1145 	[64] = PINGROUP(64, SOUTH, _, _, _, _, _, _, _, _, _),
1146 	[65] = PINGROUP(65, SOUTH, _, gp_pdm1, _, _, _, _, _, _, _),
1147 	[66] = PINGROUP(66, SOUTH, _, _, atest_usb2, _, _, _, _, _, _),
1148 	[67] = PINGROUP(67, SOUTH, _, _, atest_usb23, _, _, _, _, _, _),
1149 	[68] = PINGROUP(68, SOUTH, _, _, _, _, _, _, _, _, _),
1150 	[69] = PINGROUP(69, SOUTH, _, _, _, _, _, _, _, _, _),
1151 	[70] = PINGROUP(70, SOUTH, _, _, _, _, _, _, _, _, _),
1152 	[71] = PINGROUP(71, SOUTH, _, _, _, _, _, _, _, _, _),
1153 	[72] = PINGROUP(72, SOUTH, uim2_data, _, _, _, _, _, _, _, _),
1154 	[73] = PINGROUP(73, SOUTH, uim2_clk, _, _, _, _, _, _, _, _),
1155 	[74] = PINGROUP(74, SOUTH, uim2_reset, _, atest_usb22, _, _, _, _, _, _),
1156 	[75] = PINGROUP(75, SOUTH, uim2_present, _, atest_usb21, _, _, _, _, _, _),
1157 	[76] = PINGROUP(76, SOUTH, uim1_data, _, atest_usb20, _, _, _, _, _, _),
1158 	[77] = PINGROUP(77, SOUTH, uim1_clk, _, _, _, _, _, _, _, _),
1159 	[78] = PINGROUP(78, SOUTH, uim1_reset, gp_pdm2, _, _, _, _, _, _, _),
1160 	[79] = PINGROUP(79, SOUTH, uim1_present, _, _, _, _, _, _, _, _),
1161 	[80] = PINGROUP(80, SOUTH, mdp_vsync, _, phase_flag, qdss, _, _, _, _, _),
1162 	[81] = PINGROUP(81, SOUTH, mdp_vsync, _, phase_flag, qdss, _, _, _, _, _),
1163 	[82] = PINGROUP(82, SOUTH, mdp_vsync, _, phase_flag, qdss, _, _, _, _, _),
1164 	[83] = PINGROUP(83, SOUTH, _, phase_flag, qdss, _, _, _, _, _, _),
1165 	[84] = PINGROUP(84, SOUTH, _, phase_flag, qdss, _, _, _, _, _, _),
1166 	[85] = PINGROUP(85, SOUTH, copy_gp, _, qdss, _, _, _, _, _, _),
1167 	[86] = PINGROUP(86, SOUTH, _, qdss, _, _, _, _, _, _, _),
1168 	[87] = PINGROUP(87, WEST, tsense_pwm, _, _, _, _, _, _, _, _),
1169 	[88] = PINGROUP(88, WEST, mpm_pwr, tgu_ch3, _, phase_flag, _, _, _, _, _),
1170 	[89] = PINGROUP(89, WEST, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, mdp_vsync4, mdp_vsync5, tgu_ch0, _),
1171 	[90] = PINGROUP(90, WEST, tgu_ch1, atest_char1, _, _, _, _, _, _, _),
1172 	[91] = PINGROUP(91, WEST, vfr_1, tgu_ch2, _, phase_flag, qdss, _, _, _, _),
1173 	[92] = PINGROUP(92, WEST, qdss, atest_char0, _, _, _, _, _, _, _),
1174 	[93] = PINGROUP(93, WEST, _, phase_flag, atest_char2, _, _, _, _, _, _),
1175 	[94] = PINGROUP(94, SOUTH, gp_pdm0, _, qdss, atest_char3, _, _, _, _, _),
1176 	[95] = PINGROUP(95, SOUTH, qdss_cti, _, _, _, _, _, _, _, _),
1177 	[96] = PINGROUP(96, SOUTH, mdp_vsync, ldo_en, qdss, _, _, _, _, _, _),
1178 	[97] = PINGROUP(97, SOUTH, mdp_vsync, ldo_update, _, _, _, _, _, _, _),
1179 	[98] = PINGROUP(98, SOUTH, _, phase_flag, prng_rosc, _, _, _, _, _, _),
1180 	[99] = PINGROUP(99, SOUTH, _, _, _, _, _, _, _, _, _),
1181 	[100] = PINGROUP(100, SOUTH, dp_hot, prng_rosc, qdss, _, _, _, _, _, _),
1182 	[101] = PINGROUP(101, SOUTH, debug_hot, copy_phase, qdss_cti, _, _, _, _, _, _),
1183 	[102] = PINGROUP(102, SOUTH, usb_phy, _, qdss, atest_char, _, _, _, _, _),
1184 	[103] = PINGROUP(103, SOUTH, _, _, _, _, _, _, _, _, _),
1185 	[104] = PINGROUP(104, EAST, unused1, _, qua_mi2s, _, _, _, _, _, _),
1186 	[105] = PINGROUP(105, EAST, mss_lte, _, _, _, _, _, _, _, _),
1187 	[106] = PINGROUP(106, EAST, swr_tx, aud_sb, qua_mi2s, _, qdss_cti, _, _, _, _),
1188 	[107] = PINGROUP(107, EAST, swr_tx, aud_sb, qua_mi2s, _, qdss_cti, _, _, _, _),
1189 	[108] = PINGROUP(108, EAST, swr_tx, aud_sb, qua_mi2s, _, _, _, _, _, _),
1190 	[109] = PINGROUP(109, EAST, swr_tx, aud_sb, unused2, _, mss_lte, _, _, _, _),
1191 	[110] = PINGROUP(110, EAST, swr_rx, qua_mi2s, _, qdss_cti, _, _, _, _, _),
1192 	[111] = PINGROUP(111, EAST, swr_rx, qua_mi2s, edp_hot, _, qdss_cti, _, _, _, _),
1193 	[112] = PINGROUP(112, EAST, swr_rx, audio_ref, _, _, _, _, _, _, _),
1194 	[113] = PINGROUP(113, EAST, pri_mi2s, _, _, _, _, _, _, _, _),
1195 	[114] = PINGROUP(114, EAST, pri_mi2s_ws, qdss, _, _, _, _, _, _, _),
1196 	[115] = PINGROUP(115, EAST, pri_mi2s, qdss, _, _, _, _, _, _, _),
1197 	[116] = PINGROUP(116, EAST, pri_mi2s, adsp_ext, qdss, _, _, _, _, _, _),
1198 	[117] = PINGROUP(117, SOUTH, edp_lcd, qdss, _, _, _, _, _, _, _),
1199 	[118] = PINGROUP(118, SOUTH, mclk2, m_voc, qdss, _, _, _, _, _, _),
1200 	[119] = PINGROUP(119, SOUTH, mclk1, _, _, _, _, _, _, _, _),
1201 	[120] = PINGROUP(120, SOUTH, _, _, _, _, _, _, _, _, _),
1202 	[121] = PINGROUP(121, EAST, qca_sb, qui_mi2s, _, _, _, _, _, _, _),
1203 	[122] = PINGROUP(122, EAST, qca_sb, qui_mi2s, _, _, _, _, _, _, _),
1204 	[123] = PINGROUP(123, EAST, qui_mi2s, _, _, _, _, _, _, _, _),
1205 	[124] = PINGROUP(124, EAST, qui_mi2s, _, _, _, _, _, _, _, _),
1206 	[125] = PINGROUP(125, EAST, dmic0_clk, sec_mi2s, _, _, _, _, _, _, _),
1207 	[126] = PINGROUP(126, EAST, dmic0_data, sec_mi2s, _, _, _, _, _, _, _),
1208 	[127] = PINGROUP(127, EAST, dmic1_clk, sec_mi2s, _, _, _, _, _, _, _),
1209 	[128] = PINGROUP(128, EAST, dmic1_data, sec_mi2s, _, _, _, _, _, _, _),
1210 	[129] = PINGROUP(129, SOUTH, _, phase_flag, _, _, _, _, _, _, _),
1211 	[130] = PINGROUP(130, SOUTH, phase_flag, _, _, _, _, _, _, _, _),
1212 	[131] = PINGROUP(131, SOUTH, phase_flag, _, _, _, _, _, _, _, _),
1213 	[132] = PINGROUP(132, SOUTH, _, _, _, _, _, _, _, _, _),
1214 	[133] = UFS_RESET(ufs_reset, 0x190000),
1215 	[134] = SDC_QDSD_PINGROUP(sdc1_rclk, WEST, 0x18d000, 15, 0),
1216 	[135] = SDC_QDSD_PINGROUP(sdc1_clk, WEST, 0x18d000, 13, 6),
1217 	[136] = SDC_QDSD_PINGROUP(sdc1_cmd, WEST, 0x18d000, 11, 3),
1218 	[137] = SDC_QDSD_PINGROUP(sdc1_data, WEST, 0x18d000, 9, 0),
1219 	[138] = SDC_QDSD_PINGROUP(sdc2_clk, SOUTH, 0x58b000, 14, 6),
1220 	[139] = SDC_QDSD_PINGROUP(sdc2_cmd, SOUTH, 0x58b000, 11, 3),
1221 	[140] = SDC_QDSD_PINGROUP(sdc2_data, SOUTH, 0x58b000, 9, 0),
1222 };
1223 
1224 static const struct msm_pinctrl_soc_data sm6125_tlmm = {
1225 	.pins = sm6125_pins,
1226 	.npins = ARRAY_SIZE(sm6125_pins),
1227 	.functions = sm6125_functions,
1228 	.nfunctions = ARRAY_SIZE(sm6125_functions),
1229 	.groups = sm6125_groups,
1230 	.ngroups = ARRAY_SIZE(sm6125_groups),
1231 	.ngpios = 134,
1232 	.tiles = sm6125_tiles,
1233 	.ntiles = ARRAY_SIZE(sm6125_tiles),
1234 };
1235 
sm6125_tlmm_probe(struct platform_device * pdev)1236 static int sm6125_tlmm_probe(struct platform_device *pdev)
1237 {
1238 	return msm_pinctrl_probe(pdev, &sm6125_tlmm);
1239 }
1240 
1241 static const struct of_device_id sm6125_tlmm_of_match[] = {
1242 	{ .compatible = "qcom,sm6125-tlmm", },
1243 	{ },
1244 };
1245 
1246 static struct platform_driver sm6125_tlmm_driver = {
1247 	.driver = {
1248 		.name = "sm6125-tlmm",
1249 		.of_match_table = sm6125_tlmm_of_match,
1250 	},
1251 	.probe = sm6125_tlmm_probe,
1252 	.remove = msm_pinctrl_remove,
1253 };
1254 
sm6125_tlmm_init(void)1255 static int __init sm6125_tlmm_init(void)
1256 {
1257 	return platform_driver_register(&sm6125_tlmm_driver);
1258 }
1259 arch_initcall(sm6125_tlmm_init);
1260 
sm6125_tlmm_exit(void)1261 static void __exit sm6125_tlmm_exit(void)
1262 {
1263 	platform_driver_unregister(&sm6125_tlmm_driver);
1264 }
1265 module_exit(sm6125_tlmm_exit);
1266 
1267 MODULE_DESCRIPTION("QTI sm6125 TLMM driver");
1268 MODULE_LICENSE("GPL v2");
1269 MODULE_DEVICE_TABLE(of, sm6125_tlmm_of_match);
1270