1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Qualcomm PCIe root complex driver
4 *
5 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
6 * Copyright 2015 Linaro Limited.
7 *
8 * Author: Stanimir Varbanov <svarbanov@mm-sol.com>
9 */
10
11 #include <linux/clk.h>
12 #include <linux/crc8.h>
13 #include <linux/debugfs.h>
14 #include <linux/delay.h>
15 #include <linux/gpio/consumer.h>
16 #include <linux/interconnect.h>
17 #include <linux/interrupt.h>
18 #include <linux/io.h>
19 #include <linux/iopoll.h>
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/of.h>
23 #include <linux/of_gpio.h>
24 #include <linux/pci.h>
25 #include <linux/pm_runtime.h>
26 #include <linux/platform_device.h>
27 #include <linux/phy/pcie.h>
28 #include <linux/phy/phy.h>
29 #include <linux/regulator/consumer.h>
30 #include <linux/reset.h>
31 #include <linux/slab.h>
32 #include <linux/types.h>
33
34 #include "../../pci.h"
35 #include "pcie-designware.h"
36
37 /* PARF registers */
38 #define PARF_SYS_CTRL 0x00
39 #define PARF_PM_CTRL 0x20
40 #define PARF_PCS_DEEMPH 0x34
41 #define PARF_PCS_SWING 0x38
42 #define PARF_PHY_CTRL 0x40
43 #define PARF_PHY_REFCLK 0x4c
44 #define PARF_CONFIG_BITS 0x50
45 #define PARF_DBI_BASE_ADDR 0x168
46 #define PARF_MHI_CLOCK_RESET_CTRL 0x174
47 #define PARF_AXI_MSTR_WR_ADDR_HALT 0x178
48 #define PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1a8
49 #define PARF_Q2A_FLUSH 0x1ac
50 #define PARF_LTSSM 0x1b0
51 #define PARF_SID_OFFSET 0x234
52 #define PARF_BDF_TRANSLATE_CFG 0x24c
53 #define PARF_SLV_ADDR_SPACE_SIZE 0x358
54 #define PARF_DEVICE_TYPE 0x1000
55 #define PARF_BDF_TO_SID_TABLE_N 0x2000
56
57 /* ELBI registers */
58 #define ELBI_SYS_CTRL 0x04
59
60 /* DBI registers */
61 #define AXI_MSTR_RESP_COMP_CTRL0 0x818
62 #define AXI_MSTR_RESP_COMP_CTRL1 0x81c
63
64 /* MHI registers */
65 #define PARF_DEBUG_CNT_PM_LINKST_IN_L2 0xc04
66 #define PARF_DEBUG_CNT_PM_LINKST_IN_L1 0xc0c
67 #define PARF_DEBUG_CNT_PM_LINKST_IN_L0S 0xc10
68 #define PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1 0xc84
69 #define PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2 0xc88
70
71 /* PARF_SYS_CTRL register fields */
72 #define MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN BIT(29)
73 #define MST_WAKEUP_EN BIT(13)
74 #define SLV_WAKEUP_EN BIT(12)
75 #define MSTR_ACLK_CGC_DIS BIT(10)
76 #define SLV_ACLK_CGC_DIS BIT(9)
77 #define CORE_CLK_CGC_DIS BIT(6)
78 #define AUX_PWR_DET BIT(4)
79 #define L23_CLK_RMV_DIS BIT(2)
80 #define L1_CLK_RMV_DIS BIT(1)
81
82 /* PARF_PM_CTRL register fields */
83 #define REQ_NOT_ENTR_L1 BIT(5)
84
85 /* PARF_PCS_DEEMPH register fields */
86 #define PCS_DEEMPH_TX_DEEMPH_GEN1(x) FIELD_PREP(GENMASK(21, 16), x)
87 #define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) FIELD_PREP(GENMASK(13, 8), x)
88 #define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x) FIELD_PREP(GENMASK(5, 0), x)
89
90 /* PARF_PCS_SWING register fields */
91 #define PCS_SWING_TX_SWING_FULL(x) FIELD_PREP(GENMASK(14, 8), x)
92 #define PCS_SWING_TX_SWING_LOW(x) FIELD_PREP(GENMASK(6, 0), x)
93
94 /* PARF_PHY_CTRL register fields */
95 #define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK GENMASK(20, 16)
96 #define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) FIELD_PREP(PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK, x)
97 #define PHY_TEST_PWR_DOWN BIT(0)
98
99 /* PARF_PHY_REFCLK register fields */
100 #define PHY_REFCLK_SSP_EN BIT(16)
101 #define PHY_REFCLK_USE_PAD BIT(12)
102
103 /* PARF_CONFIG_BITS register fields */
104 #define PHY_RX0_EQ(x) FIELD_PREP(GENMASK(26, 24), x)
105
106 /* PARF_SLV_ADDR_SPACE_SIZE register value */
107 #define SLV_ADDR_SPACE_SZ 0x10000000
108
109 /* PARF_MHI_CLOCK_RESET_CTRL register fields */
110 #define AHB_CLK_EN BIT(0)
111 #define MSTR_AXI_CLK_EN BIT(1)
112 #define BYPASS BIT(4)
113
114 /* PARF_AXI_MSTR_WR_ADDR_HALT register fields */
115 #define EN BIT(31)
116
117 /* PARF_LTSSM register fields */
118 #define LTSSM_EN BIT(8)
119
120 /* PARF_DEVICE_TYPE register fields */
121 #define DEVICE_TYPE_RC 0x4
122
123 /* ELBI_SYS_CTRL register fields */
124 #define ELBI_SYS_CTRL_LT_ENABLE BIT(0)
125
126 /* AXI_MSTR_RESP_COMP_CTRL0 register fields */
127 #define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K 0x4
128 #define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_4K 0x5
129
130 /* AXI_MSTR_RESP_COMP_CTRL1 register fields */
131 #define CFG_BRIDGE_SB_INIT BIT(0)
132
133 /* PCI_EXP_SLTCAP register fields */
134 #define PCIE_CAP_SLOT_POWER_LIMIT_VAL FIELD_PREP(PCI_EXP_SLTCAP_SPLV, 250)
135 #define PCIE_CAP_SLOT_POWER_LIMIT_SCALE FIELD_PREP(PCI_EXP_SLTCAP_SPLS, 1)
136 #define PCIE_CAP_SLOT_VAL (PCI_EXP_SLTCAP_ABP | \
137 PCI_EXP_SLTCAP_PCP | \
138 PCI_EXP_SLTCAP_MRLSP | \
139 PCI_EXP_SLTCAP_AIP | \
140 PCI_EXP_SLTCAP_PIP | \
141 PCI_EXP_SLTCAP_HPS | \
142 PCI_EXP_SLTCAP_EIP | \
143 PCIE_CAP_SLOT_POWER_LIMIT_VAL | \
144 PCIE_CAP_SLOT_POWER_LIMIT_SCALE)
145
146 #define PERST_DELAY_US 1000
147
148 #define QCOM_PCIE_CRC8_POLYNOMIAL (BIT(2) | BIT(1) | BIT(0))
149
150 #define QCOM_PCIE_1_0_0_MAX_CLOCKS 4
151 struct qcom_pcie_resources_1_0_0 {
152 struct clk_bulk_data clks[QCOM_PCIE_1_0_0_MAX_CLOCKS];
153 struct reset_control *core;
154 struct regulator *vdda;
155 };
156
157 #define QCOM_PCIE_2_1_0_MAX_CLOCKS 5
158 #define QCOM_PCIE_2_1_0_MAX_RESETS 6
159 #define QCOM_PCIE_2_1_0_MAX_SUPPLY 3
160 struct qcom_pcie_resources_2_1_0 {
161 struct clk_bulk_data clks[QCOM_PCIE_2_1_0_MAX_CLOCKS];
162 struct reset_control_bulk_data resets[QCOM_PCIE_2_1_0_MAX_RESETS];
163 int num_resets;
164 struct regulator_bulk_data supplies[QCOM_PCIE_2_1_0_MAX_SUPPLY];
165 };
166
167 #define QCOM_PCIE_2_3_2_MAX_CLOCKS 4
168 #define QCOM_PCIE_2_3_2_MAX_SUPPLY 2
169 struct qcom_pcie_resources_2_3_2 {
170 struct clk_bulk_data clks[QCOM_PCIE_2_3_2_MAX_CLOCKS];
171 struct regulator_bulk_data supplies[QCOM_PCIE_2_3_2_MAX_SUPPLY];
172 };
173
174 #define QCOM_PCIE_2_3_3_MAX_CLOCKS 5
175 #define QCOM_PCIE_2_3_3_MAX_RESETS 7
176 struct qcom_pcie_resources_2_3_3 {
177 struct clk_bulk_data clks[QCOM_PCIE_2_3_3_MAX_CLOCKS];
178 struct reset_control_bulk_data rst[QCOM_PCIE_2_3_3_MAX_RESETS];
179 };
180
181 #define QCOM_PCIE_2_4_0_MAX_CLOCKS 4
182 #define QCOM_PCIE_2_4_0_MAX_RESETS 12
183 struct qcom_pcie_resources_2_4_0 {
184 struct clk_bulk_data clks[QCOM_PCIE_2_4_0_MAX_CLOCKS];
185 int num_clks;
186 struct reset_control_bulk_data resets[QCOM_PCIE_2_4_0_MAX_RESETS];
187 int num_resets;
188 };
189
190 #define QCOM_PCIE_2_7_0_MAX_CLOCKS 15
191 #define QCOM_PCIE_2_7_0_MAX_SUPPLIES 2
192 struct qcom_pcie_resources_2_7_0 {
193 struct clk_bulk_data clks[QCOM_PCIE_2_7_0_MAX_CLOCKS];
194 int num_clks;
195 struct regulator_bulk_data supplies[QCOM_PCIE_2_7_0_MAX_SUPPLIES];
196 struct reset_control *rst;
197 };
198
199 #define QCOM_PCIE_2_9_0_MAX_CLOCKS 5
200 struct qcom_pcie_resources_2_9_0 {
201 struct clk_bulk_data clks[QCOM_PCIE_2_9_0_MAX_CLOCKS];
202 struct reset_control *rst;
203 };
204
205 union qcom_pcie_resources {
206 struct qcom_pcie_resources_1_0_0 v1_0_0;
207 struct qcom_pcie_resources_2_1_0 v2_1_0;
208 struct qcom_pcie_resources_2_3_2 v2_3_2;
209 struct qcom_pcie_resources_2_3_3 v2_3_3;
210 struct qcom_pcie_resources_2_4_0 v2_4_0;
211 struct qcom_pcie_resources_2_7_0 v2_7_0;
212 struct qcom_pcie_resources_2_9_0 v2_9_0;
213 };
214
215 struct qcom_pcie;
216
217 struct qcom_pcie_ops {
218 int (*get_resources)(struct qcom_pcie *pcie);
219 int (*init)(struct qcom_pcie *pcie);
220 int (*post_init)(struct qcom_pcie *pcie);
221 void (*deinit)(struct qcom_pcie *pcie);
222 void (*ltssm_enable)(struct qcom_pcie *pcie);
223 int (*config_sid)(struct qcom_pcie *pcie);
224 };
225
226 struct qcom_pcie_cfg {
227 const struct qcom_pcie_ops *ops;
228 };
229
230 struct qcom_pcie {
231 struct dw_pcie *pci;
232 void __iomem *parf; /* DT parf */
233 void __iomem *elbi; /* DT elbi */
234 void __iomem *mhi;
235 union qcom_pcie_resources res;
236 struct phy *phy;
237 struct gpio_desc *reset;
238 struct icc_path *icc_mem;
239 const struct qcom_pcie_cfg *cfg;
240 struct dentry *debugfs;
241 bool suspended;
242 };
243
244 #define to_qcom_pcie(x) dev_get_drvdata((x)->dev)
245
qcom_ep_reset_assert(struct qcom_pcie * pcie)246 static void qcom_ep_reset_assert(struct qcom_pcie *pcie)
247 {
248 gpiod_set_value_cansleep(pcie->reset, 1);
249 usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500);
250 }
251
qcom_ep_reset_deassert(struct qcom_pcie * pcie)252 static void qcom_ep_reset_deassert(struct qcom_pcie *pcie)
253 {
254 /* Ensure that PERST has been asserted for at least 100 ms */
255 msleep(100);
256 gpiod_set_value_cansleep(pcie->reset, 0);
257 usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500);
258 }
259
qcom_pcie_start_link(struct dw_pcie * pci)260 static int qcom_pcie_start_link(struct dw_pcie *pci)
261 {
262 struct qcom_pcie *pcie = to_qcom_pcie(pci);
263
264 /* Enable Link Training state machine */
265 if (pcie->cfg->ops->ltssm_enable)
266 pcie->cfg->ops->ltssm_enable(pcie);
267
268 return 0;
269 }
270
qcom_pcie_clear_hpc(struct dw_pcie * pci)271 static void qcom_pcie_clear_hpc(struct dw_pcie *pci)
272 {
273 u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
274 u32 val;
275
276 dw_pcie_dbi_ro_wr_en(pci);
277
278 val = readl(pci->dbi_base + offset + PCI_EXP_SLTCAP);
279 val &= ~PCI_EXP_SLTCAP_HPC;
280 writel(val, pci->dbi_base + offset + PCI_EXP_SLTCAP);
281
282 dw_pcie_dbi_ro_wr_dis(pci);
283 }
284
qcom_pcie_2_1_0_ltssm_enable(struct qcom_pcie * pcie)285 static void qcom_pcie_2_1_0_ltssm_enable(struct qcom_pcie *pcie)
286 {
287 u32 val;
288
289 /* enable link training */
290 val = readl(pcie->elbi + ELBI_SYS_CTRL);
291 val |= ELBI_SYS_CTRL_LT_ENABLE;
292 writel(val, pcie->elbi + ELBI_SYS_CTRL);
293 }
294
qcom_pcie_get_resources_2_1_0(struct qcom_pcie * pcie)295 static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie)
296 {
297 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
298 struct dw_pcie *pci = pcie->pci;
299 struct device *dev = pci->dev;
300 bool is_apq = of_device_is_compatible(dev->of_node, "qcom,pcie-apq8064");
301 int ret;
302
303 res->supplies[0].supply = "vdda";
304 res->supplies[1].supply = "vdda_phy";
305 res->supplies[2].supply = "vdda_refclk";
306 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies),
307 res->supplies);
308 if (ret)
309 return ret;
310
311 res->clks[0].id = "iface";
312 res->clks[1].id = "core";
313 res->clks[2].id = "phy";
314 res->clks[3].id = "aux";
315 res->clks[4].id = "ref";
316
317 /* iface, core, phy are required */
318 ret = devm_clk_bulk_get(dev, 3, res->clks);
319 if (ret < 0)
320 return ret;
321
322 /* aux, ref are optional */
323 ret = devm_clk_bulk_get_optional(dev, 2, res->clks + 3);
324 if (ret < 0)
325 return ret;
326
327 res->resets[0].id = "pci";
328 res->resets[1].id = "axi";
329 res->resets[2].id = "ahb";
330 res->resets[3].id = "por";
331 res->resets[4].id = "phy";
332 res->resets[5].id = "ext";
333
334 /* ext is optional on APQ8016 */
335 res->num_resets = is_apq ? 5 : 6;
336 ret = devm_reset_control_bulk_get_exclusive(dev, res->num_resets, res->resets);
337 if (ret < 0)
338 return ret;
339
340 return 0;
341 }
342
qcom_pcie_deinit_2_1_0(struct qcom_pcie * pcie)343 static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie)
344 {
345 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
346
347 clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks);
348 reset_control_bulk_assert(res->num_resets, res->resets);
349
350 writel(1, pcie->parf + PARF_PHY_CTRL);
351
352 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
353 }
354
qcom_pcie_init_2_1_0(struct qcom_pcie * pcie)355 static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
356 {
357 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
358 struct dw_pcie *pci = pcie->pci;
359 struct device *dev = pci->dev;
360 int ret;
361
362 /* reset the PCIe interface as uboot can leave it undefined state */
363 ret = reset_control_bulk_assert(res->num_resets, res->resets);
364 if (ret < 0) {
365 dev_err(dev, "cannot assert resets\n");
366 return ret;
367 }
368
369 ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies);
370 if (ret < 0) {
371 dev_err(dev, "cannot enable regulators\n");
372 return ret;
373 }
374
375 ret = reset_control_bulk_deassert(res->num_resets, res->resets);
376 if (ret < 0) {
377 dev_err(dev, "cannot deassert resets\n");
378 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
379 return ret;
380 }
381
382 return 0;
383 }
384
qcom_pcie_post_init_2_1_0(struct qcom_pcie * pcie)385 static int qcom_pcie_post_init_2_1_0(struct qcom_pcie *pcie)
386 {
387 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
388 struct dw_pcie *pci = pcie->pci;
389 struct device *dev = pci->dev;
390 struct device_node *node = dev->of_node;
391 u32 val;
392 int ret;
393
394 /* enable PCIe clocks and resets */
395 val = readl(pcie->parf + PARF_PHY_CTRL);
396 val &= ~PHY_TEST_PWR_DOWN;
397 writel(val, pcie->parf + PARF_PHY_CTRL);
398
399 ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks);
400 if (ret)
401 return ret;
402
403 if (of_device_is_compatible(node, "qcom,pcie-ipq8064") ||
404 of_device_is_compatible(node, "qcom,pcie-ipq8064-v2")) {
405 writel(PCS_DEEMPH_TX_DEEMPH_GEN1(24) |
406 PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(24) |
407 PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(34),
408 pcie->parf + PARF_PCS_DEEMPH);
409 writel(PCS_SWING_TX_SWING_FULL(120) |
410 PCS_SWING_TX_SWING_LOW(120),
411 pcie->parf + PARF_PCS_SWING);
412 writel(PHY_RX0_EQ(4), pcie->parf + PARF_CONFIG_BITS);
413 }
414
415 if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) {
416 /* set TX termination offset */
417 val = readl(pcie->parf + PARF_PHY_CTRL);
418 val &= ~PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK;
419 val |= PHY_CTRL_PHY_TX0_TERM_OFFSET(7);
420 writel(val, pcie->parf + PARF_PHY_CTRL);
421 }
422
423 /* enable external reference clock */
424 val = readl(pcie->parf + PARF_PHY_REFCLK);
425 /* USE_PAD is required only for ipq806x */
426 if (!of_device_is_compatible(node, "qcom,pcie-apq8064"))
427 val &= ~PHY_REFCLK_USE_PAD;
428 val |= PHY_REFCLK_SSP_EN;
429 writel(val, pcie->parf + PARF_PHY_REFCLK);
430
431 /* wait for clock acquisition */
432 usleep_range(1000, 1500);
433
434 /* Set the Max TLP size to 2K, instead of using default of 4K */
435 writel(CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K,
436 pci->dbi_base + AXI_MSTR_RESP_COMP_CTRL0);
437 writel(CFG_BRIDGE_SB_INIT,
438 pci->dbi_base + AXI_MSTR_RESP_COMP_CTRL1);
439
440 qcom_pcie_clear_hpc(pcie->pci);
441
442 return 0;
443 }
444
qcom_pcie_get_resources_1_0_0(struct qcom_pcie * pcie)445 static int qcom_pcie_get_resources_1_0_0(struct qcom_pcie *pcie)
446 {
447 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
448 struct dw_pcie *pci = pcie->pci;
449 struct device *dev = pci->dev;
450 int ret;
451
452 res->vdda = devm_regulator_get(dev, "vdda");
453 if (IS_ERR(res->vdda))
454 return PTR_ERR(res->vdda);
455
456 res->clks[0].id = "iface";
457 res->clks[1].id = "aux";
458 res->clks[2].id = "master_bus";
459 res->clks[3].id = "slave_bus";
460
461 ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks);
462 if (ret < 0)
463 return ret;
464
465 res->core = devm_reset_control_get_exclusive(dev, "core");
466 return PTR_ERR_OR_ZERO(res->core);
467 }
468
qcom_pcie_deinit_1_0_0(struct qcom_pcie * pcie)469 static void qcom_pcie_deinit_1_0_0(struct qcom_pcie *pcie)
470 {
471 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
472
473 reset_control_assert(res->core);
474 clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks);
475 regulator_disable(res->vdda);
476 }
477
qcom_pcie_init_1_0_0(struct qcom_pcie * pcie)478 static int qcom_pcie_init_1_0_0(struct qcom_pcie *pcie)
479 {
480 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
481 struct dw_pcie *pci = pcie->pci;
482 struct device *dev = pci->dev;
483 int ret;
484
485 ret = reset_control_deassert(res->core);
486 if (ret) {
487 dev_err(dev, "cannot deassert core reset\n");
488 return ret;
489 }
490
491 ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks);
492 if (ret) {
493 dev_err(dev, "cannot prepare/enable clocks\n");
494 goto err_assert_reset;
495 }
496
497 ret = regulator_enable(res->vdda);
498 if (ret) {
499 dev_err(dev, "cannot enable vdda regulator\n");
500 goto err_disable_clks;
501 }
502
503 return 0;
504
505 err_disable_clks:
506 clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks);
507 err_assert_reset:
508 reset_control_assert(res->core);
509
510 return ret;
511 }
512
qcom_pcie_post_init_1_0_0(struct qcom_pcie * pcie)513 static int qcom_pcie_post_init_1_0_0(struct qcom_pcie *pcie)
514 {
515 /* change DBI base address */
516 writel(0, pcie->parf + PARF_DBI_BASE_ADDR);
517
518 if (IS_ENABLED(CONFIG_PCI_MSI)) {
519 u32 val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT);
520
521 val |= EN;
522 writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT);
523 }
524
525 qcom_pcie_clear_hpc(pcie->pci);
526
527 return 0;
528 }
529
qcom_pcie_2_3_2_ltssm_enable(struct qcom_pcie * pcie)530 static void qcom_pcie_2_3_2_ltssm_enable(struct qcom_pcie *pcie)
531 {
532 u32 val;
533
534 /* enable link training */
535 val = readl(pcie->parf + PARF_LTSSM);
536 val |= LTSSM_EN;
537 writel(val, pcie->parf + PARF_LTSSM);
538 }
539
qcom_pcie_get_resources_2_3_2(struct qcom_pcie * pcie)540 static int qcom_pcie_get_resources_2_3_2(struct qcom_pcie *pcie)
541 {
542 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
543 struct dw_pcie *pci = pcie->pci;
544 struct device *dev = pci->dev;
545 int ret;
546
547 res->supplies[0].supply = "vdda";
548 res->supplies[1].supply = "vddpe-3v3";
549 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies),
550 res->supplies);
551 if (ret)
552 return ret;
553
554 res->clks[0].id = "aux";
555 res->clks[1].id = "cfg";
556 res->clks[2].id = "bus_master";
557 res->clks[3].id = "bus_slave";
558
559 ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks);
560 if (ret < 0)
561 return ret;
562
563 return 0;
564 }
565
qcom_pcie_deinit_2_3_2(struct qcom_pcie * pcie)566 static void qcom_pcie_deinit_2_3_2(struct qcom_pcie *pcie)
567 {
568 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
569
570 clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks);
571 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
572 }
573
qcom_pcie_init_2_3_2(struct qcom_pcie * pcie)574 static int qcom_pcie_init_2_3_2(struct qcom_pcie *pcie)
575 {
576 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
577 struct dw_pcie *pci = pcie->pci;
578 struct device *dev = pci->dev;
579 int ret;
580
581 ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies);
582 if (ret < 0) {
583 dev_err(dev, "cannot enable regulators\n");
584 return ret;
585 }
586
587 ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks);
588 if (ret) {
589 dev_err(dev, "cannot prepare/enable clocks\n");
590 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
591 return ret;
592 }
593
594 return 0;
595 }
596
qcom_pcie_post_init_2_3_2(struct qcom_pcie * pcie)597 static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *pcie)
598 {
599 u32 val;
600
601 /* enable PCIe clocks and resets */
602 val = readl(pcie->parf + PARF_PHY_CTRL);
603 val &= ~PHY_TEST_PWR_DOWN;
604 writel(val, pcie->parf + PARF_PHY_CTRL);
605
606 /* change DBI base address */
607 writel(0, pcie->parf + PARF_DBI_BASE_ADDR);
608
609 /* MAC PHY_POWERDOWN MUX DISABLE */
610 val = readl(pcie->parf + PARF_SYS_CTRL);
611 val &= ~MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN;
612 writel(val, pcie->parf + PARF_SYS_CTRL);
613
614 val = readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);
615 val |= BYPASS;
616 writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);
617
618 val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);
619 val |= EN;
620 writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);
621
622 qcom_pcie_clear_hpc(pcie->pci);
623
624 return 0;
625 }
626
qcom_pcie_get_resources_2_4_0(struct qcom_pcie * pcie)627 static int qcom_pcie_get_resources_2_4_0(struct qcom_pcie *pcie)
628 {
629 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
630 struct dw_pcie *pci = pcie->pci;
631 struct device *dev = pci->dev;
632 bool is_ipq = of_device_is_compatible(dev->of_node, "qcom,pcie-ipq4019");
633 int ret;
634
635 res->clks[0].id = "aux";
636 res->clks[1].id = "master_bus";
637 res->clks[2].id = "slave_bus";
638 res->clks[3].id = "iface";
639
640 /* qcom,pcie-ipq4019 is defined without "iface" */
641 res->num_clks = is_ipq ? 3 : 4;
642
643 ret = devm_clk_bulk_get(dev, res->num_clks, res->clks);
644 if (ret < 0)
645 return ret;
646
647 res->resets[0].id = "axi_m";
648 res->resets[1].id = "axi_s";
649 res->resets[2].id = "axi_m_sticky";
650 res->resets[3].id = "pipe_sticky";
651 res->resets[4].id = "pwr";
652 res->resets[5].id = "ahb";
653 res->resets[6].id = "pipe";
654 res->resets[7].id = "axi_m_vmid";
655 res->resets[8].id = "axi_s_xpu";
656 res->resets[9].id = "parf";
657 res->resets[10].id = "phy";
658 res->resets[11].id = "phy_ahb";
659
660 res->num_resets = is_ipq ? 12 : 6;
661
662 ret = devm_reset_control_bulk_get_exclusive(dev, res->num_resets, res->resets);
663 if (ret < 0)
664 return ret;
665
666 return 0;
667 }
668
qcom_pcie_deinit_2_4_0(struct qcom_pcie * pcie)669 static void qcom_pcie_deinit_2_4_0(struct qcom_pcie *pcie)
670 {
671 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
672
673 reset_control_bulk_assert(res->num_resets, res->resets);
674 clk_bulk_disable_unprepare(res->num_clks, res->clks);
675 }
676
qcom_pcie_init_2_4_0(struct qcom_pcie * pcie)677 static int qcom_pcie_init_2_4_0(struct qcom_pcie *pcie)
678 {
679 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
680 struct dw_pcie *pci = pcie->pci;
681 struct device *dev = pci->dev;
682 int ret;
683
684 ret = reset_control_bulk_assert(res->num_resets, res->resets);
685 if (ret < 0) {
686 dev_err(dev, "cannot assert resets\n");
687 return ret;
688 }
689
690 usleep_range(10000, 12000);
691
692 ret = reset_control_bulk_deassert(res->num_resets, res->resets);
693 if (ret < 0) {
694 dev_err(dev, "cannot deassert resets\n");
695 return ret;
696 }
697
698 usleep_range(10000, 12000);
699
700 ret = clk_bulk_prepare_enable(res->num_clks, res->clks);
701 if (ret) {
702 reset_control_bulk_assert(res->num_resets, res->resets);
703 return ret;
704 }
705
706 return 0;
707 }
708
qcom_pcie_get_resources_2_3_3(struct qcom_pcie * pcie)709 static int qcom_pcie_get_resources_2_3_3(struct qcom_pcie *pcie)
710 {
711 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
712 struct dw_pcie *pci = pcie->pci;
713 struct device *dev = pci->dev;
714 int ret;
715
716 res->clks[0].id = "iface";
717 res->clks[1].id = "axi_m";
718 res->clks[2].id = "axi_s";
719 res->clks[3].id = "ahb";
720 res->clks[4].id = "aux";
721
722 ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks);
723 if (ret < 0)
724 return ret;
725
726 res->rst[0].id = "axi_m";
727 res->rst[1].id = "axi_s";
728 res->rst[2].id = "pipe";
729 res->rst[3].id = "axi_m_sticky";
730 res->rst[4].id = "sticky";
731 res->rst[5].id = "ahb";
732 res->rst[6].id = "sleep";
733
734 ret = devm_reset_control_bulk_get_exclusive(dev, ARRAY_SIZE(res->rst), res->rst);
735 if (ret < 0)
736 return ret;
737
738 return 0;
739 }
740
qcom_pcie_deinit_2_3_3(struct qcom_pcie * pcie)741 static void qcom_pcie_deinit_2_3_3(struct qcom_pcie *pcie)
742 {
743 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
744
745 clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks);
746 }
747
qcom_pcie_init_2_3_3(struct qcom_pcie * pcie)748 static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie)
749 {
750 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
751 struct dw_pcie *pci = pcie->pci;
752 struct device *dev = pci->dev;
753 int ret;
754
755 ret = reset_control_bulk_assert(ARRAY_SIZE(res->rst), res->rst);
756 if (ret < 0) {
757 dev_err(dev, "cannot assert resets\n");
758 return ret;
759 }
760
761 usleep_range(2000, 2500);
762
763 ret = reset_control_bulk_deassert(ARRAY_SIZE(res->rst), res->rst);
764 if (ret < 0) {
765 dev_err(dev, "cannot deassert resets\n");
766 return ret;
767 }
768
769 /*
770 * Don't have a way to see if the reset has completed.
771 * Wait for some time.
772 */
773 usleep_range(2000, 2500);
774
775 ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks);
776 if (ret) {
777 dev_err(dev, "cannot prepare/enable clocks\n");
778 goto err_assert_resets;
779 }
780
781 return 0;
782
783 err_assert_resets:
784 /*
785 * Not checking for failure, will anyway return
786 * the original failure in 'ret'.
787 */
788 reset_control_bulk_assert(ARRAY_SIZE(res->rst), res->rst);
789
790 return ret;
791 }
792
qcom_pcie_post_init_2_3_3(struct qcom_pcie * pcie)793 static int qcom_pcie_post_init_2_3_3(struct qcom_pcie *pcie)
794 {
795 struct dw_pcie *pci = pcie->pci;
796 u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
797 u32 val;
798
799 writel(SLV_ADDR_SPACE_SZ, pcie->parf + PARF_SLV_ADDR_SPACE_SIZE);
800
801 val = readl(pcie->parf + PARF_PHY_CTRL);
802 val &= ~PHY_TEST_PWR_DOWN;
803 writel(val, pcie->parf + PARF_PHY_CTRL);
804
805 writel(0, pcie->parf + PARF_DBI_BASE_ADDR);
806
807 writel(MST_WAKEUP_EN | SLV_WAKEUP_EN | MSTR_ACLK_CGC_DIS
808 | SLV_ACLK_CGC_DIS | CORE_CLK_CGC_DIS |
809 AUX_PWR_DET | L23_CLK_RMV_DIS | L1_CLK_RMV_DIS,
810 pcie->parf + PARF_SYS_CTRL);
811 writel(0, pcie->parf + PARF_Q2A_FLUSH);
812
813 writel(PCI_COMMAND_MASTER, pci->dbi_base + PCI_COMMAND);
814
815 dw_pcie_dbi_ro_wr_en(pci);
816
817 writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
818
819 val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP);
820 val &= ~PCI_EXP_LNKCAP_ASPMS;
821 writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP);
822
823 writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset +
824 PCI_EXP_DEVCTL2);
825
826 dw_pcie_dbi_ro_wr_dis(pci);
827
828 return 0;
829 }
830
qcom_pcie_get_resources_2_7_0(struct qcom_pcie * pcie)831 static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie)
832 {
833 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
834 struct dw_pcie *pci = pcie->pci;
835 struct device *dev = pci->dev;
836 unsigned int num_clks, num_opt_clks;
837 unsigned int idx;
838 int ret;
839
840 res->rst = devm_reset_control_array_get_exclusive(dev);
841 if (IS_ERR(res->rst))
842 return PTR_ERR(res->rst);
843
844 res->supplies[0].supply = "vdda";
845 res->supplies[1].supply = "vddpe-3v3";
846 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies),
847 res->supplies);
848 if (ret)
849 return ret;
850
851 idx = 0;
852 res->clks[idx++].id = "aux";
853 res->clks[idx++].id = "cfg";
854 res->clks[idx++].id = "bus_master";
855 res->clks[idx++].id = "bus_slave";
856 res->clks[idx++].id = "slave_q2a";
857
858 num_clks = idx;
859
860 ret = devm_clk_bulk_get(dev, num_clks, res->clks);
861 if (ret < 0)
862 return ret;
863
864 res->clks[idx++].id = "tbu";
865 res->clks[idx++].id = "ddrss_sf_tbu";
866 res->clks[idx++].id = "aggre0";
867 res->clks[idx++].id = "aggre1";
868 res->clks[idx++].id = "noc_aggr";
869 res->clks[idx++].id = "noc_aggr_4";
870 res->clks[idx++].id = "noc_aggr_south_sf";
871 res->clks[idx++].id = "cnoc_qx";
872 res->clks[idx++].id = "sleep";
873 res->clks[idx++].id = "cnoc_sf_axi";
874
875 num_opt_clks = idx - num_clks;
876 res->num_clks = idx;
877
878 ret = devm_clk_bulk_get_optional(dev, num_opt_clks, res->clks + num_clks);
879 if (ret < 0)
880 return ret;
881
882 return 0;
883 }
884
qcom_pcie_init_2_7_0(struct qcom_pcie * pcie)885 static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)
886 {
887 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
888 struct dw_pcie *pci = pcie->pci;
889 struct device *dev = pci->dev;
890 u32 val;
891 int ret;
892
893 ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies);
894 if (ret < 0) {
895 dev_err(dev, "cannot enable regulators\n");
896 return ret;
897 }
898
899 ret = clk_bulk_prepare_enable(res->num_clks, res->clks);
900 if (ret < 0)
901 goto err_disable_regulators;
902
903 ret = reset_control_assert(res->rst);
904 if (ret) {
905 dev_err(dev, "reset assert failed (%d)\n", ret);
906 goto err_disable_clocks;
907 }
908
909 usleep_range(1000, 1500);
910
911 ret = reset_control_deassert(res->rst);
912 if (ret) {
913 dev_err(dev, "reset deassert failed (%d)\n", ret);
914 goto err_disable_clocks;
915 }
916
917 /* Wait for reset to complete, required on SM8450 */
918 usleep_range(1000, 1500);
919
920 /* configure PCIe to RC mode */
921 writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE);
922
923 /* enable PCIe clocks and resets */
924 val = readl(pcie->parf + PARF_PHY_CTRL);
925 val &= ~PHY_TEST_PWR_DOWN;
926 writel(val, pcie->parf + PARF_PHY_CTRL);
927
928 /* change DBI base address */
929 writel(0, pcie->parf + PARF_DBI_BASE_ADDR);
930
931 /* MAC PHY_POWERDOWN MUX DISABLE */
932 val = readl(pcie->parf + PARF_SYS_CTRL);
933 val &= ~MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN;
934 writel(val, pcie->parf + PARF_SYS_CTRL);
935
936 val = readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);
937 val |= BYPASS;
938 writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);
939
940 /* Enable L1 and L1SS */
941 val = readl(pcie->parf + PARF_PM_CTRL);
942 val &= ~REQ_NOT_ENTR_L1;
943 writel(val, pcie->parf + PARF_PM_CTRL);
944
945 val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);
946 val |= EN;
947 writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);
948
949 return 0;
950 err_disable_clocks:
951 clk_bulk_disable_unprepare(res->num_clks, res->clks);
952 err_disable_regulators:
953 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
954
955 return ret;
956 }
957
qcom_pcie_post_init_2_7_0(struct qcom_pcie * pcie)958 static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie)
959 {
960 qcom_pcie_clear_hpc(pcie->pci);
961
962 return 0;
963 }
964
qcom_pcie_deinit_2_7_0(struct qcom_pcie * pcie)965 static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie)
966 {
967 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
968
969 clk_bulk_disable_unprepare(res->num_clks, res->clks);
970
971 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
972 }
973
qcom_pcie_config_sid_1_9_0(struct qcom_pcie * pcie)974 static int qcom_pcie_config_sid_1_9_0(struct qcom_pcie *pcie)
975 {
976 /* iommu map structure */
977 struct {
978 u32 bdf;
979 u32 phandle;
980 u32 smmu_sid;
981 u32 smmu_sid_len;
982 } *map;
983 void __iomem *bdf_to_sid_base = pcie->parf + PARF_BDF_TO_SID_TABLE_N;
984 struct device *dev = pcie->pci->dev;
985 u8 qcom_pcie_crc8_table[CRC8_TABLE_SIZE];
986 int i, nr_map, size = 0;
987 u32 smmu_sid_base;
988
989 of_get_property(dev->of_node, "iommu-map", &size);
990 if (!size)
991 return 0;
992
993 map = kzalloc(size, GFP_KERNEL);
994 if (!map)
995 return -ENOMEM;
996
997 of_property_read_u32_array(dev->of_node, "iommu-map", (u32 *)map,
998 size / sizeof(u32));
999
1000 nr_map = size / (sizeof(*map));
1001
1002 crc8_populate_msb(qcom_pcie_crc8_table, QCOM_PCIE_CRC8_POLYNOMIAL);
1003
1004 /* Registers need to be zero out first */
1005 memset_io(bdf_to_sid_base, 0, CRC8_TABLE_SIZE * sizeof(u32));
1006
1007 /* Extract the SMMU SID base from the first entry of iommu-map */
1008 smmu_sid_base = map[0].smmu_sid;
1009
1010 /* Look for an available entry to hold the mapping */
1011 for (i = 0; i < nr_map; i++) {
1012 __be16 bdf_be = cpu_to_be16(map[i].bdf);
1013 u32 val;
1014 u8 hash;
1015
1016 hash = crc8(qcom_pcie_crc8_table, (u8 *)&bdf_be, sizeof(bdf_be), 0);
1017
1018 val = readl(bdf_to_sid_base + hash * sizeof(u32));
1019
1020 /* If the register is already populated, look for next available entry */
1021 while (val) {
1022 u8 current_hash = hash++;
1023 u8 next_mask = 0xff;
1024
1025 /* If NEXT field is NULL then update it with next hash */
1026 if (!(val & next_mask)) {
1027 val |= (u32)hash;
1028 writel(val, bdf_to_sid_base + current_hash * sizeof(u32));
1029 }
1030
1031 val = readl(bdf_to_sid_base + hash * sizeof(u32));
1032 }
1033
1034 /* BDF [31:16] | SID [15:8] | NEXT [7:0] */
1035 val = map[i].bdf << 16 | (map[i].smmu_sid - smmu_sid_base) << 8 | 0;
1036 writel(val, bdf_to_sid_base + hash * sizeof(u32));
1037 }
1038
1039 kfree(map);
1040
1041 return 0;
1042 }
1043
qcom_pcie_get_resources_2_9_0(struct qcom_pcie * pcie)1044 static int qcom_pcie_get_resources_2_9_0(struct qcom_pcie *pcie)
1045 {
1046 struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0;
1047 struct dw_pcie *pci = pcie->pci;
1048 struct device *dev = pci->dev;
1049 int ret;
1050
1051 res->clks[0].id = "iface";
1052 res->clks[1].id = "axi_m";
1053 res->clks[2].id = "axi_s";
1054 res->clks[3].id = "axi_bridge";
1055 res->clks[4].id = "rchng";
1056
1057 ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks);
1058 if (ret < 0)
1059 return ret;
1060
1061 res->rst = devm_reset_control_array_get_exclusive(dev);
1062 if (IS_ERR(res->rst))
1063 return PTR_ERR(res->rst);
1064
1065 return 0;
1066 }
1067
qcom_pcie_deinit_2_9_0(struct qcom_pcie * pcie)1068 static void qcom_pcie_deinit_2_9_0(struct qcom_pcie *pcie)
1069 {
1070 struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0;
1071
1072 clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks);
1073 }
1074
qcom_pcie_init_2_9_0(struct qcom_pcie * pcie)1075 static int qcom_pcie_init_2_9_0(struct qcom_pcie *pcie)
1076 {
1077 struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0;
1078 struct device *dev = pcie->pci->dev;
1079 int ret;
1080
1081 ret = reset_control_assert(res->rst);
1082 if (ret) {
1083 dev_err(dev, "reset assert failed (%d)\n", ret);
1084 return ret;
1085 }
1086
1087 /*
1088 * Delay periods before and after reset deassert are working values
1089 * from downstream Codeaurora kernel
1090 */
1091 usleep_range(2000, 2500);
1092
1093 ret = reset_control_deassert(res->rst);
1094 if (ret) {
1095 dev_err(dev, "reset deassert failed (%d)\n", ret);
1096 return ret;
1097 }
1098
1099 usleep_range(2000, 2500);
1100
1101 return clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks);
1102 }
1103
qcom_pcie_post_init_2_9_0(struct qcom_pcie * pcie)1104 static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie)
1105 {
1106 struct dw_pcie *pci = pcie->pci;
1107 u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
1108 u32 val;
1109 int i;
1110
1111 writel(SLV_ADDR_SPACE_SZ,
1112 pcie->parf + PARF_SLV_ADDR_SPACE_SIZE);
1113
1114 val = readl(pcie->parf + PARF_PHY_CTRL);
1115 val &= ~PHY_TEST_PWR_DOWN;
1116 writel(val, pcie->parf + PARF_PHY_CTRL);
1117
1118 writel(0, pcie->parf + PARF_DBI_BASE_ADDR);
1119
1120 writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE);
1121 writel(BYPASS | MSTR_AXI_CLK_EN | AHB_CLK_EN,
1122 pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);
1123 writel(GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS |
1124 GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL,
1125 pci->dbi_base + GEN3_RELATED_OFF);
1126
1127 writel(MST_WAKEUP_EN | SLV_WAKEUP_EN | MSTR_ACLK_CGC_DIS |
1128 SLV_ACLK_CGC_DIS | CORE_CLK_CGC_DIS |
1129 AUX_PWR_DET | L23_CLK_RMV_DIS | L1_CLK_RMV_DIS,
1130 pcie->parf + PARF_SYS_CTRL);
1131
1132 writel(0, pcie->parf + PARF_Q2A_FLUSH);
1133
1134 dw_pcie_dbi_ro_wr_en(pci);
1135
1136 writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
1137
1138 val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP);
1139 val &= ~PCI_EXP_LNKCAP_ASPMS;
1140 writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP);
1141
1142 writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset +
1143 PCI_EXP_DEVCTL2);
1144
1145 dw_pcie_dbi_ro_wr_dis(pci);
1146
1147 for (i = 0; i < 256; i++)
1148 writel(0, pcie->parf + PARF_BDF_TO_SID_TABLE_N + (4 * i));
1149
1150 return 0;
1151 }
1152
qcom_pcie_link_up(struct dw_pcie * pci)1153 static int qcom_pcie_link_up(struct dw_pcie *pci)
1154 {
1155 u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
1156 u16 val = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA);
1157
1158 return !!(val & PCI_EXP_LNKSTA_DLLLA);
1159 }
1160
qcom_pcie_host_init(struct dw_pcie_rp * pp)1161 static int qcom_pcie_host_init(struct dw_pcie_rp *pp)
1162 {
1163 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
1164 struct qcom_pcie *pcie = to_qcom_pcie(pci);
1165 int ret;
1166
1167 qcom_ep_reset_assert(pcie);
1168
1169 ret = pcie->cfg->ops->init(pcie);
1170 if (ret)
1171 return ret;
1172
1173 ret = phy_set_mode_ext(pcie->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_RC);
1174 if (ret)
1175 goto err_deinit;
1176
1177 ret = phy_power_on(pcie->phy);
1178 if (ret)
1179 goto err_deinit;
1180
1181 if (pcie->cfg->ops->post_init) {
1182 ret = pcie->cfg->ops->post_init(pcie);
1183 if (ret)
1184 goto err_disable_phy;
1185 }
1186
1187 qcom_ep_reset_deassert(pcie);
1188
1189 if (pcie->cfg->ops->config_sid) {
1190 ret = pcie->cfg->ops->config_sid(pcie);
1191 if (ret)
1192 goto err_assert_reset;
1193 }
1194
1195 return 0;
1196
1197 err_assert_reset:
1198 qcom_ep_reset_assert(pcie);
1199 err_disable_phy:
1200 phy_power_off(pcie->phy);
1201 err_deinit:
1202 pcie->cfg->ops->deinit(pcie);
1203
1204 return ret;
1205 }
1206
qcom_pcie_host_deinit(struct dw_pcie_rp * pp)1207 static void qcom_pcie_host_deinit(struct dw_pcie_rp *pp)
1208 {
1209 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
1210 struct qcom_pcie *pcie = to_qcom_pcie(pci);
1211
1212 qcom_ep_reset_assert(pcie);
1213 phy_power_off(pcie->phy);
1214 pcie->cfg->ops->deinit(pcie);
1215 }
1216
1217 static const struct dw_pcie_host_ops qcom_pcie_dw_ops = {
1218 .host_init = qcom_pcie_host_init,
1219 .host_deinit = qcom_pcie_host_deinit,
1220 };
1221
1222 /* Qcom IP rev.: 2.1.0 Synopsys IP rev.: 4.01a */
1223 static const struct qcom_pcie_ops ops_2_1_0 = {
1224 .get_resources = qcom_pcie_get_resources_2_1_0,
1225 .init = qcom_pcie_init_2_1_0,
1226 .post_init = qcom_pcie_post_init_2_1_0,
1227 .deinit = qcom_pcie_deinit_2_1_0,
1228 .ltssm_enable = qcom_pcie_2_1_0_ltssm_enable,
1229 };
1230
1231 /* Qcom IP rev.: 1.0.0 Synopsys IP rev.: 4.11a */
1232 static const struct qcom_pcie_ops ops_1_0_0 = {
1233 .get_resources = qcom_pcie_get_resources_1_0_0,
1234 .init = qcom_pcie_init_1_0_0,
1235 .post_init = qcom_pcie_post_init_1_0_0,
1236 .deinit = qcom_pcie_deinit_1_0_0,
1237 .ltssm_enable = qcom_pcie_2_1_0_ltssm_enable,
1238 };
1239
1240 /* Qcom IP rev.: 2.3.2 Synopsys IP rev.: 4.21a */
1241 static const struct qcom_pcie_ops ops_2_3_2 = {
1242 .get_resources = qcom_pcie_get_resources_2_3_2,
1243 .init = qcom_pcie_init_2_3_2,
1244 .post_init = qcom_pcie_post_init_2_3_2,
1245 .deinit = qcom_pcie_deinit_2_3_2,
1246 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1247 };
1248
1249 /* Qcom IP rev.: 2.4.0 Synopsys IP rev.: 4.20a */
1250 static const struct qcom_pcie_ops ops_2_4_0 = {
1251 .get_resources = qcom_pcie_get_resources_2_4_0,
1252 .init = qcom_pcie_init_2_4_0,
1253 .post_init = qcom_pcie_post_init_2_3_2,
1254 .deinit = qcom_pcie_deinit_2_4_0,
1255 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1256 };
1257
1258 /* Qcom IP rev.: 2.3.3 Synopsys IP rev.: 4.30a */
1259 static const struct qcom_pcie_ops ops_2_3_3 = {
1260 .get_resources = qcom_pcie_get_resources_2_3_3,
1261 .init = qcom_pcie_init_2_3_3,
1262 .post_init = qcom_pcie_post_init_2_3_3,
1263 .deinit = qcom_pcie_deinit_2_3_3,
1264 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1265 };
1266
1267 /* Qcom IP rev.: 2.7.0 Synopsys IP rev.: 4.30a */
1268 static const struct qcom_pcie_ops ops_2_7_0 = {
1269 .get_resources = qcom_pcie_get_resources_2_7_0,
1270 .init = qcom_pcie_init_2_7_0,
1271 .post_init = qcom_pcie_post_init_2_7_0,
1272 .deinit = qcom_pcie_deinit_2_7_0,
1273 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1274 };
1275
1276 /* Qcom IP rev.: 1.9.0 */
1277 static const struct qcom_pcie_ops ops_1_9_0 = {
1278 .get_resources = qcom_pcie_get_resources_2_7_0,
1279 .init = qcom_pcie_init_2_7_0,
1280 .post_init = qcom_pcie_post_init_2_7_0,
1281 .deinit = qcom_pcie_deinit_2_7_0,
1282 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1283 .config_sid = qcom_pcie_config_sid_1_9_0,
1284 };
1285
1286 /* Qcom IP rev.: 2.9.0 Synopsys IP rev.: 5.00a */
1287 static const struct qcom_pcie_ops ops_2_9_0 = {
1288 .get_resources = qcom_pcie_get_resources_2_9_0,
1289 .init = qcom_pcie_init_2_9_0,
1290 .post_init = qcom_pcie_post_init_2_9_0,
1291 .deinit = qcom_pcie_deinit_2_9_0,
1292 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1293 };
1294
1295 static const struct qcom_pcie_cfg cfg_1_0_0 = {
1296 .ops = &ops_1_0_0,
1297 };
1298
1299 static const struct qcom_pcie_cfg cfg_1_9_0 = {
1300 .ops = &ops_1_9_0,
1301 };
1302
1303 static const struct qcom_pcie_cfg cfg_2_1_0 = {
1304 .ops = &ops_2_1_0,
1305 };
1306
1307 static const struct qcom_pcie_cfg cfg_2_3_2 = {
1308 .ops = &ops_2_3_2,
1309 };
1310
1311 static const struct qcom_pcie_cfg cfg_2_3_3 = {
1312 .ops = &ops_2_3_3,
1313 };
1314
1315 static const struct qcom_pcie_cfg cfg_2_4_0 = {
1316 .ops = &ops_2_4_0,
1317 };
1318
1319 static const struct qcom_pcie_cfg cfg_2_7_0 = {
1320 .ops = &ops_2_7_0,
1321 };
1322
1323 static const struct qcom_pcie_cfg cfg_2_9_0 = {
1324 .ops = &ops_2_9_0,
1325 };
1326
1327 static const struct dw_pcie_ops dw_pcie_ops = {
1328 .link_up = qcom_pcie_link_up,
1329 .start_link = qcom_pcie_start_link,
1330 };
1331
qcom_pcie_icc_init(struct qcom_pcie * pcie)1332 static int qcom_pcie_icc_init(struct qcom_pcie *pcie)
1333 {
1334 struct dw_pcie *pci = pcie->pci;
1335 int ret;
1336
1337 pcie->icc_mem = devm_of_icc_get(pci->dev, "pcie-mem");
1338 if (IS_ERR(pcie->icc_mem))
1339 return PTR_ERR(pcie->icc_mem);
1340
1341 /*
1342 * Some Qualcomm platforms require interconnect bandwidth constraints
1343 * to be set before enabling interconnect clocks.
1344 *
1345 * Set an initial peak bandwidth corresponding to single-lane Gen 1
1346 * for the pcie-mem path.
1347 */
1348 ret = icc_set_bw(pcie->icc_mem, 0, MBps_to_icc(250));
1349 if (ret) {
1350 dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n",
1351 ret);
1352 return ret;
1353 }
1354
1355 return 0;
1356 }
1357
qcom_pcie_icc_update(struct qcom_pcie * pcie)1358 static void qcom_pcie_icc_update(struct qcom_pcie *pcie)
1359 {
1360 struct dw_pcie *pci = pcie->pci;
1361 u32 offset, status, bw;
1362 int speed, width;
1363 int ret;
1364
1365 if (!pcie->icc_mem)
1366 return;
1367
1368 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
1369 status = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA);
1370
1371 /* Only update constraints if link is up. */
1372 if (!(status & PCI_EXP_LNKSTA_DLLLA))
1373 return;
1374
1375 speed = FIELD_GET(PCI_EXP_LNKSTA_CLS, status);
1376 width = FIELD_GET(PCI_EXP_LNKSTA_NLW, status);
1377
1378 switch (speed) {
1379 case 1:
1380 bw = MBps_to_icc(250);
1381 break;
1382 case 2:
1383 bw = MBps_to_icc(500);
1384 break;
1385 default:
1386 WARN_ON_ONCE(1);
1387 fallthrough;
1388 case 3:
1389 bw = MBps_to_icc(985);
1390 break;
1391 }
1392
1393 ret = icc_set_bw(pcie->icc_mem, 0, width * bw);
1394 if (ret) {
1395 dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n",
1396 ret);
1397 }
1398 }
1399
qcom_pcie_link_transition_count(struct seq_file * s,void * data)1400 static int qcom_pcie_link_transition_count(struct seq_file *s, void *data)
1401 {
1402 struct qcom_pcie *pcie = (struct qcom_pcie *)dev_get_drvdata(s->private);
1403
1404 seq_printf(s, "L0s transition count: %u\n",
1405 readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_PM_LINKST_IN_L0S));
1406
1407 seq_printf(s, "L1 transition count: %u\n",
1408 readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_PM_LINKST_IN_L1));
1409
1410 seq_printf(s, "L1.1 transition count: %u\n",
1411 readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1));
1412
1413 seq_printf(s, "L1.2 transition count: %u\n",
1414 readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2));
1415
1416 seq_printf(s, "L2 transition count: %u\n",
1417 readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_PM_LINKST_IN_L2));
1418
1419 return 0;
1420 }
1421
qcom_pcie_init_debugfs(struct qcom_pcie * pcie)1422 static void qcom_pcie_init_debugfs(struct qcom_pcie *pcie)
1423 {
1424 struct dw_pcie *pci = pcie->pci;
1425 struct device *dev = pci->dev;
1426 char *name;
1427
1428 name = devm_kasprintf(dev, GFP_KERNEL, "%pOFP", dev->of_node);
1429 if (!name)
1430 return;
1431
1432 pcie->debugfs = debugfs_create_dir(name, NULL);
1433 debugfs_create_devm_seqfile(dev, "link_transition_count", pcie->debugfs,
1434 qcom_pcie_link_transition_count);
1435 }
1436
qcom_pcie_probe(struct platform_device * pdev)1437 static int qcom_pcie_probe(struct platform_device *pdev)
1438 {
1439 const struct qcom_pcie_cfg *pcie_cfg;
1440 struct device *dev = &pdev->dev;
1441 struct qcom_pcie *pcie;
1442 struct dw_pcie_rp *pp;
1443 struct resource *res;
1444 struct dw_pcie *pci;
1445 int ret;
1446
1447 pcie_cfg = of_device_get_match_data(dev);
1448 if (!pcie_cfg || !pcie_cfg->ops) {
1449 dev_err(dev, "Invalid platform data\n");
1450 return -EINVAL;
1451 }
1452
1453 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
1454 if (!pcie)
1455 return -ENOMEM;
1456
1457 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
1458 if (!pci)
1459 return -ENOMEM;
1460
1461 pm_runtime_enable(dev);
1462 ret = pm_runtime_get_sync(dev);
1463 if (ret < 0)
1464 goto err_pm_runtime_put;
1465
1466 pci->dev = dev;
1467 pci->ops = &dw_pcie_ops;
1468 pp = &pci->pp;
1469
1470 pcie->pci = pci;
1471
1472 pcie->cfg = pcie_cfg;
1473
1474 pcie->reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_HIGH);
1475 if (IS_ERR(pcie->reset)) {
1476 ret = PTR_ERR(pcie->reset);
1477 goto err_pm_runtime_put;
1478 }
1479
1480 pcie->parf = devm_platform_ioremap_resource_byname(pdev, "parf");
1481 if (IS_ERR(pcie->parf)) {
1482 ret = PTR_ERR(pcie->parf);
1483 goto err_pm_runtime_put;
1484 }
1485
1486 pcie->elbi = devm_platform_ioremap_resource_byname(pdev, "elbi");
1487 if (IS_ERR(pcie->elbi)) {
1488 ret = PTR_ERR(pcie->elbi);
1489 goto err_pm_runtime_put;
1490 }
1491
1492 /* MHI region is optional */
1493 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mhi");
1494 if (res) {
1495 pcie->mhi = devm_ioremap_resource(dev, res);
1496 if (IS_ERR(pcie->mhi)) {
1497 ret = PTR_ERR(pcie->mhi);
1498 goto err_pm_runtime_put;
1499 }
1500 }
1501
1502 pcie->phy = devm_phy_optional_get(dev, "pciephy");
1503 if (IS_ERR(pcie->phy)) {
1504 ret = PTR_ERR(pcie->phy);
1505 goto err_pm_runtime_put;
1506 }
1507
1508 ret = qcom_pcie_icc_init(pcie);
1509 if (ret)
1510 goto err_pm_runtime_put;
1511
1512 ret = pcie->cfg->ops->get_resources(pcie);
1513 if (ret)
1514 goto err_pm_runtime_put;
1515
1516 pp->ops = &qcom_pcie_dw_ops;
1517
1518 ret = phy_init(pcie->phy);
1519 if (ret)
1520 goto err_pm_runtime_put;
1521
1522 platform_set_drvdata(pdev, pcie);
1523
1524 ret = dw_pcie_host_init(pp);
1525 if (ret) {
1526 dev_err(dev, "cannot initialize host\n");
1527 goto err_phy_exit;
1528 }
1529
1530 qcom_pcie_icc_update(pcie);
1531
1532 if (pcie->mhi)
1533 qcom_pcie_init_debugfs(pcie);
1534
1535 return 0;
1536
1537 err_phy_exit:
1538 phy_exit(pcie->phy);
1539 err_pm_runtime_put:
1540 pm_runtime_put(dev);
1541 pm_runtime_disable(dev);
1542
1543 return ret;
1544 }
1545
qcom_pcie_suspend_noirq(struct device * dev)1546 static int qcom_pcie_suspend_noirq(struct device *dev)
1547 {
1548 struct qcom_pcie *pcie = dev_get_drvdata(dev);
1549 int ret;
1550
1551 /*
1552 * Set minimum bandwidth required to keep data path functional during
1553 * suspend.
1554 */
1555 ret = icc_set_bw(pcie->icc_mem, 0, kBps_to_icc(1));
1556 if (ret) {
1557 dev_err(dev, "Failed to set interconnect bandwidth: %d\n", ret);
1558 return ret;
1559 }
1560
1561 /*
1562 * Turn OFF the resources only for controllers without active PCIe
1563 * devices. For controllers with active devices, the resources are kept
1564 * ON and the link is expected to be in L0/L1 (sub)states.
1565 *
1566 * Turning OFF the resources for controllers with active PCIe devices
1567 * will trigger access violation during the end of the suspend cycle,
1568 * as kernel tries to access the PCIe devices config space for masking
1569 * MSIs.
1570 *
1571 * Also, it is not desirable to put the link into L2/L3 state as that
1572 * implies VDD supply will be removed and the devices may go into
1573 * powerdown state. This will affect the lifetime of the storage devices
1574 * like NVMe.
1575 */
1576 if (!dw_pcie_link_up(pcie->pci)) {
1577 qcom_pcie_host_deinit(&pcie->pci->pp);
1578 pcie->suspended = true;
1579 }
1580
1581 return 0;
1582 }
1583
qcom_pcie_resume_noirq(struct device * dev)1584 static int qcom_pcie_resume_noirq(struct device *dev)
1585 {
1586 struct qcom_pcie *pcie = dev_get_drvdata(dev);
1587 int ret;
1588
1589 if (pcie->suspended) {
1590 ret = qcom_pcie_host_init(&pcie->pci->pp);
1591 if (ret)
1592 return ret;
1593
1594 pcie->suspended = false;
1595 }
1596
1597 qcom_pcie_icc_update(pcie);
1598
1599 return 0;
1600 }
1601
1602 static const struct of_device_id qcom_pcie_match[] = {
1603 { .compatible = "qcom,pcie-apq8064", .data = &cfg_2_1_0 },
1604 { .compatible = "qcom,pcie-apq8084", .data = &cfg_1_0_0 },
1605 { .compatible = "qcom,pcie-ipq4019", .data = &cfg_2_4_0 },
1606 { .compatible = "qcom,pcie-ipq6018", .data = &cfg_2_9_0 },
1607 { .compatible = "qcom,pcie-ipq8064", .data = &cfg_2_1_0 },
1608 { .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 },
1609 { .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 },
1610 { .compatible = "qcom,pcie-ipq8074-gen3", .data = &cfg_2_9_0 },
1611 { .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 },
1612 { .compatible = "qcom,pcie-qcs404", .data = &cfg_2_4_0 },
1613 { .compatible = "qcom,pcie-sa8540p", .data = &cfg_1_9_0 },
1614 { .compatible = "qcom,pcie-sa8775p", .data = &cfg_1_9_0},
1615 { .compatible = "qcom,pcie-sc7280", .data = &cfg_1_9_0 },
1616 { .compatible = "qcom,pcie-sc8180x", .data = &cfg_1_9_0 },
1617 { .compatible = "qcom,pcie-sc8280xp", .data = &cfg_1_9_0 },
1618 { .compatible = "qcom,pcie-sdm845", .data = &cfg_2_7_0 },
1619 { .compatible = "qcom,pcie-sdx55", .data = &cfg_1_9_0 },
1620 { .compatible = "qcom,pcie-sm8150", .data = &cfg_1_9_0 },
1621 { .compatible = "qcom,pcie-sm8250", .data = &cfg_1_9_0 },
1622 { .compatible = "qcom,pcie-sm8350", .data = &cfg_1_9_0 },
1623 { .compatible = "qcom,pcie-sm8450-pcie0", .data = &cfg_1_9_0 },
1624 { .compatible = "qcom,pcie-sm8450-pcie1", .data = &cfg_1_9_0 },
1625 { .compatible = "qcom,pcie-sm8550", .data = &cfg_1_9_0 },
1626 { }
1627 };
1628
qcom_fixup_class(struct pci_dev * dev)1629 static void qcom_fixup_class(struct pci_dev *dev)
1630 {
1631 dev->class = PCI_CLASS_BRIDGE_PCI_NORMAL;
1632 }
1633 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0101, qcom_fixup_class);
1634 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0104, qcom_fixup_class);
1635 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0106, qcom_fixup_class);
1636 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0107, qcom_fixup_class);
1637 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0302, qcom_fixup_class);
1638 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x1000, qcom_fixup_class);
1639 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x1001, qcom_fixup_class);
1640
1641 static const struct dev_pm_ops qcom_pcie_pm_ops = {
1642 NOIRQ_SYSTEM_SLEEP_PM_OPS(qcom_pcie_suspend_noirq, qcom_pcie_resume_noirq)
1643 };
1644
1645 static struct platform_driver qcom_pcie_driver = {
1646 .probe = qcom_pcie_probe,
1647 .driver = {
1648 .name = "qcom-pcie",
1649 .suppress_bind_attrs = true,
1650 .of_match_table = qcom_pcie_match,
1651 .pm = &qcom_pcie_pm_ops,
1652 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1653 },
1654 };
1655 builtin_platform_driver(qcom_pcie_driver);
1656