1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * This file is part of wl1271
4  *
5  * Copyright (C) 1998-2009 Texas Instruments. All rights reserved.
6  * Copyright (C) 2008-2010 Nokia Corporation
7  *
8  * Contact: Luciano Coelho <luciano.coelho@nokia.com>
9  */
10 
11 #ifndef __ACX_H__
12 #define __ACX_H__
13 
14 #include "wlcore.h"
15 #include "cmd.h"
16 
17 /*************************************************************************
18 
19     Host Interrupt Register (WiLink -> Host)
20 
21 **************************************************************************/
22 /* HW Initiated interrupt Watchdog timer expiration */
23 #define WL1271_ACX_INTR_WATCHDOG           BIT(0)
24 /* Init sequence is done (masked interrupt, detection through polling only ) */
25 #define WL1271_ACX_INTR_INIT_COMPLETE      BIT(1)
26 /* Event was entered to Event MBOX #A*/
27 #define WL1271_ACX_INTR_EVENT_A            BIT(2)
28 /* Event was entered to Event MBOX #B*/
29 #define WL1271_ACX_INTR_EVENT_B            BIT(3)
30 /* Command processing completion*/
31 #define WL1271_ACX_INTR_CMD_COMPLETE       BIT(4)
32 /* Signaling the host on HW wakeup */
33 #define WL1271_ACX_INTR_HW_AVAILABLE       BIT(5)
34 /* The MISC bit is used for aggregation of RX, TxComplete and TX rate update */
35 #define WL1271_ACX_INTR_DATA               BIT(6)
36 /* Trace message on MBOX #A */
37 #define WL1271_ACX_INTR_TRACE_A            BIT(7)
38 /* Trace message on MBOX #B */
39 #define WL1271_ACX_INTR_TRACE_B            BIT(8)
40 /* SW FW Initiated interrupt Watchdog timer expiration */
41 #define WL1271_ACX_SW_INTR_WATCHDOG        BIT(9)
42 
43 #define WL1271_ACX_INTR_ALL             0xFFFFFFFF
44 
45 /* all possible interrupts - only appropriate ones will be masked in */
46 #define WLCORE_ALL_INTR_MASK		(WL1271_ACX_INTR_WATCHDOG     | \
47 					WL1271_ACX_INTR_EVENT_A       | \
48 					WL1271_ACX_INTR_EVENT_B       | \
49 					WL1271_ACX_INTR_HW_AVAILABLE  | \
50 					WL1271_ACX_INTR_DATA          | \
51 					WL1271_ACX_SW_INTR_WATCHDOG)
52 
53 /* Target's information element */
54 struct acx_header {
55 	struct wl1271_cmd_header cmd;
56 
57 	/* acx (or information element) header */
58 	__le16 id;
59 
60 	/* payload length (not including headers */
61 	__le16 len;
62 } __packed;
63 
64 struct acx_error_counter {
65 	struct acx_header header;
66 
67 	/* The number of PLCP errors since the last time this */
68 	/* information element was interrogated. This field is */
69 	/* automatically cleared when it is interrogated.*/
70 	__le32 PLCP_error;
71 
72 	/* The number of FCS errors since the last time this */
73 	/* information element was interrogated. This field is */
74 	/* automatically cleared when it is interrogated.*/
75 	__le32 FCS_error;
76 
77 	/* The number of MPDUs without PLCP header errors received*/
78 	/* since the last time this information element was interrogated. */
79 	/* This field is automatically cleared when it is interrogated.*/
80 	__le32 valid_frame;
81 
82 	/* the number of missed sequence numbers in the squentially */
83 	/* values of frames seq numbers */
84 	__le32 seq_num_miss;
85 } __packed;
86 
87 enum wl12xx_role {
88 	WL1271_ROLE_STA = 0,
89 	WL1271_ROLE_IBSS,
90 	WL1271_ROLE_AP,
91 	WL1271_ROLE_DEVICE,
92 	WL1271_ROLE_P2P_CL,
93 	WL1271_ROLE_P2P_GO,
94 	WL1271_ROLE_MESH_POINT,
95 
96 	WL12XX_INVALID_ROLE_TYPE = 0xff
97 };
98 
99 enum wl1271_psm_mode {
100 	/* Active mode */
101 	WL1271_PSM_CAM = 0,
102 
103 	/* Power save mode */
104 	WL1271_PSM_PS = 1,
105 
106 	/* Extreme low power */
107 	WL1271_PSM_ELP = 2,
108 
109 	WL1271_PSM_MAX = WL1271_PSM_ELP,
110 
111 	/* illegal out of band value of PSM mode */
112 	WL1271_PSM_ILLEGAL = 0xff
113 };
114 
115 struct acx_sleep_auth {
116 	struct acx_header header;
117 
118 	/* The sleep level authorization of the device. */
119 	/* 0 - Always active*/
120 	/* 1 - Power down mode: light / fast sleep*/
121 	/* 2 - ELP mode: Deep / Max sleep*/
122 	u8  sleep_auth;
123 	u8  padding[3];
124 } __packed;
125 
126 enum {
127 	HOSTIF_PCI_MASTER_HOST_INDIRECT,
128 	HOSTIF_PCI_MASTER_HOST_DIRECT,
129 	HOSTIF_SLAVE,
130 	HOSTIF_PKT_RING,
131 	HOSTIF_DONTCARE = 0xFF
132 };
133 
134 #define DEFAULT_UCAST_PRIORITY          0
135 #define DEFAULT_RX_Q_PRIORITY           0
136 #define DEFAULT_RXQ_PRIORITY            0 /* low 0 .. 15 high  */
137 #define DEFAULT_RXQ_TYPE                0x07    /* All frames, Data/Ctrl/Mgmt */
138 #define TRACE_BUFFER_MAX_SIZE           256
139 
140 #define  DP_RX_PACKET_RING_CHUNK_SIZE 1600
141 #define  DP_TX_PACKET_RING_CHUNK_SIZE 1600
142 #define  DP_RX_PACKET_RING_CHUNK_NUM 2
143 #define  DP_TX_PACKET_RING_CHUNK_NUM 2
144 #define  DP_TX_COMPLETE_TIME_OUT 20
145 
146 #define TX_MSDU_LIFETIME_MIN       0
147 #define TX_MSDU_LIFETIME_MAX       3000
148 #define TX_MSDU_LIFETIME_DEF       512
149 #define RX_MSDU_LIFETIME_MIN       0
150 #define RX_MSDU_LIFETIME_MAX       0xFFFFFFFF
151 #define RX_MSDU_LIFETIME_DEF       512000
152 
153 struct acx_rx_msdu_lifetime {
154 	struct acx_header header;
155 
156 	/*
157 	 * The maximum amount of time, in TU, before the
158 	 * firmware discards the MSDU.
159 	 */
160 	__le32 lifetime;
161 } __packed;
162 
163 enum acx_slot_type {
164 	SLOT_TIME_LONG = 0,
165 	SLOT_TIME_SHORT = 1,
166 	DEFAULT_SLOT_TIME = SLOT_TIME_SHORT,
167 	MAX_SLOT_TIMES = 0xFF
168 };
169 
170 #define STATION_WONE_INDEX 0
171 
172 struct acx_slot {
173 	struct acx_header header;
174 
175 	u8 role_id;
176 	u8 wone_index; /* Reserved */
177 	u8 slot_time;
178 	u8 reserved[5];
179 } __packed;
180 
181 
182 #define ACX_MC_ADDRESS_GROUP_MAX	(8)
183 #define ADDRESS_GROUP_MAX_LEN	        (ETH_ALEN * ACX_MC_ADDRESS_GROUP_MAX)
184 
185 struct acx_dot11_grp_addr_tbl {
186 	struct acx_header header;
187 
188 	u8 role_id;
189 	u8 enabled;
190 	u8 num_groups;
191 	u8 pad[1];
192 	u8 mac_table[ADDRESS_GROUP_MAX_LEN];
193 } __packed;
194 
195 struct acx_rx_timeout {
196 	struct acx_header header;
197 
198 	u8 role_id;
199 	u8 reserved;
200 	__le16 ps_poll_timeout;
201 	__le16 upsd_timeout;
202 	u8 padding[2];
203 } __packed;
204 
205 struct acx_rts_threshold {
206 	struct acx_header header;
207 
208 	u8 role_id;
209 	u8 reserved;
210 	__le16 threshold;
211 } __packed;
212 
213 struct acx_beacon_filter_option {
214 	struct acx_header header;
215 
216 	u8 role_id;
217 	u8 enable;
218 	/*
219 	 * The number of beacons without the unicast TIM
220 	 * bit set that the firmware buffers before
221 	 * signaling the host about ready frames.
222 	 * When set to 0 and the filter is enabled, beacons
223 	 * without the unicast TIM bit set are dropped.
224 	 */
225 	u8 max_num_beacons;
226 	u8 pad[1];
227 } __packed;
228 
229 /*
230  * ACXBeaconFilterEntry (not 221)
231  * Byte Offset     Size (Bytes)    Definition
232  * ===========     ============    ==========
233  * 0               1               IE identifier
234  * 1               1               Treatment bit mask
235  *
236  * ACXBeaconFilterEntry (221)
237  * Byte Offset     Size (Bytes)    Definition
238  * ===========     ============    ==========
239  * 0               1               IE identifier
240  * 1               1               Treatment bit mask
241  * 2               3               OUI
242  * 5               1               Type
243  * 6               2               Version
244  *
245  *
246  * Treatment bit mask - The information element handling:
247  * bit 0 - The information element is compared and transferred
248  * in case of change.
249  * bit 1 - The information element is transferred to the host
250  * with each appearance or disappearance.
251  * Note that both bits can be set at the same time.
252  */
253 #define	BEACON_FILTER_TABLE_MAX_IE_NUM		       (32)
254 #define BEACON_FILTER_TABLE_MAX_VENDOR_SPECIFIC_IE_NUM (6)
255 #define BEACON_FILTER_TABLE_IE_ENTRY_SIZE	       (2)
256 #define BEACON_FILTER_TABLE_EXTRA_VENDOR_SPECIFIC_IE_SIZE (6)
257 #define BEACON_FILTER_TABLE_MAX_SIZE ((BEACON_FILTER_TABLE_MAX_IE_NUM * \
258 			    BEACON_FILTER_TABLE_IE_ENTRY_SIZE) + \
259 			   (BEACON_FILTER_TABLE_MAX_VENDOR_SPECIFIC_IE_NUM * \
260 			    BEACON_FILTER_TABLE_EXTRA_VENDOR_SPECIFIC_IE_SIZE))
261 
262 struct acx_beacon_filter_ie_table {
263 	struct acx_header header;
264 
265 	u8 role_id;
266 	u8 num_ie;
267 	u8 pad[2];
268 	u8 table[BEACON_FILTER_TABLE_MAX_SIZE];
269 } __packed;
270 
271 struct acx_conn_monit_params {
272        struct acx_header header;
273 
274 	   u8 role_id;
275 	   u8 padding[3];
276        __le32 synch_fail_thold; /* number of beacons missed */
277        __le32 bss_lose_timeout; /* number of TU's from synch fail */
278 } __packed;
279 
280 struct acx_bt_wlan_coex {
281 	struct acx_header header;
282 
283 	u8 enable;
284 	u8 pad[3];
285 } __packed;
286 
287 struct acx_bt_wlan_coex_param {
288 	struct acx_header header;
289 
290 	__le32 params[WLCORE_CONF_SG_PARAMS_MAX];
291 	u8 param_idx;
292 	u8 padding[3];
293 } __packed;
294 
295 struct acx_dco_itrim_params {
296 	struct acx_header header;
297 
298 	u8 enable;
299 	u8 padding[3];
300 	__le32 timeout;
301 } __packed;
302 
303 struct acx_energy_detection {
304 	struct acx_header header;
305 
306 	/* The RX Clear Channel Assessment threshold in the PHY */
307 	__le16 rx_cca_threshold;
308 	u8 tx_energy_detection;
309 	u8 pad;
310 } __packed;
311 
312 struct acx_beacon_broadcast {
313 	struct acx_header header;
314 
315 	u8 role_id;
316 	/* Enables receiving of broadcast packets in PS mode */
317 	u8 rx_broadcast_in_ps;
318 
319 	__le16 beacon_rx_timeout;
320 	__le16 broadcast_timeout;
321 
322 	/* Consecutive PS Poll failures before updating the host */
323 	u8 ps_poll_threshold;
324 	u8 pad[1];
325 } __packed;
326 
327 struct acx_event_mask {
328 	struct acx_header header;
329 
330 	__le32 event_mask;
331 	__le32 high_event_mask; /* Unused */
332 } __packed;
333 
334 #define SCAN_PASSIVE		BIT(0)
335 #define SCAN_5GHZ_BAND		BIT(1)
336 #define SCAN_TRIGGERED		BIT(2)
337 #define SCAN_PRIORITY_HIGH	BIT(3)
338 
339 /* When set, disable HW encryption */
340 #define DF_ENCRYPTION_DISABLE      0x01
341 #define DF_SNIFF_MODE_ENABLE       0x80
342 
343 struct acx_feature_config {
344 	struct acx_header header;
345 
346 	u8 role_id;
347 	u8 padding[3];
348 	__le32 options;
349 	__le32 data_flow_options;
350 } __packed;
351 
352 struct acx_current_tx_power {
353 	struct acx_header header;
354 
355 	u8  role_id;
356 	u8  current_tx_power;
357 	u8  padding[2];
358 } __packed;
359 
360 struct acx_wake_up_condition {
361 	struct acx_header header;
362 
363 	u8 role_id;
364 	u8 wake_up_event; /* Only one bit can be set */
365 	u8 listen_interval;
366 	u8 pad[1];
367 } __packed;
368 
369 struct acx_aid {
370 	struct acx_header header;
371 
372 	/*
373 	 * To be set when associated with an AP.
374 	 */
375 	u8 role_id;
376 	u8 reserved;
377 	__le16 aid;
378 } __packed;
379 
380 enum acx_preamble_type {
381 	ACX_PREAMBLE_LONG = 0,
382 	ACX_PREAMBLE_SHORT = 1
383 };
384 
385 struct acx_preamble {
386 	struct acx_header header;
387 
388 	/*
389 	 * When set, the WiLink transmits the frames with a short preamble and
390 	 * when cleared, the WiLink transmits the frames with a long preamble.
391 	 */
392 	u8 role_id;
393 	u8 preamble;
394 	u8 padding[2];
395 } __packed;
396 
397 enum acx_ctsprotect_type {
398 	CTSPROTECT_DISABLE = 0,
399 	CTSPROTECT_ENABLE = 1
400 };
401 
402 struct acx_ctsprotect {
403 	struct acx_header header;
404 	u8 role_id;
405 	u8 ctsprotect;
406 	u8 padding[2];
407 } __packed;
408 
409 struct acx_rate_class {
410 	__le32 enabled_rates;
411 	u8 short_retry_limit;
412 	u8 long_retry_limit;
413 	u8 aflags;
414 	u8 reserved;
415 };
416 
417 struct acx_rate_policy {
418 	struct acx_header header;
419 
420 	__le32 rate_policy_idx;
421 	struct acx_rate_class rate_policy;
422 } __packed;
423 
424 struct acx_ac_cfg {
425 	struct acx_header header;
426 	u8 role_id;
427 	u8 ac;
428 	u8 aifsn;
429 	u8 cw_min;
430 	__le16 cw_max;
431 	__le16 tx_op_limit;
432 } __packed;
433 
434 struct acx_tid_config {
435 	struct acx_header header;
436 	u8 role_id;
437 	u8 queue_id;
438 	u8 channel_type;
439 	u8 tsid;
440 	u8 ps_scheme;
441 	u8 ack_policy;
442 	u8 padding[2];
443 	__le32 apsd_conf[2];
444 } __packed;
445 
446 struct acx_frag_threshold {
447 	struct acx_header header;
448 	__le16 frag_threshold;
449 	u8 padding[2];
450 } __packed;
451 
452 struct acx_tx_config_options {
453 	struct acx_header header;
454 	__le16 tx_compl_timeout;     /* msec */
455 	__le16 tx_compl_threshold;   /* number of packets */
456 } __packed;
457 
458 struct wl12xx_acx_config_memory {
459 	struct acx_header header;
460 
461 	u8 rx_mem_block_num;
462 	u8 tx_min_mem_block_num;
463 	u8 num_stations;
464 	u8 num_ssid_profiles;
465 	__le32 total_tx_descriptors;
466 	u8 dyn_mem_enable;
467 	u8 tx_free_req;
468 	u8 rx_free_req;
469 	u8 tx_min;
470 	u8 fwlog_blocks;
471 	u8 padding[3];
472 } __packed;
473 
474 struct wl1271_acx_mem_map {
475 	struct acx_header header;
476 
477 	__le32 code_start;
478 	__le32 code_end;
479 
480 	__le32 wep_defkey_start;
481 	__le32 wep_defkey_end;
482 
483 	__le32 sta_table_start;
484 	__le32 sta_table_end;
485 
486 	__le32 packet_template_start;
487 	__le32 packet_template_end;
488 
489 	/* Address of the TX result interface (control block) */
490 	__le32 tx_result;
491 	__le32 tx_result_queue_start;
492 
493 	__le32 queue_memory_start;
494 	__le32 queue_memory_end;
495 
496 	__le32 packet_memory_pool_start;
497 	__le32 packet_memory_pool_end;
498 
499 	__le32 debug_buffer1_start;
500 	__le32 debug_buffer1_end;
501 
502 	__le32 debug_buffer2_start;
503 	__le32 debug_buffer2_end;
504 
505 	/* Number of blocks FW allocated for TX packets */
506 	__le32 num_tx_mem_blocks;
507 
508 	/* Number of blocks FW allocated for RX packets */
509 	__le32 num_rx_mem_blocks;
510 
511 	/* the following 4 fields are valid in SLAVE mode only */
512 	u8 *tx_cbuf;
513 	u8 *rx_cbuf;
514 	__le32 rx_ctrl;
515 	__le32 tx_ctrl;
516 } __packed;
517 
518 struct wl1271_acx_rx_config_opt {
519 	struct acx_header header;
520 
521 	__le16 mblk_threshold;
522 	__le16 threshold;
523 	__le16 timeout;
524 	u8 queue_type;
525 	u8 reserved;
526 } __packed;
527 
528 
529 struct wl1271_acx_bet_enable {
530 	struct acx_header header;
531 
532 	u8 role_id;
533 	u8 enable;
534 	u8 max_consecutive;
535 	u8 padding[1];
536 } __packed;
537 
538 #define ACX_IPV4_VERSION 4
539 #define ACX_IPV6_VERSION 6
540 #define ACX_IPV4_ADDR_SIZE 4
541 
542 /* bitmap of enabled arp_filter features */
543 #define ACX_ARP_FILTER_ARP_FILTERING	BIT(0)
544 #define ACX_ARP_FILTER_AUTO_ARP		BIT(1)
545 
546 struct wl1271_acx_arp_filter {
547 	struct acx_header header;
548 	u8 role_id;
549 	u8 version;         /* ACX_IPV4_VERSION, ACX_IPV6_VERSION */
550 	u8 enable;          /* bitmap of enabled ARP filtering features */
551 	u8 padding[1];
552 	u8 address[16];     /* The configured device IP address - all ARP
553 			       requests directed to this IP address will pass
554 			       through. For IPv4, the first four bytes are
555 			       used. */
556 } __packed;
557 
558 struct wl1271_acx_pm_config {
559 	struct acx_header header;
560 
561 	__le32 host_clk_settling_time;
562 	u8 host_fast_wakeup_support;
563 	u8 padding[3];
564 } __packed;
565 
566 struct wl1271_acx_keep_alive_mode {
567 	struct acx_header header;
568 
569 	u8 role_id;
570 	u8 enabled;
571 	u8 padding[2];
572 } __packed;
573 
574 enum {
575 	ACX_KEEP_ALIVE_NO_TX = 0,
576 	ACX_KEEP_ALIVE_PERIOD_ONLY
577 };
578 
579 enum {
580 	ACX_KEEP_ALIVE_TPL_INVALID = 0,
581 	ACX_KEEP_ALIVE_TPL_VALID
582 };
583 
584 struct wl1271_acx_keep_alive_config {
585 	struct acx_header header;
586 
587 	u8 role_id;
588 	u8 index;
589 	u8 tpl_validation;
590 	u8 trigger;
591 	__le32 period;
592 } __packed;
593 
594 /* TODO: maybe this needs to be moved somewhere else? */
595 #define HOST_IF_CFG_RX_FIFO_ENABLE     BIT(0)
596 #define HOST_IF_CFG_TX_EXTRA_BLKS_SWAP BIT(1)
597 #define HOST_IF_CFG_TX_PAD_TO_SDIO_BLK BIT(3)
598 #define HOST_IF_CFG_RX_PAD_TO_SDIO_BLK BIT(4)
599 #define HOST_IF_CFG_ADD_RX_ALIGNMENT   BIT(6)
600 
601 enum {
602 	WL1271_ACX_TRIG_TYPE_LEVEL = 0,
603 	WL1271_ACX_TRIG_TYPE_EDGE,
604 };
605 
606 enum {
607 	WL1271_ACX_TRIG_DIR_LOW = 0,
608 	WL1271_ACX_TRIG_DIR_HIGH,
609 	WL1271_ACX_TRIG_DIR_BIDIR,
610 };
611 
612 enum {
613 	WL1271_ACX_TRIG_ENABLE = 1,
614 	WL1271_ACX_TRIG_DISABLE,
615 };
616 
617 enum {
618 	WL1271_ACX_TRIG_METRIC_RSSI_BEACON = 0,
619 	WL1271_ACX_TRIG_METRIC_RSSI_DATA,
620 	WL1271_ACX_TRIG_METRIC_SNR_BEACON,
621 	WL1271_ACX_TRIG_METRIC_SNR_DATA,
622 };
623 
624 enum {
625 	WL1271_ACX_TRIG_IDX_RSSI = 0,
626 	WL1271_ACX_TRIG_COUNT = 8,
627 };
628 
629 struct wl1271_acx_rssi_snr_trigger {
630 	struct acx_header header;
631 
632 	u8 role_id;
633 	u8 metric;
634 	u8 type;
635 	u8 dir;
636 	__le16 threshold;
637 	__le16 pacing; /* 0 - 60000 ms */
638 	u8 hysteresis;
639 	u8 index;
640 	u8 enable;
641 	u8 padding[1];
642 };
643 
644 struct wl1271_acx_rssi_snr_avg_weights {
645 	struct acx_header header;
646 
647 	u8 role_id;
648 	u8 padding[3];
649 	u8 rssi_beacon;
650 	u8 rssi_data;
651 	u8 snr_beacon;
652 	u8 snr_data;
653 };
654 
655 
656 /* special capability bit (not employed by the 802.11n spec) */
657 #define WL12XX_HT_CAP_HT_OPERATION BIT(16)
658 
659 /*
660  * ACX_PEER_HT_CAP
661  * Configure HT capabilities - declare the capabilities of the peer
662  * we are connected to.
663  */
664 struct wl1271_acx_ht_capabilities {
665 	struct acx_header header;
666 
667 	/* bitmask of capability bits supported by the peer */
668 	__le32 ht_capabilites;
669 
670 	/* Indicates to which link these capabilities apply. */
671 	u8 hlid;
672 
673 	/*
674 	 * This the maximum A-MPDU length supported by the AP. The FW may not
675 	 * exceed this length when sending A-MPDUs
676 	 */
677 	u8 ampdu_max_length;
678 
679 	/* This is the minimal spacing required when sending A-MPDUs to the AP*/
680 	u8 ampdu_min_spacing;
681 
682 	u8 padding;
683 } __packed;
684 
685 /*
686  * ACX_HT_BSS_OPERATION
687  * Configure HT capabilities - AP rules for behavior in the BSS.
688  */
689 struct wl1271_acx_ht_information {
690 	struct acx_header header;
691 
692 	u8 role_id;
693 
694 	/* Values: 0 - RIFS not allowed, 1 - RIFS allowed */
695 	u8 rifs_mode;
696 
697 	/* Values: 0 - 3 like in spec */
698 	u8 ht_protection;
699 
700 	/* Values: 0 - GF protection not required, 1 - GF protection required */
701 	u8 gf_protection;
702 
703 	/*Values: 0 - TX Burst limit not required, 1 - TX Burst Limit required*/
704 	u8 ht_tx_burst_limit;
705 
706 	/*
707 	 * Values: 0 - Dual CTS protection not required,
708 	 *         1 - Dual CTS Protection required
709 	 * Note: When this value is set to 1 FW will protect all TXOP with RTS
710 	 * frame and will not use CTS-to-self regardless of the value of the
711 	 * ACX_CTS_PROTECTION information element
712 	 */
713 	u8 dual_cts_protection;
714 
715 	u8 padding[2];
716 } __packed;
717 
718 struct wl1271_acx_ba_initiator_policy {
719 	struct acx_header header;
720 
721 	/* Specifies role Id, Range 0-7, 0xFF means ANY role. */
722 	u8 role_id;
723 
724 	/*
725 	 * Per TID setting for allowing TX BA. Set a bit to 1 to allow
726 	 * TX BA sessions for the corresponding TID.
727 	 */
728 	u8 tid_bitmap;
729 
730 	/* Windows size in number of packets */
731 	u8 win_size;
732 
733 	u8 padding1[1];
734 
735 	/* As initiator inactivity timeout in time units(TU) of 1024us */
736 	u16 inactivity_timeout;
737 
738 	u8 padding[2];
739 } __packed;
740 
741 struct wl1271_acx_ba_receiver_setup {
742 	struct acx_header header;
743 
744 	/* Specifies link id, range 0-31 */
745 	u8 hlid;
746 
747 	u8 tid;
748 
749 	u8 enable;
750 
751 	/* Windows size in number of packets */
752 	u8 win_size;
753 
754 	/* BA session starting sequence number.  RANGE 0-FFF */
755 	u16 ssn;
756 
757 	u8 padding[2];
758 } __packed;
759 
760 struct wl12xx_acx_fw_tsf_information {
761 	struct acx_header header;
762 
763 	u8 role_id;
764 	u8 padding1[3];
765 	__le32 current_tsf_high;
766 	__le32 current_tsf_low;
767 	__le32 last_bttt_high;
768 	__le32 last_tbtt_low;
769 	u8 last_dtim_count;
770 	u8 padding2[3];
771 } __packed;
772 
773 struct wl1271_acx_ps_rx_streaming {
774 	struct acx_header header;
775 
776 	u8 role_id;
777 	u8 tid;
778 	u8 enable;
779 
780 	/* interval between triggers (10-100 msec) */
781 	u8 period;
782 
783 	/* timeout before first trigger (0-200 msec) */
784 	u8 timeout;
785 	u8 padding[3];
786 } __packed;
787 
788 struct wl1271_acx_ap_max_tx_retry {
789 	struct acx_header header;
790 
791 	u8 role_id;
792 	u8 padding_1;
793 
794 	/*
795 	 * the number of frames transmission failures before
796 	 * issuing the aging event.
797 	 */
798 	__le16 max_tx_retry;
799 } __packed;
800 
801 struct wl1271_acx_config_ps {
802 	struct acx_header header;
803 
804 	u8 exit_retries;
805 	u8 enter_retries;
806 	u8 padding[2];
807 	__le32 null_data_rate;
808 } __packed;
809 
810 struct wl1271_acx_inconnection_sta {
811 	struct acx_header header;
812 
813 	u8 addr[ETH_ALEN];
814 	u8 role_id;
815 	u8 padding;
816 } __packed;
817 
818 /*
819  * ACX_FM_COEX_CFG
820  * set the FM co-existence parameters.
821  */
822 struct wl1271_acx_fm_coex {
823 	struct acx_header header;
824 	/* enable(1) / disable(0) the FM Coex feature */
825 	u8 enable;
826 	/*
827 	 * Swallow period used in COEX PLL swallowing mechanism.
828 	 * 0xFF = use FW default
829 	 */
830 	u8 swallow_period;
831 	/*
832 	 * The N divider used in COEX PLL swallowing mechanism for Fref of
833 	 * 38.4/19.2 Mhz. 0xFF = use FW default
834 	 */
835 	u8 n_divider_fref_set_1;
836 	/*
837 	 * The N divider used in COEX PLL swallowing mechanism for Fref of
838 	 * 26/52 Mhz. 0xFF = use FW default
839 	 */
840 	u8 n_divider_fref_set_2;
841 	/*
842 	 * The M divider used in COEX PLL swallowing mechanism for Fref of
843 	 * 38.4/19.2 Mhz. 0xFFFF = use FW default
844 	 */
845 	__le16 m_divider_fref_set_1;
846 	/*
847 	 * The M divider used in COEX PLL swallowing mechanism for Fref of
848 	 * 26/52 Mhz. 0xFFFF = use FW default
849 	 */
850 	__le16 m_divider_fref_set_2;
851 	/*
852 	 * The time duration in uSec required for COEX PLL to stabilize.
853 	 * 0xFFFFFFFF = use FW default
854 	 */
855 	__le32 coex_pll_stabilization_time;
856 	/*
857 	 * The time duration in uSec required for LDO to stabilize.
858 	 * 0xFFFFFFFF = use FW default
859 	 */
860 	__le16 ldo_stabilization_time;
861 	/*
862 	 * The disturbed frequency band margin around the disturbed frequency
863 	 * center (single sided).
864 	 * For example, if 2 is configured, the following channels will be
865 	 * considered disturbed channel:
866 	 *   80 +- 0.1 MHz, 91 +- 0.1 MHz, 98 +- 0.1 MHz, 102 +- 0.1 MH
867 	 * 0xFF = use FW default
868 	 */
869 	u8 fm_disturbed_band_margin;
870 	/*
871 	 * The swallow clock difference of the swallowing mechanism.
872 	 * 0xFF = use FW default
873 	 */
874 	u8 swallow_clk_diff;
875 } __packed;
876 
877 #define ACX_RATE_MGMT_ALL_PARAMS 0xff
878 struct wl12xx_acx_set_rate_mgmt_params {
879 	struct acx_header header;
880 
881 	u8 index; /* 0xff to configure all params */
882 	u8 padding1;
883 	__le16 rate_retry_score;
884 	__le16 per_add;
885 	__le16 per_th1;
886 	__le16 per_th2;
887 	__le16 max_per;
888 	u8 inverse_curiosity_factor;
889 	u8 tx_fail_low_th;
890 	u8 tx_fail_high_th;
891 	u8 per_alpha_shift;
892 	u8 per_add_shift;
893 	u8 per_beta1_shift;
894 	u8 per_beta2_shift;
895 	u8 rate_check_up;
896 	u8 rate_check_down;
897 	u8 rate_retry_policy[ACX_RATE_MGMT_NUM_OF_RATES];
898 	u8 padding2[2];
899 } __packed;
900 
901 struct wl12xx_acx_config_hangover {
902 	struct acx_header header;
903 
904 	__le32 recover_time;
905 	u8 hangover_period;
906 	u8 dynamic_mode;
907 	u8 early_termination_mode;
908 	u8 max_period;
909 	u8 min_period;
910 	u8 increase_delta;
911 	u8 decrease_delta;
912 	u8 quiet_time;
913 	u8 increase_time;
914 	u8 window_size;
915 	u8 padding[2];
916 } __packed;
917 
918 
919 struct acx_default_rx_filter {
920 	struct acx_header header;
921 	u8 enable;
922 
923 	/* action of type FILTER_XXX */
924 	u8 default_action;
925 
926 	u8 pad[2];
927 } __packed;
928 
929 
930 struct acx_rx_filter_cfg {
931 	struct acx_header header;
932 
933 	u8 enable;
934 
935 	/* 0 - WL1271_MAX_RX_FILTERS-1 */
936 	u8 index;
937 
938 	u8 action;
939 
940 	u8 num_fields;
941 	u8 fields[];
942 } __packed;
943 
944 struct acx_roaming_stats {
945 	struct acx_header header;
946 
947 	u8	role_id;
948 	u8	pad[3];
949 	u32	missed_beacons;
950 	u8	snr_data;
951 	u8	snr_bacon;
952 	s8	rssi_data;
953 	s8	rssi_beacon;
954 } __packed;
955 
956 enum {
957 	ACX_WAKE_UP_CONDITIONS           = 0x0000,
958 	ACX_MEM_CFG                      = 0x0001,
959 	ACX_SLOT                         = 0x0002,
960 	ACX_AC_CFG                       = 0x0003,
961 	ACX_MEM_MAP                      = 0x0004,
962 	ACX_AID                          = 0x0005,
963 	ACX_MEDIUM_USAGE                 = 0x0006,
964 	ACX_STATISTICS                   = 0x0007,
965 	ACX_PWR_CONSUMPTION_STATISTICS   = 0x0008,
966 	ACX_TID_CFG                      = 0x0009,
967 	ACX_PS_RX_STREAMING              = 0x000A,
968 	ACX_BEACON_FILTER_OPT            = 0x000B,
969 	ACX_NOISE_HIST                   = 0x000C,
970 	ACX_HDK_VERSION                  = 0x000D,
971 	ACX_PD_THRESHOLD                 = 0x000E,
972 	ACX_TX_CONFIG_OPT                = 0x000F,
973 	ACX_CCA_THRESHOLD                = 0x0010,
974 	ACX_EVENT_MBOX_MASK              = 0x0011,
975 	ACX_CONN_MONIT_PARAMS            = 0x0012,
976 	ACX_DISABLE_BROADCASTS           = 0x0013,
977 	ACX_BCN_DTIM_OPTIONS             = 0x0014,
978 	ACX_SG_ENABLE                    = 0x0015,
979 	ACX_SG_CFG                       = 0x0016,
980 	ACX_FM_COEX_CFG                  = 0x0017,
981 	ACX_BEACON_FILTER_TABLE          = 0x0018,
982 	ACX_ARP_IP_FILTER                = 0x0019,
983 	ACX_ROAMING_STATISTICS_TBL       = 0x001A,
984 	ACX_RATE_POLICY                  = 0x001B,
985 	ACX_CTS_PROTECTION               = 0x001C,
986 	ACX_SLEEP_AUTH                   = 0x001D,
987 	ACX_PREAMBLE_TYPE                = 0x001E,
988 	ACX_ERROR_CNT                    = 0x001F,
989 	ACX_IBSS_FILTER                  = 0x0020,
990 	ACX_SERVICE_PERIOD_TIMEOUT       = 0x0021,
991 	ACX_TSF_INFO                     = 0x0022,
992 	ACX_CONFIG_PS_WMM                = 0x0023,
993 	ACX_ENABLE_RX_DATA_FILTER        = 0x0024,
994 	ACX_SET_RX_DATA_FILTER           = 0x0025,
995 	ACX_GET_DATA_FILTER_STATISTICS   = 0x0026,
996 	ACX_RX_CONFIG_OPT                = 0x0027,
997 	ACX_FRAG_CFG                     = 0x0028,
998 	ACX_BET_ENABLE                   = 0x0029,
999 	ACX_RSSI_SNR_TRIGGER             = 0x002A,
1000 	ACX_RSSI_SNR_WEIGHTS             = 0x002B,
1001 	ACX_KEEP_ALIVE_MODE              = 0x002C,
1002 	ACX_SET_KEEP_ALIVE_CONFIG        = 0x002D,
1003 	ACX_BA_SESSION_INIT_POLICY       = 0x002E,
1004 	ACX_BA_SESSION_RX_SETUP          = 0x002F,
1005 	ACX_PEER_HT_CAP                  = 0x0030,
1006 	ACX_HT_BSS_OPERATION             = 0x0031,
1007 	ACX_COEX_ACTIVITY                = 0x0032,
1008 	ACX_BURST_MODE                   = 0x0033,
1009 	ACX_SET_RATE_MGMT_PARAMS         = 0x0034,
1010 	ACX_GET_RATE_MGMT_PARAMS         = 0x0035,
1011 	ACX_SET_RATE_ADAPT_PARAMS        = 0x0036,
1012 	ACX_SET_DCO_ITRIM_PARAMS         = 0x0037,
1013 	ACX_GEN_FW_CMD                   = 0x0038,
1014 	ACX_HOST_IF_CFG_BITMAP           = 0x0039,
1015 	ACX_MAX_TX_FAILURE               = 0x003A,
1016 	ACX_UPDATE_INCONNECTION_STA_LIST = 0x003B,
1017 	DOT11_RX_MSDU_LIFE_TIME          = 0x003C,
1018 	DOT11_CUR_TX_PWR                 = 0x003D,
1019 	DOT11_RTS_THRESHOLD              = 0x003E,
1020 	DOT11_GROUP_ADDRESS_TBL          = 0x003F,
1021 	ACX_PM_CONFIG                    = 0x0040,
1022 	ACX_CONFIG_PS                    = 0x0041,
1023 	ACX_CONFIG_HANGOVER              = 0x0042,
1024 	ACX_FEATURE_CFG                  = 0x0043,
1025 	ACX_PROTECTION_CFG               = 0x0044,
1026 };
1027 
1028 
1029 int wl1271_acx_wake_up_conditions(struct wl1271 *wl,
1030 				  struct wl12xx_vif *wlvif,
1031 				  u8 wake_up_event, u8 listen_interval);
1032 int wl1271_acx_sleep_auth(struct wl1271 *wl, u8 sleep_auth);
1033 int wl1271_acx_tx_power(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1034 			int power);
1035 int wl1271_acx_feature_cfg(struct wl1271 *wl, struct wl12xx_vif *wlvif);
1036 int wl1271_acx_mem_map(struct wl1271 *wl,
1037 		       struct acx_header *mem_map, size_t len);
1038 int wl1271_acx_rx_msdu_life_time(struct wl1271 *wl);
1039 int wl1271_acx_slot(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1040 		    enum acx_slot_type slot_time);
1041 int wl1271_acx_group_address_tbl(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1042 				 bool enable, void *mc_list, u32 mc_list_len);
1043 int wl1271_acx_service_period_timeout(struct wl1271 *wl,
1044 				      struct wl12xx_vif *wlvif);
1045 int wl1271_acx_rts_threshold(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1046 			     u32 rts_threshold);
1047 int wl1271_acx_dco_itrim_params(struct wl1271 *wl);
1048 int wl1271_acx_beacon_filter_opt(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1049 				 bool enable_filter);
1050 int wl1271_acx_beacon_filter_table(struct wl1271 *wl,
1051 				   struct wl12xx_vif *wlvif);
1052 int wl1271_acx_conn_monit_params(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1053 				 bool enable);
1054 int wl1271_acx_sg_enable(struct wl1271 *wl, bool enable);
1055 int wl12xx_acx_sg_cfg(struct wl1271 *wl);
1056 int wl1271_acx_cca_threshold(struct wl1271 *wl);
1057 int wl1271_acx_bcn_dtim_options(struct wl1271 *wl, struct wl12xx_vif *wlvif);
1058 int wl1271_acx_aid(struct wl1271 *wl, struct wl12xx_vif *wlvif, u16 aid);
1059 int wl1271_acx_event_mbox_mask(struct wl1271 *wl, u32 event_mask);
1060 int wl1271_acx_set_preamble(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1061 			    enum acx_preamble_type preamble);
1062 int wl1271_acx_cts_protect(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1063 			   enum acx_ctsprotect_type ctsprotect);
1064 int wl1271_acx_statistics(struct wl1271 *wl, void *stats);
1065 int wl1271_acx_sta_rate_policies(struct wl1271 *wl, struct wl12xx_vif *wlvif);
1066 int wl1271_acx_ap_rate_policy(struct wl1271 *wl, struct conf_tx_rate_class *c,
1067 		      u8 idx);
1068 int wl1271_acx_ac_cfg(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1069 		      u8 ac, u8 cw_min, u16 cw_max, u8 aifsn, u16 txop);
1070 int wl1271_acx_tid_cfg(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1071 		       u8 queue_id, u8 channel_type,
1072 		       u8 tsid, u8 ps_scheme, u8 ack_policy,
1073 		       u32 apsd_conf0, u32 apsd_conf1);
1074 int wl1271_acx_frag_threshold(struct wl1271 *wl, u32 frag_threshold);
1075 int wl1271_acx_tx_config_options(struct wl1271 *wl);
1076 int wl12xx_acx_mem_cfg(struct wl1271 *wl);
1077 int wl1271_acx_init_mem_config(struct wl1271 *wl);
1078 int wl1271_acx_init_rx_interrupt(struct wl1271 *wl);
1079 int wl1271_acx_smart_reflex(struct wl1271 *wl);
1080 int wl1271_acx_bet_enable(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1081 			  bool enable);
1082 int wl1271_acx_arp_ip_filter(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1083 			     u8 enable, __be32 address);
1084 int wl1271_acx_pm_config(struct wl1271 *wl);
1085 int wl1271_acx_keep_alive_mode(struct wl1271 *wl, struct wl12xx_vif *vif,
1086 			       bool enable);
1087 int wl1271_acx_keep_alive_config(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1088 				 u8 index, u8 tpl_valid);
1089 int wl1271_acx_rssi_snr_trigger(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1090 				bool enable, s16 thold, u8 hyst);
1091 int wl1271_acx_rssi_snr_avg_weights(struct wl1271 *wl,
1092 				    struct wl12xx_vif *wlvif);
1093 int wl1271_acx_set_ht_capabilities(struct wl1271 *wl,
1094 				    struct ieee80211_sta_ht_cap *ht_cap,
1095 				    bool allow_ht_operation, u8 hlid);
1096 int wl1271_acx_set_ht_information(struct wl1271 *wl,
1097 				   struct wl12xx_vif *wlvif,
1098 				   u16 ht_operation_mode);
1099 int wl12xx_acx_set_ba_initiator_policy(struct wl1271 *wl,
1100 				       struct wl12xx_vif *wlvif);
1101 int wl12xx_acx_set_ba_receiver_session(struct wl1271 *wl, u8 tid_index,
1102 				       u16 ssn, bool enable, u8 peer_hlid,
1103 				       u8 win_size);
1104 int wl12xx_acx_tsf_info(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1105 			u64 *mactime);
1106 int wl1271_acx_ps_rx_streaming(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1107 			       bool enable);
1108 int wl1271_acx_ap_max_tx_retry(struct wl1271 *wl, struct wl12xx_vif *wlvif);
1109 int wl12xx_acx_config_ps(struct wl1271 *wl, struct wl12xx_vif *wlvif);
1110 int wl1271_acx_set_inconnection_sta(struct wl1271 *wl,
1111 				    struct wl12xx_vif *wlvif, u8 *addr);
1112 int wl1271_acx_fm_coex(struct wl1271 *wl);
1113 int wl12xx_acx_set_rate_mgmt_params(struct wl1271 *wl);
1114 int wl12xx_acx_config_hangover(struct wl1271 *wl);
1115 int wlcore_acx_average_rssi(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1116 			    s8 *avg_rssi);
1117 
1118 int wl1271_acx_default_rx_filter_enable(struct wl1271 *wl, bool enable,
1119 					enum rx_filter_action action);
1120 int wl1271_acx_set_rx_filter(struct wl1271 *wl, u8 index, bool enable,
1121 			     struct wl12xx_rx_filter *filter);
1122 #endif /* __WL1271_ACX_H__ */
1123