1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2013 Realtek Corporation.*/
3
4 #include "../wifi.h"
5 #include "../efuse.h"
6 #include "../base.h"
7 #include "../regd.h"
8 #include "../cam.h"
9 #include "../ps.h"
10 #include "../pci.h"
11 #include "../pwrseqcmd.h"
12 #include "reg.h"
13 #include "def.h"
14 #include "phy.h"
15 #include "dm.h"
16 #include "fw.h"
17 #include "led.h"
18 #include "hw.h"
19 #include "pwrseq.h"
20
21 #define LLT_CONFIG 5
22
_rtl88ee_set_bcn_ctrl_reg(struct ieee80211_hw * hw,u8 set_bits,u8 clear_bits)23 static void _rtl88ee_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
24 u8 set_bits, u8 clear_bits)
25 {
26 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
27 struct rtl_priv *rtlpriv = rtl_priv(hw);
28
29 rtlpci->reg_bcn_ctrl_val |= set_bits;
30 rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
31
32 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val);
33 }
34
_rtl88ee_stop_tx_beacon(struct ieee80211_hw * hw)35 static void _rtl88ee_stop_tx_beacon(struct ieee80211_hw *hw)
36 {
37 struct rtl_priv *rtlpriv = rtl_priv(hw);
38 u8 tmp1byte;
39
40 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
41 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
42 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
43 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
44 tmp1byte &= ~(BIT(0));
45 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
46 }
47
_rtl88ee_resume_tx_beacon(struct ieee80211_hw * hw)48 static void _rtl88ee_resume_tx_beacon(struct ieee80211_hw *hw)
49 {
50 struct rtl_priv *rtlpriv = rtl_priv(hw);
51 u8 tmp1byte;
52
53 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
54 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
55 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
56 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
57 tmp1byte |= BIT(0);
58 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
59 }
60
_rtl88ee_enable_bcn_sub_func(struct ieee80211_hw * hw)61 static void _rtl88ee_enable_bcn_sub_func(struct ieee80211_hw *hw)
62 {
63 _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(1));
64 }
65
_rtl88ee_return_beacon_queue_skb(struct ieee80211_hw * hw)66 static void _rtl88ee_return_beacon_queue_skb(struct ieee80211_hw *hw)
67 {
68 struct rtl_priv *rtlpriv = rtl_priv(hw);
69 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
70 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[BEACON_QUEUE];
71 struct sk_buff_head free_list;
72 unsigned long flags;
73
74 skb_queue_head_init(&free_list);
75 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
76 while (skb_queue_len(&ring->queue)) {
77 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
78 struct sk_buff *skb = __skb_dequeue(&ring->queue);
79
80 dma_unmap_single(&rtlpci->pdev->dev,
81 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
82 true, HW_DESC_TXBUFF_ADDR),
83 skb->len, DMA_TO_DEVICE);
84 __skb_queue_tail(&free_list, skb);
85 ring->idx = (ring->idx + 1) % ring->entries;
86 }
87 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
88
89 __skb_queue_purge(&free_list);
90 }
91
_rtl88ee_disable_bcn_sub_func(struct ieee80211_hw * hw)92 static void _rtl88ee_disable_bcn_sub_func(struct ieee80211_hw *hw)
93 {
94 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(1), 0);
95 }
96
_rtl88ee_set_fw_clock_on(struct ieee80211_hw * hw,u8 rpwm_val,bool b_need_turn_off_ckk)97 static void _rtl88ee_set_fw_clock_on(struct ieee80211_hw *hw,
98 u8 rpwm_val, bool b_need_turn_off_ckk)
99 {
100 struct rtl_priv *rtlpriv = rtl_priv(hw);
101 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
102 bool b_support_remote_wake_up;
103 u32 count = 0, isr_regaddr, content;
104 bool schedule_timer = b_need_turn_off_ckk;
105 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
106 (u8 *)(&b_support_remote_wake_up));
107
108 if (!rtlhal->fw_ready)
109 return;
110 if (!rtlpriv->psc.fw_current_inpsmode)
111 return;
112
113 while (1) {
114 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
115 if (rtlhal->fw_clk_change_in_progress) {
116 while (rtlhal->fw_clk_change_in_progress) {
117 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
118 count++;
119 udelay(100);
120 if (count > 1000)
121 return;
122 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
123 }
124 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
125 } else {
126 rtlhal->fw_clk_change_in_progress = false;
127 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
128 break;
129 }
130 }
131
132 if (IS_IN_LOW_POWER_STATE_88E(rtlhal->fw_ps_state)) {
133 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_SET_RPWM, &rpwm_val);
134 if (FW_PS_IS_ACK(rpwm_val)) {
135 isr_regaddr = REG_HISR;
136 content = rtl_read_dword(rtlpriv, isr_regaddr);
137 while (!(content & IMR_CPWM) && (count < 500)) {
138 udelay(50);
139 count++;
140 content = rtl_read_dword(rtlpriv, isr_regaddr);
141 }
142
143 if (content & IMR_CPWM) {
144 rtl_write_word(rtlpriv, isr_regaddr, 0x0100);
145 rtlhal->fw_ps_state = FW_PS_STATE_RF_ON_88E;
146 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
147 "Receive CPWM INT!!! Set pHalData->FwPSState = %X\n",
148 rtlhal->fw_ps_state);
149 }
150 }
151
152 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
153 rtlhal->fw_clk_change_in_progress = false;
154 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
155 if (schedule_timer) {
156 mod_timer(&rtlpriv->works.fw_clockoff_timer,
157 jiffies + MSECS(10));
158 }
159
160 } else {
161 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
162 rtlhal->fw_clk_change_in_progress = false;
163 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
164 }
165 }
166
_rtl88ee_set_fw_clock_off(struct ieee80211_hw * hw,u8 rpwm_val)167 static void _rtl88ee_set_fw_clock_off(struct ieee80211_hw *hw,
168 u8 rpwm_val)
169 {
170 struct rtl_priv *rtlpriv = rtl_priv(hw);
171 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
172 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
173 struct rtl8192_tx_ring *ring;
174 enum rf_pwrstate rtstate;
175 bool schedule_timer = false;
176 u8 queue;
177
178 if (!rtlhal->fw_ready)
179 return;
180 if (!rtlpriv->psc.fw_current_inpsmode)
181 return;
182 if (!rtlhal->allow_sw_to_change_hwclc)
183 return;
184 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, (u8 *)(&rtstate));
185 if (rtstate == ERFOFF || rtlpriv->psc.inactive_pwrstate == ERFOFF)
186 return;
187
188 for (queue = 0; queue < RTL_PCI_MAX_TX_QUEUE_COUNT; queue++) {
189 ring = &rtlpci->tx_ring[queue];
190 if (skb_queue_len(&ring->queue)) {
191 schedule_timer = true;
192 break;
193 }
194 }
195
196 if (schedule_timer) {
197 mod_timer(&rtlpriv->works.fw_clockoff_timer,
198 jiffies + MSECS(10));
199 return;
200 }
201
202 if (FW_PS_STATE(rtlhal->fw_ps_state) !=
203 FW_PS_STATE_RF_OFF_LOW_PWR_88E) {
204 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
205 if (!rtlhal->fw_clk_change_in_progress) {
206 rtlhal->fw_clk_change_in_progress = true;
207 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
208 rtlhal->fw_ps_state = FW_PS_STATE(rpwm_val);
209 rtl_write_word(rtlpriv, REG_HISR, 0x0100);
210 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
211 &rpwm_val);
212 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
213 rtlhal->fw_clk_change_in_progress = false;
214 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
215 } else {
216 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
217 mod_timer(&rtlpriv->works.fw_clockoff_timer,
218 jiffies + MSECS(10));
219 }
220 }
221 }
222
_rtl88ee_set_fw_ps_rf_on(struct ieee80211_hw * hw)223 static void _rtl88ee_set_fw_ps_rf_on(struct ieee80211_hw *hw)
224 {
225 u8 rpwm_val = 0;
226
227 rpwm_val |= (FW_PS_STATE_RF_OFF_88E | FW_PS_ACK);
228 _rtl88ee_set_fw_clock_on(hw, rpwm_val, true);
229 }
230
_rtl88ee_set_fw_ps_rf_off_low_power(struct ieee80211_hw * hw)231 static void _rtl88ee_set_fw_ps_rf_off_low_power(struct ieee80211_hw *hw)
232 {
233 u8 rpwm_val = 0;
234 rpwm_val |= FW_PS_STATE_RF_OFF_LOW_PWR_88E;
235 _rtl88ee_set_fw_clock_off(hw, rpwm_val);
236 }
237
rtl88ee_fw_clk_off_timer_callback(struct timer_list * t)238 void rtl88ee_fw_clk_off_timer_callback(struct timer_list *t)
239 {
240 struct rtl_priv *rtlpriv = from_timer(rtlpriv, t,
241 works.fw_clockoff_timer);
242 struct ieee80211_hw *hw = rtlpriv->hw;
243
244 _rtl88ee_set_fw_ps_rf_off_low_power(hw);
245 }
246
_rtl88ee_fwlps_leave(struct ieee80211_hw * hw)247 static void _rtl88ee_fwlps_leave(struct ieee80211_hw *hw)
248 {
249 struct rtl_priv *rtlpriv = rtl_priv(hw);
250 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
251 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
252 bool fw_current_inps = false;
253 u8 rpwm_val = 0, fw_pwrmode = FW_PS_ACTIVE_MODE;
254
255 if (ppsc->low_power_enable) {
256 rpwm_val = (FW_PS_STATE_ALL_ON_88E|FW_PS_ACK);/* RF on */
257 _rtl88ee_set_fw_clock_on(hw, rpwm_val, false);
258 rtlhal->allow_sw_to_change_hwclc = false;
259 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
260 &fw_pwrmode);
261 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
262 (u8 *)(&fw_current_inps));
263 } else {
264 rpwm_val = FW_PS_STATE_ALL_ON_88E; /* RF on */
265 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, &rpwm_val);
266 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
267 &fw_pwrmode);
268 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
269 (u8 *)(&fw_current_inps));
270 }
271 }
272
_rtl88ee_fwlps_enter(struct ieee80211_hw * hw)273 static void _rtl88ee_fwlps_enter(struct ieee80211_hw *hw)
274 {
275 struct rtl_priv *rtlpriv = rtl_priv(hw);
276 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
277 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
278 bool fw_current_inps = true;
279 u8 rpwm_val;
280
281 if (ppsc->low_power_enable) {
282 rpwm_val = FW_PS_STATE_RF_OFF_LOW_PWR_88E; /* RF off */
283 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
284 (u8 *)(&fw_current_inps));
285 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
286 &ppsc->fwctrl_psmode);
287 rtlhal->allow_sw_to_change_hwclc = true;
288 _rtl88ee_set_fw_clock_off(hw, rpwm_val);
289 } else {
290 rpwm_val = FW_PS_STATE_RF_OFF_88E; /* RF off */
291 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
292 (u8 *)(&fw_current_inps));
293 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
294 &ppsc->fwctrl_psmode);
295 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, &rpwm_val);
296 }
297 }
298
rtl88ee_get_hw_reg(struct ieee80211_hw * hw,u8 variable,u8 * val)299 void rtl88ee_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
300 {
301 struct rtl_priv *rtlpriv = rtl_priv(hw);
302 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
303 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
304
305 switch (variable) {
306 case HW_VAR_RCR:
307 *((u32 *)(val)) = rtlpci->receive_config;
308 break;
309 case HW_VAR_RF_STATE:
310 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
311 break;
312 case HW_VAR_FWLPS_RF_ON:{
313 enum rf_pwrstate rfstate;
314 u32 val_rcr;
315
316 rtlpriv->cfg->ops->get_hw_reg(hw,
317 HW_VAR_RF_STATE,
318 (u8 *)(&rfstate));
319 if (rfstate == ERFOFF) {
320 *((bool *)(val)) = true;
321 } else {
322 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
323 val_rcr &= 0x00070000;
324 if (val_rcr)
325 *((bool *)(val)) = false;
326 else
327 *((bool *)(val)) = true;
328 }
329 break; }
330 case HW_VAR_FW_PSMODE_STATUS:
331 *((bool *)(val)) = ppsc->fw_current_inpsmode;
332 break;
333 case HW_VAR_CORRECT_TSF:{
334 u64 tsf;
335 u32 *ptsf_low = (u32 *)&tsf;
336 u32 *ptsf_high = ((u32 *)&tsf) + 1;
337
338 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
339 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
340
341 *((u64 *)(val)) = tsf;
342 break; }
343 case HAL_DEF_WOWLAN:
344 break;
345 default:
346 pr_err("switch case %#x not processed\n", variable);
347 break;
348 }
349 }
350
rtl88ee_set_hw_reg(struct ieee80211_hw * hw,u8 variable,u8 * val)351 void rtl88ee_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
352 {
353 struct rtl_priv *rtlpriv = rtl_priv(hw);
354 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
355 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
356 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
357 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
358 u8 idx;
359
360 switch (variable) {
361 case HW_VAR_ETHER_ADDR:
362 for (idx = 0; idx < ETH_ALEN; idx++) {
363 rtl_write_byte(rtlpriv, (REG_MACID + idx),
364 val[idx]);
365 }
366 break;
367 case HW_VAR_BASIC_RATE:{
368 u16 b_rate_cfg = ((u16 *)val)[0];
369 u8 rate_index = 0;
370 b_rate_cfg = b_rate_cfg & 0x15f;
371 b_rate_cfg |= 0x01;
372 rtl_write_byte(rtlpriv, REG_RRSR, b_rate_cfg & 0xff);
373 rtl_write_byte(rtlpriv, REG_RRSR + 1,
374 (b_rate_cfg >> 8) & 0xff);
375 while (b_rate_cfg > 0x1) {
376 b_rate_cfg = (b_rate_cfg >> 1);
377 rate_index++;
378 }
379 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
380 rate_index);
381 break;
382 }
383 case HW_VAR_BSSID:
384 for (idx = 0; idx < ETH_ALEN; idx++) {
385 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
386 val[idx]);
387 }
388 break;
389 case HW_VAR_SIFS:
390 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
391 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
392
393 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
394 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
395
396 if (!mac->ht_enable)
397 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
398 0x0e0e);
399 else
400 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
401 *((u16 *)val));
402 break;
403 case HW_VAR_SLOT_TIME:{
404 u8 e_aci;
405
406 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
407 "HW_VAR_SLOT_TIME %x\n", val[0]);
408
409 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
410
411 for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
412 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM,
413 &e_aci);
414 }
415 break;
416 }
417 case HW_VAR_ACK_PREAMBLE:{
418 u8 reg_tmp;
419 u8 short_preamble = (bool)*val;
420 reg_tmp = rtl_read_byte(rtlpriv, REG_TRXPTCL_CTL+2);
421 if (short_preamble) {
422 reg_tmp |= 0x02;
423 rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL +
424 2, reg_tmp);
425 } else {
426 reg_tmp |= 0xFD;
427 rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL +
428 2, reg_tmp);
429 }
430 break; }
431 case HW_VAR_WPA_CONFIG:
432 rtl_write_byte(rtlpriv, REG_SECCFG, *val);
433 break;
434 case HW_VAR_AMPDU_MIN_SPACE:{
435 u8 min_spacing_to_set;
436 u8 sec_min_space;
437
438 min_spacing_to_set = *val;
439 if (min_spacing_to_set <= 7) {
440 sec_min_space = 0;
441
442 if (min_spacing_to_set < sec_min_space)
443 min_spacing_to_set = sec_min_space;
444
445 mac->min_space_cfg = ((mac->min_space_cfg &
446 0xf8) |
447 min_spacing_to_set);
448
449 *val = min_spacing_to_set;
450
451 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
452 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
453 mac->min_space_cfg);
454
455 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
456 mac->min_space_cfg);
457 }
458 break; }
459 case HW_VAR_SHORTGI_DENSITY:{
460 u8 density_to_set;
461
462 density_to_set = *val;
463 mac->min_space_cfg |= (density_to_set << 3);
464
465 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
466 "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
467 mac->min_space_cfg);
468
469 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
470 mac->min_space_cfg);
471 break;
472 }
473 case HW_VAR_AMPDU_FACTOR:{
474 u8 regtoset_normal[4] = { 0x41, 0xa8, 0x72, 0xb9 };
475 u8 factor_toset;
476 u8 *p_regtoset = NULL;
477 u8 index = 0;
478
479 p_regtoset = regtoset_normal;
480
481 factor_toset = *val;
482 if (factor_toset <= 3) {
483 factor_toset = (1 << (factor_toset + 2));
484 if (factor_toset > 0xf)
485 factor_toset = 0xf;
486
487 for (index = 0; index < 4; index++) {
488 if ((p_regtoset[index] & 0xf0) >
489 (factor_toset << 4))
490 p_regtoset[index] =
491 (p_regtoset[index] & 0x0f) |
492 (factor_toset << 4);
493
494 if ((p_regtoset[index] & 0x0f) >
495 factor_toset)
496 p_regtoset[index] =
497 (p_regtoset[index] & 0xf0) |
498 (factor_toset);
499
500 rtl_write_byte(rtlpriv,
501 (REG_AGGLEN_LMT + index),
502 p_regtoset[index]);
503
504 }
505
506 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
507 "Set HW_VAR_AMPDU_FACTOR: %#x\n",
508 factor_toset);
509 }
510 break; }
511 case HW_VAR_AC_PARAM:{
512 u8 e_aci = *val;
513 rtl88e_dm_init_edca_turbo(hw);
514
515 if (rtlpci->acm_method != EACMWAY2_SW)
516 rtlpriv->cfg->ops->set_hw_reg(hw,
517 HW_VAR_ACM_CTRL,
518 &e_aci);
519 break; }
520 case HW_VAR_ACM_CTRL:{
521 u8 e_aci = *val;
522 union aci_aifsn *p_aci_aifsn =
523 (union aci_aifsn *)(&(mac->ac[0].aifs));
524 u8 acm = p_aci_aifsn->f.acm;
525 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
526
527 acm_ctrl = acm_ctrl |
528 ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
529
530 if (acm) {
531 switch (e_aci) {
532 case AC0_BE:
533 acm_ctrl |= ACMHW_BEQEN;
534 break;
535 case AC2_VI:
536 acm_ctrl |= ACMHW_VIQEN;
537 break;
538 case AC3_VO:
539 acm_ctrl |= ACMHW_VOQEN;
540 break;
541 default:
542 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
543 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
544 acm);
545 break;
546 }
547 } else {
548 switch (e_aci) {
549 case AC0_BE:
550 acm_ctrl &= (~ACMHW_BEQEN);
551 break;
552 case AC2_VI:
553 acm_ctrl &= (~ACMHW_VIQEN);
554 break;
555 case AC3_VO:
556 acm_ctrl &= (~ACMHW_VOQEN);
557 break;
558 default:
559 pr_err("switch case %#x not processed\n",
560 e_aci);
561 break;
562 }
563 }
564
565 rtl_dbg(rtlpriv, COMP_QOS, DBG_TRACE,
566 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
567 acm_ctrl);
568 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
569 break; }
570 case HW_VAR_RCR:
571 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *)(val))[0]);
572 rtlpci->receive_config = ((u32 *)(val))[0];
573 break;
574 case HW_VAR_RETRY_LIMIT:{
575 u8 retry_limit = *val;
576
577 rtl_write_word(rtlpriv, REG_RL,
578 retry_limit << RETRY_LIMIT_SHORT_SHIFT |
579 retry_limit << RETRY_LIMIT_LONG_SHIFT);
580 break; }
581 case HW_VAR_DUAL_TSF_RST:
582 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
583 break;
584 case HW_VAR_EFUSE_BYTES:
585 rtlefuse->efuse_usedbytes = *((u16 *)val);
586 break;
587 case HW_VAR_EFUSE_USAGE:
588 rtlefuse->efuse_usedpercentage = *val;
589 break;
590 case HW_VAR_IO_CMD:
591 rtl88e_phy_set_io_cmd(hw, (*(enum io_type *)val));
592 break;
593 case HW_VAR_SET_RPWM:{
594 u8 rpwm_val;
595
596 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
597 udelay(1);
598
599 if (rpwm_val & BIT(7)) {
600 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, *val);
601 } else {
602 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, *val | BIT(7));
603 }
604 break; }
605 case HW_VAR_H2C_FW_PWRMODE:
606 rtl88e_set_fw_pwrmode_cmd(hw, *val);
607 break;
608 case HW_VAR_FW_PSMODE_STATUS:
609 ppsc->fw_current_inpsmode = *((bool *)val);
610 break;
611 case HW_VAR_RESUME_CLK_ON:
612 _rtl88ee_set_fw_ps_rf_on(hw);
613 break;
614 case HW_VAR_FW_LPS_ACTION:{
615 bool enter_fwlps = *((bool *)val);
616
617 if (enter_fwlps)
618 _rtl88ee_fwlps_enter(hw);
619 else
620 _rtl88ee_fwlps_leave(hw);
621
622 break; }
623 case HW_VAR_H2C_FW_JOINBSSRPT:{
624 u8 mstatus = *val;
625 u8 tmp_regcr, tmp_reg422, bcnvalid_reg;
626 u8 count = 0, dlbcn_count = 0;
627 bool b_recover = false;
628
629 if (mstatus == RT_MEDIA_CONNECT) {
630 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID,
631 NULL);
632
633 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
634 rtl_write_byte(rtlpriv, REG_CR + 1,
635 (tmp_regcr | BIT(0)));
636
637 _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(3));
638 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(4), 0);
639
640 tmp_reg422 =
641 rtl_read_byte(rtlpriv,
642 REG_FWHW_TXQ_CTRL + 2);
643 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
644 tmp_reg422 & (~BIT(6)));
645 if (tmp_reg422 & BIT(6))
646 b_recover = true;
647
648 do {
649 bcnvalid_reg = rtl_read_byte(rtlpriv,
650 REG_TDECTRL+2);
651 rtl_write_byte(rtlpriv, REG_TDECTRL+2,
652 (bcnvalid_reg | BIT(0)));
653 _rtl88ee_return_beacon_queue_skb(hw);
654
655 rtl88e_set_fw_rsvdpagepkt(hw, 0);
656 bcnvalid_reg = rtl_read_byte(rtlpriv,
657 REG_TDECTRL+2);
658 count = 0;
659 while (!(bcnvalid_reg & BIT(0)) && count < 20) {
660 count++;
661 udelay(10);
662 bcnvalid_reg =
663 rtl_read_byte(rtlpriv, REG_TDECTRL+2);
664 }
665 dlbcn_count++;
666 } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5);
667
668 if (bcnvalid_reg & BIT(0))
669 rtl_write_byte(rtlpriv, REG_TDECTRL+2, BIT(0));
670
671 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(3), 0);
672 _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(4));
673
674 if (b_recover) {
675 rtl_write_byte(rtlpriv,
676 REG_FWHW_TXQ_CTRL + 2,
677 tmp_reg422);
678 }
679
680 rtl_write_byte(rtlpriv, REG_CR + 1,
681 (tmp_regcr & ~(BIT(0))));
682 }
683 rtl88e_set_fw_joinbss_report_cmd(hw, (*(u8 *)val));
684 break; }
685 case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
686 rtl88e_set_p2p_ps_offload_cmd(hw, *val);
687 break;
688 case HW_VAR_AID:{
689 u16 u2btmp;
690
691 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
692 u2btmp &= 0xC000;
693 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp |
694 mac->assoc_id));
695 break; }
696 case HW_VAR_CORRECT_TSF:{
697 u8 btype_ibss = *val;
698
699 if (btype_ibss)
700 _rtl88ee_stop_tx_beacon(hw);
701
702 _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(3));
703
704 rtl_write_dword(rtlpriv, REG_TSFTR,
705 (u32)(mac->tsf & 0xffffffff));
706 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
707 (u32)((mac->tsf >> 32) & 0xffffffff));
708
709 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(3), 0);
710
711 if (btype_ibss)
712 _rtl88ee_resume_tx_beacon(hw);
713 break; }
714 case HW_VAR_KEEP_ALIVE: {
715 u8 array[2];
716
717 array[0] = 0xff;
718 array[1] = *((u8 *)val);
719 rtl88e_fill_h2c_cmd(hw, H2C_88E_KEEP_ALIVE_CTRL,
720 2, array);
721 break; }
722 default:
723 pr_err("switch case %#x not processed\n", variable);
724 break;
725 }
726 }
727
_rtl88ee_llt_write(struct ieee80211_hw * hw,u32 address,u32 data)728 static bool _rtl88ee_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
729 {
730 struct rtl_priv *rtlpriv = rtl_priv(hw);
731 bool status = true;
732 long count = 0;
733 u32 value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) |
734 _LLT_OP(_LLT_WRITE_ACCESS);
735
736 rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
737
738 do {
739 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
740 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
741 break;
742
743 if (count > POLLING_LLT_THRESHOLD) {
744 pr_err("Failed to polling write LLT done at address %d!\n",
745 address);
746 status = false;
747 break;
748 }
749 } while (++count);
750
751 return status;
752 }
753
_rtl88ee_llt_table_init(struct ieee80211_hw * hw)754 static bool _rtl88ee_llt_table_init(struct ieee80211_hw *hw)
755 {
756 struct rtl_priv *rtlpriv = rtl_priv(hw);
757 unsigned short i;
758 u8 txpktbuf_bndy;
759 u8 maxpage;
760 bool status;
761
762 maxpage = 0xAF;
763 txpktbuf_bndy = 0xAB;
764
765 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x01);
766 rtl_write_dword(rtlpriv, REG_RQPN, 0x80730d29);
767
768 /*0x2600 MaxRxBuff=10k-max(TxReportSize(64*8), WOLPattern(16*24)) */
769 rtl_write_dword(rtlpriv, REG_TRXFF_BNDY, (0x25FF0000 | txpktbuf_bndy));
770 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
771
772 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
773 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
774
775 rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);
776 rtl_write_byte(rtlpriv, REG_PBP, 0x11);
777 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
778
779 for (i = 0; i < (txpktbuf_bndy - 1); i++) {
780 status = _rtl88ee_llt_write(hw, i, i + 1);
781 if (!status)
782 return status;
783 }
784
785 status = _rtl88ee_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
786 if (!status)
787 return status;
788
789 for (i = txpktbuf_bndy; i < maxpage; i++) {
790 status = _rtl88ee_llt_write(hw, i, (i + 1));
791 if (!status)
792 return status;
793 }
794
795 status = _rtl88ee_llt_write(hw, maxpage, txpktbuf_bndy);
796 if (!status)
797 return status;
798
799 return true;
800 }
801
_rtl88ee_gen_refresh_led_state(struct ieee80211_hw * hw)802 static void _rtl88ee_gen_refresh_led_state(struct ieee80211_hw *hw)
803 {
804 struct rtl_priv *rtlpriv = rtl_priv(hw);
805 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
806 enum rtl_led_pin pin0 = rtlpriv->ledctl.sw_led0;
807
808 if (rtlpriv->rtlhal.up_first_time)
809 return;
810
811 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
812 rtl88ee_sw_led_on(hw, pin0);
813 else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
814 rtl88ee_sw_led_on(hw, pin0);
815 else
816 rtl88ee_sw_led_off(hw, pin0);
817 }
818
_rtl88ee_init_mac(struct ieee80211_hw * hw)819 static bool _rtl88ee_init_mac(struct ieee80211_hw *hw)
820 {
821 struct rtl_priv *rtlpriv = rtl_priv(hw);
822 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
823 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
824
825 u8 bytetmp;
826 u16 wordtmp;
827
828 /*Disable XTAL OUTPUT for power saving. YJ,add,111206. */
829 bytetmp = rtl_read_byte(rtlpriv, REG_XCK_OUT_CTRL) & (~BIT(0));
830 rtl_write_byte(rtlpriv, REG_XCK_OUT_CTRL, bytetmp);
831 /*Auto Power Down to CHIP-off State*/
832 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) & (~BIT(7));
833 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
834
835 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
836 /* HW Power on sequence */
837 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK,
838 PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,
839 RTL8188EE_NIC_ENABLE_FLOW)) {
840 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
841 "init MAC Fail as rtl_hal_pwrseqcmdparsing\n");
842 return false;
843 }
844
845 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO) | BIT(4);
846 rtl_write_byte(rtlpriv, REG_APS_FSMCO, bytetmp);
847
848 bytetmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG+2);
849 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG+2, bytetmp|BIT(2));
850
851 bytetmp = rtl_read_byte(rtlpriv, REG_WATCH_DOG+1);
852 rtl_write_byte(rtlpriv, REG_WATCH_DOG+1, bytetmp|BIT(7));
853
854 bytetmp = rtl_read_byte(rtlpriv, REG_AFE_XTAL_CTRL_EXT+1);
855 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL_EXT+1, bytetmp|BIT(1));
856
857 bytetmp = rtl_read_byte(rtlpriv, REG_TX_RPT_CTRL);
858 rtl_write_byte(rtlpriv, REG_TX_RPT_CTRL, bytetmp|BIT(1)|BIT(0));
859 rtl_write_byte(rtlpriv, REG_TX_RPT_CTRL+1, 2);
860 rtl_write_word(rtlpriv, REG_TX_RPT_TIME, 0xcdf0);
861
862 /*Add for wake up online*/
863 bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CLKR);
864
865 rtl_write_byte(rtlpriv, REG_SYS_CLKR, bytetmp|BIT(3));
866 bytetmp = rtl_read_byte(rtlpriv, REG_GPIO_MUXCFG+1);
867 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG+1, (bytetmp & (~BIT(4))));
868 rtl_write_byte(rtlpriv, 0x367, 0x80);
869
870 rtl_write_word(rtlpriv, REG_CR, 0x2ff);
871 rtl_write_byte(rtlpriv, REG_CR+1, 0x06);
872 rtl_write_byte(rtlpriv, MSR, 0x00);
873
874 if (!rtlhal->mac_func_enable) {
875 if (!_rtl88ee_llt_table_init(hw)) {
876 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
877 "LLT table init fail\n");
878 return false;
879 }
880 }
881 rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
882 rtl_write_dword(rtlpriv, REG_HISRE, 0xffffffff);
883
884 wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
885 wordtmp &= 0xf;
886 wordtmp |= 0xE771;
887 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
888
889 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
890 rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xffff);
891 rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);
892
893 rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
894 ((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) &
895 DMA_BIT_MASK(32));
896 rtl_write_dword(rtlpriv, REG_MGQ_DESA,
897 (u64) rtlpci->tx_ring[MGNT_QUEUE].dma &
898 DMA_BIT_MASK(32));
899 rtl_write_dword(rtlpriv, REG_VOQ_DESA,
900 (u64) rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
901 rtl_write_dword(rtlpriv, REG_VIQ_DESA,
902 (u64) rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
903 rtl_write_dword(rtlpriv, REG_BEQ_DESA,
904 (u64) rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
905 rtl_write_dword(rtlpriv, REG_BKQ_DESA,
906 (u64) rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
907 rtl_write_dword(rtlpriv, REG_HQ_DESA,
908 (u64) rtlpci->tx_ring[HIGH_QUEUE].dma &
909 DMA_BIT_MASK(32));
910 rtl_write_dword(rtlpriv, REG_RX_DESA,
911 (u64) rtlpci->rx_ring[RX_MPDU_QUEUE].dma &
912 DMA_BIT_MASK(32));
913
914 /* if we want to support 64 bit DMA, we should set it here,
915 * but now we do not support 64 bit DMA
916 */
917 rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
918
919 rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);
920 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG+1, 0);/*Enable RX DMA */
921
922 if (rtlhal->earlymode_enable) {/*Early mode enable*/
923 bytetmp = rtl_read_byte(rtlpriv, REG_EARLY_MODE_CONTROL);
924 bytetmp |= 0x1f;
925 rtl_write_byte(rtlpriv, REG_EARLY_MODE_CONTROL, bytetmp);
926 rtl_write_byte(rtlpriv, REG_EARLY_MODE_CONTROL+3, 0x81);
927 }
928 _rtl88ee_gen_refresh_led_state(hw);
929 return true;
930 }
931
_rtl88ee_hw_configure(struct ieee80211_hw * hw)932 static void _rtl88ee_hw_configure(struct ieee80211_hw *hw)
933 {
934 struct rtl_priv *rtlpriv = rtl_priv(hw);
935 u32 reg_prsr;
936
937 reg_prsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
938
939 rtl_write_dword(rtlpriv, REG_RRSR, reg_prsr);
940 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
941 }
942
_rtl88ee_enable_aspm_back_door(struct ieee80211_hw * hw)943 static void _rtl88ee_enable_aspm_back_door(struct ieee80211_hw *hw)
944 {
945 struct rtl_priv *rtlpriv = rtl_priv(hw);
946 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
947 u8 tmp1byte = 0;
948 u32 tmp4byte = 0, count = 0;
949
950 rtl_write_word(rtlpriv, 0x354, 0x8104);
951 rtl_write_word(rtlpriv, 0x358, 0x24);
952
953 rtl_write_word(rtlpriv, 0x350, 0x70c);
954 rtl_write_byte(rtlpriv, 0x352, 0x2);
955 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
956 count = 0;
957 while (tmp1byte && count < 20) {
958 udelay(10);
959 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
960 count++;
961 }
962 if (0 == tmp1byte) {
963 tmp4byte = rtl_read_dword(rtlpriv, 0x34c);
964 rtl_write_dword(rtlpriv, 0x348, tmp4byte|BIT(31));
965 rtl_write_word(rtlpriv, 0x350, 0xf70c);
966 rtl_write_byte(rtlpriv, 0x352, 0x1);
967 }
968
969 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
970 count = 0;
971 while (tmp1byte && count < 20) {
972 udelay(10);
973 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
974 count++;
975 }
976
977 rtl_write_word(rtlpriv, 0x350, 0x718);
978 rtl_write_byte(rtlpriv, 0x352, 0x2);
979 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
980 count = 0;
981 while (tmp1byte && count < 20) {
982 udelay(10);
983 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
984 count++;
985 }
986
987 if (ppsc->support_backdoor || (0 == tmp1byte)) {
988 tmp4byte = rtl_read_dword(rtlpriv, 0x34c);
989 rtl_write_dword(rtlpriv, 0x348, tmp4byte|BIT(11)|BIT(12));
990 rtl_write_word(rtlpriv, 0x350, 0xf718);
991 rtl_write_byte(rtlpriv, 0x352, 0x1);
992 }
993
994 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
995 count = 0;
996 while (tmp1byte && count < 20) {
997 udelay(10);
998 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
999 count++;
1000 }
1001 }
1002
rtl88ee_enable_hw_security_config(struct ieee80211_hw * hw)1003 void rtl88ee_enable_hw_security_config(struct ieee80211_hw *hw)
1004 {
1005 struct rtl_priv *rtlpriv = rtl_priv(hw);
1006 u8 sec_reg_value;
1007
1008 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1009 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
1010 rtlpriv->sec.pairwise_enc_algorithm,
1011 rtlpriv->sec.group_enc_algorithm);
1012
1013 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
1014 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
1015 "not open hw encryption\n");
1016 return;
1017 }
1018
1019 sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE;
1020
1021 if (rtlpriv->sec.use_defaultkey) {
1022 sec_reg_value |= SCR_TXUSEDK;
1023 sec_reg_value |= SCR_RXUSEDK;
1024 }
1025
1026 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
1027
1028 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
1029
1030 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
1031 "The SECR-value %x\n", sec_reg_value);
1032
1033 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
1034 }
1035
rtl88ee_hw_init(struct ieee80211_hw * hw)1036 int rtl88ee_hw_init(struct ieee80211_hw *hw)
1037 {
1038 struct rtl_priv *rtlpriv = rtl_priv(hw);
1039 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1040 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1041 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1042 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1043 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1044 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1045 bool rtstatus;
1046 int err = 0;
1047 u8 tmp_u1b, u1byte;
1048 unsigned long flags;
1049
1050 rtlpriv->rtlhal.being_init_adapter = true;
1051 /* As this function can take a very long time (up to 350 ms)
1052 * and can be called with irqs disabled, reenable the irqs
1053 * to let the other devices continue being serviced.
1054 *
1055 * It is safe doing so since our own interrupts will only be enabled
1056 * in a subsequent step.
1057 */
1058 local_save_flags(flags);
1059 local_irq_enable();
1060 rtlhal->fw_ready = false;
1061
1062 rtlpriv->intf_ops->disable_aspm(hw);
1063
1064 tmp_u1b = rtl_read_byte(rtlpriv, REG_SYS_CLKR+1);
1065 u1byte = rtl_read_byte(rtlpriv, REG_CR);
1066 if ((tmp_u1b & BIT(3)) && (u1byte != 0 && u1byte != 0xEA)) {
1067 rtlhal->mac_func_enable = true;
1068 } else {
1069 rtlhal->mac_func_enable = false;
1070 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_88E;
1071 }
1072
1073 rtstatus = _rtl88ee_init_mac(hw);
1074 if (!rtstatus) {
1075 pr_info("Init MAC failed\n");
1076 err = 1;
1077 goto exit;
1078 }
1079
1080 err = rtl88e_download_fw(hw, false);
1081 if (err) {
1082 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1083 "Failed to download FW. Init HW without FW now..\n");
1084 err = 1;
1085 goto exit;
1086 }
1087 rtlhal->fw_ready = true;
1088 /*fw related variable initialize */
1089 rtlhal->last_hmeboxnum = 0;
1090 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_88E;
1091 rtlhal->fw_clk_change_in_progress = false;
1092 rtlhal->allow_sw_to_change_hwclc = false;
1093 ppsc->fw_current_inpsmode = false;
1094
1095 rtl88e_phy_mac_config(hw);
1096 /* because last function modify RCR, so we update
1097 * rcr var here, or TP will unstable for receive_config
1098 * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx
1099 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252
1100 */
1101 rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
1102 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
1103
1104 rtl88e_phy_bb_config(hw);
1105 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
1106 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
1107
1108 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
1109 rtl88e_phy_rf_config(hw);
1110
1111 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
1112 RF_CHNLBW, RFREG_OFFSET_MASK);
1113 rtlphy->rfreg_chnlval[0] = rtlphy->rfreg_chnlval[0] & 0xfff00fff;
1114
1115 _rtl88ee_hw_configure(hw);
1116 rtl_cam_reset_all_entry(hw);
1117 rtl88ee_enable_hw_security_config(hw);
1118
1119 rtlhal->mac_func_enable = true;
1120 ppsc->rfpwr_state = ERFON;
1121
1122 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1123 _rtl88ee_enable_aspm_back_door(hw);
1124 rtlpriv->intf_ops->enable_aspm(hw);
1125
1126 if (ppsc->rfpwr_state == ERFON) {
1127 if ((rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV) ||
1128 ((rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV) &&
1129 (rtlhal->oem_id == RT_CID_819X_HP))) {
1130 rtl88e_phy_set_rfpath_switch(hw, true);
1131 rtlpriv->dm.fat_table.rx_idle_ant = MAIN_ANT;
1132 } else {
1133 rtl88e_phy_set_rfpath_switch(hw, false);
1134 rtlpriv->dm.fat_table.rx_idle_ant = AUX_ANT;
1135 }
1136 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "rx idle ant %s\n",
1137 (rtlpriv->dm.fat_table.rx_idle_ant == MAIN_ANT) ?
1138 ("MAIN_ANT") : ("AUX_ANT"));
1139
1140 if (rtlphy->iqk_initialized) {
1141 rtl88e_phy_iq_calibrate(hw, true);
1142 } else {
1143 rtl88e_phy_iq_calibrate(hw, false);
1144 rtlphy->iqk_initialized = true;
1145 }
1146
1147 rtl88e_dm_check_txpower_tracking(hw);
1148 rtl88e_phy_lc_calibrate(hw);
1149 }
1150
1151 tmp_u1b = efuse_read_1byte(hw, 0x1FA);
1152 if (!(tmp_u1b & BIT(0))) {
1153 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0F, 0x05);
1154 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "PA BIAS path A\n");
1155 }
1156
1157 if (!(tmp_u1b & BIT(4))) {
1158 tmp_u1b = rtl_read_byte(rtlpriv, 0x16);
1159 tmp_u1b &= 0x0F;
1160 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x80);
1161 udelay(10);
1162 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x90);
1163 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "under 1.5V\n");
1164 }
1165 rtl_write_byte(rtlpriv, REG_NAV_CTRL+2, ((30000+127)/128));
1166 rtl88e_dm_init(hw);
1167 exit:
1168 local_irq_restore(flags);
1169 rtlpriv->rtlhal.being_init_adapter = false;
1170 return err;
1171 }
1172
_rtl88ee_read_chip_version(struct ieee80211_hw * hw)1173 static enum version_8188e _rtl88ee_read_chip_version(struct ieee80211_hw *hw)
1174 {
1175 struct rtl_priv *rtlpriv = rtl_priv(hw);
1176 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1177 enum version_8188e version = VERSION_UNKNOWN;
1178 u32 value32;
1179
1180 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
1181 if (value32 & TRP_VAUX_EN) {
1182 version = (enum version_8188e) VERSION_TEST_CHIP_88E;
1183 } else {
1184 version = NORMAL_CHIP;
1185 version = version | ((value32 & TYPE_ID) ? RF_TYPE_2T2R : 0);
1186 version = version | ((value32 & VENDOR_ID) ?
1187 CHIP_VENDOR_UMC : 0);
1188 }
1189
1190 rtlphy->rf_type = RF_1T1R;
1191 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1192 "Chip RF Type: %s\n", (rtlphy->rf_type == RF_2T2R) ?
1193 "RF_2T2R" : "RF_1T1R");
1194
1195 return version;
1196 }
1197
_rtl88ee_set_media_status(struct ieee80211_hw * hw,enum nl80211_iftype type)1198 static int _rtl88ee_set_media_status(struct ieee80211_hw *hw,
1199 enum nl80211_iftype type)
1200 {
1201 struct rtl_priv *rtlpriv = rtl_priv(hw);
1202 u8 bt_msr = rtl_read_byte(rtlpriv, MSR) & 0xfc;
1203 enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1204 u8 mode = MSR_NOLINK;
1205
1206 switch (type) {
1207 case NL80211_IFTYPE_UNSPECIFIED:
1208 mode = MSR_NOLINK;
1209 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1210 "Set Network type to NO LINK!\n");
1211 break;
1212 case NL80211_IFTYPE_ADHOC:
1213 case NL80211_IFTYPE_MESH_POINT:
1214 mode = MSR_ADHOC;
1215 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1216 "Set Network type to Ad Hoc!\n");
1217 break;
1218 case NL80211_IFTYPE_STATION:
1219 mode = MSR_INFRA;
1220 ledaction = LED_CTL_LINK;
1221 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1222 "Set Network type to STA!\n");
1223 break;
1224 case NL80211_IFTYPE_AP:
1225 mode = MSR_AP;
1226 ledaction = LED_CTL_LINK;
1227 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1228 "Set Network type to AP!\n");
1229 break;
1230 default:
1231 pr_err("Network type %d not support!\n", type);
1232 return 1;
1233 }
1234
1235 /* MSR_INFRA == Link in infrastructure network;
1236 * MSR_ADHOC == Link in ad hoc network;
1237 * Therefore, check link state is necessary.
1238 *
1239 * MSR_AP == AP mode; link state is not cared here.
1240 */
1241 if (mode != MSR_AP && rtlpriv->mac80211.link_state < MAC80211_LINKED) {
1242 mode = MSR_NOLINK;
1243 ledaction = LED_CTL_NO_LINK;
1244 }
1245
1246 if (mode == MSR_NOLINK || mode == MSR_INFRA) {
1247 _rtl88ee_stop_tx_beacon(hw);
1248 _rtl88ee_enable_bcn_sub_func(hw);
1249 } else if (mode == MSR_ADHOC || mode == MSR_AP) {
1250 _rtl88ee_resume_tx_beacon(hw);
1251 _rtl88ee_disable_bcn_sub_func(hw);
1252 } else {
1253 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1254 "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",
1255 mode);
1256 }
1257
1258 rtl_write_byte(rtlpriv, MSR, bt_msr | mode);
1259 rtlpriv->cfg->ops->led_control(hw, ledaction);
1260 if (mode == MSR_AP)
1261 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1262 else
1263 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1264 return 0;
1265 }
1266
rtl88ee_set_check_bssid(struct ieee80211_hw * hw,bool check_bssid)1267 void rtl88ee_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1268 {
1269 struct rtl_priv *rtlpriv = rtl_priv(hw);
1270 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1271 u32 reg_rcr = rtlpci->receive_config;
1272
1273 if (rtlpriv->psc.rfpwr_state != ERFON)
1274 return;
1275
1276 if (check_bssid) {
1277 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1278 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1279 (u8 *)(®_rcr));
1280 _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(4));
1281 } else if (!check_bssid) {
1282 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1283 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(4), 0);
1284 rtlpriv->cfg->ops->set_hw_reg(hw,
1285 HW_VAR_RCR, (u8 *)(®_rcr));
1286 }
1287
1288 }
1289
rtl88ee_set_network_type(struct ieee80211_hw * hw,enum nl80211_iftype type)1290 int rtl88ee_set_network_type(struct ieee80211_hw *hw,
1291 enum nl80211_iftype type)
1292 {
1293 struct rtl_priv *rtlpriv = rtl_priv(hw);
1294
1295 if (_rtl88ee_set_media_status(hw, type))
1296 return -EOPNOTSUPP;
1297
1298 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1299 if (type != NL80211_IFTYPE_AP &&
1300 type != NL80211_IFTYPE_MESH_POINT)
1301 rtl88ee_set_check_bssid(hw, true);
1302 } else {
1303 rtl88ee_set_check_bssid(hw, false);
1304 }
1305
1306 return 0;
1307 }
1308
1309 /* don't set REG_EDCA_BE_PARAM here
1310 * because mac80211 will send pkt when scan
1311 */
rtl88ee_set_qos(struct ieee80211_hw * hw,int aci)1312 void rtl88ee_set_qos(struct ieee80211_hw *hw, int aci)
1313 {
1314 struct rtl_priv *rtlpriv = rtl_priv(hw);
1315 rtl88e_dm_init_edca_turbo(hw);
1316 switch (aci) {
1317 case AC1_BK:
1318 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
1319 break;
1320 case AC0_BE:
1321 break;
1322 case AC2_VI:
1323 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
1324 break;
1325 case AC3_VO:
1326 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
1327 break;
1328 default:
1329 WARN_ONCE(true, "rtl8188ee: invalid aci: %d !\n", aci);
1330 break;
1331 }
1332 }
1333
rtl88ee_enable_interrupt(struct ieee80211_hw * hw)1334 void rtl88ee_enable_interrupt(struct ieee80211_hw *hw)
1335 {
1336 struct rtl_priv *rtlpriv = rtl_priv(hw);
1337 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1338
1339 rtl_write_dword(rtlpriv, REG_HIMR,
1340 rtlpci->irq_mask[0] & 0xFFFFFFFF);
1341 rtl_write_dword(rtlpriv, REG_HIMRE,
1342 rtlpci->irq_mask[1] & 0xFFFFFFFF);
1343 rtlpci->irq_enabled = true;
1344 /* there are some C2H CMDs have been sent
1345 * before system interrupt is enabled, e.g., C2H, CPWM.
1346 * So we need to clear all C2H events that FW has notified,
1347 * otherwise FW won't schedule any commands anymore.
1348 */
1349 rtl_write_byte(rtlpriv, REG_C2HEVT_CLEAR, 0);
1350 /*enable system interrupt*/
1351 rtl_write_dword(rtlpriv, REG_HSIMR,
1352 rtlpci->sys_irq_mask & 0xFFFFFFFF);
1353 }
1354
rtl88ee_disable_interrupt(struct ieee80211_hw * hw)1355 void rtl88ee_disable_interrupt(struct ieee80211_hw *hw)
1356 {
1357 struct rtl_priv *rtlpriv = rtl_priv(hw);
1358 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1359
1360 rtl_write_dword(rtlpriv, REG_HIMR, IMR_DISABLED);
1361 rtl_write_dword(rtlpriv, REG_HIMRE, IMR_DISABLED);
1362 rtlpci->irq_enabled = false;
1363 /*synchronize_irq(rtlpci->pdev->irq);*/
1364 }
1365
_rtl88ee_poweroff_adapter(struct ieee80211_hw * hw)1366 static void _rtl88ee_poweroff_adapter(struct ieee80211_hw *hw)
1367 {
1368 struct rtl_priv *rtlpriv = rtl_priv(hw);
1369 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1370 u8 u1b_tmp;
1371 u32 count = 0;
1372 rtlhal->mac_func_enable = false;
1373 rtlpriv->intf_ops->enable_aspm(hw);
1374
1375 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "POWER OFF adapter\n");
1376 u1b_tmp = rtl_read_byte(rtlpriv, REG_TX_RPT_CTRL);
1377 rtl_write_byte(rtlpriv, REG_TX_RPT_CTRL, u1b_tmp & (~BIT(1)));
1378
1379 u1b_tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1380 while (!(u1b_tmp & BIT(1)) && (count++ < 100)) {
1381 udelay(10);
1382 u1b_tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1383 count++;
1384 }
1385 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG+1, 0xFF);
1386
1387 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1388 PWR_INTF_PCI_MSK,
1389 RTL8188EE_NIC_LPS_ENTER_FLOW);
1390
1391 rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00);
1392
1393 if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) && rtlhal->fw_ready)
1394 rtl88e_firmware_selfreset(hw);
1395
1396 u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN+1);
1397 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, (u1b_tmp & (~BIT(2))));
1398 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1399
1400 u1b_tmp = rtl_read_byte(rtlpriv, REG_32K_CTRL);
1401 rtl_write_byte(rtlpriv, REG_32K_CTRL, (u1b_tmp & (~BIT(0))));
1402
1403 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1404 PWR_INTF_PCI_MSK, RTL8188EE_NIC_DISABLE_FLOW);
1405
1406 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL+1);
1407 rtl_write_byte(rtlpriv, REG_RSV_CTRL+1, (u1b_tmp & (~BIT(3))));
1408 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL+1);
1409 rtl_write_byte(rtlpriv, REG_RSV_CTRL+1, (u1b_tmp | BIT(3)));
1410
1411 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0E);
1412
1413 u1b_tmp = rtl_read_byte(rtlpriv, GPIO_IN);
1414 rtl_write_byte(rtlpriv, GPIO_OUT, u1b_tmp);
1415 rtl_write_byte(rtlpriv, GPIO_IO_SEL, 0x7F);
1416
1417 u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL);
1418 rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL, (u1b_tmp << 4) | u1b_tmp);
1419 u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL+1);
1420 rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL+1, u1b_tmp | 0x0F);
1421
1422 rtl_write_dword(rtlpriv, REG_GPIO_IO_SEL_2+2, 0x00080808);
1423 }
1424
rtl88ee_card_disable(struct ieee80211_hw * hw)1425 void rtl88ee_card_disable(struct ieee80211_hw *hw)
1426 {
1427 struct rtl_priv *rtlpriv = rtl_priv(hw);
1428 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1429 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1430 enum nl80211_iftype opmode;
1431
1432 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "RTL8188ee card disable\n");
1433
1434 mac->link_state = MAC80211_NOLINK;
1435 opmode = NL80211_IFTYPE_UNSPECIFIED;
1436
1437 _rtl88ee_set_media_status(hw, opmode);
1438
1439 if (rtlpriv->rtlhal.driver_is_goingto_unload ||
1440 ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1441 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1442
1443 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1444 _rtl88ee_poweroff_adapter(hw);
1445
1446 /* after power off we should do iqk again */
1447 rtlpriv->phy.iqk_initialized = false;
1448 }
1449
rtl88ee_interrupt_recognized(struct ieee80211_hw * hw,struct rtl_int * intvec)1450 void rtl88ee_interrupt_recognized(struct ieee80211_hw *hw,
1451 struct rtl_int *intvec)
1452 {
1453 struct rtl_priv *rtlpriv = rtl_priv(hw);
1454 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1455
1456 intvec->inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1457 rtl_write_dword(rtlpriv, ISR, intvec->inta);
1458
1459 intvec->intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1];
1460 rtl_write_dword(rtlpriv, REG_HISRE, intvec->intb);
1461
1462 }
1463
rtl88ee_set_beacon_related_registers(struct ieee80211_hw * hw)1464 void rtl88ee_set_beacon_related_registers(struct ieee80211_hw *hw)
1465 {
1466 struct rtl_priv *rtlpriv = rtl_priv(hw);
1467 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1468 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1469 u16 bcn_interval, atim_window;
1470
1471 bcn_interval = mac->beacon_interval;
1472 atim_window = 2; /*FIX MERGE */
1473 rtl88ee_disable_interrupt(hw);
1474 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1475 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1476 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
1477 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
1478 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
1479 rtl_write_byte(rtlpriv, 0x606, 0x30);
1480 rtlpci->reg_bcn_ctrl_val |= BIT(3);
1481 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val);
1482 /*rtl88ee_enable_interrupt(hw);*/
1483 }
1484
rtl88ee_set_beacon_interval(struct ieee80211_hw * hw)1485 void rtl88ee_set_beacon_interval(struct ieee80211_hw *hw)
1486 {
1487 struct rtl_priv *rtlpriv = rtl_priv(hw);
1488 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1489 u16 bcn_interval = mac->beacon_interval;
1490
1491 rtl_dbg(rtlpriv, COMP_BEACON, DBG_DMESG,
1492 "beacon_interval:%d\n", bcn_interval);
1493 /*rtl88ee_disable_interrupt(hw);*/
1494 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1495 /*rtl88ee_enable_interrupt(hw);*/
1496 }
1497
rtl88ee_update_interrupt_mask(struct ieee80211_hw * hw,u32 add_msr,u32 rm_msr)1498 void rtl88ee_update_interrupt_mask(struct ieee80211_hw *hw,
1499 u32 add_msr, u32 rm_msr)
1500 {
1501 struct rtl_priv *rtlpriv = rtl_priv(hw);
1502 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1503
1504 rtl_dbg(rtlpriv, COMP_INTR, DBG_LOUD,
1505 "add_msr:%x, rm_msr:%x\n", add_msr, rm_msr);
1506
1507 if (add_msr)
1508 rtlpci->irq_mask[0] |= add_msr;
1509 if (rm_msr)
1510 rtlpci->irq_mask[0] &= (~rm_msr);
1511 rtl88ee_disable_interrupt(hw);
1512 rtl88ee_enable_interrupt(hw);
1513 }
1514
_rtl88e_get_chnl_group(u8 chnl)1515 static u8 _rtl88e_get_chnl_group(u8 chnl)
1516 {
1517 u8 group = 0;
1518
1519 if (chnl < 3)
1520 group = 0;
1521 else if (chnl < 6)
1522 group = 1;
1523 else if (chnl < 9)
1524 group = 2;
1525 else if (chnl < 12)
1526 group = 3;
1527 else if (chnl < 14)
1528 group = 4;
1529 else if (chnl == 14)
1530 group = 5;
1531
1532 return group;
1533 }
1534
set_24g_base(struct txpower_info_2g * pwrinfo24g,u32 rfpath)1535 static void set_24g_base(struct txpower_info_2g *pwrinfo24g, u32 rfpath)
1536 {
1537 int group, txcnt;
1538
1539 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
1540 pwrinfo24g->index_cck_base[rfpath][group] = 0x2D;
1541 pwrinfo24g->index_bw40_base[rfpath][group] = 0x2D;
1542 }
1543 for (txcnt = 0; txcnt < MAX_TX_COUNT; txcnt++) {
1544 if (txcnt == 0) {
1545 pwrinfo24g->bw20_diff[rfpath][0] = 0x02;
1546 pwrinfo24g->ofdm_diff[rfpath][0] = 0x04;
1547 } else {
1548 pwrinfo24g->bw20_diff[rfpath][txcnt] = 0xFE;
1549 pwrinfo24g->bw40_diff[rfpath][txcnt] = 0xFE;
1550 pwrinfo24g->cck_diff[rfpath][txcnt] = 0xFE;
1551 pwrinfo24g->ofdm_diff[rfpath][txcnt] = 0xFE;
1552 }
1553 }
1554 }
1555
read_power_value_fromprom(struct ieee80211_hw * hw,struct txpower_info_2g * pwrinfo24g,struct txpower_info_5g * pwrinfo5g,bool autoload_fail,u8 * hwinfo)1556 static void read_power_value_fromprom(struct ieee80211_hw *hw,
1557 struct txpower_info_2g *pwrinfo24g,
1558 struct txpower_info_5g *pwrinfo5g,
1559 bool autoload_fail, u8 *hwinfo)
1560 {
1561 struct rtl_priv *rtlpriv = rtl_priv(hw);
1562 u32 rfpath, eeaddr = EEPROM_TX_PWR_INX, group, txcnt = 0;
1563
1564 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1565 "hal_ReadPowerValueFromPROM88E():PROMContent[0x%x]=0x%x\n",
1566 (eeaddr + 1), hwinfo[eeaddr + 1]);
1567 if (0xFF == hwinfo[eeaddr+1]) /*YJ,add,120316*/
1568 autoload_fail = true;
1569
1570 if (autoload_fail) {
1571 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1572 "auto load fail : Use Default value!\n");
1573 for (rfpath = 0 ; rfpath < MAX_RF_PATH ; rfpath++) {
1574 /* 2.4G default value */
1575 set_24g_base(pwrinfo24g, rfpath);
1576 }
1577 return;
1578 }
1579
1580 for (rfpath = 0 ; rfpath < MAX_RF_PATH ; rfpath++) {
1581 /*2.4G default value*/
1582 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
1583 pwrinfo24g->index_cck_base[rfpath][group] =
1584 hwinfo[eeaddr++];
1585 if (pwrinfo24g->index_cck_base[rfpath][group] == 0xFF)
1586 pwrinfo24g->index_cck_base[rfpath][group] =
1587 0x2D;
1588 }
1589 for (group = 0 ; group < MAX_CHNL_GROUP_24G-1; group++) {
1590 pwrinfo24g->index_bw40_base[rfpath][group] =
1591 hwinfo[eeaddr++];
1592 if (pwrinfo24g->index_bw40_base[rfpath][group] == 0xFF)
1593 pwrinfo24g->index_bw40_base[rfpath][group] =
1594 0x2D;
1595 }
1596 pwrinfo24g->bw40_diff[rfpath][0] = 0;
1597 if (hwinfo[eeaddr] == 0xFF) {
1598 pwrinfo24g->bw20_diff[rfpath][0] = 0x02;
1599 } else {
1600 pwrinfo24g->bw20_diff[rfpath][0] =
1601 (hwinfo[eeaddr]&0xf0)>>4;
1602 /*bit sign number to 8 bit sign number*/
1603 if (pwrinfo24g->bw20_diff[rfpath][0] & BIT(3))
1604 pwrinfo24g->bw20_diff[rfpath][0] |= 0xF0;
1605 }
1606
1607 if (hwinfo[eeaddr] == 0xFF) {
1608 pwrinfo24g->ofdm_diff[rfpath][0] = 0x04;
1609 } else {
1610 pwrinfo24g->ofdm_diff[rfpath][0] =
1611 (hwinfo[eeaddr]&0x0f);
1612 /*bit sign number to 8 bit sign number*/
1613 if (pwrinfo24g->ofdm_diff[rfpath][0] & BIT(3))
1614 pwrinfo24g->ofdm_diff[rfpath][0] |= 0xF0;
1615 }
1616 pwrinfo24g->cck_diff[rfpath][0] = 0;
1617 eeaddr++;
1618 for (txcnt = 1; txcnt < MAX_TX_COUNT; txcnt++) {
1619 if (hwinfo[eeaddr] == 0xFF) {
1620 pwrinfo24g->bw40_diff[rfpath][txcnt] = 0xFE;
1621 } else {
1622 pwrinfo24g->bw40_diff[rfpath][txcnt] =
1623 (hwinfo[eeaddr]&0xf0)>>4;
1624 if (pwrinfo24g->bw40_diff[rfpath][txcnt] &
1625 BIT(3))
1626 pwrinfo24g->bw40_diff[rfpath][txcnt] |=
1627 0xF0;
1628 }
1629
1630 if (hwinfo[eeaddr] == 0xFF) {
1631 pwrinfo24g->bw20_diff[rfpath][txcnt] =
1632 0xFE;
1633 } else {
1634 pwrinfo24g->bw20_diff[rfpath][txcnt] =
1635 (hwinfo[eeaddr]&0x0f);
1636 if (pwrinfo24g->bw20_diff[rfpath][txcnt] &
1637 BIT(3))
1638 pwrinfo24g->bw20_diff[rfpath][txcnt] |=
1639 0xF0;
1640 }
1641 eeaddr++;
1642
1643 if (hwinfo[eeaddr] == 0xFF) {
1644 pwrinfo24g->ofdm_diff[rfpath][txcnt] = 0xFE;
1645 } else {
1646 pwrinfo24g->ofdm_diff[rfpath][txcnt] =
1647 (hwinfo[eeaddr]&0xf0)>>4;
1648 if (pwrinfo24g->ofdm_diff[rfpath][txcnt] &
1649 BIT(3))
1650 pwrinfo24g->ofdm_diff[rfpath][txcnt] |=
1651 0xF0;
1652 }
1653
1654 if (hwinfo[eeaddr] == 0xFF) {
1655 pwrinfo24g->cck_diff[rfpath][txcnt] = 0xFE;
1656 } else {
1657 pwrinfo24g->cck_diff[rfpath][txcnt] =
1658 (hwinfo[eeaddr]&0x0f);
1659 if (pwrinfo24g->cck_diff[rfpath][txcnt] &
1660 BIT(3))
1661 pwrinfo24g->cck_diff[rfpath][txcnt] |=
1662 0xF0;
1663 }
1664 eeaddr++;
1665 }
1666
1667 /*5G default value*/
1668 for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++) {
1669 pwrinfo5g->index_bw40_base[rfpath][group] =
1670 hwinfo[eeaddr++];
1671 if (pwrinfo5g->index_bw40_base[rfpath][group] == 0xFF)
1672 pwrinfo5g->index_bw40_base[rfpath][group] =
1673 0xFE;
1674 }
1675
1676 pwrinfo5g->bw40_diff[rfpath][0] = 0;
1677
1678 if (hwinfo[eeaddr] == 0xFF) {
1679 pwrinfo5g->bw20_diff[rfpath][0] = 0;
1680 } else {
1681 pwrinfo5g->bw20_diff[rfpath][0] =
1682 (hwinfo[eeaddr]&0xf0)>>4;
1683 if (pwrinfo5g->bw20_diff[rfpath][0] & BIT(3))
1684 pwrinfo5g->bw20_diff[rfpath][0] |= 0xF0;
1685 }
1686
1687 if (hwinfo[eeaddr] == 0xFF) {
1688 pwrinfo5g->ofdm_diff[rfpath][0] = 0x04;
1689 } else {
1690 pwrinfo5g->ofdm_diff[rfpath][0] = (hwinfo[eeaddr]&0x0f);
1691 if (pwrinfo5g->ofdm_diff[rfpath][0] & BIT(3))
1692 pwrinfo5g->ofdm_diff[rfpath][0] |= 0xF0;
1693 }
1694 eeaddr++;
1695 for (txcnt = 1; txcnt < MAX_TX_COUNT; txcnt++) {
1696 if (hwinfo[eeaddr] == 0xFF) {
1697 pwrinfo5g->bw40_diff[rfpath][txcnt] = 0xFE;
1698 } else {
1699 pwrinfo5g->bw40_diff[rfpath][txcnt] =
1700 (hwinfo[eeaddr]&0xf0)>>4;
1701 if (pwrinfo5g->bw40_diff[rfpath][txcnt] &
1702 BIT(3))
1703 pwrinfo5g->bw40_diff[rfpath][txcnt] |=
1704 0xF0;
1705 }
1706
1707 if (hwinfo[eeaddr] == 0xFF) {
1708 pwrinfo5g->bw20_diff[rfpath][txcnt] = 0xFE;
1709 } else {
1710 pwrinfo5g->bw20_diff[rfpath][txcnt] =
1711 (hwinfo[eeaddr]&0x0f);
1712 if (pwrinfo5g->bw20_diff[rfpath][txcnt] &
1713 BIT(3))
1714 pwrinfo5g->bw20_diff[rfpath][txcnt] |=
1715 0xF0;
1716 }
1717 eeaddr++;
1718 }
1719
1720 if (hwinfo[eeaddr] == 0xFF) {
1721 pwrinfo5g->ofdm_diff[rfpath][1] = 0xFE;
1722 pwrinfo5g->ofdm_diff[rfpath][2] = 0xFE;
1723 } else {
1724 pwrinfo5g->ofdm_diff[rfpath][1] =
1725 (hwinfo[eeaddr]&0xf0)>>4;
1726 pwrinfo5g->ofdm_diff[rfpath][2] =
1727 (hwinfo[eeaddr]&0x0f);
1728 }
1729 eeaddr++;
1730
1731 if (hwinfo[eeaddr] == 0xFF)
1732 pwrinfo5g->ofdm_diff[rfpath][3] = 0xFE;
1733 else
1734 pwrinfo5g->ofdm_diff[rfpath][3] = (hwinfo[eeaddr]&0x0f);
1735 eeaddr++;
1736
1737 for (txcnt = 1; txcnt < MAX_TX_COUNT; txcnt++) {
1738 if (pwrinfo5g->ofdm_diff[rfpath][txcnt] == 0xFF)
1739 pwrinfo5g->ofdm_diff[rfpath][txcnt] = 0xFE;
1740 else if (pwrinfo5g->ofdm_diff[rfpath][txcnt] & BIT(3))
1741 pwrinfo5g->ofdm_diff[rfpath][txcnt] |= 0xF0;
1742 }
1743 }
1744 }
1745
_rtl88ee_read_txpower_info_from_hwpg(struct ieee80211_hw * hw,bool autoload_fail,u8 * hwinfo)1746 static void _rtl88ee_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1747 bool autoload_fail,
1748 u8 *hwinfo)
1749 {
1750 struct rtl_priv *rtlpriv = rtl_priv(hw);
1751 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1752 struct txpower_info_2g pwrinfo24g;
1753 struct txpower_info_5g pwrinfo5g;
1754 u8 rf_path, index;
1755 u8 i;
1756
1757 read_power_value_fromprom(hw, &pwrinfo24g,
1758 &pwrinfo5g, autoload_fail, hwinfo);
1759
1760 for (rf_path = 0; rf_path < 2; rf_path++) {
1761 for (i = 0; i < 14; i++) {
1762 index = _rtl88e_get_chnl_group(i+1);
1763
1764 rtlefuse->txpwrlevel_cck[rf_path][i] =
1765 pwrinfo24g.index_cck_base[rf_path][index];
1766 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
1767 pwrinfo24g.index_bw40_base[rf_path][index];
1768 rtlefuse->txpwr_ht20diff[rf_path][i] =
1769 pwrinfo24g.bw20_diff[rf_path][0];
1770 rtlefuse->txpwr_legacyhtdiff[rf_path][i] =
1771 pwrinfo24g.ofdm_diff[rf_path][0];
1772 }
1773
1774 for (i = 0; i < 14; i++) {
1775 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1776 "RF(%d)-Ch(%d) [CCK / HT40_1S ] = [0x%x / 0x%x ]\n",
1777 rf_path, i,
1778 rtlefuse->txpwrlevel_cck[rf_path][i],
1779 rtlefuse->txpwrlevel_ht40_1s[rf_path][i]);
1780 }
1781 }
1782
1783 if (!autoload_fail)
1784 rtlefuse->eeprom_thermalmeter =
1785 hwinfo[EEPROM_THERMAL_METER_88E];
1786 else
1787 rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
1788
1789 if (rtlefuse->eeprom_thermalmeter == 0xff || autoload_fail) {
1790 rtlefuse->apk_thermalmeterignore = true;
1791 rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
1792 }
1793
1794 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
1795 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1796 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
1797
1798 if (!autoload_fail) {
1799 rtlefuse->eeprom_regulatory =
1800 hwinfo[EEPROM_RF_BOARD_OPTION_88E] & 0x07;/*bit0~2*/
1801 if (hwinfo[EEPROM_RF_BOARD_OPTION_88E] == 0xFF)
1802 rtlefuse->eeprom_regulatory = 0;
1803 } else {
1804 rtlefuse->eeprom_regulatory = 0;
1805 }
1806 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1807 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
1808 }
1809
_rtl88ee_read_adapter_info(struct ieee80211_hw * hw)1810 static void _rtl88ee_read_adapter_info(struct ieee80211_hw *hw)
1811 {
1812 struct rtl_priv *rtlpriv = rtl_priv(hw);
1813 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1814 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1815 int params[] = {RTL8188E_EEPROM_ID, EEPROM_VID, EEPROM_DID,
1816 EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR,
1817 EEPROM_CHANNELPLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID,
1818 COUNTRY_CODE_WORLD_WIDE_13};
1819 u8 *hwinfo;
1820
1821 hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL);
1822 if (!hwinfo)
1823 return;
1824
1825 if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params))
1826 goto exit;
1827
1828 if (rtlefuse->eeprom_oemid == 0xFF)
1829 rtlefuse->eeprom_oemid = 0;
1830
1831 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1832 "EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid);
1833 /* set channel plan from efuse */
1834 rtlefuse->channel_plan = rtlefuse->eeprom_channelplan;
1835 /*tx power*/
1836 _rtl88ee_read_txpower_info_from_hwpg(hw,
1837 rtlefuse->autoload_failflag,
1838 hwinfo);
1839 rtlefuse->txpwr_fromeprom = true;
1840
1841 rtl8188ee_read_bt_coexist_info_from_hwpg(hw,
1842 rtlefuse->autoload_failflag,
1843 hwinfo);
1844
1845 /*board type*/
1846 rtlefuse->board_type =
1847 ((hwinfo[EEPROM_RF_BOARD_OPTION_88E] & 0xE0) >> 5);
1848 rtlhal->board_type = rtlefuse->board_type;
1849 /*Wake on wlan*/
1850 rtlefuse->wowlan_enable =
1851 ((hwinfo[EEPROM_RF_FEATURE_OPTION_88E] & 0x40) >> 6);
1852 /*parse xtal*/
1853 rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_88E];
1854 if (hwinfo[EEPROM_XTAL_88E])
1855 rtlefuse->crystalcap = 0x20;
1856 /*antenna diversity*/
1857 rtlefuse->antenna_div_cfg =
1858 (hwinfo[EEPROM_RF_BOARD_OPTION_88E] & 0x18) >> 3;
1859 if (hwinfo[EEPROM_RF_BOARD_OPTION_88E] == 0xFF)
1860 rtlefuse->antenna_div_cfg = 0;
1861 if (rtlpriv->btcoexist.eeprom_bt_coexist != 0 &&
1862 rtlpriv->btcoexist.eeprom_bt_ant_num == ANT_X1)
1863 rtlefuse->antenna_div_cfg = 0;
1864
1865 rtlefuse->antenna_div_type = hwinfo[EEPROM_RF_ANTENNA_OPT_88E];
1866 if (rtlefuse->antenna_div_type == 0xFF)
1867 rtlefuse->antenna_div_type = 0x01;
1868 if (rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV ||
1869 rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV)
1870 rtlefuse->antenna_div_cfg = 1;
1871
1872 if (rtlhal->oem_id == RT_CID_DEFAULT) {
1873 switch (rtlefuse->eeprom_oemid) {
1874 case EEPROM_CID_DEFAULT:
1875 if (rtlefuse->eeprom_did == 0x8179) {
1876 if (rtlefuse->eeprom_svid == 0x1025) {
1877 rtlhal->oem_id = RT_CID_819X_ACER;
1878 } else if ((rtlefuse->eeprom_svid == 0x10EC &&
1879 rtlefuse->eeprom_smid == 0x0179) ||
1880 (rtlefuse->eeprom_svid == 0x17AA &&
1881 rtlefuse->eeprom_smid == 0x0179)) {
1882 rtlhal->oem_id = RT_CID_819X_LENOVO;
1883 } else if (rtlefuse->eeprom_svid == 0x103c &&
1884 rtlefuse->eeprom_smid == 0x197d) {
1885 rtlhal->oem_id = RT_CID_819X_HP;
1886 } else {
1887 rtlhal->oem_id = RT_CID_DEFAULT;
1888 }
1889 } else {
1890 rtlhal->oem_id = RT_CID_DEFAULT;
1891 }
1892 break;
1893 case EEPROM_CID_TOSHIBA:
1894 rtlhal->oem_id = RT_CID_TOSHIBA;
1895 break;
1896 case EEPROM_CID_QMI:
1897 rtlhal->oem_id = RT_CID_819X_QMI;
1898 break;
1899 case EEPROM_CID_WHQL:
1900 default:
1901 rtlhal->oem_id = RT_CID_DEFAULT;
1902 break;
1903
1904 }
1905 }
1906 exit:
1907 kfree(hwinfo);
1908 }
1909
_rtl88ee_hal_customized_behavior(struct ieee80211_hw * hw)1910 static void _rtl88ee_hal_customized_behavior(struct ieee80211_hw *hw)
1911 {
1912 struct rtl_priv *rtlpriv = rtl_priv(hw);
1913 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1914
1915 rtlpriv->ledctl.led_opendrain = true;
1916
1917 switch (rtlhal->oem_id) {
1918 case RT_CID_819X_HP:
1919 rtlpriv->ledctl.led_opendrain = true;
1920 break;
1921 case RT_CID_819X_LENOVO:
1922 case RT_CID_DEFAULT:
1923 case RT_CID_TOSHIBA:
1924 case RT_CID_CCX:
1925 case RT_CID_819X_ACER:
1926 case RT_CID_WHQL:
1927 default:
1928 break;
1929 }
1930 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1931 "RT Customized ID: 0x%02X\n", rtlhal->oem_id);
1932 }
1933
rtl88ee_read_eeprom_info(struct ieee80211_hw * hw)1934 void rtl88ee_read_eeprom_info(struct ieee80211_hw *hw)
1935 {
1936 struct rtl_priv *rtlpriv = rtl_priv(hw);
1937 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1938 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1939 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1940 u8 tmp_u1b;
1941
1942 rtlhal->version = _rtl88ee_read_chip_version(hw);
1943 if (get_rf_type(rtlphy) == RF_1T1R)
1944 rtlpriv->dm.rfpath_rxenable[0] = true;
1945 else
1946 rtlpriv->dm.rfpath_rxenable[0] =
1947 rtlpriv->dm.rfpath_rxenable[1] = true;
1948 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
1949 rtlhal->version);
1950 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
1951 if (tmp_u1b & BIT(4)) {
1952 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
1953 rtlefuse->epromtype = EEPROM_93C46;
1954 } else {
1955 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
1956 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
1957 }
1958 if (tmp_u1b & BIT(5)) {
1959 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1960 rtlefuse->autoload_failflag = false;
1961 _rtl88ee_read_adapter_info(hw);
1962 } else {
1963 pr_err("Autoload ERR!!\n");
1964 }
1965 _rtl88ee_hal_customized_behavior(hw);
1966 }
1967
rtl88ee_update_hal_rate_table(struct ieee80211_hw * hw,struct ieee80211_sta * sta)1968 static void rtl88ee_update_hal_rate_table(struct ieee80211_hw *hw,
1969 struct ieee80211_sta *sta)
1970 {
1971 struct rtl_priv *rtlpriv = rtl_priv(hw);
1972 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1973 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1974 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1975 u32 ratr_value;
1976 u8 ratr_index = 0;
1977 u8 b_nmode = mac->ht_enable;
1978 /*u8 mimo_ps = IEEE80211_SMPS_OFF;*/
1979 u16 shortgi_rate;
1980 u32 tmp_ratr_value;
1981 u8 curtxbw_40mhz = mac->bw_40;
1982 u8 curshortgi_40mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1983 1 : 0;
1984 u8 curshortgi_20mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1985 1 : 0;
1986 enum wireless_mode wirelessmode = mac->mode;
1987 u32 ratr_mask;
1988
1989 if (rtlhal->current_bandtype == BAND_ON_5G)
1990 ratr_value = sta->deflink.supp_rates[1] << 4;
1991 else
1992 ratr_value = sta->deflink.supp_rates[0];
1993 if (mac->opmode == NL80211_IFTYPE_ADHOC)
1994 ratr_value = 0xfff;
1995 ratr_value |= (sta->deflink.ht_cap.mcs.rx_mask[1] << 20 |
1996 sta->deflink.ht_cap.mcs.rx_mask[0] << 12);
1997 switch (wirelessmode) {
1998 case WIRELESS_MODE_B:
1999 if (ratr_value & 0x0000000c)
2000 ratr_value &= 0x0000000d;
2001 else
2002 ratr_value &= 0x0000000f;
2003 break;
2004 case WIRELESS_MODE_G:
2005 ratr_value &= 0x00000FF5;
2006 break;
2007 case WIRELESS_MODE_N_24G:
2008 case WIRELESS_MODE_N_5G:
2009 b_nmode = 1;
2010 if (get_rf_type(rtlphy) == RF_1T2R ||
2011 get_rf_type(rtlphy) == RF_1T1R)
2012 ratr_mask = 0x000ff005;
2013 else
2014 ratr_mask = 0x0f0ff005;
2015
2016 ratr_value &= ratr_mask;
2017 break;
2018 default:
2019 if (rtlphy->rf_type == RF_1T2R)
2020 ratr_value &= 0x000ff0ff;
2021 else
2022 ratr_value &= 0x0f0ff0ff;
2023
2024 break;
2025 }
2026
2027 if ((rtlpriv->btcoexist.bt_coexistence) &&
2028 (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) &&
2029 (rtlpriv->btcoexist.bt_cur_state) &&
2030 (rtlpriv->btcoexist.bt_ant_isolation) &&
2031 ((rtlpriv->btcoexist.bt_service == BT_SCO) ||
2032 (rtlpriv->btcoexist.bt_service == BT_BUSY)))
2033 ratr_value &= 0x0fffcfc0;
2034 else
2035 ratr_value &= 0x0FFFFFFF;
2036
2037 if (b_nmode &&
2038 ((curtxbw_40mhz && curshortgi_40mhz) ||
2039 (!curtxbw_40mhz && curshortgi_20mhz))) {
2040 ratr_value |= 0x10000000;
2041 tmp_ratr_value = (ratr_value >> 12);
2042
2043 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
2044 if ((1 << shortgi_rate) & tmp_ratr_value)
2045 break;
2046 }
2047
2048 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
2049 (shortgi_rate << 4) | (shortgi_rate);
2050 }
2051
2052 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
2053
2054 rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG,
2055 "%x\n", rtl_read_dword(rtlpriv, REG_ARFR0));
2056 }
2057
rtl88ee_update_hal_rate_mask(struct ieee80211_hw * hw,struct ieee80211_sta * sta,u8 rssi_level,bool update_bw)2058 static void rtl88ee_update_hal_rate_mask(struct ieee80211_hw *hw,
2059 struct ieee80211_sta *sta, u8 rssi_level, bool update_bw)
2060 {
2061 struct rtl_priv *rtlpriv = rtl_priv(hw);
2062 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2063 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2064 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2065 struct rtl_sta_info *sta_entry = NULL;
2066 u32 ratr_bitmap;
2067 u8 ratr_index;
2068 u8 curtxbw_40mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)
2069 ? 1 : 0;
2070 u8 curshortgi_40mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2071 1 : 0;
2072 u8 curshortgi_20mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2073 1 : 0;
2074 enum wireless_mode wirelessmode = 0;
2075 bool b_shortgi = false;
2076 u8 rate_mask[5];
2077 u8 macid = 0;
2078 /*u8 mimo_ps = IEEE80211_SMPS_OFF;*/
2079
2080 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
2081 wirelessmode = sta_entry->wireless_mode;
2082 if (mac->opmode == NL80211_IFTYPE_STATION ||
2083 mac->opmode == NL80211_IFTYPE_MESH_POINT)
2084 curtxbw_40mhz = mac->bw_40;
2085 else if (mac->opmode == NL80211_IFTYPE_AP ||
2086 mac->opmode == NL80211_IFTYPE_ADHOC)
2087 macid = sta->aid + 1;
2088
2089 if (rtlhal->current_bandtype == BAND_ON_5G)
2090 ratr_bitmap = sta->deflink.supp_rates[1] << 4;
2091 else
2092 ratr_bitmap = sta->deflink.supp_rates[0];
2093 if (mac->opmode == NL80211_IFTYPE_ADHOC)
2094 ratr_bitmap = 0xfff;
2095 ratr_bitmap |= (sta->deflink.ht_cap.mcs.rx_mask[1] << 20 |
2096 sta->deflink.ht_cap.mcs.rx_mask[0] << 12);
2097 switch (wirelessmode) {
2098 case WIRELESS_MODE_B:
2099 ratr_index = RATR_INX_WIRELESS_B;
2100 if (ratr_bitmap & 0x0000000c)
2101 ratr_bitmap &= 0x0000000d;
2102 else
2103 ratr_bitmap &= 0x0000000f;
2104 break;
2105 case WIRELESS_MODE_G:
2106 ratr_index = RATR_INX_WIRELESS_GB;
2107
2108 if (rssi_level == 1)
2109 ratr_bitmap &= 0x00000f00;
2110 else if (rssi_level == 2)
2111 ratr_bitmap &= 0x00000ff0;
2112 else
2113 ratr_bitmap &= 0x00000ff5;
2114 break;
2115 case WIRELESS_MODE_N_24G:
2116 case WIRELESS_MODE_N_5G:
2117 ratr_index = RATR_INX_WIRELESS_NGB;
2118 if (rtlphy->rf_type == RF_1T2R ||
2119 rtlphy->rf_type == RF_1T1R) {
2120 if (curtxbw_40mhz) {
2121 if (rssi_level == 1)
2122 ratr_bitmap &= 0x000f0000;
2123 else if (rssi_level == 2)
2124 ratr_bitmap &= 0x000ff000;
2125 else
2126 ratr_bitmap &= 0x000ff015;
2127 } else {
2128 if (rssi_level == 1)
2129 ratr_bitmap &= 0x000f0000;
2130 else if (rssi_level == 2)
2131 ratr_bitmap &= 0x000ff000;
2132 else
2133 ratr_bitmap &= 0x000ff005;
2134 }
2135 } else {
2136 if (curtxbw_40mhz) {
2137 if (rssi_level == 1)
2138 ratr_bitmap &= 0x0f8f0000;
2139 else if (rssi_level == 2)
2140 ratr_bitmap &= 0x0f8ff000;
2141 else
2142 ratr_bitmap &= 0x0f8ff015;
2143 } else {
2144 if (rssi_level == 1)
2145 ratr_bitmap &= 0x0f8f0000;
2146 else if (rssi_level == 2)
2147 ratr_bitmap &= 0x0f8ff000;
2148 else
2149 ratr_bitmap &= 0x0f8ff005;
2150 }
2151 }
2152 /*}*/
2153
2154 if ((curtxbw_40mhz && curshortgi_40mhz) ||
2155 (!curtxbw_40mhz && curshortgi_20mhz)) {
2156
2157 if (macid == 0)
2158 b_shortgi = true;
2159 else if (macid == 1)
2160 b_shortgi = false;
2161 }
2162 break;
2163 default:
2164 ratr_index = RATR_INX_WIRELESS_NGB;
2165
2166 if (rtlphy->rf_type == RF_1T2R)
2167 ratr_bitmap &= 0x000ff0ff;
2168 else
2169 ratr_bitmap &= 0x0f0ff0ff;
2170 break;
2171 }
2172 sta_entry->ratr_index = ratr_index;
2173
2174 rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG,
2175 "ratr_bitmap :%x\n", ratr_bitmap);
2176 *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) |
2177 (ratr_index << 28);
2178 rate_mask[4] = macid | (b_shortgi ? 0x20 : 0x00) | 0x80;
2179 rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG,
2180 "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x\n",
2181 ratr_index, ratr_bitmap,
2182 rate_mask[0], rate_mask[1],
2183 rate_mask[2], rate_mask[3],
2184 rate_mask[4]);
2185 rtl88e_fill_h2c_cmd(hw, H2C_88E_RA_MASK, 5, rate_mask);
2186 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(3), 0);
2187 }
2188
rtl88ee_update_hal_rate_tbl(struct ieee80211_hw * hw,struct ieee80211_sta * sta,u8 rssi_level,bool update_bw)2189 void rtl88ee_update_hal_rate_tbl(struct ieee80211_hw *hw,
2190 struct ieee80211_sta *sta, u8 rssi_level, bool update_bw)
2191 {
2192 struct rtl_priv *rtlpriv = rtl_priv(hw);
2193
2194 if (rtlpriv->dm.useramask)
2195 rtl88ee_update_hal_rate_mask(hw, sta, rssi_level, update_bw);
2196 else
2197 rtl88ee_update_hal_rate_table(hw, sta);
2198 }
2199
rtl88ee_update_channel_access_setting(struct ieee80211_hw * hw)2200 void rtl88ee_update_channel_access_setting(struct ieee80211_hw *hw)
2201 {
2202 struct rtl_priv *rtlpriv = rtl_priv(hw);
2203 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2204 u16 sifs_timer;
2205
2206 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME, &mac->slot_time);
2207 if (!mac->ht_enable)
2208 sifs_timer = 0x0a0a;
2209 else
2210 sifs_timer = 0x0e0e;
2211 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2212 }
2213
rtl88ee_gpio_radio_on_off_checking(struct ieee80211_hw * hw,u8 * valid)2214 bool rtl88ee_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2215 {
2216 struct rtl_priv *rtlpriv = rtl_priv(hw);
2217 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2218 enum rf_pwrstate e_rfpowerstate_toset;
2219 u32 u4tmp;
2220 bool b_actuallyset = false;
2221
2222 if (rtlpriv->rtlhal.being_init_adapter)
2223 return false;
2224
2225 if (ppsc->swrf_processing)
2226 return false;
2227
2228 spin_lock(&rtlpriv->locks.rf_ps_lock);
2229 if (ppsc->rfchange_inprogress) {
2230 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2231 return false;
2232 } else {
2233 ppsc->rfchange_inprogress = true;
2234 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2235 }
2236
2237 u4tmp = rtl_read_dword(rtlpriv, REG_GPIO_OUTPUT);
2238 e_rfpowerstate_toset = (u4tmp & BIT(31)) ? ERFON : ERFOFF;
2239
2240 if (ppsc->hwradiooff && (e_rfpowerstate_toset == ERFON)) {
2241 rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
2242 "GPIOChangeRF - HW Radio ON, RF ON\n");
2243
2244 e_rfpowerstate_toset = ERFON;
2245 ppsc->hwradiooff = false;
2246 b_actuallyset = true;
2247 } else if ((!ppsc->hwradiooff) &&
2248 (e_rfpowerstate_toset == ERFOFF)) {
2249 rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
2250 "GPIOChangeRF - HW Radio OFF, RF OFF\n");
2251
2252 e_rfpowerstate_toset = ERFOFF;
2253 ppsc->hwradiooff = true;
2254 b_actuallyset = true;
2255 }
2256
2257 if (b_actuallyset) {
2258 spin_lock(&rtlpriv->locks.rf_ps_lock);
2259 ppsc->rfchange_inprogress = false;
2260 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2261 } else {
2262 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
2263 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2264
2265 spin_lock(&rtlpriv->locks.rf_ps_lock);
2266 ppsc->rfchange_inprogress = false;
2267 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2268 }
2269
2270 *valid = 1;
2271 return !ppsc->hwradiooff;
2272
2273 }
2274
rtl88ee_set_key(struct ieee80211_hw * hw,u32 key_index,u8 * p_macaddr,bool is_group,u8 enc_algo,bool is_wepkey,bool clear_all)2275 void rtl88ee_set_key(struct ieee80211_hw *hw, u32 key_index,
2276 u8 *p_macaddr, bool is_group, u8 enc_algo,
2277 bool is_wepkey, bool clear_all)
2278 {
2279 struct rtl_priv *rtlpriv = rtl_priv(hw);
2280 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2281 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2282 u8 *macaddr = p_macaddr;
2283 u32 entry_id = 0;
2284 bool is_pairwise = false;
2285 static u8 cam_const_addr[4][6] = {
2286 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2287 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2288 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2289 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2290 };
2291 static u8 cam_const_broad[] = {
2292 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2293 };
2294
2295 if (clear_all) {
2296 u8 idx = 0;
2297 u8 cam_offset = 0;
2298 u8 clear_number = 5;
2299
2300 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2301
2302 for (idx = 0; idx < clear_number; idx++) {
2303 rtl_cam_mark_invalid(hw, cam_offset + idx);
2304 rtl_cam_empty_entry(hw, cam_offset + idx);
2305
2306 if (idx < 5) {
2307 memset(rtlpriv->sec.key_buf[idx], 0,
2308 MAX_KEY_LEN);
2309 rtlpriv->sec.key_len[idx] = 0;
2310 }
2311 }
2312
2313 } else {
2314 switch (enc_algo) {
2315 case WEP40_ENCRYPTION:
2316 enc_algo = CAM_WEP40;
2317 break;
2318 case WEP104_ENCRYPTION:
2319 enc_algo = CAM_WEP104;
2320 break;
2321 case TKIP_ENCRYPTION:
2322 enc_algo = CAM_TKIP;
2323 break;
2324 case AESCCMP_ENCRYPTION:
2325 enc_algo = CAM_AES;
2326 break;
2327 default:
2328 pr_err("switch case %#x not processed\n",
2329 enc_algo);
2330 enc_algo = CAM_TKIP;
2331 break;
2332 }
2333
2334 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2335 macaddr = cam_const_addr[key_index];
2336 entry_id = key_index;
2337 } else {
2338 if (is_group) {
2339 macaddr = cam_const_broad;
2340 entry_id = key_index;
2341 } else {
2342 if (mac->opmode == NL80211_IFTYPE_AP ||
2343 mac->opmode == NL80211_IFTYPE_MESH_POINT) {
2344 entry_id =
2345 rtl_cam_get_free_entry(hw, p_macaddr);
2346 if (entry_id >= TOTAL_CAM_ENTRY) {
2347 pr_err("Can not find free hw security cam entry\n");
2348 return;
2349 }
2350 } else {
2351 entry_id = CAM_PAIRWISE_KEY_POSITION;
2352 }
2353 key_index = PAIRWISE_KEYIDX;
2354 is_pairwise = true;
2355 }
2356 }
2357
2358 if (rtlpriv->sec.key_len[key_index] == 0) {
2359 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
2360 "delete one entry, entry_id is %d\n",
2361 entry_id);
2362 if (mac->opmode == NL80211_IFTYPE_AP ||
2363 mac->opmode == NL80211_IFTYPE_MESH_POINT)
2364 rtl_cam_del_entry(hw, p_macaddr);
2365 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2366 } else {
2367 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
2368 "add one entry\n");
2369 if (is_pairwise) {
2370 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
2371 "set Pairwise key\n");
2372
2373 rtl_cam_add_one_entry(hw, macaddr, key_index,
2374 entry_id, enc_algo,
2375 CAM_CONFIG_NO_USEDK,
2376 rtlpriv->sec.key_buf[key_index]);
2377 } else {
2378 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
2379 "set group key\n");
2380
2381 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2382 rtl_cam_add_one_entry(hw,
2383 rtlefuse->dev_addr,
2384 PAIRWISE_KEYIDX,
2385 CAM_PAIRWISE_KEY_POSITION,
2386 enc_algo,
2387 CAM_CONFIG_NO_USEDK,
2388 rtlpriv->sec.key_buf
2389 [entry_id]);
2390 }
2391
2392 rtl_cam_add_one_entry(hw, macaddr, key_index,
2393 entry_id, enc_algo,
2394 CAM_CONFIG_NO_USEDK,
2395 rtlpriv->sec.key_buf[entry_id]);
2396 }
2397
2398 }
2399 }
2400 }
2401
rtl8188ee_bt_var_init(struct ieee80211_hw * hw)2402 static void rtl8188ee_bt_var_init(struct ieee80211_hw *hw)
2403 {
2404 struct rtl_priv *rtlpriv = rtl_priv(hw);
2405
2406 rtlpriv->btcoexist.bt_coexistence =
2407 rtlpriv->btcoexist.eeprom_bt_coexist;
2408 rtlpriv->btcoexist.bt_ant_num = rtlpriv->btcoexist.eeprom_bt_ant_num;
2409 rtlpriv->btcoexist.bt_coexist_type = rtlpriv->btcoexist.eeprom_bt_type;
2410
2411 if (rtlpriv->btcoexist.reg_bt_iso == 2)
2412 rtlpriv->btcoexist.bt_ant_isolation =
2413 rtlpriv->btcoexist.eeprom_bt_ant_isol;
2414 else
2415 rtlpriv->btcoexist.bt_ant_isolation =
2416 rtlpriv->btcoexist.reg_bt_iso;
2417
2418 rtlpriv->btcoexist.bt_radio_shared_type =
2419 rtlpriv->btcoexist.eeprom_bt_radio_shared;
2420
2421 if (rtlpriv->btcoexist.bt_coexistence) {
2422 if (rtlpriv->btcoexist.reg_bt_sco == 1)
2423 rtlpriv->btcoexist.bt_service = BT_OTHER_ACTION;
2424 else if (rtlpriv->btcoexist.reg_bt_sco == 2)
2425 rtlpriv->btcoexist.bt_service = BT_SCO;
2426 else if (rtlpriv->btcoexist.reg_bt_sco == 4)
2427 rtlpriv->btcoexist.bt_service = BT_BUSY;
2428 else if (rtlpriv->btcoexist.reg_bt_sco == 5)
2429 rtlpriv->btcoexist.bt_service = BT_OTHERBUSY;
2430 else
2431 rtlpriv->btcoexist.bt_service = BT_IDLE;
2432
2433 rtlpriv->btcoexist.bt_edca_ul = 0;
2434 rtlpriv->btcoexist.bt_edca_dl = 0;
2435 rtlpriv->btcoexist.bt_rssi_state = 0xff;
2436 }
2437 }
2438
rtl8188ee_read_bt_coexist_info_from_hwpg(struct ieee80211_hw * hw,bool auto_load_fail,u8 * hwinfo)2439 void rtl8188ee_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
2440 bool auto_load_fail, u8 *hwinfo)
2441 {
2442 struct rtl_priv *rtlpriv = rtl_priv(hw);
2443 u8 value;
2444
2445 if (!auto_load_fail) {
2446 rtlpriv->btcoexist.eeprom_bt_coexist =
2447 ((hwinfo[EEPROM_RF_FEATURE_OPTION_88E] & 0xe0) >> 5);
2448 if (hwinfo[EEPROM_RF_FEATURE_OPTION_88E] == 0xFF)
2449 rtlpriv->btcoexist.eeprom_bt_coexist = 0;
2450 value = hwinfo[EEPROM_RF_BT_SETTING_88E];
2451 rtlpriv->btcoexist.eeprom_bt_type = ((value & 0xe) >> 1);
2452 rtlpriv->btcoexist.eeprom_bt_ant_num = (value & 0x1);
2453 rtlpriv->btcoexist.eeprom_bt_ant_isol = ((value & 0x10) >> 4);
2454 rtlpriv->btcoexist.eeprom_bt_radio_shared =
2455 ((value & 0x20) >> 5);
2456 } else {
2457 rtlpriv->btcoexist.eeprom_bt_coexist = 0;
2458 rtlpriv->btcoexist.eeprom_bt_type = BT_2WIRE;
2459 rtlpriv->btcoexist.eeprom_bt_ant_num = ANT_X2;
2460 rtlpriv->btcoexist.eeprom_bt_ant_isol = 0;
2461 rtlpriv->btcoexist.eeprom_bt_radio_shared = BT_RADIO_SHARED;
2462 }
2463
2464 rtl8188ee_bt_var_init(hw);
2465 }
2466
rtl8188ee_bt_reg_init(struct ieee80211_hw * hw)2467 void rtl8188ee_bt_reg_init(struct ieee80211_hw *hw)
2468 {
2469 struct rtl_priv *rtlpriv = rtl_priv(hw);
2470
2471 /* 0:Low, 1:High, 2:From Efuse. */
2472 rtlpriv->btcoexist.reg_bt_iso = 2;
2473 /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
2474 rtlpriv->btcoexist.reg_bt_sco = 0;
2475 }
2476
rtl8188ee_bt_hw_init(struct ieee80211_hw * hw)2477 void rtl8188ee_bt_hw_init(struct ieee80211_hw *hw)
2478 {
2479 struct rtl_priv *rtlpriv = rtl_priv(hw);
2480 struct rtl_phy *rtlphy = &rtlpriv->phy;
2481 u8 u1_tmp;
2482
2483 if (rtlpriv->btcoexist.bt_coexistence &&
2484 ((rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) ||
2485 rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC8)) {
2486 if (rtlpriv->btcoexist.bt_ant_isolation)
2487 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0);
2488
2489 u1_tmp = rtl_read_byte(rtlpriv, 0x4fd) & BIT(0);
2490 u1_tmp = u1_tmp |
2491 ((rtlpriv->btcoexist.bt_ant_isolation == 1) ?
2492 0 : BIT((1)) |
2493 ((rtlpriv->btcoexist.bt_service == BT_SCO) ?
2494 0 : BIT(2)));
2495 rtl_write_byte(rtlpriv, 0x4fd, u1_tmp);
2496
2497 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+4, 0xaaaa9aaa);
2498 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+8, 0xffbd0040);
2499 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+0xc, 0x40000010);
2500
2501 /* Config to 1T1R. */
2502 if (rtlphy->rf_type == RF_1T1R) {
2503 u1_tmp = rtl_read_byte(rtlpriv, ROFDM0_TRXPATHENABLE);
2504 u1_tmp &= ~(BIT(1));
2505 rtl_write_byte(rtlpriv, ROFDM0_TRXPATHENABLE, u1_tmp);
2506
2507 u1_tmp = rtl_read_byte(rtlpriv, ROFDM1_TRXPATHENABLE);
2508 u1_tmp &= ~(BIT(1));
2509 rtl_write_byte(rtlpriv, ROFDM1_TRXPATHENABLE, u1_tmp);
2510 }
2511 }
2512 }
2513
rtl88ee_suspend(struct ieee80211_hw * hw)2514 void rtl88ee_suspend(struct ieee80211_hw *hw)
2515 {
2516 }
2517
rtl88ee_resume(struct ieee80211_hw * hw)2518 void rtl88ee_resume(struct ieee80211_hw *hw)
2519 {
2520 }
2521