1 /*
2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32 
33 #include <net/tc_act/tc_gact.h>
34 #include <linux/mlx5/fs.h>
35 #include <net/vxlan.h>
36 #include <net/geneve.h>
37 #include <linux/bpf.h>
38 #include <linux/debugfs.h>
39 #include <linux/if_bridge.h>
40 #include <linux/filter.h>
41 #include <net/page_pool/types.h>
42 #include <net/pkt_sched.h>
43 #include <net/xdp_sock_drv.h>
44 #include "eswitch.h"
45 #include "en.h"
46 #include "en/txrx.h"
47 #include "en_tc.h"
48 #include "en_rep.h"
49 #include "en_accel/ipsec.h"
50 #include "en_accel/macsec.h"
51 #include "en_accel/en_accel.h"
52 #include "en_accel/ktls.h"
53 #include "lib/vxlan.h"
54 #include "lib/clock.h"
55 #include "en/port.h"
56 #include "en/xdp.h"
57 #include "lib/eq.h"
58 #include "en/monitor_stats.h"
59 #include "en/health.h"
60 #include "en/params.h"
61 #include "en/xsk/pool.h"
62 #include "en/xsk/setup.h"
63 #include "en/xsk/rx.h"
64 #include "en/xsk/tx.h"
65 #include "en/hv_vhca_stats.h"
66 #include "en/devlink.h"
67 #include "lib/mlx5.h"
68 #include "en/ptp.h"
69 #include "en/htb.h"
70 #include "qos.h"
71 #include "en/trap.h"
72 
mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev * mdev,u8 page_shift,enum mlx5e_mpwrq_umr_mode umr_mode)73 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev, u8 page_shift,
74 					    enum mlx5e_mpwrq_umr_mode umr_mode)
75 {
76 	u16 umr_wqebbs, max_wqebbs;
77 	bool striding_rq_umr;
78 
79 	striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) && MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
80 			  MLX5_CAP_ETH(mdev, reg_umr_sq);
81 	if (!striding_rq_umr)
82 		return false;
83 
84 	umr_wqebbs = mlx5e_mpwrq_umr_wqebbs(mdev, page_shift, umr_mode);
85 	max_wqebbs = mlx5e_get_max_sq_aligned_wqebbs(mdev);
86 	/* Sanity check; should never happen, because mlx5e_mpwrq_umr_wqebbs is
87 	 * calculated from mlx5e_get_max_sq_aligned_wqebbs.
88 	 */
89 	if (WARN_ON(umr_wqebbs > max_wqebbs))
90 		return false;
91 
92 	return true;
93 }
94 
mlx5e_update_carrier(struct mlx5e_priv * priv)95 void mlx5e_update_carrier(struct mlx5e_priv *priv)
96 {
97 	struct mlx5_core_dev *mdev = priv->mdev;
98 	u8 port_state;
99 	bool up;
100 
101 	port_state = mlx5_query_vport_state(mdev,
102 					    MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT,
103 					    0);
104 
105 	up = port_state == VPORT_STATE_UP;
106 	if (up == netif_carrier_ok(priv->netdev))
107 		netif_carrier_event(priv->netdev);
108 	if (up) {
109 		netdev_info(priv->netdev, "Link up\n");
110 		netif_carrier_on(priv->netdev);
111 	} else {
112 		netdev_info(priv->netdev, "Link down\n");
113 		netif_carrier_off(priv->netdev);
114 	}
115 }
116 
mlx5e_update_carrier_work(struct work_struct * work)117 static void mlx5e_update_carrier_work(struct work_struct *work)
118 {
119 	struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
120 					       update_carrier_work);
121 
122 	mutex_lock(&priv->state_lock);
123 	if (test_bit(MLX5E_STATE_OPENED, &priv->state))
124 		if (priv->profile->update_carrier)
125 			priv->profile->update_carrier(priv);
126 	mutex_unlock(&priv->state_lock);
127 }
128 
mlx5e_update_stats_work(struct work_struct * work)129 static void mlx5e_update_stats_work(struct work_struct *work)
130 {
131 	struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
132 					       update_stats_work);
133 
134 	mutex_lock(&priv->state_lock);
135 	priv->profile->update_stats(priv);
136 	mutex_unlock(&priv->state_lock);
137 }
138 
mlx5e_queue_update_stats(struct mlx5e_priv * priv)139 void mlx5e_queue_update_stats(struct mlx5e_priv *priv)
140 {
141 	if (!priv->profile->update_stats)
142 		return;
143 
144 	if (unlikely(test_bit(MLX5E_STATE_DESTROYING, &priv->state)))
145 		return;
146 
147 	queue_work(priv->wq, &priv->update_stats_work);
148 }
149 
async_event(struct notifier_block * nb,unsigned long event,void * data)150 static int async_event(struct notifier_block *nb, unsigned long event, void *data)
151 {
152 	struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, events_nb);
153 	struct mlx5_eqe   *eqe = data;
154 
155 	if (event != MLX5_EVENT_TYPE_PORT_CHANGE)
156 		return NOTIFY_DONE;
157 
158 	switch (eqe->sub_type) {
159 	case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
160 	case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
161 		queue_work(priv->wq, &priv->update_carrier_work);
162 		break;
163 	default:
164 		return NOTIFY_DONE;
165 	}
166 
167 	return NOTIFY_OK;
168 }
169 
mlx5e_enable_async_events(struct mlx5e_priv * priv)170 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
171 {
172 	priv->events_nb.notifier_call = async_event;
173 	mlx5_notifier_register(priv->mdev, &priv->events_nb);
174 }
175 
mlx5e_disable_async_events(struct mlx5e_priv * priv)176 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
177 {
178 	mlx5_notifier_unregister(priv->mdev, &priv->events_nb);
179 }
180 
blocking_event(struct notifier_block * nb,unsigned long event,void * data)181 static int blocking_event(struct notifier_block *nb, unsigned long event, void *data)
182 {
183 	struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, blocking_events_nb);
184 	struct mlx5_devlink_trap_event_ctx *trap_event_ctx = data;
185 	int err;
186 
187 	switch (event) {
188 	case MLX5_DRIVER_EVENT_TYPE_TRAP:
189 		err = mlx5e_handle_trap_event(priv, trap_event_ctx->trap);
190 		if (err) {
191 			trap_event_ctx->err = err;
192 			return NOTIFY_BAD;
193 		}
194 		break;
195 	default:
196 		return NOTIFY_DONE;
197 	}
198 	return NOTIFY_OK;
199 }
200 
mlx5e_enable_blocking_events(struct mlx5e_priv * priv)201 static void mlx5e_enable_blocking_events(struct mlx5e_priv *priv)
202 {
203 	priv->blocking_events_nb.notifier_call = blocking_event;
204 	mlx5_blocking_notifier_register(priv->mdev, &priv->blocking_events_nb);
205 }
206 
mlx5e_disable_blocking_events(struct mlx5e_priv * priv)207 static void mlx5e_disable_blocking_events(struct mlx5e_priv *priv)
208 {
209 	mlx5_blocking_notifier_unregister(priv->mdev, &priv->blocking_events_nb);
210 }
211 
mlx5e_mpwrq_umr_octowords(u32 entries,enum mlx5e_mpwrq_umr_mode umr_mode)212 static u16 mlx5e_mpwrq_umr_octowords(u32 entries, enum mlx5e_mpwrq_umr_mode umr_mode)
213 {
214 	u8 umr_entry_size = mlx5e_mpwrq_umr_entry_size(umr_mode);
215 	u32 sz;
216 
217 	sz = ALIGN(entries * umr_entry_size, MLX5_UMR_FLEX_ALIGNMENT);
218 
219 	return sz / MLX5_OCTWORD;
220 }
221 
mlx5e_build_umr_wqe(struct mlx5e_rq * rq,struct mlx5e_icosq * sq,struct mlx5e_umr_wqe * wqe)222 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
223 				       struct mlx5e_icosq *sq,
224 				       struct mlx5e_umr_wqe *wqe)
225 {
226 	struct mlx5_wqe_ctrl_seg      *cseg = &wqe->ctrl;
227 	struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
228 	u16 octowords;
229 	u8 ds_cnt;
230 
231 	ds_cnt = DIV_ROUND_UP(mlx5e_mpwrq_umr_wqe_sz(rq->mdev, rq->mpwqe.page_shift,
232 						     rq->mpwqe.umr_mode),
233 			      MLX5_SEND_WQE_DS);
234 
235 	cseg->qpn_ds    = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
236 				      ds_cnt);
237 	cseg->umr_mkey  = rq->mpwqe.umr_mkey_be;
238 
239 	ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE;
240 	octowords = mlx5e_mpwrq_umr_octowords(rq->mpwqe.pages_per_wqe, rq->mpwqe.umr_mode);
241 	ucseg->xlt_octowords = cpu_to_be16(octowords);
242 	ucseg->mkey_mask     = cpu_to_be64(MLX5_MKEY_MASK_FREE);
243 }
244 
mlx5e_rq_shampo_hd_alloc(struct mlx5e_rq * rq,int node)245 static int mlx5e_rq_shampo_hd_alloc(struct mlx5e_rq *rq, int node)
246 {
247 	rq->mpwqe.shampo = kvzalloc_node(sizeof(*rq->mpwqe.shampo),
248 					 GFP_KERNEL, node);
249 	if (!rq->mpwqe.shampo)
250 		return -ENOMEM;
251 	return 0;
252 }
253 
mlx5e_rq_shampo_hd_free(struct mlx5e_rq * rq)254 static void mlx5e_rq_shampo_hd_free(struct mlx5e_rq *rq)
255 {
256 	kvfree(rq->mpwqe.shampo);
257 }
258 
mlx5e_rq_shampo_hd_info_alloc(struct mlx5e_rq * rq,int node)259 static int mlx5e_rq_shampo_hd_info_alloc(struct mlx5e_rq *rq, int node)
260 {
261 	struct mlx5e_shampo_hd *shampo = rq->mpwqe.shampo;
262 
263 	shampo->bitmap = bitmap_zalloc_node(shampo->hd_per_wq, GFP_KERNEL,
264 					    node);
265 	shampo->info = kvzalloc_node(array_size(shampo->hd_per_wq,
266 						sizeof(*shampo->info)),
267 				     GFP_KERNEL, node);
268 	shampo->pages = kvzalloc_node(array_size(shampo->hd_per_wq,
269 						 sizeof(*shampo->pages)),
270 				     GFP_KERNEL, node);
271 	if (!shampo->bitmap || !shampo->info || !shampo->pages)
272 		goto err_nomem;
273 
274 	return 0;
275 
276 err_nomem:
277 	kvfree(shampo->info);
278 	kvfree(shampo->bitmap);
279 	kvfree(shampo->pages);
280 
281 	return -ENOMEM;
282 }
283 
mlx5e_rq_shampo_hd_info_free(struct mlx5e_rq * rq)284 static void mlx5e_rq_shampo_hd_info_free(struct mlx5e_rq *rq)
285 {
286 	kvfree(rq->mpwqe.shampo->bitmap);
287 	kvfree(rq->mpwqe.shampo->info);
288 	kvfree(rq->mpwqe.shampo->pages);
289 }
290 
mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq * rq,int node)291 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq, int node)
292 {
293 	int wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
294 	size_t alloc_size;
295 
296 	alloc_size = array_size(wq_sz, struct_size(rq->mpwqe.info,
297 						   alloc_units.frag_pages,
298 						   rq->mpwqe.pages_per_wqe));
299 
300 	rq->mpwqe.info = kvzalloc_node(alloc_size, GFP_KERNEL, node);
301 	if (!rq->mpwqe.info)
302 		return -ENOMEM;
303 
304 	/* For deferred page release (release right before alloc), make sure
305 	 * that on first round release is not called.
306 	 */
307 	for (int i = 0; i < wq_sz; i++) {
308 		struct mlx5e_mpw_info *wi = mlx5e_get_mpw_info(rq, i);
309 
310 		bitmap_fill(wi->skip_release_bitmap, rq->mpwqe.pages_per_wqe);
311 	}
312 
313 	mlx5e_build_umr_wqe(rq, rq->icosq, &rq->mpwqe.umr_wqe);
314 
315 	return 0;
316 }
317 
318 
mlx5e_mpwrq_access_mode(enum mlx5e_mpwrq_umr_mode umr_mode)319 static u8 mlx5e_mpwrq_access_mode(enum mlx5e_mpwrq_umr_mode umr_mode)
320 {
321 	switch (umr_mode) {
322 	case MLX5E_MPWRQ_UMR_MODE_ALIGNED:
323 		return MLX5_MKC_ACCESS_MODE_MTT;
324 	case MLX5E_MPWRQ_UMR_MODE_UNALIGNED:
325 		return MLX5_MKC_ACCESS_MODE_KSM;
326 	case MLX5E_MPWRQ_UMR_MODE_OVERSIZED:
327 		return MLX5_MKC_ACCESS_MODE_KLMS;
328 	case MLX5E_MPWRQ_UMR_MODE_TRIPLE:
329 		return MLX5_MKC_ACCESS_MODE_KSM;
330 	}
331 	WARN_ONCE(1, "MPWRQ UMR mode %d is not known\n", umr_mode);
332 	return 0;
333 }
334 
mlx5e_create_umr_mkey(struct mlx5_core_dev * mdev,u32 npages,u8 page_shift,u32 * umr_mkey,dma_addr_t filler_addr,enum mlx5e_mpwrq_umr_mode umr_mode,u32 xsk_chunk_size)335 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
336 				 u32 npages, u8 page_shift, u32 *umr_mkey,
337 				 dma_addr_t filler_addr,
338 				 enum mlx5e_mpwrq_umr_mode umr_mode,
339 				 u32 xsk_chunk_size)
340 {
341 	struct mlx5_mtt *mtt;
342 	struct mlx5_ksm *ksm;
343 	struct mlx5_klm *klm;
344 	u32 octwords;
345 	int inlen;
346 	void *mkc;
347 	u32 *in;
348 	int err;
349 	int i;
350 
351 	if ((umr_mode == MLX5E_MPWRQ_UMR_MODE_UNALIGNED ||
352 	     umr_mode == MLX5E_MPWRQ_UMR_MODE_TRIPLE) &&
353 	    !MLX5_CAP_GEN(mdev, fixed_buffer_size)) {
354 		mlx5_core_warn(mdev, "Unaligned AF_XDP requires fixed_buffer_size capability\n");
355 		return -EINVAL;
356 	}
357 
358 	octwords = mlx5e_mpwrq_umr_octowords(npages, umr_mode);
359 
360 	inlen = MLX5_FLEXIBLE_INLEN(mdev, MLX5_ST_SZ_BYTES(create_mkey_in),
361 				    MLX5_OCTWORD, octwords);
362 	if (inlen < 0)
363 		return inlen;
364 
365 	in = kvzalloc(inlen, GFP_KERNEL);
366 	if (!in)
367 		return -ENOMEM;
368 
369 	mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
370 
371 	MLX5_SET(mkc, mkc, free, 1);
372 	MLX5_SET(mkc, mkc, umr_en, 1);
373 	MLX5_SET(mkc, mkc, lw, 1);
374 	MLX5_SET(mkc, mkc, lr, 1);
375 	MLX5_SET(mkc, mkc, access_mode_1_0, mlx5e_mpwrq_access_mode(umr_mode));
376 	mlx5e_mkey_set_relaxed_ordering(mdev, mkc);
377 	MLX5_SET(mkc, mkc, qpn, 0xffffff);
378 	MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.hw_objs.pdn);
379 	MLX5_SET64(mkc, mkc, len, npages << page_shift);
380 	MLX5_SET(mkc, mkc, translations_octword_size, octwords);
381 	if (umr_mode == MLX5E_MPWRQ_UMR_MODE_TRIPLE)
382 		MLX5_SET(mkc, mkc, log_page_size, page_shift - 2);
383 	else if (umr_mode != MLX5E_MPWRQ_UMR_MODE_OVERSIZED)
384 		MLX5_SET(mkc, mkc, log_page_size, page_shift);
385 	MLX5_SET(create_mkey_in, in, translations_octword_actual_size, octwords);
386 
387 	/* Initialize the mkey with all MTTs pointing to a default
388 	 * page (filler_addr). When the channels are activated, UMR
389 	 * WQEs will redirect the RX WQEs to the actual memory from
390 	 * the RQ's pool, while the gaps (wqe_overflow) remain mapped
391 	 * to the default page.
392 	 */
393 	switch (umr_mode) {
394 	case MLX5E_MPWRQ_UMR_MODE_OVERSIZED:
395 		klm = MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt);
396 		for (i = 0; i < npages; i++) {
397 			klm[i << 1] = (struct mlx5_klm) {
398 				.va = cpu_to_be64(filler_addr),
399 				.bcount = cpu_to_be32(xsk_chunk_size),
400 				.key = cpu_to_be32(mdev->mlx5e_res.hw_objs.mkey),
401 			};
402 			klm[(i << 1) + 1] = (struct mlx5_klm) {
403 				.va = cpu_to_be64(filler_addr),
404 				.bcount = cpu_to_be32((1 << page_shift) - xsk_chunk_size),
405 				.key = cpu_to_be32(mdev->mlx5e_res.hw_objs.mkey),
406 			};
407 		}
408 		break;
409 	case MLX5E_MPWRQ_UMR_MODE_UNALIGNED:
410 		ksm = MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt);
411 		for (i = 0; i < npages; i++)
412 			ksm[i] = (struct mlx5_ksm) {
413 				.key = cpu_to_be32(mdev->mlx5e_res.hw_objs.mkey),
414 				.va = cpu_to_be64(filler_addr),
415 			};
416 		break;
417 	case MLX5E_MPWRQ_UMR_MODE_ALIGNED:
418 		mtt = MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt);
419 		for (i = 0; i < npages; i++)
420 			mtt[i] = (struct mlx5_mtt) {
421 				.ptag = cpu_to_be64(filler_addr),
422 			};
423 		break;
424 	case MLX5E_MPWRQ_UMR_MODE_TRIPLE:
425 		ksm = MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt);
426 		for (i = 0; i < npages * 4; i++) {
427 			ksm[i] = (struct mlx5_ksm) {
428 				.key = cpu_to_be32(mdev->mlx5e_res.hw_objs.mkey),
429 				.va = cpu_to_be64(filler_addr),
430 			};
431 		}
432 		break;
433 	}
434 
435 	err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
436 
437 	kvfree(in);
438 	return err;
439 }
440 
mlx5e_create_umr_klm_mkey(struct mlx5_core_dev * mdev,u64 nentries,u32 * umr_mkey)441 static int mlx5e_create_umr_klm_mkey(struct mlx5_core_dev *mdev,
442 				     u64 nentries,
443 				     u32 *umr_mkey)
444 {
445 	int inlen;
446 	void *mkc;
447 	u32 *in;
448 	int err;
449 
450 	inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
451 
452 	in = kvzalloc(inlen, GFP_KERNEL);
453 	if (!in)
454 		return -ENOMEM;
455 
456 	mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
457 
458 	MLX5_SET(mkc, mkc, free, 1);
459 	MLX5_SET(mkc, mkc, umr_en, 1);
460 	MLX5_SET(mkc, mkc, lw, 1);
461 	MLX5_SET(mkc, mkc, lr, 1);
462 	MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_KLMS);
463 	mlx5e_mkey_set_relaxed_ordering(mdev, mkc);
464 	MLX5_SET(mkc, mkc, qpn, 0xffffff);
465 	MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.hw_objs.pdn);
466 	MLX5_SET(mkc, mkc, translations_octword_size, nentries);
467 	MLX5_SET(mkc, mkc, length64, 1);
468 	err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
469 
470 	kvfree(in);
471 	return err;
472 }
473 
mlx5e_create_rq_umr_mkey(struct mlx5_core_dev * mdev,struct mlx5e_rq * rq)474 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
475 {
476 	u32 xsk_chunk_size = rq->xsk_pool ? rq->xsk_pool->chunk_size : 0;
477 	u32 wq_size = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
478 	u32 num_entries, max_num_entries;
479 	u32 umr_mkey;
480 	int err;
481 
482 	max_num_entries = mlx5e_mpwrq_max_num_entries(mdev, rq->mpwqe.umr_mode);
483 
484 	/* Shouldn't overflow, the result is at most MLX5E_MAX_RQ_NUM_MTTS. */
485 	if (WARN_ON_ONCE(check_mul_overflow(wq_size, (u32)rq->mpwqe.mtts_per_wqe,
486 					    &num_entries) ||
487 			 num_entries > max_num_entries))
488 		mlx5_core_err(mdev, "%s: multiplication overflow: %u * %u > %u\n",
489 			      __func__, wq_size, rq->mpwqe.mtts_per_wqe,
490 			      max_num_entries);
491 
492 	err = mlx5e_create_umr_mkey(mdev, num_entries, rq->mpwqe.page_shift,
493 				    &umr_mkey, rq->wqe_overflow.addr,
494 				    rq->mpwqe.umr_mode, xsk_chunk_size);
495 	rq->mpwqe.umr_mkey_be = cpu_to_be32(umr_mkey);
496 	return err;
497 }
498 
mlx5e_create_rq_hd_umr_mkey(struct mlx5_core_dev * mdev,struct mlx5e_rq * rq)499 static int mlx5e_create_rq_hd_umr_mkey(struct mlx5_core_dev *mdev,
500 				       struct mlx5e_rq *rq)
501 {
502 	u32 max_klm_size = BIT(MLX5_CAP_GEN(mdev, log_max_klm_list_size));
503 
504 	if (max_klm_size < rq->mpwqe.shampo->hd_per_wq) {
505 		mlx5_core_err(mdev, "max klm list size 0x%x is smaller than shampo header buffer list size 0x%x\n",
506 			      max_klm_size, rq->mpwqe.shampo->hd_per_wq);
507 		return -EINVAL;
508 	}
509 	return mlx5e_create_umr_klm_mkey(mdev, rq->mpwqe.shampo->hd_per_wq,
510 					 &rq->mpwqe.shampo->mkey);
511 }
512 
mlx5e_init_frags_partition(struct mlx5e_rq * rq)513 static void mlx5e_init_frags_partition(struct mlx5e_rq *rq)
514 {
515 	struct mlx5e_wqe_frag_info next_frag = {};
516 	struct mlx5e_wqe_frag_info *prev = NULL;
517 	int i;
518 
519 	WARN_ON(rq->xsk_pool);
520 
521 	next_frag.frag_page = &rq->wqe.alloc_units->frag_pages[0];
522 
523 	/* Skip first release due to deferred release. */
524 	next_frag.flags = BIT(MLX5E_WQE_FRAG_SKIP_RELEASE);
525 
526 	for (i = 0; i < mlx5_wq_cyc_get_size(&rq->wqe.wq); i++) {
527 		struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
528 		struct mlx5e_wqe_frag_info *frag =
529 			&rq->wqe.frags[i << rq->wqe.info.log_num_frags];
530 		int f;
531 
532 		for (f = 0; f < rq->wqe.info.num_frags; f++, frag++) {
533 			if (next_frag.offset + frag_info[f].frag_stride > PAGE_SIZE) {
534 				/* Pages are assigned at runtime. */
535 				next_frag.frag_page++;
536 				next_frag.offset = 0;
537 				if (prev)
538 					prev->flags |= BIT(MLX5E_WQE_FRAG_LAST_IN_PAGE);
539 			}
540 			*frag = next_frag;
541 
542 			/* prepare next */
543 			next_frag.offset += frag_info[f].frag_stride;
544 			prev = frag;
545 		}
546 	}
547 
548 	if (prev)
549 		prev->flags |= BIT(MLX5E_WQE_FRAG_LAST_IN_PAGE);
550 }
551 
mlx5e_init_xsk_buffs(struct mlx5e_rq * rq)552 static void mlx5e_init_xsk_buffs(struct mlx5e_rq *rq)
553 {
554 	int i;
555 
556 	/* Assumptions used by XSK batched allocator. */
557 	WARN_ON(rq->wqe.info.num_frags != 1);
558 	WARN_ON(rq->wqe.info.log_num_frags != 0);
559 	WARN_ON(rq->wqe.info.arr[0].frag_stride != PAGE_SIZE);
560 
561 	/* Considering the above assumptions a fragment maps to a single
562 	 * xsk_buff.
563 	 */
564 	for (i = 0; i < mlx5_wq_cyc_get_size(&rq->wqe.wq); i++) {
565 		rq->wqe.frags[i].xskp = &rq->wqe.alloc_units->xsk_buffs[i];
566 
567 		/* Skip first release due to deferred release as WQES are
568 		 * not allocated yet.
569 		 */
570 		rq->wqe.frags[i].flags |= BIT(MLX5E_WQE_FRAG_SKIP_RELEASE);
571 	}
572 }
573 
mlx5e_init_wqe_alloc_info(struct mlx5e_rq * rq,int node)574 static int mlx5e_init_wqe_alloc_info(struct mlx5e_rq *rq, int node)
575 {
576 	int wq_sz = mlx5_wq_cyc_get_size(&rq->wqe.wq);
577 	int len = wq_sz << rq->wqe.info.log_num_frags;
578 	struct mlx5e_wqe_frag_info *frags;
579 	union mlx5e_alloc_units *aus;
580 	int aus_sz;
581 
582 	if (rq->xsk_pool)
583 		aus_sz = sizeof(*aus->xsk_buffs);
584 	else
585 		aus_sz = sizeof(*aus->frag_pages);
586 
587 	aus = kvzalloc_node(array_size(len, aus_sz), GFP_KERNEL, node);
588 	if (!aus)
589 		return -ENOMEM;
590 
591 	frags = kvzalloc_node(array_size(len, sizeof(*frags)), GFP_KERNEL, node);
592 	if (!frags) {
593 		kvfree(aus);
594 		return -ENOMEM;
595 	}
596 
597 	rq->wqe.alloc_units = aus;
598 	rq->wqe.frags = frags;
599 
600 	if (rq->xsk_pool)
601 		mlx5e_init_xsk_buffs(rq);
602 	else
603 		mlx5e_init_frags_partition(rq);
604 
605 	return 0;
606 }
607 
mlx5e_free_wqe_alloc_info(struct mlx5e_rq * rq)608 static void mlx5e_free_wqe_alloc_info(struct mlx5e_rq *rq)
609 {
610 	kvfree(rq->wqe.frags);
611 	kvfree(rq->wqe.alloc_units);
612 }
613 
mlx5e_rq_err_cqe_work(struct work_struct * recover_work)614 static void mlx5e_rq_err_cqe_work(struct work_struct *recover_work)
615 {
616 	struct mlx5e_rq *rq = container_of(recover_work, struct mlx5e_rq, recover_work);
617 
618 	mlx5e_reporter_rq_cqe_err(rq);
619 }
620 
mlx5e_alloc_mpwqe_rq_drop_page(struct mlx5e_rq * rq)621 static int mlx5e_alloc_mpwqe_rq_drop_page(struct mlx5e_rq *rq)
622 {
623 	rq->wqe_overflow.page = alloc_page(GFP_KERNEL);
624 	if (!rq->wqe_overflow.page)
625 		return -ENOMEM;
626 
627 	rq->wqe_overflow.addr = dma_map_page(rq->pdev, rq->wqe_overflow.page, 0,
628 					     PAGE_SIZE, rq->buff.map_dir);
629 	if (dma_mapping_error(rq->pdev, rq->wqe_overflow.addr)) {
630 		__free_page(rq->wqe_overflow.page);
631 		return -ENOMEM;
632 	}
633 	return 0;
634 }
635 
mlx5e_free_mpwqe_rq_drop_page(struct mlx5e_rq * rq)636 static void mlx5e_free_mpwqe_rq_drop_page(struct mlx5e_rq *rq)
637 {
638 	 dma_unmap_page(rq->pdev, rq->wqe_overflow.addr, PAGE_SIZE,
639 			rq->buff.map_dir);
640 	 __free_page(rq->wqe_overflow.page);
641 }
642 
mlx5e_init_rxq_rq(struct mlx5e_channel * c,struct mlx5e_params * params,u32 xdp_frag_size,struct mlx5e_rq * rq)643 static int mlx5e_init_rxq_rq(struct mlx5e_channel *c, struct mlx5e_params *params,
644 			     u32 xdp_frag_size, struct mlx5e_rq *rq)
645 {
646 	struct mlx5_core_dev *mdev = c->mdev;
647 	int err;
648 
649 	rq->wq_type      = params->rq_wq_type;
650 	rq->pdev         = c->pdev;
651 	rq->netdev       = c->netdev;
652 	rq->priv         = c->priv;
653 	rq->tstamp       = c->tstamp;
654 	rq->clock        = &mdev->clock;
655 	rq->icosq        = &c->icosq;
656 	rq->ix           = c->ix;
657 	rq->channel      = c;
658 	rq->mdev         = mdev;
659 	rq->hw_mtu =
660 		MLX5E_SW2HW_MTU(params, params->sw_mtu) - ETH_FCS_LEN * !params->scatter_fcs_en;
661 	rq->xdpsq        = &c->rq_xdpsq;
662 	rq->stats        = &c->priv->channel_stats[c->ix]->rq;
663 	rq->ptp_cyc2time = mlx5_rq_ts_translator(mdev);
664 	err = mlx5e_rq_set_handlers(rq, params, NULL);
665 	if (err)
666 		return err;
667 
668 	return __xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq->ix, c->napi.napi_id,
669 				  xdp_frag_size);
670 }
671 
mlx5_rq_shampo_alloc(struct mlx5_core_dev * mdev,struct mlx5e_params * params,struct mlx5e_rq_param * rqp,struct mlx5e_rq * rq,u32 * pool_size,int node)672 static int mlx5_rq_shampo_alloc(struct mlx5_core_dev *mdev,
673 				struct mlx5e_params *params,
674 				struct mlx5e_rq_param *rqp,
675 				struct mlx5e_rq *rq,
676 				u32 *pool_size,
677 				int node)
678 {
679 	void *wqc = MLX5_ADDR_OF(rqc, rqp->rqc, wq);
680 	int wq_size;
681 	int err;
682 
683 	if (!test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state))
684 		return 0;
685 	err = mlx5e_rq_shampo_hd_alloc(rq, node);
686 	if (err)
687 		goto out;
688 	rq->mpwqe.shampo->hd_per_wq =
689 		mlx5e_shampo_hd_per_wq(mdev, params, rqp);
690 	err = mlx5e_create_rq_hd_umr_mkey(mdev, rq);
691 	if (err)
692 		goto err_shampo_hd;
693 	err = mlx5e_rq_shampo_hd_info_alloc(rq, node);
694 	if (err)
695 		goto err_shampo_info;
696 	rq->hw_gro_data = kvzalloc_node(sizeof(*rq->hw_gro_data), GFP_KERNEL, node);
697 	if (!rq->hw_gro_data) {
698 		err = -ENOMEM;
699 		goto err_hw_gro_data;
700 	}
701 	rq->mpwqe.shampo->key =
702 		cpu_to_be32(rq->mpwqe.shampo->mkey);
703 	rq->mpwqe.shampo->hd_per_wqe =
704 		mlx5e_shampo_hd_per_wqe(mdev, params, rqp);
705 	wq_size = BIT(MLX5_GET(wq, wqc, log_wq_sz));
706 	*pool_size += (rq->mpwqe.shampo->hd_per_wqe * wq_size) /
707 		     MLX5E_SHAMPO_WQ_HEADER_PER_PAGE;
708 	return 0;
709 
710 err_hw_gro_data:
711 	mlx5e_rq_shampo_hd_info_free(rq);
712 err_shampo_info:
713 	mlx5_core_destroy_mkey(mdev, rq->mpwqe.shampo->mkey);
714 err_shampo_hd:
715 	mlx5e_rq_shampo_hd_free(rq);
716 out:
717 	return err;
718 }
719 
mlx5e_rq_free_shampo(struct mlx5e_rq * rq)720 static void mlx5e_rq_free_shampo(struct mlx5e_rq *rq)
721 {
722 	if (!test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state))
723 		return;
724 
725 	kvfree(rq->hw_gro_data);
726 	mlx5e_rq_shampo_hd_info_free(rq);
727 	mlx5_core_destroy_mkey(rq->mdev, rq->mpwqe.shampo->mkey);
728 	mlx5e_rq_shampo_hd_free(rq);
729 }
730 
mlx5e_alloc_rq(struct mlx5e_params * params,struct mlx5e_xsk_param * xsk,struct mlx5e_rq_param * rqp,int node,struct mlx5e_rq * rq)731 static int mlx5e_alloc_rq(struct mlx5e_params *params,
732 			  struct mlx5e_xsk_param *xsk,
733 			  struct mlx5e_rq_param *rqp,
734 			  int node, struct mlx5e_rq *rq)
735 {
736 	struct mlx5_core_dev *mdev = rq->mdev;
737 	void *rqc = rqp->rqc;
738 	void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
739 	u32 pool_size;
740 	int wq_sz;
741 	int err;
742 	int i;
743 
744 	rqp->wq.db_numa_node = node;
745 	INIT_WORK(&rq->recover_work, mlx5e_rq_err_cqe_work);
746 
747 	if (params->xdp_prog)
748 		bpf_prog_inc(params->xdp_prog);
749 	RCU_INIT_POINTER(rq->xdp_prog, params->xdp_prog);
750 
751 	rq->buff.map_dir = params->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
752 	rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params, xsk);
753 	pool_size = 1 << params->log_rq_mtu_frames;
754 
755 	rq->mkey_be = cpu_to_be32(mdev->mlx5e_res.hw_objs.mkey);
756 
757 	switch (rq->wq_type) {
758 	case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
759 		err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->mpwqe.wq,
760 					&rq->wq_ctrl);
761 		if (err)
762 			goto err_rq_xdp_prog;
763 
764 		err = mlx5e_alloc_mpwqe_rq_drop_page(rq);
765 		if (err)
766 			goto err_rq_wq_destroy;
767 
768 		rq->mpwqe.wq.db = &rq->mpwqe.wq.db[MLX5_RCV_DBR];
769 
770 		wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
771 
772 		rq->mpwqe.page_shift = mlx5e_mpwrq_page_shift(mdev, xsk);
773 		rq->mpwqe.umr_mode = mlx5e_mpwrq_umr_mode(mdev, xsk);
774 		rq->mpwqe.pages_per_wqe =
775 			mlx5e_mpwrq_pages_per_wqe(mdev, rq->mpwqe.page_shift,
776 						  rq->mpwqe.umr_mode);
777 		rq->mpwqe.umr_wqebbs =
778 			mlx5e_mpwrq_umr_wqebbs(mdev, rq->mpwqe.page_shift,
779 					       rq->mpwqe.umr_mode);
780 		rq->mpwqe.mtts_per_wqe =
781 			mlx5e_mpwrq_mtts_per_wqe(mdev, rq->mpwqe.page_shift,
782 						 rq->mpwqe.umr_mode);
783 
784 		pool_size = rq->mpwqe.pages_per_wqe <<
785 			mlx5e_mpwqe_get_log_rq_size(mdev, params, xsk);
786 
787 		if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params, xsk) && params->xdp_prog)
788 			pool_size *= 2; /* additional page per packet for the linear part */
789 
790 		rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk);
791 		rq->mpwqe.num_strides =
792 			BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk));
793 		rq->mpwqe.min_wqe_bulk = mlx5e_mpwqe_get_min_wqe_bulk(wq_sz);
794 
795 		rq->buff.frame0_sz = (1 << rq->mpwqe.log_stride_sz);
796 
797 		err = mlx5e_create_rq_umr_mkey(mdev, rq);
798 		if (err)
799 			goto err_rq_drop_page;
800 
801 		err = mlx5e_rq_alloc_mpwqe_info(rq, node);
802 		if (err)
803 			goto err_rq_mkey;
804 
805 		err = mlx5_rq_shampo_alloc(mdev, params, rqp, rq, &pool_size, node);
806 		if (err)
807 			goto err_free_mpwqe_info;
808 
809 		break;
810 	default: /* MLX5_WQ_TYPE_CYCLIC */
811 		err = mlx5_wq_cyc_create(mdev, &rqp->wq, rqc_wq, &rq->wqe.wq,
812 					 &rq->wq_ctrl);
813 		if (err)
814 			goto err_rq_xdp_prog;
815 
816 		rq->wqe.wq.db = &rq->wqe.wq.db[MLX5_RCV_DBR];
817 
818 		wq_sz = mlx5_wq_cyc_get_size(&rq->wqe.wq);
819 
820 		rq->wqe.info = rqp->frags_info;
821 		rq->buff.frame0_sz = rq->wqe.info.arr[0].frag_stride;
822 
823 		err = mlx5e_init_wqe_alloc_info(rq, node);
824 		if (err)
825 			goto err_rq_wq_destroy;
826 	}
827 
828 	if (xsk) {
829 		err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
830 						 MEM_TYPE_XSK_BUFF_POOL, NULL);
831 		xsk_pool_set_rxq_info(rq->xsk_pool, &rq->xdp_rxq);
832 	} else {
833 		/* Create a page_pool and register it with rxq */
834 		struct page_pool_params pp_params = { 0 };
835 
836 		pp_params.order     = 0;
837 		pp_params.flags     = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV | PP_FLAG_PAGE_FRAG;
838 		pp_params.pool_size = pool_size;
839 		pp_params.nid       = node;
840 		pp_params.dev       = rq->pdev;
841 		pp_params.napi      = rq->cq.napi;
842 		pp_params.dma_dir   = rq->buff.map_dir;
843 		pp_params.max_len   = PAGE_SIZE;
844 
845 		/* page_pool can be used even when there is no rq->xdp_prog,
846 		 * given page_pool does not handle DMA mapping there is no
847 		 * required state to clear. And page_pool gracefully handle
848 		 * elevated refcnt.
849 		 */
850 		rq->page_pool = page_pool_create(&pp_params);
851 		if (IS_ERR(rq->page_pool)) {
852 			err = PTR_ERR(rq->page_pool);
853 			rq->page_pool = NULL;
854 			goto err_free_by_rq_type;
855 		}
856 		if (xdp_rxq_info_is_reg(&rq->xdp_rxq))
857 			err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
858 							 MEM_TYPE_PAGE_POOL, rq->page_pool);
859 	}
860 	if (err)
861 		goto err_destroy_page_pool;
862 
863 	for (i = 0; i < wq_sz; i++) {
864 		if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
865 			struct mlx5e_rx_wqe_ll *wqe =
866 				mlx5_wq_ll_get_wqe(&rq->mpwqe.wq, i);
867 			u32 byte_count =
868 				rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
869 			u64 dma_offset = mul_u32_u32(i, rq->mpwqe.mtts_per_wqe) <<
870 				rq->mpwqe.page_shift;
871 			u16 headroom = test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state) ?
872 				       0 : rq->buff.headroom;
873 
874 			wqe->data[0].addr = cpu_to_be64(dma_offset + headroom);
875 			wqe->data[0].byte_count = cpu_to_be32(byte_count);
876 			wqe->data[0].lkey = rq->mpwqe.umr_mkey_be;
877 		} else {
878 			struct mlx5e_rx_wqe_cyc *wqe =
879 				mlx5_wq_cyc_get_wqe(&rq->wqe.wq, i);
880 			int f;
881 
882 			for (f = 0; f < rq->wqe.info.num_frags; f++) {
883 				u32 frag_size = rq->wqe.info.arr[f].frag_size |
884 					MLX5_HW_START_PADDING;
885 
886 				wqe->data[f].byte_count = cpu_to_be32(frag_size);
887 				wqe->data[f].lkey = rq->mkey_be;
888 			}
889 			/* check if num_frags is not a pow of two */
890 			if (rq->wqe.info.num_frags < (1 << rq->wqe.info.log_num_frags)) {
891 				wqe->data[f].byte_count = 0;
892 				wqe->data[f].lkey = params->terminate_lkey_be;
893 				wqe->data[f].addr = 0;
894 			}
895 		}
896 	}
897 
898 	INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
899 
900 	switch (params->rx_cq_moderation.cq_period_mode) {
901 	case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
902 		rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_CQE;
903 		break;
904 	case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
905 	default:
906 		rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
907 	}
908 
909 	return 0;
910 
911 err_destroy_page_pool:
912 	page_pool_destroy(rq->page_pool);
913 err_free_by_rq_type:
914 	switch (rq->wq_type) {
915 	case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
916 		mlx5e_rq_free_shampo(rq);
917 err_free_mpwqe_info:
918 		kvfree(rq->mpwqe.info);
919 err_rq_mkey:
920 		mlx5_core_destroy_mkey(mdev, be32_to_cpu(rq->mpwqe.umr_mkey_be));
921 err_rq_drop_page:
922 		mlx5e_free_mpwqe_rq_drop_page(rq);
923 		break;
924 	default: /* MLX5_WQ_TYPE_CYCLIC */
925 		mlx5e_free_wqe_alloc_info(rq);
926 	}
927 err_rq_wq_destroy:
928 	mlx5_wq_destroy(&rq->wq_ctrl);
929 err_rq_xdp_prog:
930 	if (params->xdp_prog)
931 		bpf_prog_put(params->xdp_prog);
932 
933 	return err;
934 }
935 
mlx5e_free_rq(struct mlx5e_rq * rq)936 static void mlx5e_free_rq(struct mlx5e_rq *rq)
937 {
938 	struct bpf_prog *old_prog;
939 
940 	if (xdp_rxq_info_is_reg(&rq->xdp_rxq)) {
941 		old_prog = rcu_dereference_protected(rq->xdp_prog,
942 						     lockdep_is_held(&rq->priv->state_lock));
943 		if (old_prog)
944 			bpf_prog_put(old_prog);
945 	}
946 
947 	switch (rq->wq_type) {
948 	case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
949 		kvfree(rq->mpwqe.info);
950 		mlx5_core_destroy_mkey(rq->mdev, be32_to_cpu(rq->mpwqe.umr_mkey_be));
951 		mlx5e_free_mpwqe_rq_drop_page(rq);
952 		mlx5e_rq_free_shampo(rq);
953 		break;
954 	default: /* MLX5_WQ_TYPE_CYCLIC */
955 		mlx5e_free_wqe_alloc_info(rq);
956 	}
957 
958 	xdp_rxq_info_unreg(&rq->xdp_rxq);
959 	page_pool_destroy(rq->page_pool);
960 	mlx5_wq_destroy(&rq->wq_ctrl);
961 }
962 
mlx5e_create_rq(struct mlx5e_rq * rq,struct mlx5e_rq_param * param)963 int mlx5e_create_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
964 {
965 	struct mlx5_core_dev *mdev = rq->mdev;
966 	u8 ts_format;
967 	void *in;
968 	void *rqc;
969 	void *wq;
970 	int inlen;
971 	int err;
972 
973 	inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
974 		sizeof(u64) * rq->wq_ctrl.buf.npages;
975 	in = kvzalloc(inlen, GFP_KERNEL);
976 	if (!in)
977 		return -ENOMEM;
978 
979 	ts_format = mlx5_is_real_time_rq(mdev) ?
980 			    MLX5_TIMESTAMP_FORMAT_REAL_TIME :
981 			    MLX5_TIMESTAMP_FORMAT_FREE_RUNNING;
982 	rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
983 	wq  = MLX5_ADDR_OF(rqc, rqc, wq);
984 
985 	memcpy(rqc, param->rqc, sizeof(param->rqc));
986 
987 	MLX5_SET(rqc,  rqc, cqn,		rq->cq.mcq.cqn);
988 	MLX5_SET(rqc,  rqc, state,		MLX5_RQC_STATE_RST);
989 	MLX5_SET(rqc,  rqc, ts_format,		ts_format);
990 	MLX5_SET(wq,   wq,  log_wq_pg_sz,	rq->wq_ctrl.buf.page_shift -
991 						MLX5_ADAPTER_PAGE_SHIFT);
992 	MLX5_SET64(wq, wq,  dbr_addr,		rq->wq_ctrl.db.dma);
993 
994 	if (test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state)) {
995 		MLX5_SET(wq, wq, log_headers_buffer_entry_num,
996 			 order_base_2(rq->mpwqe.shampo->hd_per_wq));
997 		MLX5_SET(wq, wq, headers_mkey, rq->mpwqe.shampo->mkey);
998 	}
999 
1000 	mlx5_fill_page_frag_array(&rq->wq_ctrl.buf,
1001 				  (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1002 
1003 	err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
1004 
1005 	kvfree(in);
1006 
1007 	return err;
1008 }
1009 
mlx5e_modify_rq_state(struct mlx5e_rq * rq,int curr_state,int next_state)1010 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state, int next_state)
1011 {
1012 	struct mlx5_core_dev *mdev = rq->mdev;
1013 
1014 	void *in;
1015 	void *rqc;
1016 	int inlen;
1017 	int err;
1018 
1019 	inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1020 	in = kvzalloc(inlen, GFP_KERNEL);
1021 	if (!in)
1022 		return -ENOMEM;
1023 
1024 	if (curr_state == MLX5_RQC_STATE_RST && next_state == MLX5_RQC_STATE_RDY)
1025 		mlx5e_rqwq_reset(rq);
1026 
1027 	rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1028 
1029 	MLX5_SET(modify_rq_in, in, rq_state, curr_state);
1030 	MLX5_SET(rqc, rqc, state, next_state);
1031 
1032 	err = mlx5_core_modify_rq(mdev, rq->rqn, in);
1033 
1034 	kvfree(in);
1035 
1036 	return err;
1037 }
1038 
mlx5e_flush_rq_cq(struct mlx5e_rq * rq)1039 static void mlx5e_flush_rq_cq(struct mlx5e_rq *rq)
1040 {
1041 	struct mlx5_cqwq *cqwq = &rq->cq.wq;
1042 	struct mlx5_cqe64 *cqe;
1043 
1044 	if (test_bit(MLX5E_RQ_STATE_MINI_CQE_ENHANCED, &rq->state)) {
1045 		while ((cqe = mlx5_cqwq_get_cqe_enahnced_comp(cqwq)))
1046 			mlx5_cqwq_pop(cqwq);
1047 	} else {
1048 		while ((cqe = mlx5_cqwq_get_cqe(cqwq)))
1049 			mlx5_cqwq_pop(cqwq);
1050 	}
1051 
1052 	mlx5_cqwq_update_db_record(cqwq);
1053 }
1054 
mlx5e_flush_rq(struct mlx5e_rq * rq,int curr_state)1055 int mlx5e_flush_rq(struct mlx5e_rq *rq, int curr_state)
1056 {
1057 	struct net_device *dev = rq->netdev;
1058 	int err;
1059 
1060 	err = mlx5e_modify_rq_state(rq, curr_state, MLX5_RQC_STATE_RST);
1061 	if (err) {
1062 		netdev_err(dev, "Failed to move rq 0x%x to reset\n", rq->rqn);
1063 		return err;
1064 	}
1065 
1066 	mlx5e_free_rx_descs(rq);
1067 	mlx5e_flush_rq_cq(rq);
1068 
1069 	err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
1070 	if (err) {
1071 		netdev_err(dev, "Failed to move rq 0x%x to ready\n", rq->rqn);
1072 		return err;
1073 	}
1074 
1075 	return 0;
1076 }
1077 
mlx5e_modify_rq_vsd(struct mlx5e_rq * rq,bool vsd)1078 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
1079 {
1080 	struct mlx5_core_dev *mdev = rq->mdev;
1081 	void *in;
1082 	void *rqc;
1083 	int inlen;
1084 	int err;
1085 
1086 	inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1087 	in = kvzalloc(inlen, GFP_KERNEL);
1088 	if (!in)
1089 		return -ENOMEM;
1090 
1091 	rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1092 
1093 	MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
1094 	MLX5_SET64(modify_rq_in, in, modify_bitmask,
1095 		   MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
1096 	MLX5_SET(rqc, rqc, vsd, vsd);
1097 	MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
1098 
1099 	err = mlx5_core_modify_rq(mdev, rq->rqn, in);
1100 
1101 	kvfree(in);
1102 
1103 	return err;
1104 }
1105 
mlx5e_destroy_rq(struct mlx5e_rq * rq)1106 void mlx5e_destroy_rq(struct mlx5e_rq *rq)
1107 {
1108 	mlx5_core_destroy_rq(rq->mdev, rq->rqn);
1109 }
1110 
mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq * rq,int wait_time)1111 int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time)
1112 {
1113 	unsigned long exp_time = jiffies + msecs_to_jiffies(wait_time);
1114 
1115 	u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5e_rqwq_get_size(rq));
1116 
1117 	do {
1118 		if (mlx5e_rqwq_get_cur_sz(rq) >= min_wqes)
1119 			return 0;
1120 
1121 		msleep(20);
1122 	} while (time_before(jiffies, exp_time));
1123 
1124 	netdev_warn(rq->netdev, "Failed to get min RX wqes on Channel[%d] RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
1125 		    rq->ix, rq->rqn, mlx5e_rqwq_get_cur_sz(rq), min_wqes);
1126 
1127 	mlx5e_reporter_rx_timeout(rq);
1128 	return -ETIMEDOUT;
1129 }
1130 
mlx5e_free_rx_missing_descs(struct mlx5e_rq * rq)1131 void mlx5e_free_rx_missing_descs(struct mlx5e_rq *rq)
1132 {
1133 	struct mlx5_wq_ll *wq;
1134 	u16 head;
1135 	int i;
1136 
1137 	if (rq->wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
1138 		return;
1139 
1140 	wq = &rq->mpwqe.wq;
1141 	head = wq->head;
1142 
1143 	/* Release WQEs that are in missing state: they have been
1144 	 * popped from the list after completion but were not freed
1145 	 * due to deferred release.
1146 	 * Also free the linked-list reserved entry, hence the "+ 1".
1147 	 */
1148 	for (i = 0; i < mlx5_wq_ll_missing(wq) + 1; i++) {
1149 		rq->dealloc_wqe(rq, head);
1150 		head = mlx5_wq_ll_get_wqe_next_ix(wq, head);
1151 	}
1152 
1153 	if (test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state)) {
1154 		u16 len;
1155 
1156 		len = (rq->mpwqe.shampo->pi - rq->mpwqe.shampo->ci) &
1157 		      (rq->mpwqe.shampo->hd_per_wq - 1);
1158 		mlx5e_shampo_dealloc_hd(rq, len, rq->mpwqe.shampo->ci, false);
1159 		rq->mpwqe.shampo->pi = rq->mpwqe.shampo->ci;
1160 	}
1161 
1162 	rq->mpwqe.actual_wq_head = wq->head;
1163 	rq->mpwqe.umr_in_progress = 0;
1164 	rq->mpwqe.umr_completed = 0;
1165 }
1166 
mlx5e_free_rx_descs(struct mlx5e_rq * rq)1167 void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
1168 {
1169 	__be16 wqe_ix_be;
1170 	u16 wqe_ix;
1171 
1172 	if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
1173 		struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
1174 
1175 		mlx5e_free_rx_missing_descs(rq);
1176 
1177 		while (!mlx5_wq_ll_is_empty(wq)) {
1178 			struct mlx5e_rx_wqe_ll *wqe;
1179 
1180 			wqe_ix_be = *wq->tail_next;
1181 			wqe_ix    = be16_to_cpu(wqe_ix_be);
1182 			wqe       = mlx5_wq_ll_get_wqe(wq, wqe_ix);
1183 			rq->dealloc_wqe(rq, wqe_ix);
1184 			mlx5_wq_ll_pop(wq, wqe_ix_be,
1185 				       &wqe->next.next_wqe_index);
1186 		}
1187 
1188 		if (test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state))
1189 			mlx5e_shampo_dealloc_hd(rq, rq->mpwqe.shampo->hd_per_wq,
1190 						0, true);
1191 	} else {
1192 		struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1193 		u16 missing = mlx5_wq_cyc_missing(wq);
1194 		u16 head = mlx5_wq_cyc_get_head(wq);
1195 
1196 		while (!mlx5_wq_cyc_is_empty(wq)) {
1197 			wqe_ix = mlx5_wq_cyc_get_tail(wq);
1198 			rq->dealloc_wqe(rq, wqe_ix);
1199 			mlx5_wq_cyc_pop(wq);
1200 		}
1201 		/* Missing slots might also contain unreleased pages due to
1202 		 * deferred release.
1203 		 */
1204 		while (missing--) {
1205 			wqe_ix = mlx5_wq_cyc_ctr2ix(wq, head++);
1206 			rq->dealloc_wqe(rq, wqe_ix);
1207 		}
1208 	}
1209 
1210 }
1211 
mlx5e_open_rq(struct mlx5e_params * params,struct mlx5e_rq_param * param,struct mlx5e_xsk_param * xsk,int node,struct mlx5e_rq * rq)1212 int mlx5e_open_rq(struct mlx5e_params *params, struct mlx5e_rq_param *param,
1213 		  struct mlx5e_xsk_param *xsk, int node,
1214 		  struct mlx5e_rq *rq)
1215 {
1216 	struct mlx5_core_dev *mdev = rq->mdev;
1217 	int err;
1218 
1219 	if (params->packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO)
1220 		__set_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state);
1221 
1222 	err = mlx5e_alloc_rq(params, xsk, param, node, rq);
1223 	if (err)
1224 		return err;
1225 
1226 	err = mlx5e_create_rq(rq, param);
1227 	if (err)
1228 		goto err_free_rq;
1229 
1230 	err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
1231 	if (err)
1232 		goto err_destroy_rq;
1233 
1234 	if (MLX5_CAP_ETH(mdev, cqe_checksum_full))
1235 		__set_bit(MLX5E_RQ_STATE_CSUM_FULL, &rq->state);
1236 
1237 	if (params->rx_dim_enabled)
1238 		__set_bit(MLX5E_RQ_STATE_DIM, &rq->state);
1239 
1240 	/* We disable csum_complete when XDP is enabled since
1241 	 * XDP programs might manipulate packets which will render
1242 	 * skb->checksum incorrect.
1243 	 */
1244 	if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE) || params->xdp_prog)
1245 		__set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &rq->state);
1246 
1247 	/* For CQE compression on striding RQ, use stride index provided by
1248 	 * HW if capability is supported.
1249 	 */
1250 	if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) &&
1251 	    MLX5_CAP_GEN(mdev, mini_cqe_resp_stride_index))
1252 		__set_bit(MLX5E_RQ_STATE_MINI_CQE_HW_STRIDX, &rq->state);
1253 
1254 	/* For enhanced CQE compression packet processing. decompress
1255 	 * session according to the enhanced layout.
1256 	 */
1257 	if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS) &&
1258 	    MLX5_CAP_GEN(mdev, enhanced_cqe_compression))
1259 		__set_bit(MLX5E_RQ_STATE_MINI_CQE_ENHANCED, &rq->state);
1260 
1261 	return 0;
1262 
1263 err_destroy_rq:
1264 	mlx5e_destroy_rq(rq);
1265 err_free_rq:
1266 	mlx5e_free_rq(rq);
1267 
1268 	return err;
1269 }
1270 
mlx5e_activate_rq(struct mlx5e_rq * rq)1271 void mlx5e_activate_rq(struct mlx5e_rq *rq)
1272 {
1273 	set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
1274 }
1275 
mlx5e_deactivate_rq(struct mlx5e_rq * rq)1276 void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
1277 {
1278 	clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
1279 	synchronize_net(); /* Sync with NAPI to prevent mlx5e_post_rx_wqes. */
1280 }
1281 
mlx5e_close_rq(struct mlx5e_rq * rq)1282 void mlx5e_close_rq(struct mlx5e_rq *rq)
1283 {
1284 	cancel_work_sync(&rq->dim.work);
1285 	cancel_work_sync(&rq->recover_work);
1286 	mlx5e_destroy_rq(rq);
1287 	mlx5e_free_rx_descs(rq);
1288 	mlx5e_free_rq(rq);
1289 }
1290 
mlx5e_free_xdpsq_db(struct mlx5e_xdpsq * sq)1291 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
1292 {
1293 	kvfree(sq->db.xdpi_fifo.xi);
1294 	kvfree(sq->db.wqe_info);
1295 }
1296 
mlx5e_alloc_xdpsq_fifo(struct mlx5e_xdpsq * sq,int numa)1297 static int mlx5e_alloc_xdpsq_fifo(struct mlx5e_xdpsq *sq, int numa)
1298 {
1299 	struct mlx5e_xdp_info_fifo *xdpi_fifo = &sq->db.xdpi_fifo;
1300 	int wq_sz        = mlx5_wq_cyc_get_size(&sq->wq);
1301 	int entries;
1302 	size_t size;
1303 
1304 	/* upper bound for maximum num of entries of all xmit_modes. */
1305 	entries = roundup_pow_of_two(wq_sz * MLX5_SEND_WQEBB_NUM_DS *
1306 				     MLX5E_XDP_FIFO_ENTRIES2DS_MAX_RATIO);
1307 
1308 	size = array_size(sizeof(*xdpi_fifo->xi), entries);
1309 	xdpi_fifo->xi = kvzalloc_node(size, GFP_KERNEL, numa);
1310 	if (!xdpi_fifo->xi)
1311 		return -ENOMEM;
1312 
1313 	xdpi_fifo->pc   = &sq->xdpi_fifo_pc;
1314 	xdpi_fifo->cc   = &sq->xdpi_fifo_cc;
1315 	xdpi_fifo->mask = entries - 1;
1316 
1317 	return 0;
1318 }
1319 
mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq * sq,int numa)1320 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
1321 {
1322 	int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1323 	size_t size;
1324 	int err;
1325 
1326 	size = array_size(sizeof(*sq->db.wqe_info), wq_sz);
1327 	sq->db.wqe_info = kvzalloc_node(size, GFP_KERNEL, numa);
1328 	if (!sq->db.wqe_info)
1329 		return -ENOMEM;
1330 
1331 	err = mlx5e_alloc_xdpsq_fifo(sq, numa);
1332 	if (err) {
1333 		mlx5e_free_xdpsq_db(sq);
1334 		return err;
1335 	}
1336 
1337 	return 0;
1338 }
1339 
mlx5e_alloc_xdpsq(struct mlx5e_channel * c,struct mlx5e_params * params,struct xsk_buff_pool * xsk_pool,struct mlx5e_sq_param * param,struct mlx5e_xdpsq * sq,bool is_redirect)1340 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
1341 			     struct mlx5e_params *params,
1342 			     struct xsk_buff_pool *xsk_pool,
1343 			     struct mlx5e_sq_param *param,
1344 			     struct mlx5e_xdpsq *sq,
1345 			     bool is_redirect)
1346 {
1347 	void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1348 	struct mlx5_core_dev *mdev = c->mdev;
1349 	struct mlx5_wq_cyc *wq = &sq->wq;
1350 	int err;
1351 
1352 	sq->pdev      = c->pdev;
1353 	sq->mkey_be   = c->mkey_be;
1354 	sq->channel   = c;
1355 	sq->uar_map   = mdev->mlx5e_res.hw_objs.bfreg.map;
1356 	sq->min_inline_mode = params->tx_min_inline_mode;
1357 	sq->hw_mtu    = MLX5E_SW2HW_MTU(params, params->sw_mtu) - ETH_FCS_LEN;
1358 	sq->xsk_pool  = xsk_pool;
1359 
1360 	sq->stats = sq->xsk_pool ?
1361 		&c->priv->channel_stats[c->ix]->xsksq :
1362 		is_redirect ?
1363 			&c->priv->channel_stats[c->ix]->xdpsq :
1364 			&c->priv->channel_stats[c->ix]->rq_xdpsq;
1365 	sq->stop_room = param->is_mpw ? mlx5e_stop_room_for_mpwqe(mdev) :
1366 					mlx5e_stop_room_for_max_wqe(mdev);
1367 	sq->max_sq_mpw_wqebbs = mlx5e_get_max_sq_aligned_wqebbs(mdev);
1368 
1369 	param->wq.db_numa_node = cpu_to_node(c->cpu);
1370 	err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1371 	if (err)
1372 		return err;
1373 	wq->db = &wq->db[MLX5_SND_DBR];
1374 
1375 	err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
1376 	if (err)
1377 		goto err_sq_wq_destroy;
1378 
1379 	return 0;
1380 
1381 err_sq_wq_destroy:
1382 	mlx5_wq_destroy(&sq->wq_ctrl);
1383 
1384 	return err;
1385 }
1386 
mlx5e_free_xdpsq(struct mlx5e_xdpsq * sq)1387 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
1388 {
1389 	mlx5e_free_xdpsq_db(sq);
1390 	mlx5_wq_destroy(&sq->wq_ctrl);
1391 }
1392 
mlx5e_free_icosq_db(struct mlx5e_icosq * sq)1393 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
1394 {
1395 	kvfree(sq->db.wqe_info);
1396 }
1397 
mlx5e_alloc_icosq_db(struct mlx5e_icosq * sq,int numa)1398 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
1399 {
1400 	int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1401 	size_t size;
1402 
1403 	size = array_size(wq_sz, sizeof(*sq->db.wqe_info));
1404 	sq->db.wqe_info = kvzalloc_node(size, GFP_KERNEL, numa);
1405 	if (!sq->db.wqe_info)
1406 		return -ENOMEM;
1407 
1408 	return 0;
1409 }
1410 
mlx5e_icosq_err_cqe_work(struct work_struct * recover_work)1411 static void mlx5e_icosq_err_cqe_work(struct work_struct *recover_work)
1412 {
1413 	struct mlx5e_icosq *sq = container_of(recover_work, struct mlx5e_icosq,
1414 					      recover_work);
1415 
1416 	mlx5e_reporter_icosq_cqe_err(sq);
1417 }
1418 
mlx5e_async_icosq_err_cqe_work(struct work_struct * recover_work)1419 static void mlx5e_async_icosq_err_cqe_work(struct work_struct *recover_work)
1420 {
1421 	struct mlx5e_icosq *sq = container_of(recover_work, struct mlx5e_icosq,
1422 					      recover_work);
1423 
1424 	/* Not implemented yet. */
1425 
1426 	netdev_warn(sq->channel->netdev, "async_icosq recovery is not implemented\n");
1427 }
1428 
mlx5e_alloc_icosq(struct mlx5e_channel * c,struct mlx5e_sq_param * param,struct mlx5e_icosq * sq,work_func_t recover_work_func)1429 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
1430 			     struct mlx5e_sq_param *param,
1431 			     struct mlx5e_icosq *sq,
1432 			     work_func_t recover_work_func)
1433 {
1434 	void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1435 	struct mlx5_core_dev *mdev = c->mdev;
1436 	struct mlx5_wq_cyc *wq = &sq->wq;
1437 	int err;
1438 
1439 	sq->channel   = c;
1440 	sq->uar_map   = mdev->mlx5e_res.hw_objs.bfreg.map;
1441 	sq->reserved_room = param->stop_room;
1442 
1443 	param->wq.db_numa_node = cpu_to_node(c->cpu);
1444 	err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1445 	if (err)
1446 		return err;
1447 	wq->db = &wq->db[MLX5_SND_DBR];
1448 
1449 	err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
1450 	if (err)
1451 		goto err_sq_wq_destroy;
1452 
1453 	INIT_WORK(&sq->recover_work, recover_work_func);
1454 
1455 	return 0;
1456 
1457 err_sq_wq_destroy:
1458 	mlx5_wq_destroy(&sq->wq_ctrl);
1459 
1460 	return err;
1461 }
1462 
mlx5e_free_icosq(struct mlx5e_icosq * sq)1463 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
1464 {
1465 	mlx5e_free_icosq_db(sq);
1466 	mlx5_wq_destroy(&sq->wq_ctrl);
1467 }
1468 
mlx5e_free_txqsq_db(struct mlx5e_txqsq * sq)1469 void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
1470 {
1471 	kvfree(sq->db.wqe_info);
1472 	kvfree(sq->db.skb_fifo.fifo);
1473 	kvfree(sq->db.dma_fifo);
1474 }
1475 
mlx5e_alloc_txqsq_db(struct mlx5e_txqsq * sq,int numa)1476 int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
1477 {
1478 	int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1479 	int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1480 
1481 	sq->db.dma_fifo = kvzalloc_node(array_size(df_sz,
1482 						   sizeof(*sq->db.dma_fifo)),
1483 					GFP_KERNEL, numa);
1484 	sq->db.skb_fifo.fifo = kvzalloc_node(array_size(df_sz,
1485 							sizeof(*sq->db.skb_fifo.fifo)),
1486 					GFP_KERNEL, numa);
1487 	sq->db.wqe_info = kvzalloc_node(array_size(wq_sz,
1488 						   sizeof(*sq->db.wqe_info)),
1489 					GFP_KERNEL, numa);
1490 	if (!sq->db.dma_fifo || !sq->db.skb_fifo.fifo || !sq->db.wqe_info) {
1491 		mlx5e_free_txqsq_db(sq);
1492 		return -ENOMEM;
1493 	}
1494 
1495 	sq->dma_fifo_mask = df_sz - 1;
1496 
1497 	sq->db.skb_fifo.pc   = &sq->skb_fifo_pc;
1498 	sq->db.skb_fifo.cc   = &sq->skb_fifo_cc;
1499 	sq->db.skb_fifo.mask = df_sz - 1;
1500 
1501 	return 0;
1502 }
1503 
mlx5e_alloc_txqsq(struct mlx5e_channel * c,int txq_ix,struct mlx5e_params * params,struct mlx5e_sq_param * param,struct mlx5e_txqsq * sq,int tc)1504 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
1505 			     int txq_ix,
1506 			     struct mlx5e_params *params,
1507 			     struct mlx5e_sq_param *param,
1508 			     struct mlx5e_txqsq *sq,
1509 			     int tc)
1510 {
1511 	void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1512 	struct mlx5_core_dev *mdev = c->mdev;
1513 	struct mlx5_wq_cyc *wq = &sq->wq;
1514 	int err;
1515 
1516 	sq->pdev      = c->pdev;
1517 	sq->clock     = &mdev->clock;
1518 	sq->mkey_be   = c->mkey_be;
1519 	sq->netdev    = c->netdev;
1520 	sq->mdev      = c->mdev;
1521 	sq->channel   = c;
1522 	sq->priv      = c->priv;
1523 	sq->ch_ix     = c->ix;
1524 	sq->txq_ix    = txq_ix;
1525 	sq->uar_map   = mdev->mlx5e_res.hw_objs.bfreg.map;
1526 	sq->min_inline_mode = params->tx_min_inline_mode;
1527 	sq->hw_mtu    = MLX5E_SW2HW_MTU(params, params->sw_mtu);
1528 	sq->max_sq_mpw_wqebbs = mlx5e_get_max_sq_aligned_wqebbs(mdev);
1529 	INIT_WORK(&sq->recover_work, mlx5e_tx_err_cqe_work);
1530 	if (!MLX5_CAP_ETH(mdev, wqe_vlan_insert))
1531 		set_bit(MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE, &sq->state);
1532 	if (mlx5_ipsec_device_caps(c->priv->mdev))
1533 		set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
1534 	if (param->is_mpw)
1535 		set_bit(MLX5E_SQ_STATE_MPWQE, &sq->state);
1536 	sq->stop_room = param->stop_room;
1537 	sq->ptp_cyc2time = mlx5_sq_ts_translator(mdev);
1538 
1539 	param->wq.db_numa_node = cpu_to_node(c->cpu);
1540 	err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1541 	if (err)
1542 		return err;
1543 	wq->db    = &wq->db[MLX5_SND_DBR];
1544 
1545 	err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
1546 	if (err)
1547 		goto err_sq_wq_destroy;
1548 
1549 	INIT_WORK(&sq->dim.work, mlx5e_tx_dim_work);
1550 	sq->dim.mode = params->tx_cq_moderation.cq_period_mode;
1551 
1552 	return 0;
1553 
1554 err_sq_wq_destroy:
1555 	mlx5_wq_destroy(&sq->wq_ctrl);
1556 
1557 	return err;
1558 }
1559 
mlx5e_free_txqsq(struct mlx5e_txqsq * sq)1560 void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1561 {
1562 	mlx5e_free_txqsq_db(sq);
1563 	mlx5_wq_destroy(&sq->wq_ctrl);
1564 }
1565 
mlx5e_create_sq(struct mlx5_core_dev * mdev,struct mlx5e_sq_param * param,struct mlx5e_create_sq_param * csp,u32 * sqn)1566 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1567 			   struct mlx5e_sq_param *param,
1568 			   struct mlx5e_create_sq_param *csp,
1569 			   u32 *sqn)
1570 {
1571 	u8 ts_format;
1572 	void *in;
1573 	void *sqc;
1574 	void *wq;
1575 	int inlen;
1576 	int err;
1577 
1578 	inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1579 		sizeof(u64) * csp->wq_ctrl->buf.npages;
1580 	in = kvzalloc(inlen, GFP_KERNEL);
1581 	if (!in)
1582 		return -ENOMEM;
1583 
1584 	ts_format = mlx5_is_real_time_sq(mdev) ?
1585 			    MLX5_TIMESTAMP_FORMAT_REAL_TIME :
1586 			    MLX5_TIMESTAMP_FORMAT_FREE_RUNNING;
1587 	sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1588 	wq = MLX5_ADDR_OF(sqc, sqc, wq);
1589 
1590 	memcpy(sqc, param->sqc, sizeof(param->sqc));
1591 	MLX5_SET(sqc,  sqc, tis_lst_sz, csp->tis_lst_sz);
1592 	MLX5_SET(sqc,  sqc, tis_num_0, csp->tisn);
1593 	MLX5_SET(sqc,  sqc, cqn, csp->cqn);
1594 	MLX5_SET(sqc,  sqc, ts_cqe_to_dest_cqn, csp->ts_cqe_to_dest_cqn);
1595 	MLX5_SET(sqc,  sqc, ts_format, ts_format);
1596 
1597 
1598 	if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1599 		MLX5_SET(sqc,  sqc, min_wqe_inline_mode, csp->min_inline_mode);
1600 
1601 	MLX5_SET(sqc,  sqc, state, MLX5_SQC_STATE_RST);
1602 	MLX5_SET(sqc,  sqc, flush_in_error_en, 1);
1603 
1604 	MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
1605 	MLX5_SET(wq,   wq, uar_page,      mdev->mlx5e_res.hw_objs.bfreg.index);
1606 	MLX5_SET(wq,   wq, log_wq_pg_sz,  csp->wq_ctrl->buf.page_shift -
1607 					  MLX5_ADAPTER_PAGE_SHIFT);
1608 	MLX5_SET64(wq, wq, dbr_addr,      csp->wq_ctrl->db.dma);
1609 
1610 	mlx5_fill_page_frag_array(&csp->wq_ctrl->buf,
1611 				  (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1612 
1613 	err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1614 
1615 	kvfree(in);
1616 
1617 	return err;
1618 }
1619 
mlx5e_modify_sq(struct mlx5_core_dev * mdev,u32 sqn,struct mlx5e_modify_sq_param * p)1620 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1621 		    struct mlx5e_modify_sq_param *p)
1622 {
1623 	u64 bitmask = 0;
1624 	void *in;
1625 	void *sqc;
1626 	int inlen;
1627 	int err;
1628 
1629 	inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1630 	in = kvzalloc(inlen, GFP_KERNEL);
1631 	if (!in)
1632 		return -ENOMEM;
1633 
1634 	sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1635 
1636 	MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1637 	MLX5_SET(sqc, sqc, state, p->next_state);
1638 	if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1639 		bitmask |= 1;
1640 		MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, p->rl_index);
1641 	}
1642 	if (p->qos_update && p->next_state == MLX5_SQC_STATE_RDY) {
1643 		bitmask |= 1 << 2;
1644 		MLX5_SET(sqc, sqc, qos_queue_group_id, p->qos_queue_group_id);
1645 	}
1646 	MLX5_SET64(modify_sq_in, in, modify_bitmask, bitmask);
1647 
1648 	err = mlx5_core_modify_sq(mdev, sqn, in);
1649 
1650 	kvfree(in);
1651 
1652 	return err;
1653 }
1654 
mlx5e_destroy_sq(struct mlx5_core_dev * mdev,u32 sqn)1655 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1656 {
1657 	mlx5_core_destroy_sq(mdev, sqn);
1658 }
1659 
mlx5e_create_sq_rdy(struct mlx5_core_dev * mdev,struct mlx5e_sq_param * param,struct mlx5e_create_sq_param * csp,u16 qos_queue_group_id,u32 * sqn)1660 int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1661 			struct mlx5e_sq_param *param,
1662 			struct mlx5e_create_sq_param *csp,
1663 			u16 qos_queue_group_id,
1664 			u32 *sqn)
1665 {
1666 	struct mlx5e_modify_sq_param msp = {0};
1667 	int err;
1668 
1669 	err = mlx5e_create_sq(mdev, param, csp, sqn);
1670 	if (err)
1671 		return err;
1672 
1673 	msp.curr_state = MLX5_SQC_STATE_RST;
1674 	msp.next_state = MLX5_SQC_STATE_RDY;
1675 	if (qos_queue_group_id) {
1676 		msp.qos_update = true;
1677 		msp.qos_queue_group_id = qos_queue_group_id;
1678 	}
1679 	err = mlx5e_modify_sq(mdev, *sqn, &msp);
1680 	if (err)
1681 		mlx5e_destroy_sq(mdev, *sqn);
1682 
1683 	return err;
1684 }
1685 
1686 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1687 				struct mlx5e_txqsq *sq, u32 rate);
1688 
mlx5e_open_txqsq(struct mlx5e_channel * c,u32 tisn,int txq_ix,struct mlx5e_params * params,struct mlx5e_sq_param * param,struct mlx5e_txqsq * sq,int tc,u16 qos_queue_group_id,struct mlx5e_sq_stats * sq_stats)1689 int mlx5e_open_txqsq(struct mlx5e_channel *c, u32 tisn, int txq_ix,
1690 		     struct mlx5e_params *params, struct mlx5e_sq_param *param,
1691 		     struct mlx5e_txqsq *sq, int tc, u16 qos_queue_group_id,
1692 		     struct mlx5e_sq_stats *sq_stats)
1693 {
1694 	struct mlx5e_create_sq_param csp = {};
1695 	u32 tx_rate;
1696 	int err;
1697 
1698 	err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq, tc);
1699 	if (err)
1700 		return err;
1701 
1702 	sq->stats = sq_stats;
1703 
1704 	csp.tisn            = tisn;
1705 	csp.tis_lst_sz      = 1;
1706 	csp.cqn             = sq->cq.mcq.cqn;
1707 	csp.wq_ctrl         = &sq->wq_ctrl;
1708 	csp.min_inline_mode = sq->min_inline_mode;
1709 	err = mlx5e_create_sq_rdy(c->mdev, param, &csp, qos_queue_group_id, &sq->sqn);
1710 	if (err)
1711 		goto err_free_txqsq;
1712 
1713 	tx_rate = c->priv->tx_rates[sq->txq_ix];
1714 	if (tx_rate)
1715 		mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1716 
1717 	if (params->tx_dim_enabled)
1718 		sq->state |= BIT(MLX5E_SQ_STATE_DIM);
1719 
1720 	return 0;
1721 
1722 err_free_txqsq:
1723 	mlx5e_free_txqsq(sq);
1724 
1725 	return err;
1726 }
1727 
mlx5e_activate_txqsq(struct mlx5e_txqsq * sq)1728 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1729 {
1730 	sq->txq = netdev_get_tx_queue(sq->netdev, sq->txq_ix);
1731 	set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1732 	netdev_tx_reset_queue(sq->txq);
1733 	netif_tx_start_queue(sq->txq);
1734 }
1735 
mlx5e_tx_disable_queue(struct netdev_queue * txq)1736 void mlx5e_tx_disable_queue(struct netdev_queue *txq)
1737 {
1738 	__netif_tx_lock_bh(txq);
1739 	netif_tx_stop_queue(txq);
1740 	__netif_tx_unlock_bh(txq);
1741 }
1742 
mlx5e_deactivate_txqsq(struct mlx5e_txqsq * sq)1743 void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1744 {
1745 	struct mlx5_wq_cyc *wq = &sq->wq;
1746 
1747 	clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1748 	synchronize_net(); /* Sync with NAPI to prevent netif_tx_wake_queue. */
1749 
1750 	mlx5e_tx_disable_queue(sq->txq);
1751 
1752 	/* last doorbell out, godspeed .. */
1753 	if (mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1)) {
1754 		u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
1755 		struct mlx5e_tx_wqe *nop;
1756 
1757 		sq->db.wqe_info[pi] = (struct mlx5e_tx_wqe_info) {
1758 			.num_wqebbs = 1,
1759 		};
1760 
1761 		nop = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
1762 		mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nop->ctrl);
1763 	}
1764 }
1765 
mlx5e_close_txqsq(struct mlx5e_txqsq * sq)1766 void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1767 {
1768 	struct mlx5_core_dev *mdev = sq->mdev;
1769 	struct mlx5_rate_limit rl = {0};
1770 
1771 	cancel_work_sync(&sq->dim.work);
1772 	cancel_work_sync(&sq->recover_work);
1773 	mlx5e_destroy_sq(mdev, sq->sqn);
1774 	if (sq->rate_limit) {
1775 		rl.rate = sq->rate_limit;
1776 		mlx5_rl_remove_rate(mdev, &rl);
1777 	}
1778 	mlx5e_free_txqsq_descs(sq);
1779 	mlx5e_free_txqsq(sq);
1780 }
1781 
mlx5e_tx_err_cqe_work(struct work_struct * recover_work)1782 void mlx5e_tx_err_cqe_work(struct work_struct *recover_work)
1783 {
1784 	struct mlx5e_txqsq *sq = container_of(recover_work, struct mlx5e_txqsq,
1785 					      recover_work);
1786 
1787 	mlx5e_reporter_tx_err_cqe(sq);
1788 }
1789 
mlx5e_open_icosq(struct mlx5e_channel * c,struct mlx5e_params * params,struct mlx5e_sq_param * param,struct mlx5e_icosq * sq,work_func_t recover_work_func)1790 static int mlx5e_open_icosq(struct mlx5e_channel *c, struct mlx5e_params *params,
1791 			    struct mlx5e_sq_param *param, struct mlx5e_icosq *sq,
1792 			    work_func_t recover_work_func)
1793 {
1794 	struct mlx5e_create_sq_param csp = {};
1795 	int err;
1796 
1797 	err = mlx5e_alloc_icosq(c, param, sq, recover_work_func);
1798 	if (err)
1799 		return err;
1800 
1801 	csp.cqn             = sq->cq.mcq.cqn;
1802 	csp.wq_ctrl         = &sq->wq_ctrl;
1803 	csp.min_inline_mode = params->tx_min_inline_mode;
1804 	err = mlx5e_create_sq_rdy(c->mdev, param, &csp, 0, &sq->sqn);
1805 	if (err)
1806 		goto err_free_icosq;
1807 
1808 	if (param->is_tls) {
1809 		sq->ktls_resync = mlx5e_ktls_rx_resync_create_resp_list();
1810 		if (IS_ERR(sq->ktls_resync)) {
1811 			err = PTR_ERR(sq->ktls_resync);
1812 			goto err_destroy_icosq;
1813 		}
1814 	}
1815 	return 0;
1816 
1817 err_destroy_icosq:
1818 	mlx5e_destroy_sq(c->mdev, sq->sqn);
1819 err_free_icosq:
1820 	mlx5e_free_icosq(sq);
1821 
1822 	return err;
1823 }
1824 
mlx5e_activate_icosq(struct mlx5e_icosq * icosq)1825 void mlx5e_activate_icosq(struct mlx5e_icosq *icosq)
1826 {
1827 	set_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state);
1828 }
1829 
mlx5e_deactivate_icosq(struct mlx5e_icosq * icosq)1830 void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq)
1831 {
1832 	clear_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state);
1833 	synchronize_net(); /* Sync with NAPI. */
1834 }
1835 
mlx5e_close_icosq(struct mlx5e_icosq * sq)1836 static void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1837 {
1838 	struct mlx5e_channel *c = sq->channel;
1839 
1840 	if (sq->ktls_resync)
1841 		mlx5e_ktls_rx_resync_destroy_resp_list(sq->ktls_resync);
1842 	mlx5e_destroy_sq(c->mdev, sq->sqn);
1843 	mlx5e_free_icosq_descs(sq);
1844 	mlx5e_free_icosq(sq);
1845 }
1846 
mlx5e_open_xdpsq(struct mlx5e_channel * c,struct mlx5e_params * params,struct mlx5e_sq_param * param,struct xsk_buff_pool * xsk_pool,struct mlx5e_xdpsq * sq,bool is_redirect)1847 int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params,
1848 		     struct mlx5e_sq_param *param, struct xsk_buff_pool *xsk_pool,
1849 		     struct mlx5e_xdpsq *sq, bool is_redirect)
1850 {
1851 	struct mlx5e_create_sq_param csp = {};
1852 	int err;
1853 
1854 	err = mlx5e_alloc_xdpsq(c, params, xsk_pool, param, sq, is_redirect);
1855 	if (err)
1856 		return err;
1857 
1858 	csp.tis_lst_sz      = 1;
1859 	csp.tisn            = c->priv->tisn[c->lag_port][0]; /* tc = 0 */
1860 	csp.cqn             = sq->cq.mcq.cqn;
1861 	csp.wq_ctrl         = &sq->wq_ctrl;
1862 	csp.min_inline_mode = sq->min_inline_mode;
1863 	set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1864 
1865 	if (param->is_xdp_mb)
1866 		set_bit(MLX5E_SQ_STATE_XDP_MULTIBUF, &sq->state);
1867 
1868 	err = mlx5e_create_sq_rdy(c->mdev, param, &csp, 0, &sq->sqn);
1869 	if (err)
1870 		goto err_free_xdpsq;
1871 
1872 	mlx5e_set_xmit_fp(sq, param->is_mpw);
1873 
1874 	if (!param->is_mpw && !test_bit(MLX5E_SQ_STATE_XDP_MULTIBUF, &sq->state)) {
1875 		unsigned int ds_cnt = MLX5E_TX_WQE_EMPTY_DS_COUNT + 1;
1876 		unsigned int inline_hdr_sz = 0;
1877 		int i;
1878 
1879 		if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1880 			inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1881 			ds_cnt++;
1882 		}
1883 
1884 		/* Pre initialize fixed WQE fields */
1885 		for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1886 			struct mlx5e_tx_wqe      *wqe  = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1887 			struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1888 			struct mlx5_wqe_eth_seg  *eseg = &wqe->eth;
1889 
1890 			sq->db.wqe_info[i] = (struct mlx5e_xdp_wqe_info) {
1891 				.num_wqebbs = 1,
1892 				.num_pkts   = 1,
1893 			};
1894 
1895 			cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1896 			eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1897 		}
1898 	}
1899 
1900 	return 0;
1901 
1902 err_free_xdpsq:
1903 	clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1904 	mlx5e_free_xdpsq(sq);
1905 
1906 	return err;
1907 }
1908 
mlx5e_close_xdpsq(struct mlx5e_xdpsq * sq)1909 void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1910 {
1911 	struct mlx5e_channel *c = sq->channel;
1912 
1913 	clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1914 	synchronize_net(); /* Sync with NAPI. */
1915 
1916 	mlx5e_destroy_sq(c->mdev, sq->sqn);
1917 	mlx5e_free_xdpsq_descs(sq);
1918 	mlx5e_free_xdpsq(sq);
1919 }
1920 
mlx5e_alloc_cq_common(struct mlx5e_priv * priv,struct mlx5e_cq_param * param,struct mlx5e_cq * cq)1921 static int mlx5e_alloc_cq_common(struct mlx5e_priv *priv,
1922 				 struct mlx5e_cq_param *param,
1923 				 struct mlx5e_cq *cq)
1924 {
1925 	struct mlx5_core_dev *mdev = priv->mdev;
1926 	struct mlx5_core_cq *mcq = &cq->mcq;
1927 	int err;
1928 	u32 i;
1929 
1930 	err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1931 			       &cq->wq_ctrl);
1932 	if (err)
1933 		return err;
1934 
1935 	mcq->cqe_sz     = 64;
1936 	mcq->set_ci_db  = cq->wq_ctrl.db.db;
1937 	mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1938 	*mcq->set_ci_db = 0;
1939 	*mcq->arm_db    = 0;
1940 	mcq->vector     = param->eq_ix;
1941 	mcq->comp       = mlx5e_completion_event;
1942 	mcq->event      = mlx5e_cq_error_event;
1943 
1944 	for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1945 		struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1946 
1947 		cqe->op_own = 0xf1;
1948 		cqe->validity_iteration_count = 0xff;
1949 	}
1950 
1951 	cq->mdev = mdev;
1952 	cq->netdev = priv->netdev;
1953 	cq->priv = priv;
1954 
1955 	return 0;
1956 }
1957 
mlx5e_alloc_cq(struct mlx5e_priv * priv,struct mlx5e_cq_param * param,struct mlx5e_create_cq_param * ccp,struct mlx5e_cq * cq)1958 static int mlx5e_alloc_cq(struct mlx5e_priv *priv,
1959 			  struct mlx5e_cq_param *param,
1960 			  struct mlx5e_create_cq_param *ccp,
1961 			  struct mlx5e_cq *cq)
1962 {
1963 	int err;
1964 
1965 	param->wq.buf_numa_node = ccp->node;
1966 	param->wq.db_numa_node  = ccp->node;
1967 	param->eq_ix            = ccp->ix;
1968 
1969 	err = mlx5e_alloc_cq_common(priv, param, cq);
1970 
1971 	cq->napi     = ccp->napi;
1972 	cq->ch_stats = ccp->ch_stats;
1973 
1974 	return err;
1975 }
1976 
mlx5e_free_cq(struct mlx5e_cq * cq)1977 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1978 {
1979 	mlx5_wq_destroy(&cq->wq_ctrl);
1980 }
1981 
mlx5e_create_cq(struct mlx5e_cq * cq,struct mlx5e_cq_param * param)1982 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1983 {
1984 	u32 out[MLX5_ST_SZ_DW(create_cq_out)];
1985 	struct mlx5_core_dev *mdev = cq->mdev;
1986 	struct mlx5_core_cq *mcq = &cq->mcq;
1987 
1988 	void *in;
1989 	void *cqc;
1990 	int inlen;
1991 	int eqn;
1992 	int err;
1993 
1994 	err = mlx5_comp_eqn_get(mdev, param->eq_ix, &eqn);
1995 	if (err)
1996 		return err;
1997 
1998 	inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1999 		sizeof(u64) * cq->wq_ctrl.buf.npages;
2000 	in = kvzalloc(inlen, GFP_KERNEL);
2001 	if (!in)
2002 		return -ENOMEM;
2003 
2004 	cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
2005 
2006 	memcpy(cqc, param->cqc, sizeof(param->cqc));
2007 
2008 	mlx5_fill_page_frag_array(&cq->wq_ctrl.buf,
2009 				  (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
2010 
2011 	MLX5_SET(cqc,   cqc, cq_period_mode, param->cq_period_mode);
2012 	MLX5_SET(cqc,   cqc, c_eqn_or_apu_element, eqn);
2013 	MLX5_SET(cqc,   cqc, uar_page,      mdev->priv.uar->index);
2014 	MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
2015 					    MLX5_ADAPTER_PAGE_SHIFT);
2016 	MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
2017 
2018 	err = mlx5_core_create_cq(mdev, mcq, in, inlen, out, sizeof(out));
2019 
2020 	kvfree(in);
2021 
2022 	if (err)
2023 		return err;
2024 
2025 	mlx5e_cq_arm(cq);
2026 
2027 	return 0;
2028 }
2029 
mlx5e_destroy_cq(struct mlx5e_cq * cq)2030 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
2031 {
2032 	mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
2033 }
2034 
mlx5e_open_cq(struct mlx5e_priv * priv,struct dim_cq_moder moder,struct mlx5e_cq_param * param,struct mlx5e_create_cq_param * ccp,struct mlx5e_cq * cq)2035 int mlx5e_open_cq(struct mlx5e_priv *priv, struct dim_cq_moder moder,
2036 		  struct mlx5e_cq_param *param, struct mlx5e_create_cq_param *ccp,
2037 		  struct mlx5e_cq *cq)
2038 {
2039 	struct mlx5_core_dev *mdev = priv->mdev;
2040 	int err;
2041 
2042 	err = mlx5e_alloc_cq(priv, param, ccp, cq);
2043 	if (err)
2044 		return err;
2045 
2046 	err = mlx5e_create_cq(cq, param);
2047 	if (err)
2048 		goto err_free_cq;
2049 
2050 	if (MLX5_CAP_GEN(mdev, cq_moderation))
2051 		mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
2052 	return 0;
2053 
2054 err_free_cq:
2055 	mlx5e_free_cq(cq);
2056 
2057 	return err;
2058 }
2059 
mlx5e_close_cq(struct mlx5e_cq * cq)2060 void mlx5e_close_cq(struct mlx5e_cq *cq)
2061 {
2062 	mlx5e_destroy_cq(cq);
2063 	mlx5e_free_cq(cq);
2064 }
2065 
mlx5e_open_tx_cqs(struct mlx5e_channel * c,struct mlx5e_params * params,struct mlx5e_create_cq_param * ccp,struct mlx5e_channel_param * cparam)2066 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
2067 			     struct mlx5e_params *params,
2068 			     struct mlx5e_create_cq_param *ccp,
2069 			     struct mlx5e_channel_param *cparam)
2070 {
2071 	int err;
2072 	int tc;
2073 
2074 	for (tc = 0; tc < c->num_tc; tc++) {
2075 		err = mlx5e_open_cq(c->priv, params->tx_cq_moderation, &cparam->txq_sq.cqp,
2076 				    ccp, &c->sq[tc].cq);
2077 		if (err)
2078 			goto err_close_tx_cqs;
2079 	}
2080 
2081 	return 0;
2082 
2083 err_close_tx_cqs:
2084 	for (tc--; tc >= 0; tc--)
2085 		mlx5e_close_cq(&c->sq[tc].cq);
2086 
2087 	return err;
2088 }
2089 
mlx5e_close_tx_cqs(struct mlx5e_channel * c)2090 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
2091 {
2092 	int tc;
2093 
2094 	for (tc = 0; tc < c->num_tc; tc++)
2095 		mlx5e_close_cq(&c->sq[tc].cq);
2096 }
2097 
mlx5e_mqprio_txq_to_tc(struct netdev_tc_txq * tc_to_txq,unsigned int txq)2098 static int mlx5e_mqprio_txq_to_tc(struct netdev_tc_txq *tc_to_txq, unsigned int txq)
2099 {
2100 	int tc;
2101 
2102 	for (tc = 0; tc < TC_MAX_QUEUE; tc++)
2103 		if (txq - tc_to_txq[tc].offset < tc_to_txq[tc].count)
2104 			return tc;
2105 
2106 	WARN(1, "Unexpected TCs configuration. No match found for txq %u", txq);
2107 	return -ENOENT;
2108 }
2109 
mlx5e_txq_get_qos_node_hw_id(struct mlx5e_params * params,int txq_ix,u32 * hw_id)2110 static int mlx5e_txq_get_qos_node_hw_id(struct mlx5e_params *params, int txq_ix,
2111 					u32 *hw_id)
2112 {
2113 	int tc;
2114 
2115 	if (params->mqprio.mode != TC_MQPRIO_MODE_CHANNEL) {
2116 		*hw_id = 0;
2117 		return 0;
2118 	}
2119 
2120 	tc = mlx5e_mqprio_txq_to_tc(params->mqprio.tc_to_txq, txq_ix);
2121 	if (tc < 0)
2122 		return tc;
2123 
2124 	if (tc >= params->mqprio.num_tc) {
2125 		WARN(1, "Unexpected TCs configuration. tc %d is out of range of %u",
2126 		     tc, params->mqprio.num_tc);
2127 		return -EINVAL;
2128 	}
2129 
2130 	*hw_id = params->mqprio.channel.hw_id[tc];
2131 	return 0;
2132 }
2133 
mlx5e_open_sqs(struct mlx5e_channel * c,struct mlx5e_params * params,struct mlx5e_channel_param * cparam)2134 static int mlx5e_open_sqs(struct mlx5e_channel *c,
2135 			  struct mlx5e_params *params,
2136 			  struct mlx5e_channel_param *cparam)
2137 {
2138 	int err, tc;
2139 
2140 	for (tc = 0; tc < mlx5e_get_dcb_num_tc(params); tc++) {
2141 		int txq_ix = c->ix + tc * params->num_channels;
2142 		u32 qos_queue_group_id;
2143 
2144 		err = mlx5e_txq_get_qos_node_hw_id(params, txq_ix, &qos_queue_group_id);
2145 		if (err)
2146 			goto err_close_sqs;
2147 
2148 		err = mlx5e_open_txqsq(c, c->priv->tisn[c->lag_port][tc], txq_ix,
2149 				       params, &cparam->txq_sq, &c->sq[tc], tc,
2150 				       qos_queue_group_id,
2151 				       &c->priv->channel_stats[c->ix]->sq[tc]);
2152 		if (err)
2153 			goto err_close_sqs;
2154 	}
2155 
2156 	return 0;
2157 
2158 err_close_sqs:
2159 	for (tc--; tc >= 0; tc--)
2160 		mlx5e_close_txqsq(&c->sq[tc]);
2161 
2162 	return err;
2163 }
2164 
mlx5e_close_sqs(struct mlx5e_channel * c)2165 static void mlx5e_close_sqs(struct mlx5e_channel *c)
2166 {
2167 	int tc;
2168 
2169 	for (tc = 0; tc < c->num_tc; tc++)
2170 		mlx5e_close_txqsq(&c->sq[tc]);
2171 }
2172 
mlx5e_set_sq_maxrate(struct net_device * dev,struct mlx5e_txqsq * sq,u32 rate)2173 static int mlx5e_set_sq_maxrate(struct net_device *dev,
2174 				struct mlx5e_txqsq *sq, u32 rate)
2175 {
2176 	struct mlx5e_priv *priv = netdev_priv(dev);
2177 	struct mlx5_core_dev *mdev = priv->mdev;
2178 	struct mlx5e_modify_sq_param msp = {0};
2179 	struct mlx5_rate_limit rl = {0};
2180 	u16 rl_index = 0;
2181 	int err;
2182 
2183 	if (rate == sq->rate_limit)
2184 		/* nothing to do */
2185 		return 0;
2186 
2187 	if (sq->rate_limit) {
2188 		rl.rate = sq->rate_limit;
2189 		/* remove current rl index to free space to next ones */
2190 		mlx5_rl_remove_rate(mdev, &rl);
2191 	}
2192 
2193 	sq->rate_limit = 0;
2194 
2195 	if (rate) {
2196 		rl.rate = rate;
2197 		err = mlx5_rl_add_rate(mdev, &rl_index, &rl);
2198 		if (err) {
2199 			netdev_err(dev, "Failed configuring rate %u: %d\n",
2200 				   rate, err);
2201 			return err;
2202 		}
2203 	}
2204 
2205 	msp.curr_state = MLX5_SQC_STATE_RDY;
2206 	msp.next_state = MLX5_SQC_STATE_RDY;
2207 	msp.rl_index   = rl_index;
2208 	msp.rl_update  = true;
2209 	err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
2210 	if (err) {
2211 		netdev_err(dev, "Failed configuring rate %u: %d\n",
2212 			   rate, err);
2213 		/* remove the rate from the table */
2214 		if (rate)
2215 			mlx5_rl_remove_rate(mdev, &rl);
2216 		return err;
2217 	}
2218 
2219 	sq->rate_limit = rate;
2220 	return 0;
2221 }
2222 
mlx5e_set_tx_maxrate(struct net_device * dev,int index,u32 rate)2223 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
2224 {
2225 	struct mlx5e_priv *priv = netdev_priv(dev);
2226 	struct mlx5_core_dev *mdev = priv->mdev;
2227 	struct mlx5e_txqsq *sq = priv->txq2sq[index];
2228 	int err = 0;
2229 
2230 	if (!mlx5_rl_is_supported(mdev)) {
2231 		netdev_err(dev, "Rate limiting is not supported on this device\n");
2232 		return -EINVAL;
2233 	}
2234 
2235 	/* rate is given in Mb/sec, HW config is in Kb/sec */
2236 	rate = rate << 10;
2237 
2238 	/* Check whether rate in valid range, 0 is always valid */
2239 	if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
2240 		netdev_err(dev, "TX rate %u, is not in range\n", rate);
2241 		return -ERANGE;
2242 	}
2243 
2244 	mutex_lock(&priv->state_lock);
2245 	if (test_bit(MLX5E_STATE_OPENED, &priv->state))
2246 		err = mlx5e_set_sq_maxrate(dev, sq, rate);
2247 	if (!err)
2248 		priv->tx_rates[index] = rate;
2249 	mutex_unlock(&priv->state_lock);
2250 
2251 	return err;
2252 }
2253 
mlx5e_open_rxq_rq(struct mlx5e_channel * c,struct mlx5e_params * params,struct mlx5e_rq_param * rq_params)2254 static int mlx5e_open_rxq_rq(struct mlx5e_channel *c, struct mlx5e_params *params,
2255 			     struct mlx5e_rq_param *rq_params)
2256 {
2257 	int err;
2258 
2259 	err = mlx5e_init_rxq_rq(c, params, rq_params->xdp_frag_size, &c->rq);
2260 	if (err)
2261 		return err;
2262 
2263 	return mlx5e_open_rq(params, rq_params, NULL, cpu_to_node(c->cpu), &c->rq);
2264 }
2265 
mlx5e_open_queues(struct mlx5e_channel * c,struct mlx5e_params * params,struct mlx5e_channel_param * cparam)2266 static int mlx5e_open_queues(struct mlx5e_channel *c,
2267 			     struct mlx5e_params *params,
2268 			     struct mlx5e_channel_param *cparam)
2269 {
2270 	struct dim_cq_moder icocq_moder = {0, 0};
2271 	struct mlx5e_create_cq_param ccp;
2272 	int err;
2273 
2274 	mlx5e_build_create_cq_param(&ccp, c);
2275 
2276 	err = mlx5e_open_cq(c->priv, icocq_moder, &cparam->async_icosq.cqp, &ccp,
2277 			    &c->async_icosq.cq);
2278 	if (err)
2279 		return err;
2280 
2281 	err = mlx5e_open_cq(c->priv, icocq_moder, &cparam->icosq.cqp, &ccp,
2282 			    &c->icosq.cq);
2283 	if (err)
2284 		goto err_close_async_icosq_cq;
2285 
2286 	err = mlx5e_open_tx_cqs(c, params, &ccp, cparam);
2287 	if (err)
2288 		goto err_close_icosq_cq;
2289 
2290 	err = mlx5e_open_cq(c->priv, params->tx_cq_moderation, &cparam->xdp_sq.cqp, &ccp,
2291 			    &c->xdpsq.cq);
2292 	if (err)
2293 		goto err_close_tx_cqs;
2294 
2295 	err = mlx5e_open_cq(c->priv, params->rx_cq_moderation, &cparam->rq.cqp, &ccp,
2296 			    &c->rq.cq);
2297 	if (err)
2298 		goto err_close_xdp_tx_cqs;
2299 
2300 	err = c->xdp ? mlx5e_open_cq(c->priv, params->tx_cq_moderation, &cparam->xdp_sq.cqp,
2301 				     &ccp, &c->rq_xdpsq.cq) : 0;
2302 	if (err)
2303 		goto err_close_rx_cq;
2304 
2305 	spin_lock_init(&c->async_icosq_lock);
2306 
2307 	err = mlx5e_open_icosq(c, params, &cparam->async_icosq, &c->async_icosq,
2308 			       mlx5e_async_icosq_err_cqe_work);
2309 	if (err)
2310 		goto err_close_xdpsq_cq;
2311 
2312 	mutex_init(&c->icosq_recovery_lock);
2313 
2314 	err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq,
2315 			       mlx5e_icosq_err_cqe_work);
2316 	if (err)
2317 		goto err_close_async_icosq;
2318 
2319 	err = mlx5e_open_sqs(c, params, cparam);
2320 	if (err)
2321 		goto err_close_icosq;
2322 
2323 	err = mlx5e_open_rxq_rq(c, params, &cparam->rq);
2324 	if (err)
2325 		goto err_close_sqs;
2326 
2327 	if (c->xdp) {
2328 		err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL,
2329 				       &c->rq_xdpsq, false);
2330 		if (err)
2331 			goto err_close_rq;
2332 	}
2333 
2334 	err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL, &c->xdpsq, true);
2335 	if (err)
2336 		goto err_close_xdp_sq;
2337 
2338 	return 0;
2339 
2340 err_close_xdp_sq:
2341 	if (c->xdp)
2342 		mlx5e_close_xdpsq(&c->rq_xdpsq);
2343 
2344 err_close_rq:
2345 	mlx5e_close_rq(&c->rq);
2346 
2347 err_close_sqs:
2348 	mlx5e_close_sqs(c);
2349 
2350 err_close_icosq:
2351 	mlx5e_close_icosq(&c->icosq);
2352 
2353 err_close_async_icosq:
2354 	mlx5e_close_icosq(&c->async_icosq);
2355 
2356 err_close_xdpsq_cq:
2357 	if (c->xdp)
2358 		mlx5e_close_cq(&c->rq_xdpsq.cq);
2359 
2360 err_close_rx_cq:
2361 	mlx5e_close_cq(&c->rq.cq);
2362 
2363 err_close_xdp_tx_cqs:
2364 	mlx5e_close_cq(&c->xdpsq.cq);
2365 
2366 err_close_tx_cqs:
2367 	mlx5e_close_tx_cqs(c);
2368 
2369 err_close_icosq_cq:
2370 	mlx5e_close_cq(&c->icosq.cq);
2371 
2372 err_close_async_icosq_cq:
2373 	mlx5e_close_cq(&c->async_icosq.cq);
2374 
2375 	return err;
2376 }
2377 
mlx5e_close_queues(struct mlx5e_channel * c)2378 static void mlx5e_close_queues(struct mlx5e_channel *c)
2379 {
2380 	mlx5e_close_xdpsq(&c->xdpsq);
2381 	if (c->xdp)
2382 		mlx5e_close_xdpsq(&c->rq_xdpsq);
2383 	/* The same ICOSQ is used for UMRs for both RQ and XSKRQ. */
2384 	cancel_work_sync(&c->icosq.recover_work);
2385 	mlx5e_close_rq(&c->rq);
2386 	mlx5e_close_sqs(c);
2387 	mlx5e_close_icosq(&c->icosq);
2388 	mutex_destroy(&c->icosq_recovery_lock);
2389 	mlx5e_close_icosq(&c->async_icosq);
2390 	if (c->xdp)
2391 		mlx5e_close_cq(&c->rq_xdpsq.cq);
2392 	mlx5e_close_cq(&c->rq.cq);
2393 	mlx5e_close_cq(&c->xdpsq.cq);
2394 	mlx5e_close_tx_cqs(c);
2395 	mlx5e_close_cq(&c->icosq.cq);
2396 	mlx5e_close_cq(&c->async_icosq.cq);
2397 }
2398 
mlx5e_enumerate_lag_port(struct mlx5_core_dev * mdev,int ix)2399 static u8 mlx5e_enumerate_lag_port(struct mlx5_core_dev *mdev, int ix)
2400 {
2401 	u16 port_aff_bias = mlx5_core_is_pf(mdev) ? 0 : MLX5_CAP_GEN(mdev, vhca_id);
2402 
2403 	return (ix + port_aff_bias) % mlx5e_get_num_lag_ports(mdev);
2404 }
2405 
mlx5e_channel_stats_alloc(struct mlx5e_priv * priv,int ix,int cpu)2406 static int mlx5e_channel_stats_alloc(struct mlx5e_priv *priv, int ix, int cpu)
2407 {
2408 	if (ix > priv->stats_nch)  {
2409 		netdev_warn(priv->netdev, "Unexpected channel stats index %d > %d\n", ix,
2410 			    priv->stats_nch);
2411 		return -EINVAL;
2412 	}
2413 
2414 	if (priv->channel_stats[ix])
2415 		return 0;
2416 
2417 	/* Asymmetric dynamic memory allocation.
2418 	 * Freed in mlx5e_priv_arrays_free, not on channel closure.
2419 	 */
2420 	netdev_dbg(priv->netdev, "Creating channel stats %d\n", ix);
2421 	priv->channel_stats[ix] = kvzalloc_node(sizeof(**priv->channel_stats),
2422 						GFP_KERNEL, cpu_to_node(cpu));
2423 	if (!priv->channel_stats[ix])
2424 		return -ENOMEM;
2425 	priv->stats_nch++;
2426 
2427 	return 0;
2428 }
2429 
mlx5e_trigger_napi_icosq(struct mlx5e_channel * c)2430 void mlx5e_trigger_napi_icosq(struct mlx5e_channel *c)
2431 {
2432 	spin_lock_bh(&c->async_icosq_lock);
2433 	mlx5e_trigger_irq(&c->async_icosq);
2434 	spin_unlock_bh(&c->async_icosq_lock);
2435 }
2436 
mlx5e_trigger_napi_sched(struct napi_struct * napi)2437 void mlx5e_trigger_napi_sched(struct napi_struct *napi)
2438 {
2439 	local_bh_disable();
2440 	napi_schedule(napi);
2441 	local_bh_enable();
2442 }
2443 
mlx5e_open_channel(struct mlx5e_priv * priv,int ix,struct mlx5e_params * params,struct mlx5e_channel_param * cparam,struct xsk_buff_pool * xsk_pool,struct mlx5e_channel ** cp)2444 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
2445 			      struct mlx5e_params *params,
2446 			      struct mlx5e_channel_param *cparam,
2447 			      struct xsk_buff_pool *xsk_pool,
2448 			      struct mlx5e_channel **cp)
2449 {
2450 	int cpu = mlx5_comp_vector_get_cpu(priv->mdev, ix);
2451 	struct net_device *netdev = priv->netdev;
2452 	struct mlx5e_xsk_param xsk;
2453 	struct mlx5e_channel *c;
2454 	unsigned int irq;
2455 	int err;
2456 
2457 	err = mlx5_comp_irqn_get(priv->mdev, ix, &irq);
2458 	if (err)
2459 		return err;
2460 
2461 	err = mlx5e_channel_stats_alloc(priv, ix, cpu);
2462 	if (err)
2463 		return err;
2464 
2465 	c = kvzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
2466 	if (!c)
2467 		return -ENOMEM;
2468 
2469 	c->priv     = priv;
2470 	c->mdev     = priv->mdev;
2471 	c->tstamp   = &priv->tstamp;
2472 	c->ix       = ix;
2473 	c->cpu      = cpu;
2474 	c->pdev     = mlx5_core_dma_dev(priv->mdev);
2475 	c->netdev   = priv->netdev;
2476 	c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.hw_objs.mkey);
2477 	c->num_tc   = mlx5e_get_dcb_num_tc(params);
2478 	c->xdp      = !!params->xdp_prog;
2479 	c->stats    = &priv->channel_stats[ix]->ch;
2480 	c->aff_mask = irq_get_effective_affinity_mask(irq);
2481 	c->lag_port = mlx5e_enumerate_lag_port(priv->mdev, ix);
2482 
2483 	netif_napi_add(netdev, &c->napi, mlx5e_napi_poll);
2484 
2485 	err = mlx5e_open_queues(c, params, cparam);
2486 	if (unlikely(err))
2487 		goto err_napi_del;
2488 
2489 	if (xsk_pool) {
2490 		mlx5e_build_xsk_param(xsk_pool, &xsk);
2491 		err = mlx5e_open_xsk(priv, params, &xsk, xsk_pool, c);
2492 		if (unlikely(err))
2493 			goto err_close_queues;
2494 	}
2495 
2496 	*cp = c;
2497 
2498 	return 0;
2499 
2500 err_close_queues:
2501 	mlx5e_close_queues(c);
2502 
2503 err_napi_del:
2504 	netif_napi_del(&c->napi);
2505 
2506 	kvfree(c);
2507 
2508 	return err;
2509 }
2510 
mlx5e_activate_channel(struct mlx5e_channel * c)2511 static void mlx5e_activate_channel(struct mlx5e_channel *c)
2512 {
2513 	int tc;
2514 
2515 	napi_enable(&c->napi);
2516 
2517 	for (tc = 0; tc < c->num_tc; tc++)
2518 		mlx5e_activate_txqsq(&c->sq[tc]);
2519 	mlx5e_activate_icosq(&c->icosq);
2520 	mlx5e_activate_icosq(&c->async_icosq);
2521 
2522 	if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2523 		mlx5e_activate_xsk(c);
2524 	else
2525 		mlx5e_activate_rq(&c->rq);
2526 }
2527 
mlx5e_deactivate_channel(struct mlx5e_channel * c)2528 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
2529 {
2530 	int tc;
2531 
2532 	if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2533 		mlx5e_deactivate_xsk(c);
2534 	else
2535 		mlx5e_deactivate_rq(&c->rq);
2536 
2537 	mlx5e_deactivate_icosq(&c->async_icosq);
2538 	mlx5e_deactivate_icosq(&c->icosq);
2539 	for (tc = 0; tc < c->num_tc; tc++)
2540 		mlx5e_deactivate_txqsq(&c->sq[tc]);
2541 	mlx5e_qos_deactivate_queues(c);
2542 
2543 	napi_disable(&c->napi);
2544 }
2545 
mlx5e_close_channel(struct mlx5e_channel * c)2546 static void mlx5e_close_channel(struct mlx5e_channel *c)
2547 {
2548 	if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2549 		mlx5e_close_xsk(c);
2550 	mlx5e_close_queues(c);
2551 	mlx5e_qos_close_queues(c);
2552 	netif_napi_del(&c->napi);
2553 
2554 	kvfree(c);
2555 }
2556 
mlx5e_open_channels(struct mlx5e_priv * priv,struct mlx5e_channels * chs)2557 int mlx5e_open_channels(struct mlx5e_priv *priv,
2558 			struct mlx5e_channels *chs)
2559 {
2560 	struct mlx5e_channel_param *cparam;
2561 	int err = -ENOMEM;
2562 	int i;
2563 
2564 	chs->num = chs->params.num_channels;
2565 
2566 	chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2567 	cparam = kvzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2568 	if (!chs->c || !cparam)
2569 		goto err_free;
2570 
2571 	err = mlx5e_build_channel_param(priv->mdev, &chs->params, priv->q_counter, cparam);
2572 	if (err)
2573 		goto err_free;
2574 
2575 	for (i = 0; i < chs->num; i++) {
2576 		struct xsk_buff_pool *xsk_pool = NULL;
2577 
2578 		if (chs->params.xdp_prog)
2579 			xsk_pool = mlx5e_xsk_get_pool(&chs->params, chs->params.xsk, i);
2580 
2581 		err = mlx5e_open_channel(priv, i, &chs->params, cparam, xsk_pool, &chs->c[i]);
2582 		if (err)
2583 			goto err_close_channels;
2584 	}
2585 
2586 	if (MLX5E_GET_PFLAG(&chs->params, MLX5E_PFLAG_TX_PORT_TS) || chs->params.ptp_rx) {
2587 		err = mlx5e_ptp_open(priv, &chs->params, chs->c[0]->lag_port, &chs->ptp);
2588 		if (err)
2589 			goto err_close_channels;
2590 	}
2591 
2592 	if (priv->htb) {
2593 		err = mlx5e_qos_open_queues(priv, chs);
2594 		if (err)
2595 			goto err_close_ptp;
2596 	}
2597 
2598 	mlx5e_health_channels_update(priv);
2599 	kvfree(cparam);
2600 	return 0;
2601 
2602 err_close_ptp:
2603 	if (chs->ptp)
2604 		mlx5e_ptp_close(chs->ptp);
2605 
2606 err_close_channels:
2607 	for (i--; i >= 0; i--)
2608 		mlx5e_close_channel(chs->c[i]);
2609 
2610 err_free:
2611 	kfree(chs->c);
2612 	kvfree(cparam);
2613 	chs->num = 0;
2614 	return err;
2615 }
2616 
mlx5e_activate_channels(struct mlx5e_priv * priv,struct mlx5e_channels * chs)2617 static void mlx5e_activate_channels(struct mlx5e_priv *priv, struct mlx5e_channels *chs)
2618 {
2619 	int i;
2620 
2621 	for (i = 0; i < chs->num; i++)
2622 		mlx5e_activate_channel(chs->c[i]);
2623 
2624 	if (priv->htb)
2625 		mlx5e_qos_activate_queues(priv);
2626 
2627 	for (i = 0; i < chs->num; i++)
2628 		mlx5e_trigger_napi_icosq(chs->c[i]);
2629 
2630 	if (chs->ptp)
2631 		mlx5e_ptp_activate_channel(chs->ptp);
2632 }
2633 
mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels * chs)2634 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2635 {
2636 	int err = 0;
2637 	int i;
2638 
2639 	for (i = 0; i < chs->num; i++) {
2640 		int timeout = err ? 0 : MLX5E_RQ_WQES_TIMEOUT;
2641 		struct mlx5e_channel *c = chs->c[i];
2642 
2643 		if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2644 			continue;
2645 
2646 		err |= mlx5e_wait_for_min_rx_wqes(&c->rq, timeout);
2647 
2648 		/* Don't wait on the XSK RQ, because the newer xdpsock sample
2649 		 * doesn't provide any Fill Ring entries at the setup stage.
2650 		 */
2651 	}
2652 
2653 	return err ? -ETIMEDOUT : 0;
2654 }
2655 
mlx5e_deactivate_channels(struct mlx5e_channels * chs)2656 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2657 {
2658 	int i;
2659 
2660 	if (chs->ptp)
2661 		mlx5e_ptp_deactivate_channel(chs->ptp);
2662 
2663 	for (i = 0; i < chs->num; i++)
2664 		mlx5e_deactivate_channel(chs->c[i]);
2665 }
2666 
mlx5e_close_channels(struct mlx5e_channels * chs)2667 void mlx5e_close_channels(struct mlx5e_channels *chs)
2668 {
2669 	int i;
2670 
2671 	ASSERT_RTNL();
2672 	if (chs->ptp) {
2673 		mlx5e_ptp_close(chs->ptp);
2674 		chs->ptp = NULL;
2675 	}
2676 	for (i = 0; i < chs->num; i++)
2677 		mlx5e_close_channel(chs->c[i]);
2678 
2679 	kfree(chs->c);
2680 	chs->num = 0;
2681 }
2682 
mlx5e_modify_tirs_packet_merge(struct mlx5e_priv * priv)2683 static int mlx5e_modify_tirs_packet_merge(struct mlx5e_priv *priv)
2684 {
2685 	struct mlx5e_rx_res *res = priv->rx_res;
2686 
2687 	return mlx5e_rx_res_packet_merge_set_param(res, &priv->channels.params.packet_merge);
2688 }
2689 
2690 static MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_modify_tirs_packet_merge);
2691 
mlx5e_set_mtu(struct mlx5_core_dev * mdev,struct mlx5e_params * params,u16 mtu)2692 static int mlx5e_set_mtu(struct mlx5_core_dev *mdev,
2693 			 struct mlx5e_params *params, u16 mtu)
2694 {
2695 	u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu);
2696 	int err;
2697 
2698 	err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2699 	if (err)
2700 		return err;
2701 
2702 	/* Update vport context MTU */
2703 	mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2704 	return 0;
2705 }
2706 
mlx5e_query_mtu(struct mlx5_core_dev * mdev,struct mlx5e_params * params,u16 * mtu)2707 static void mlx5e_query_mtu(struct mlx5_core_dev *mdev,
2708 			    struct mlx5e_params *params, u16 *mtu)
2709 {
2710 	u16 hw_mtu = 0;
2711 	int err;
2712 
2713 	err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2714 	if (err || !hw_mtu) /* fallback to port oper mtu */
2715 		mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2716 
2717 	*mtu = MLX5E_HW2SW_MTU(params, hw_mtu);
2718 }
2719 
mlx5e_set_dev_port_mtu(struct mlx5e_priv * priv)2720 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2721 {
2722 	struct mlx5e_params *params = &priv->channels.params;
2723 	struct net_device *netdev = priv->netdev;
2724 	struct mlx5_core_dev *mdev = priv->mdev;
2725 	u16 mtu;
2726 	int err;
2727 
2728 	err = mlx5e_set_mtu(mdev, params, params->sw_mtu);
2729 	if (err)
2730 		return err;
2731 
2732 	mlx5e_query_mtu(mdev, params, &mtu);
2733 	if (mtu != params->sw_mtu)
2734 		netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2735 			    __func__, mtu, params->sw_mtu);
2736 
2737 	params->sw_mtu = mtu;
2738 	return 0;
2739 }
2740 
2741 MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_set_dev_port_mtu);
2742 
mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv * priv)2743 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv)
2744 {
2745 	struct mlx5e_params *params = &priv->channels.params;
2746 	struct net_device *netdev   = priv->netdev;
2747 	struct mlx5_core_dev *mdev  = priv->mdev;
2748 	u16 max_mtu;
2749 
2750 	/* MTU range: 68 - hw-specific max */
2751 	netdev->min_mtu = ETH_MIN_MTU;
2752 
2753 	mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2754 	netdev->max_mtu = min_t(unsigned int, MLX5E_HW2SW_MTU(params, max_mtu),
2755 				ETH_MAX_MTU);
2756 }
2757 
mlx5e_netdev_set_tcs(struct net_device * netdev,u16 nch,u8 ntc,struct netdev_tc_txq * tc_to_txq)2758 static int mlx5e_netdev_set_tcs(struct net_device *netdev, u16 nch, u8 ntc,
2759 				struct netdev_tc_txq *tc_to_txq)
2760 {
2761 	int tc, err;
2762 
2763 	netdev_reset_tc(netdev);
2764 
2765 	if (ntc == 1)
2766 		return 0;
2767 
2768 	err = netdev_set_num_tc(netdev, ntc);
2769 	if (err) {
2770 		netdev_WARN(netdev, "netdev_set_num_tc failed (%d), ntc = %d\n", err, ntc);
2771 		return err;
2772 	}
2773 
2774 	for (tc = 0; tc < ntc; tc++) {
2775 		u16 count, offset;
2776 
2777 		count = tc_to_txq[tc].count;
2778 		offset = tc_to_txq[tc].offset;
2779 		netdev_set_tc_queue(netdev, tc, count, offset);
2780 	}
2781 
2782 	return 0;
2783 }
2784 
mlx5e_update_tx_netdev_queues(struct mlx5e_priv * priv)2785 int mlx5e_update_tx_netdev_queues(struct mlx5e_priv *priv)
2786 {
2787 	int nch, ntc, num_txqs, err;
2788 	int qos_queues = 0;
2789 
2790 	if (priv->htb)
2791 		qos_queues = mlx5e_htb_cur_leaf_nodes(priv->htb);
2792 
2793 	nch = priv->channels.params.num_channels;
2794 	ntc = mlx5e_get_dcb_num_tc(&priv->channels.params);
2795 	num_txqs = nch * ntc + qos_queues;
2796 	if (MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_TX_PORT_TS))
2797 		num_txqs += ntc;
2798 
2799 	netdev_dbg(priv->netdev, "Setting num_txqs %d\n", num_txqs);
2800 	err = netif_set_real_num_tx_queues(priv->netdev, num_txqs);
2801 	if (err)
2802 		netdev_warn(priv->netdev, "netif_set_real_num_tx_queues failed, %d\n", err);
2803 
2804 	return err;
2805 }
2806 
mlx5e_update_netdev_queues(struct mlx5e_priv * priv)2807 static int mlx5e_update_netdev_queues(struct mlx5e_priv *priv)
2808 {
2809 	struct netdev_tc_txq old_tc_to_txq[TC_MAX_QUEUE], *tc_to_txq;
2810 	struct net_device *netdev = priv->netdev;
2811 	int old_num_txqs, old_ntc;
2812 	int nch, ntc;
2813 	int err;
2814 	int i;
2815 
2816 	old_num_txqs = netdev->real_num_tx_queues;
2817 	old_ntc = netdev->num_tc ? : 1;
2818 	for (i = 0; i < ARRAY_SIZE(old_tc_to_txq); i++)
2819 		old_tc_to_txq[i] = netdev->tc_to_txq[i];
2820 
2821 	nch = priv->channels.params.num_channels;
2822 	ntc = priv->channels.params.mqprio.num_tc;
2823 	tc_to_txq = priv->channels.params.mqprio.tc_to_txq;
2824 
2825 	err = mlx5e_netdev_set_tcs(netdev, nch, ntc, tc_to_txq);
2826 	if (err)
2827 		goto err_out;
2828 	err = mlx5e_update_tx_netdev_queues(priv);
2829 	if (err)
2830 		goto err_tcs;
2831 	err = netif_set_real_num_rx_queues(netdev, nch);
2832 	if (err) {
2833 		netdev_warn(netdev, "netif_set_real_num_rx_queues failed, %d\n", err);
2834 		goto err_txqs;
2835 	}
2836 
2837 	return 0;
2838 
2839 err_txqs:
2840 	/* netif_set_real_num_rx_queues could fail only when nch increased. Only
2841 	 * one of nch and ntc is changed in this function. That means, the call
2842 	 * to netif_set_real_num_tx_queues below should not fail, because it
2843 	 * decreases the number of TX queues.
2844 	 */
2845 	WARN_ON_ONCE(netif_set_real_num_tx_queues(netdev, old_num_txqs));
2846 
2847 err_tcs:
2848 	WARN_ON_ONCE(mlx5e_netdev_set_tcs(netdev, old_num_txqs / old_ntc, old_ntc,
2849 					  old_tc_to_txq));
2850 err_out:
2851 	return err;
2852 }
2853 
2854 static MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_update_netdev_queues);
2855 
mlx5e_set_default_xps_cpumasks(struct mlx5e_priv * priv,struct mlx5e_params * params)2856 static void mlx5e_set_default_xps_cpumasks(struct mlx5e_priv *priv,
2857 					   struct mlx5e_params *params)
2858 {
2859 	struct mlx5_core_dev *mdev = priv->mdev;
2860 	int num_comp_vectors, ix, irq;
2861 
2862 	num_comp_vectors = mlx5_comp_vectors_max(mdev);
2863 
2864 	for (ix = 0; ix < params->num_channels; ix++) {
2865 		cpumask_clear(priv->scratchpad.cpumask);
2866 
2867 		for (irq = ix; irq < num_comp_vectors; irq += params->num_channels) {
2868 			int cpu = mlx5_comp_vector_get_cpu(mdev, irq);
2869 
2870 			cpumask_set_cpu(cpu, priv->scratchpad.cpumask);
2871 		}
2872 
2873 		netif_set_xps_queue(priv->netdev, priv->scratchpad.cpumask, ix);
2874 	}
2875 }
2876 
mlx5e_num_channels_changed(struct mlx5e_priv * priv)2877 static int mlx5e_num_channels_changed(struct mlx5e_priv *priv)
2878 {
2879 	u16 count = priv->channels.params.num_channels;
2880 	int err;
2881 
2882 	err = mlx5e_update_netdev_queues(priv);
2883 	if (err)
2884 		return err;
2885 
2886 	mlx5e_set_default_xps_cpumasks(priv, &priv->channels.params);
2887 
2888 	/* This function may be called on attach, before priv->rx_res is created. */
2889 	if (!netif_is_rxfh_configured(priv->netdev) && priv->rx_res)
2890 		mlx5e_rx_res_rss_set_indir_uniform(priv->rx_res, count);
2891 
2892 	return 0;
2893 }
2894 
2895 MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_num_channels_changed);
2896 
mlx5e_build_txq_maps(struct mlx5e_priv * priv)2897 static void mlx5e_build_txq_maps(struct mlx5e_priv *priv)
2898 {
2899 	int i, ch, tc, num_tc;
2900 
2901 	ch = priv->channels.num;
2902 	num_tc = mlx5e_get_dcb_num_tc(&priv->channels.params);
2903 
2904 	for (i = 0; i < ch; i++) {
2905 		for (tc = 0; tc < num_tc; tc++) {
2906 			struct mlx5e_channel *c = priv->channels.c[i];
2907 			struct mlx5e_txqsq *sq = &c->sq[tc];
2908 
2909 			priv->txq2sq[sq->txq_ix] = sq;
2910 		}
2911 	}
2912 
2913 	if (!priv->channels.ptp)
2914 		goto out;
2915 
2916 	if (!test_bit(MLX5E_PTP_STATE_TX, priv->channels.ptp->state))
2917 		goto out;
2918 
2919 	for (tc = 0; tc < num_tc; tc++) {
2920 		struct mlx5e_ptp *c = priv->channels.ptp;
2921 		struct mlx5e_txqsq *sq = &c->ptpsq[tc].txqsq;
2922 
2923 		priv->txq2sq[sq->txq_ix] = sq;
2924 	}
2925 
2926 out:
2927 	/* Make the change to txq2sq visible before the queue is started.
2928 	 * As mlx5e_xmit runs under a spinlock, there is an implicit ACQUIRE,
2929 	 * which pairs with this barrier.
2930 	 */
2931 	smp_wmb();
2932 }
2933 
mlx5e_activate_priv_channels(struct mlx5e_priv * priv)2934 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2935 {
2936 	mlx5e_build_txq_maps(priv);
2937 	mlx5e_activate_channels(priv, &priv->channels);
2938 	mlx5e_xdp_tx_enable(priv);
2939 
2940 	/* dev_watchdog() wants all TX queues to be started when the carrier is
2941 	 * OK, including the ones in range real_num_tx_queues..num_tx_queues-1.
2942 	 * Make it happy to avoid TX timeout false alarms.
2943 	 */
2944 	netif_tx_start_all_queues(priv->netdev);
2945 
2946 	if (mlx5e_is_vport_rep(priv))
2947 		mlx5e_rep_activate_channels(priv);
2948 
2949 	set_bit(MLX5E_STATE_CHANNELS_ACTIVE, &priv->state);
2950 
2951 	mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2952 
2953 	if (priv->rx_res)
2954 		mlx5e_rx_res_channels_activate(priv->rx_res, &priv->channels);
2955 }
2956 
mlx5e_cancel_tx_timeout_work(struct mlx5e_priv * priv)2957 static void mlx5e_cancel_tx_timeout_work(struct mlx5e_priv *priv)
2958 {
2959 	WARN_ON_ONCE(test_bit(MLX5E_STATE_CHANNELS_ACTIVE, &priv->state));
2960 	if (current_work() != &priv->tx_timeout_work)
2961 		cancel_work_sync(&priv->tx_timeout_work);
2962 }
2963 
mlx5e_deactivate_priv_channels(struct mlx5e_priv * priv)2964 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2965 {
2966 	if (priv->rx_res)
2967 		mlx5e_rx_res_channels_deactivate(priv->rx_res);
2968 
2969 	clear_bit(MLX5E_STATE_CHANNELS_ACTIVE, &priv->state);
2970 	mlx5e_cancel_tx_timeout_work(priv);
2971 
2972 	if (mlx5e_is_vport_rep(priv))
2973 		mlx5e_rep_deactivate_channels(priv);
2974 
2975 	/* The results of ndo_select_queue are unreliable, while netdev config
2976 	 * is being changed (real_num_tx_queues, num_tc). Stop all queues to
2977 	 * prevent ndo_start_xmit from being called, so that it can assume that
2978 	 * the selected queue is always valid.
2979 	 */
2980 	netif_tx_disable(priv->netdev);
2981 
2982 	mlx5e_xdp_tx_disable(priv);
2983 	mlx5e_deactivate_channels(&priv->channels);
2984 }
2985 
mlx5e_switch_priv_params(struct mlx5e_priv * priv,struct mlx5e_params * new_params,mlx5e_fp_preactivate preactivate,void * context)2986 static int mlx5e_switch_priv_params(struct mlx5e_priv *priv,
2987 				    struct mlx5e_params *new_params,
2988 				    mlx5e_fp_preactivate preactivate,
2989 				    void *context)
2990 {
2991 	struct mlx5e_params old_params;
2992 
2993 	old_params = priv->channels.params;
2994 	priv->channels.params = *new_params;
2995 
2996 	if (preactivate) {
2997 		int err;
2998 
2999 		err = preactivate(priv, context);
3000 		if (err) {
3001 			priv->channels.params = old_params;
3002 			return err;
3003 		}
3004 	}
3005 
3006 	return 0;
3007 }
3008 
mlx5e_switch_priv_channels(struct mlx5e_priv * priv,struct mlx5e_channels * new_chs,mlx5e_fp_preactivate preactivate,void * context)3009 static int mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
3010 				      struct mlx5e_channels *new_chs,
3011 				      mlx5e_fp_preactivate preactivate,
3012 				      void *context)
3013 {
3014 	struct net_device *netdev = priv->netdev;
3015 	struct mlx5e_channels old_chs;
3016 	int carrier_ok;
3017 	int err = 0;
3018 
3019 	carrier_ok = netif_carrier_ok(netdev);
3020 	netif_carrier_off(netdev);
3021 
3022 	mlx5e_deactivate_priv_channels(priv);
3023 
3024 	old_chs = priv->channels;
3025 	priv->channels = *new_chs;
3026 
3027 	/* New channels are ready to roll, call the preactivate hook if needed
3028 	 * to modify HW settings or update kernel parameters.
3029 	 */
3030 	if (preactivate) {
3031 		err = preactivate(priv, context);
3032 		if (err) {
3033 			priv->channels = old_chs;
3034 			goto out;
3035 		}
3036 	}
3037 
3038 	mlx5e_close_channels(&old_chs);
3039 	priv->profile->update_rx(priv);
3040 
3041 	mlx5e_selq_apply(&priv->selq);
3042 out:
3043 	mlx5e_activate_priv_channels(priv);
3044 
3045 	/* return carrier back if needed */
3046 	if (carrier_ok)
3047 		netif_carrier_on(netdev);
3048 
3049 	return err;
3050 }
3051 
mlx5e_safe_switch_params(struct mlx5e_priv * priv,struct mlx5e_params * params,mlx5e_fp_preactivate preactivate,void * context,bool reset)3052 int mlx5e_safe_switch_params(struct mlx5e_priv *priv,
3053 			     struct mlx5e_params *params,
3054 			     mlx5e_fp_preactivate preactivate,
3055 			     void *context, bool reset)
3056 {
3057 	struct mlx5e_channels *new_chs;
3058 	int err;
3059 
3060 	reset &= test_bit(MLX5E_STATE_OPENED, &priv->state);
3061 	if (!reset)
3062 		return mlx5e_switch_priv_params(priv, params, preactivate, context);
3063 
3064 	new_chs = kzalloc(sizeof(*new_chs), GFP_KERNEL);
3065 	if (!new_chs)
3066 		return -ENOMEM;
3067 	new_chs->params = *params;
3068 
3069 	mlx5e_selq_prepare_params(&priv->selq, &new_chs->params);
3070 
3071 	err = mlx5e_open_channels(priv, new_chs);
3072 	if (err)
3073 		goto err_cancel_selq;
3074 
3075 	err = mlx5e_switch_priv_channels(priv, new_chs, preactivate, context);
3076 	if (err)
3077 		goto err_close;
3078 
3079 	kfree(new_chs);
3080 	return 0;
3081 
3082 err_close:
3083 	mlx5e_close_channels(new_chs);
3084 
3085 err_cancel_selq:
3086 	mlx5e_selq_cancel(&priv->selq);
3087 	kfree(new_chs);
3088 	return err;
3089 }
3090 
mlx5e_safe_reopen_channels(struct mlx5e_priv * priv)3091 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv)
3092 {
3093 	return mlx5e_safe_switch_params(priv, &priv->channels.params, NULL, NULL, true);
3094 }
3095 
mlx5e_timestamp_init(struct mlx5e_priv * priv)3096 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
3097 {
3098 	priv->tstamp.tx_type   = HWTSTAMP_TX_OFF;
3099 	priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
3100 }
3101 
mlx5e_modify_admin_state(struct mlx5_core_dev * mdev,enum mlx5_port_status state)3102 static void mlx5e_modify_admin_state(struct mlx5_core_dev *mdev,
3103 				     enum mlx5_port_status state)
3104 {
3105 	struct mlx5_eswitch *esw = mdev->priv.eswitch;
3106 	int vport_admin_state;
3107 
3108 	mlx5_set_port_admin_status(mdev, state);
3109 
3110 	if (mlx5_eswitch_mode(mdev) == MLX5_ESWITCH_OFFLOADS ||
3111 	    !MLX5_CAP_GEN(mdev, uplink_follow))
3112 		return;
3113 
3114 	if (state == MLX5_PORT_UP)
3115 		vport_admin_state = MLX5_VPORT_ADMIN_STATE_AUTO;
3116 	else
3117 		vport_admin_state = MLX5_VPORT_ADMIN_STATE_DOWN;
3118 
3119 	mlx5_eswitch_set_vport_state(esw, MLX5_VPORT_UPLINK, vport_admin_state);
3120 }
3121 
mlx5e_open_locked(struct net_device * netdev)3122 int mlx5e_open_locked(struct net_device *netdev)
3123 {
3124 	struct mlx5e_priv *priv = netdev_priv(netdev);
3125 	int err;
3126 
3127 	mlx5e_selq_prepare_params(&priv->selq, &priv->channels.params);
3128 
3129 	set_bit(MLX5E_STATE_OPENED, &priv->state);
3130 
3131 	err = mlx5e_open_channels(priv, &priv->channels);
3132 	if (err)
3133 		goto err_clear_state_opened_flag;
3134 
3135 	err = priv->profile->update_rx(priv);
3136 	if (err)
3137 		goto err_close_channels;
3138 
3139 	mlx5e_selq_apply(&priv->selq);
3140 	mlx5e_activate_priv_channels(priv);
3141 	mlx5e_apply_traps(priv, true);
3142 	if (priv->profile->update_carrier)
3143 		priv->profile->update_carrier(priv);
3144 
3145 	mlx5e_queue_update_stats(priv);
3146 	return 0;
3147 
3148 err_close_channels:
3149 	mlx5e_close_channels(&priv->channels);
3150 err_clear_state_opened_flag:
3151 	clear_bit(MLX5E_STATE_OPENED, &priv->state);
3152 	mlx5e_selq_cancel(&priv->selq);
3153 	return err;
3154 }
3155 
mlx5e_open(struct net_device * netdev)3156 int mlx5e_open(struct net_device *netdev)
3157 {
3158 	struct mlx5e_priv *priv = netdev_priv(netdev);
3159 	int err;
3160 
3161 	mutex_lock(&priv->state_lock);
3162 	err = mlx5e_open_locked(netdev);
3163 	if (!err)
3164 		mlx5e_modify_admin_state(priv->mdev, MLX5_PORT_UP);
3165 	mutex_unlock(&priv->state_lock);
3166 
3167 	return err;
3168 }
3169 
mlx5e_close_locked(struct net_device * netdev)3170 int mlx5e_close_locked(struct net_device *netdev)
3171 {
3172 	struct mlx5e_priv *priv = netdev_priv(netdev);
3173 
3174 	/* May already be CLOSED in case a previous configuration operation
3175 	 * (e.g RX/TX queue size change) that involves close&open failed.
3176 	 */
3177 	if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3178 		return 0;
3179 
3180 	mlx5e_apply_traps(priv, false);
3181 	clear_bit(MLX5E_STATE_OPENED, &priv->state);
3182 
3183 	netif_carrier_off(priv->netdev);
3184 	mlx5e_deactivate_priv_channels(priv);
3185 	mlx5e_close_channels(&priv->channels);
3186 
3187 	return 0;
3188 }
3189 
mlx5e_close(struct net_device * netdev)3190 int mlx5e_close(struct net_device *netdev)
3191 {
3192 	struct mlx5e_priv *priv = netdev_priv(netdev);
3193 	int err;
3194 
3195 	if (!netif_device_present(netdev))
3196 		return -ENODEV;
3197 
3198 	mutex_lock(&priv->state_lock);
3199 	mlx5e_modify_admin_state(priv->mdev, MLX5_PORT_DOWN);
3200 	err = mlx5e_close_locked(netdev);
3201 	mutex_unlock(&priv->state_lock);
3202 
3203 	return err;
3204 }
3205 
mlx5e_free_drop_rq(struct mlx5e_rq * rq)3206 static void mlx5e_free_drop_rq(struct mlx5e_rq *rq)
3207 {
3208 	mlx5_wq_destroy(&rq->wq_ctrl);
3209 }
3210 
mlx5e_alloc_drop_rq(struct mlx5_core_dev * mdev,struct mlx5e_rq * rq,struct mlx5e_rq_param * param)3211 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
3212 			       struct mlx5e_rq *rq,
3213 			       struct mlx5e_rq_param *param)
3214 {
3215 	void *rqc = param->rqc;
3216 	void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
3217 	int err;
3218 
3219 	param->wq.db_numa_node = param->wq.buf_numa_node;
3220 
3221 	err = mlx5_wq_cyc_create(mdev, &param->wq, rqc_wq, &rq->wqe.wq,
3222 				 &rq->wq_ctrl);
3223 	if (err)
3224 		return err;
3225 
3226 	/* Mark as unused given "Drop-RQ" packets never reach XDP */
3227 	xdp_rxq_info_unused(&rq->xdp_rxq);
3228 
3229 	rq->mdev = mdev;
3230 
3231 	return 0;
3232 }
3233 
mlx5e_alloc_drop_cq(struct mlx5e_priv * priv,struct mlx5e_cq * cq,struct mlx5e_cq_param * param)3234 static int mlx5e_alloc_drop_cq(struct mlx5e_priv *priv,
3235 			       struct mlx5e_cq *cq,
3236 			       struct mlx5e_cq_param *param)
3237 {
3238 	struct mlx5_core_dev *mdev = priv->mdev;
3239 
3240 	param->wq.buf_numa_node = dev_to_node(mlx5_core_dma_dev(mdev));
3241 	param->wq.db_numa_node  = dev_to_node(mlx5_core_dma_dev(mdev));
3242 
3243 	return mlx5e_alloc_cq_common(priv, param, cq);
3244 }
3245 
mlx5e_open_drop_rq(struct mlx5e_priv * priv,struct mlx5e_rq * drop_rq)3246 int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
3247 		       struct mlx5e_rq *drop_rq)
3248 {
3249 	struct mlx5_core_dev *mdev = priv->mdev;
3250 	struct mlx5e_cq_param cq_param = {};
3251 	struct mlx5e_rq_param rq_param = {};
3252 	struct mlx5e_cq *cq = &drop_rq->cq;
3253 	int err;
3254 
3255 	mlx5e_build_drop_rq_param(mdev, priv->drop_rq_q_counter, &rq_param);
3256 
3257 	err = mlx5e_alloc_drop_cq(priv, cq, &cq_param);
3258 	if (err)
3259 		return err;
3260 
3261 	err = mlx5e_create_cq(cq, &cq_param);
3262 	if (err)
3263 		goto err_free_cq;
3264 
3265 	err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
3266 	if (err)
3267 		goto err_destroy_cq;
3268 
3269 	err = mlx5e_create_rq(drop_rq, &rq_param);
3270 	if (err)
3271 		goto err_free_rq;
3272 
3273 	err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3274 	if (err)
3275 		mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err);
3276 
3277 	return 0;
3278 
3279 err_free_rq:
3280 	mlx5e_free_drop_rq(drop_rq);
3281 
3282 err_destroy_cq:
3283 	mlx5e_destroy_cq(cq);
3284 
3285 err_free_cq:
3286 	mlx5e_free_cq(cq);
3287 
3288 	return err;
3289 }
3290 
mlx5e_close_drop_rq(struct mlx5e_rq * drop_rq)3291 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
3292 {
3293 	mlx5e_destroy_rq(drop_rq);
3294 	mlx5e_free_drop_rq(drop_rq);
3295 	mlx5e_destroy_cq(&drop_rq->cq);
3296 	mlx5e_free_cq(&drop_rq->cq);
3297 }
3298 
mlx5e_create_tis(struct mlx5_core_dev * mdev,void * in,u32 * tisn)3299 int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn)
3300 {
3301 	void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3302 
3303 	MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.hw_objs.td.tdn);
3304 
3305 	if (MLX5_GET(tisc, tisc, tls_en))
3306 		MLX5_SET(tisc, tisc, pd, mdev->mlx5e_res.hw_objs.pdn);
3307 
3308 	if (mlx5_lag_is_lacp_owner(mdev))
3309 		MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
3310 
3311 	return mlx5_core_create_tis(mdev, in, tisn);
3312 }
3313 
mlx5e_destroy_tis(struct mlx5_core_dev * mdev,u32 tisn)3314 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
3315 {
3316 	mlx5_core_destroy_tis(mdev, tisn);
3317 }
3318 
mlx5e_destroy_tises(struct mlx5e_priv * priv)3319 void mlx5e_destroy_tises(struct mlx5e_priv *priv)
3320 {
3321 	int tc, i;
3322 
3323 	for (i = 0; i < mlx5e_get_num_lag_ports(priv->mdev); i++)
3324 		for (tc = 0; tc < priv->profile->max_tc; tc++)
3325 			mlx5e_destroy_tis(priv->mdev, priv->tisn[i][tc]);
3326 }
3327 
mlx5e_lag_should_assign_affinity(struct mlx5_core_dev * mdev)3328 static bool mlx5e_lag_should_assign_affinity(struct mlx5_core_dev *mdev)
3329 {
3330 	return MLX5_CAP_GEN(mdev, lag_tx_port_affinity) && mlx5e_get_num_lag_ports(mdev) > 1;
3331 }
3332 
mlx5e_create_tises(struct mlx5e_priv * priv)3333 int mlx5e_create_tises(struct mlx5e_priv *priv)
3334 {
3335 	int tc, i;
3336 	int err;
3337 
3338 	for (i = 0; i < mlx5e_get_num_lag_ports(priv->mdev); i++) {
3339 		for (tc = 0; tc < priv->profile->max_tc; tc++) {
3340 			u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {};
3341 			void *tisc;
3342 
3343 			tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3344 
3345 			MLX5_SET(tisc, tisc, prio, tc << 1);
3346 
3347 			if (mlx5e_lag_should_assign_affinity(priv->mdev))
3348 				MLX5_SET(tisc, tisc, lag_tx_port_affinity, i + 1);
3349 
3350 			err = mlx5e_create_tis(priv->mdev, in, &priv->tisn[i][tc]);
3351 			if (err)
3352 				goto err_close_tises;
3353 		}
3354 	}
3355 
3356 	return 0;
3357 
3358 err_close_tises:
3359 	for (; i >= 0; i--) {
3360 		for (tc--; tc >= 0; tc--)
3361 			mlx5e_destroy_tis(priv->mdev, priv->tisn[i][tc]);
3362 		tc = priv->profile->max_tc;
3363 	}
3364 
3365 	return err;
3366 }
3367 
mlx5e_cleanup_nic_tx(struct mlx5e_priv * priv)3368 static void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
3369 {
3370 	if (priv->mqprio_rl) {
3371 		mlx5e_mqprio_rl_cleanup(priv->mqprio_rl);
3372 		mlx5e_mqprio_rl_free(priv->mqprio_rl);
3373 		priv->mqprio_rl = NULL;
3374 	}
3375 	mlx5e_accel_cleanup_tx(priv);
3376 	mlx5e_destroy_tises(priv);
3377 }
3378 
mlx5e_modify_channels_vsd(struct mlx5e_channels * chs,bool vsd)3379 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
3380 {
3381 	int err;
3382 	int i;
3383 
3384 	for (i = 0; i < chs->num; i++) {
3385 		err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
3386 		if (err)
3387 			return err;
3388 	}
3389 	if (chs->ptp && test_bit(MLX5E_PTP_STATE_RX, chs->ptp->state))
3390 		return mlx5e_modify_rq_vsd(&chs->ptp->rq, vsd);
3391 
3392 	return 0;
3393 }
3394 
mlx5e_mqprio_build_default_tc_to_txq(struct netdev_tc_txq * tc_to_txq,int ntc,int nch)3395 static void mlx5e_mqprio_build_default_tc_to_txq(struct netdev_tc_txq *tc_to_txq,
3396 						 int ntc, int nch)
3397 {
3398 	int tc;
3399 
3400 	memset(tc_to_txq, 0, sizeof(*tc_to_txq) * TC_MAX_QUEUE);
3401 
3402 	/* Map netdev TCs to offset 0.
3403 	 * We have our own UP to TXQ mapping for DCB mode of QoS
3404 	 */
3405 	for (tc = 0; tc < ntc; tc++) {
3406 		tc_to_txq[tc] = (struct netdev_tc_txq) {
3407 			.count = nch,
3408 			.offset = 0,
3409 		};
3410 	}
3411 }
3412 
mlx5e_mqprio_build_tc_to_txq(struct netdev_tc_txq * tc_to_txq,struct tc_mqprio_qopt * qopt)3413 static void mlx5e_mqprio_build_tc_to_txq(struct netdev_tc_txq *tc_to_txq,
3414 					 struct tc_mqprio_qopt *qopt)
3415 {
3416 	int tc;
3417 
3418 	for (tc = 0; tc < TC_MAX_QUEUE; tc++) {
3419 		tc_to_txq[tc] = (struct netdev_tc_txq) {
3420 			.count = qopt->count[tc],
3421 			.offset = qopt->offset[tc],
3422 		};
3423 	}
3424 }
3425 
mlx5e_params_mqprio_dcb_set(struct mlx5e_params * params,u8 num_tc)3426 static void mlx5e_params_mqprio_dcb_set(struct mlx5e_params *params, u8 num_tc)
3427 {
3428 	params->mqprio.mode = TC_MQPRIO_MODE_DCB;
3429 	params->mqprio.num_tc = num_tc;
3430 	mlx5e_mqprio_build_default_tc_to_txq(params->mqprio.tc_to_txq, num_tc,
3431 					     params->num_channels);
3432 }
3433 
mlx5e_mqprio_rl_update_params(struct mlx5e_params * params,struct mlx5e_mqprio_rl * rl)3434 static void mlx5e_mqprio_rl_update_params(struct mlx5e_params *params,
3435 					  struct mlx5e_mqprio_rl *rl)
3436 {
3437 	int tc;
3438 
3439 	for (tc = 0; tc < TC_MAX_QUEUE; tc++) {
3440 		u32 hw_id = 0;
3441 
3442 		if (rl)
3443 			mlx5e_mqprio_rl_get_node_hw_id(rl, tc, &hw_id);
3444 		params->mqprio.channel.hw_id[tc] = hw_id;
3445 	}
3446 }
3447 
mlx5e_params_mqprio_channel_set(struct mlx5e_params * params,struct tc_mqprio_qopt_offload * mqprio,struct mlx5e_mqprio_rl * rl)3448 static void mlx5e_params_mqprio_channel_set(struct mlx5e_params *params,
3449 					    struct tc_mqprio_qopt_offload *mqprio,
3450 					    struct mlx5e_mqprio_rl *rl)
3451 {
3452 	int tc;
3453 
3454 	params->mqprio.mode = TC_MQPRIO_MODE_CHANNEL;
3455 	params->mqprio.num_tc = mqprio->qopt.num_tc;
3456 
3457 	for (tc = 0; tc < TC_MAX_QUEUE; tc++)
3458 		params->mqprio.channel.max_rate[tc] = mqprio->max_rate[tc];
3459 
3460 	mlx5e_mqprio_rl_update_params(params, rl);
3461 	mlx5e_mqprio_build_tc_to_txq(params->mqprio.tc_to_txq, &mqprio->qopt);
3462 }
3463 
mlx5e_params_mqprio_reset(struct mlx5e_params * params)3464 static void mlx5e_params_mqprio_reset(struct mlx5e_params *params)
3465 {
3466 	mlx5e_params_mqprio_dcb_set(params, 1);
3467 }
3468 
mlx5e_setup_tc_mqprio_dcb(struct mlx5e_priv * priv,struct tc_mqprio_qopt * mqprio)3469 static int mlx5e_setup_tc_mqprio_dcb(struct mlx5e_priv *priv,
3470 				     struct tc_mqprio_qopt *mqprio)
3471 {
3472 	struct mlx5e_params new_params;
3473 	u8 tc = mqprio->num_tc;
3474 	int err;
3475 
3476 	mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3477 
3478 	if (tc && tc != MLX5E_MAX_NUM_TC)
3479 		return -EINVAL;
3480 
3481 	new_params = priv->channels.params;
3482 	mlx5e_params_mqprio_dcb_set(&new_params, tc ? tc : 1);
3483 
3484 	err = mlx5e_safe_switch_params(priv, &new_params,
3485 				       mlx5e_num_channels_changed_ctx, NULL, true);
3486 
3487 	if (!err && priv->mqprio_rl) {
3488 		mlx5e_mqprio_rl_cleanup(priv->mqprio_rl);
3489 		mlx5e_mqprio_rl_free(priv->mqprio_rl);
3490 		priv->mqprio_rl = NULL;
3491 	}
3492 
3493 	priv->max_opened_tc = max_t(u8, priv->max_opened_tc,
3494 				    mlx5e_get_dcb_num_tc(&priv->channels.params));
3495 	return err;
3496 }
3497 
mlx5e_mqprio_channel_validate(struct mlx5e_priv * priv,struct tc_mqprio_qopt_offload * mqprio)3498 static int mlx5e_mqprio_channel_validate(struct mlx5e_priv *priv,
3499 					 struct tc_mqprio_qopt_offload *mqprio)
3500 {
3501 	struct net_device *netdev = priv->netdev;
3502 	struct mlx5e_ptp *ptp_channel;
3503 	int agg_count = 0;
3504 	int i;
3505 
3506 	ptp_channel = priv->channels.ptp;
3507 	if (ptp_channel && test_bit(MLX5E_PTP_STATE_TX, ptp_channel->state)) {
3508 		netdev_err(netdev,
3509 			   "Cannot activate MQPRIO mode channel since it conflicts with TX port TS\n");
3510 		return -EINVAL;
3511 	}
3512 
3513 	if (mqprio->qopt.offset[0] != 0 || mqprio->qopt.num_tc < 1 ||
3514 	    mqprio->qopt.num_tc > MLX5E_MAX_NUM_MQPRIO_CH_TC)
3515 		return -EINVAL;
3516 
3517 	for (i = 0; i < mqprio->qopt.num_tc; i++) {
3518 		if (!mqprio->qopt.count[i]) {
3519 			netdev_err(netdev, "Zero size for queue-group (%d) is not supported\n", i);
3520 			return -EINVAL;
3521 		}
3522 		if (mqprio->min_rate[i]) {
3523 			netdev_err(netdev, "Min tx rate is not supported\n");
3524 			return -EINVAL;
3525 		}
3526 
3527 		if (mqprio->max_rate[i]) {
3528 			int err;
3529 
3530 			err = mlx5e_qos_bytes_rate_check(priv->mdev, mqprio->max_rate[i]);
3531 			if (err)
3532 				return err;
3533 		}
3534 
3535 		if (mqprio->qopt.offset[i] != agg_count) {
3536 			netdev_err(netdev, "Discontinuous queues config is not supported\n");
3537 			return -EINVAL;
3538 		}
3539 		agg_count += mqprio->qopt.count[i];
3540 	}
3541 
3542 	if (priv->channels.params.num_channels != agg_count) {
3543 		netdev_err(netdev, "Num of queues (%d) does not match available (%d)\n",
3544 			   agg_count, priv->channels.params.num_channels);
3545 		return -EINVAL;
3546 	}
3547 
3548 	return 0;
3549 }
3550 
mlx5e_mqprio_rate_limit(u8 num_tc,u64 max_rate[])3551 static bool mlx5e_mqprio_rate_limit(u8 num_tc, u64 max_rate[])
3552 {
3553 	int tc;
3554 
3555 	for (tc = 0; tc < num_tc; tc++)
3556 		if (max_rate[tc])
3557 			return true;
3558 	return false;
3559 }
3560 
mlx5e_mqprio_rl_create(struct mlx5_core_dev * mdev,u8 num_tc,u64 max_rate[])3561 static struct mlx5e_mqprio_rl *mlx5e_mqprio_rl_create(struct mlx5_core_dev *mdev,
3562 						      u8 num_tc, u64 max_rate[])
3563 {
3564 	struct mlx5e_mqprio_rl *rl;
3565 	int err;
3566 
3567 	if (!mlx5e_mqprio_rate_limit(num_tc, max_rate))
3568 		return NULL;
3569 
3570 	rl = mlx5e_mqprio_rl_alloc();
3571 	if (!rl)
3572 		return ERR_PTR(-ENOMEM);
3573 
3574 	err = mlx5e_mqprio_rl_init(rl, mdev, num_tc, max_rate);
3575 	if (err) {
3576 		mlx5e_mqprio_rl_free(rl);
3577 		return ERR_PTR(err);
3578 	}
3579 
3580 	return rl;
3581 }
3582 
mlx5e_setup_tc_mqprio_channel(struct mlx5e_priv * priv,struct tc_mqprio_qopt_offload * mqprio)3583 static int mlx5e_setup_tc_mqprio_channel(struct mlx5e_priv *priv,
3584 					 struct tc_mqprio_qopt_offload *mqprio)
3585 {
3586 	mlx5e_fp_preactivate preactivate;
3587 	struct mlx5e_params new_params;
3588 	struct mlx5e_mqprio_rl *rl;
3589 	bool nch_changed;
3590 	int err;
3591 
3592 	err = mlx5e_mqprio_channel_validate(priv, mqprio);
3593 	if (err)
3594 		return err;
3595 
3596 	rl = mlx5e_mqprio_rl_create(priv->mdev, mqprio->qopt.num_tc, mqprio->max_rate);
3597 	if (IS_ERR(rl))
3598 		return PTR_ERR(rl);
3599 
3600 	new_params = priv->channels.params;
3601 	mlx5e_params_mqprio_channel_set(&new_params, mqprio, rl);
3602 
3603 	nch_changed = mlx5e_get_dcb_num_tc(&priv->channels.params) > 1;
3604 	preactivate = nch_changed ? mlx5e_num_channels_changed_ctx :
3605 		mlx5e_update_netdev_queues_ctx;
3606 	err = mlx5e_safe_switch_params(priv, &new_params, preactivate, NULL, true);
3607 	if (err) {
3608 		if (rl) {
3609 			mlx5e_mqprio_rl_cleanup(rl);
3610 			mlx5e_mqprio_rl_free(rl);
3611 		}
3612 		return err;
3613 	}
3614 
3615 	if (priv->mqprio_rl) {
3616 		mlx5e_mqprio_rl_cleanup(priv->mqprio_rl);
3617 		mlx5e_mqprio_rl_free(priv->mqprio_rl);
3618 	}
3619 	priv->mqprio_rl = rl;
3620 
3621 	return 0;
3622 }
3623 
mlx5e_setup_tc_mqprio(struct mlx5e_priv * priv,struct tc_mqprio_qopt_offload * mqprio)3624 static int mlx5e_setup_tc_mqprio(struct mlx5e_priv *priv,
3625 				 struct tc_mqprio_qopt_offload *mqprio)
3626 {
3627 	/* MQPRIO is another toplevel qdisc that can't be attached
3628 	 * simultaneously with the offloaded HTB.
3629 	 */
3630 	if (WARN_ON(mlx5e_selq_is_htb_enabled(&priv->selq)))
3631 		return -EINVAL;
3632 
3633 	switch (mqprio->mode) {
3634 	case TC_MQPRIO_MODE_DCB:
3635 		return mlx5e_setup_tc_mqprio_dcb(priv, &mqprio->qopt);
3636 	case TC_MQPRIO_MODE_CHANNEL:
3637 		return mlx5e_setup_tc_mqprio_channel(priv, mqprio);
3638 	default:
3639 		return -EOPNOTSUPP;
3640 	}
3641 }
3642 
3643 static LIST_HEAD(mlx5e_block_cb_list);
3644 
mlx5e_setup_tc(struct net_device * dev,enum tc_setup_type type,void * type_data)3645 static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3646 			  void *type_data)
3647 {
3648 	struct mlx5e_priv *priv = netdev_priv(dev);
3649 	bool tc_unbind = false;
3650 	int err;
3651 
3652 	if (type == TC_SETUP_BLOCK &&
3653 	    ((struct flow_block_offload *)type_data)->command == FLOW_BLOCK_UNBIND)
3654 		tc_unbind = true;
3655 
3656 	if (!netif_device_present(dev) && !tc_unbind)
3657 		return -ENODEV;
3658 
3659 	switch (type) {
3660 	case TC_SETUP_BLOCK: {
3661 		struct flow_block_offload *f = type_data;
3662 
3663 		f->unlocked_driver_cb = true;
3664 		return flow_block_cb_setup_simple(type_data,
3665 						  &mlx5e_block_cb_list,
3666 						  mlx5e_setup_tc_block_cb,
3667 						  priv, priv, true);
3668 	}
3669 	case TC_SETUP_QDISC_MQPRIO:
3670 		mutex_lock(&priv->state_lock);
3671 		err = mlx5e_setup_tc_mqprio(priv, type_data);
3672 		mutex_unlock(&priv->state_lock);
3673 		return err;
3674 	case TC_SETUP_QDISC_HTB:
3675 		mutex_lock(&priv->state_lock);
3676 		err = mlx5e_htb_setup_tc(priv, type_data);
3677 		mutex_unlock(&priv->state_lock);
3678 		return err;
3679 	default:
3680 		return -EOPNOTSUPP;
3681 	}
3682 }
3683 
mlx5e_fold_sw_stats64(struct mlx5e_priv * priv,struct rtnl_link_stats64 * s)3684 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s)
3685 {
3686 	int i;
3687 
3688 	for (i = 0; i < priv->stats_nch; i++) {
3689 		struct mlx5e_channel_stats *channel_stats = priv->channel_stats[i];
3690 		struct mlx5e_rq_stats *xskrq_stats = &channel_stats->xskrq;
3691 		struct mlx5e_rq_stats *rq_stats = &channel_stats->rq;
3692 		int j;
3693 
3694 		s->rx_packets   += rq_stats->packets + xskrq_stats->packets;
3695 		s->rx_bytes     += rq_stats->bytes + xskrq_stats->bytes;
3696 		s->multicast    += rq_stats->mcast_packets + xskrq_stats->mcast_packets;
3697 
3698 		for (j = 0; j < priv->max_opened_tc; j++) {
3699 			struct mlx5e_sq_stats *sq_stats = &channel_stats->sq[j];
3700 
3701 			s->tx_packets    += sq_stats->packets;
3702 			s->tx_bytes      += sq_stats->bytes;
3703 			s->tx_dropped    += sq_stats->dropped;
3704 		}
3705 	}
3706 	if (priv->tx_ptp_opened) {
3707 		for (i = 0; i < priv->max_opened_tc; i++) {
3708 			struct mlx5e_sq_stats *sq_stats = &priv->ptp_stats.sq[i];
3709 
3710 			s->tx_packets    += sq_stats->packets;
3711 			s->tx_bytes      += sq_stats->bytes;
3712 			s->tx_dropped    += sq_stats->dropped;
3713 		}
3714 	}
3715 	if (priv->rx_ptp_opened) {
3716 		struct mlx5e_rq_stats *rq_stats = &priv->ptp_stats.rq;
3717 
3718 		s->rx_packets   += rq_stats->packets;
3719 		s->rx_bytes     += rq_stats->bytes;
3720 		s->multicast    += rq_stats->mcast_packets;
3721 	}
3722 }
3723 
3724 void
mlx5e_get_stats(struct net_device * dev,struct rtnl_link_stats64 * stats)3725 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3726 {
3727 	struct mlx5e_priv *priv = netdev_priv(dev);
3728 	struct mlx5e_pport_stats *pstats = &priv->stats.pport;
3729 
3730 	if (!netif_device_present(dev))
3731 		return;
3732 
3733 	/* In switchdev mode, monitor counters doesn't monitor
3734 	 * rx/tx stats of 802_3. The update stats mechanism
3735 	 * should keep the 802_3 layout counters updated
3736 	 */
3737 	if (!mlx5e_monitor_counter_supported(priv) ||
3738 	    mlx5e_is_uplink_rep(priv)) {
3739 		/* update HW stats in background for next time */
3740 		mlx5e_queue_update_stats(priv);
3741 	}
3742 
3743 	if (mlx5e_is_uplink_rep(priv)) {
3744 		struct mlx5e_vport_stats *vstats = &priv->stats.vport;
3745 
3746 		stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3747 		stats->rx_bytes   = PPORT_802_3_GET(pstats, a_octets_received_ok);
3748 		stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3749 		stats->tx_bytes   = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3750 
3751 		/* vport multicast also counts packets that are dropped due to steering
3752 		 * or rx out of buffer
3753 		 */
3754 		stats->multicast = VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
3755 	} else {
3756 		mlx5e_fold_sw_stats64(priv, stats);
3757 	}
3758 
3759 	stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
3760 
3761 	stats->rx_length_errors =
3762 		PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3763 		PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3764 		PPORT_802_3_GET(pstats, a_frame_too_long_errors) +
3765 		VNIC_ENV_GET(&priv->stats.vnic, eth_wqe_too_small);
3766 	stats->rx_crc_errors =
3767 		PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3768 	stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3769 	stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
3770 	stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3771 			   stats->rx_frame_errors;
3772 	stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3773 }
3774 
mlx5e_nic_set_rx_mode(struct mlx5e_priv * priv)3775 static void mlx5e_nic_set_rx_mode(struct mlx5e_priv *priv)
3776 {
3777 	if (mlx5e_is_uplink_rep(priv))
3778 		return; /* no rx mode for uplink rep */
3779 
3780 	queue_work(priv->wq, &priv->set_rx_mode_work);
3781 }
3782 
mlx5e_set_rx_mode(struct net_device * dev)3783 static void mlx5e_set_rx_mode(struct net_device *dev)
3784 {
3785 	struct mlx5e_priv *priv = netdev_priv(dev);
3786 
3787 	mlx5e_nic_set_rx_mode(priv);
3788 }
3789 
mlx5e_set_mac(struct net_device * netdev,void * addr)3790 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3791 {
3792 	struct mlx5e_priv *priv = netdev_priv(netdev);
3793 	struct sockaddr *saddr = addr;
3794 
3795 	if (!is_valid_ether_addr(saddr->sa_data))
3796 		return -EADDRNOTAVAIL;
3797 
3798 	netif_addr_lock_bh(netdev);
3799 	eth_hw_addr_set(netdev, saddr->sa_data);
3800 	netif_addr_unlock_bh(netdev);
3801 
3802 	mlx5e_nic_set_rx_mode(priv);
3803 
3804 	return 0;
3805 }
3806 
3807 #define MLX5E_SET_FEATURE(features, feature, enable)	\
3808 	do {						\
3809 		if (enable)				\
3810 			*features |= feature;		\
3811 		else					\
3812 			*features &= ~feature;		\
3813 	} while (0)
3814 
3815 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3816 
set_feature_lro(struct net_device * netdev,bool enable)3817 static int set_feature_lro(struct net_device *netdev, bool enable)
3818 {
3819 	struct mlx5e_priv *priv = netdev_priv(netdev);
3820 	struct mlx5_core_dev *mdev = priv->mdev;
3821 	struct mlx5e_params *cur_params;
3822 	struct mlx5e_params new_params;
3823 	bool reset = true;
3824 	int err = 0;
3825 
3826 	mutex_lock(&priv->state_lock);
3827 
3828 	cur_params = &priv->channels.params;
3829 	new_params = *cur_params;
3830 
3831 	if (enable)
3832 		new_params.packet_merge.type = MLX5E_PACKET_MERGE_LRO;
3833 	else if (new_params.packet_merge.type == MLX5E_PACKET_MERGE_LRO)
3834 		new_params.packet_merge.type = MLX5E_PACKET_MERGE_NONE;
3835 	else
3836 		goto out;
3837 
3838 	if (!(cur_params->packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO &&
3839 	      new_params.packet_merge.type == MLX5E_PACKET_MERGE_LRO)) {
3840 		if (cur_params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
3841 			if (mlx5e_rx_mpwqe_is_linear_skb(mdev, cur_params, NULL) ==
3842 			    mlx5e_rx_mpwqe_is_linear_skb(mdev, &new_params, NULL))
3843 				reset = false;
3844 		}
3845 	}
3846 
3847 	err = mlx5e_safe_switch_params(priv, &new_params,
3848 				       mlx5e_modify_tirs_packet_merge_ctx, NULL, reset);
3849 out:
3850 	mutex_unlock(&priv->state_lock);
3851 	return err;
3852 }
3853 
set_feature_hw_gro(struct net_device * netdev,bool enable)3854 static int set_feature_hw_gro(struct net_device *netdev, bool enable)
3855 {
3856 	struct mlx5e_priv *priv = netdev_priv(netdev);
3857 	struct mlx5e_params new_params;
3858 	bool reset = true;
3859 	int err = 0;
3860 
3861 	mutex_lock(&priv->state_lock);
3862 	new_params = priv->channels.params;
3863 
3864 	if (enable) {
3865 		new_params.packet_merge.type = MLX5E_PACKET_MERGE_SHAMPO;
3866 		new_params.packet_merge.shampo.match_criteria_type =
3867 			MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED;
3868 		new_params.packet_merge.shampo.alignment_granularity =
3869 			MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE;
3870 	} else if (new_params.packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO) {
3871 		new_params.packet_merge.type = MLX5E_PACKET_MERGE_NONE;
3872 	} else {
3873 		goto out;
3874 	}
3875 
3876 	err = mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, reset);
3877 out:
3878 	mutex_unlock(&priv->state_lock);
3879 	return err;
3880 }
3881 
set_feature_cvlan_filter(struct net_device * netdev,bool enable)3882 static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
3883 {
3884 	struct mlx5e_priv *priv = netdev_priv(netdev);
3885 
3886 	if (enable)
3887 		mlx5e_enable_cvlan_filter(priv->fs,
3888 					  !!(priv->netdev->flags & IFF_PROMISC));
3889 	else
3890 		mlx5e_disable_cvlan_filter(priv->fs,
3891 					   !!(priv->netdev->flags & IFF_PROMISC));
3892 
3893 	return 0;
3894 }
3895 
set_feature_hw_tc(struct net_device * netdev,bool enable)3896 static int set_feature_hw_tc(struct net_device *netdev, bool enable)
3897 {
3898 	struct mlx5e_priv *priv = netdev_priv(netdev);
3899 	int err = 0;
3900 
3901 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
3902 	int tc_flag = mlx5e_is_uplink_rep(priv) ? MLX5_TC_FLAG(ESW_OFFLOAD) :
3903 						  MLX5_TC_FLAG(NIC_OFFLOAD);
3904 	if (!enable && mlx5e_tc_num_filters(priv, tc_flag)) {
3905 		netdev_err(netdev,
3906 			   "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3907 		return -EINVAL;
3908 	}
3909 #endif
3910 
3911 	mutex_lock(&priv->state_lock);
3912 	if (!enable && mlx5e_selq_is_htb_enabled(&priv->selq)) {
3913 		netdev_err(netdev, "Active HTB offload, can't turn hw_tc_offload off\n");
3914 		err = -EINVAL;
3915 	}
3916 	mutex_unlock(&priv->state_lock);
3917 
3918 	return err;
3919 }
3920 
set_feature_rx_all(struct net_device * netdev,bool enable)3921 static int set_feature_rx_all(struct net_device *netdev, bool enable)
3922 {
3923 	struct mlx5e_priv *priv = netdev_priv(netdev);
3924 	struct mlx5_core_dev *mdev = priv->mdev;
3925 
3926 	return mlx5_set_port_fcs(mdev, !enable);
3927 }
3928 
mlx5e_set_rx_port_ts(struct mlx5_core_dev * mdev,bool enable)3929 static int mlx5e_set_rx_port_ts(struct mlx5_core_dev *mdev, bool enable)
3930 {
3931 	u32 in[MLX5_ST_SZ_DW(pcmr_reg)] = {};
3932 	bool supported, curr_state;
3933 	int err;
3934 
3935 	if (!MLX5_CAP_GEN(mdev, ports_check))
3936 		return 0;
3937 
3938 	err = mlx5_query_ports_check(mdev, in, sizeof(in));
3939 	if (err)
3940 		return err;
3941 
3942 	supported = MLX5_GET(pcmr_reg, in, rx_ts_over_crc_cap);
3943 	curr_state = MLX5_GET(pcmr_reg, in, rx_ts_over_crc);
3944 
3945 	if (!supported || enable == curr_state)
3946 		return 0;
3947 
3948 	MLX5_SET(pcmr_reg, in, local_port, 1);
3949 	MLX5_SET(pcmr_reg, in, rx_ts_over_crc, enable);
3950 
3951 	return mlx5_set_ports_check(mdev, in, sizeof(in));
3952 }
3953 
mlx5e_set_rx_port_ts_wrap(struct mlx5e_priv * priv,void * ctx)3954 static int mlx5e_set_rx_port_ts_wrap(struct mlx5e_priv *priv, void *ctx)
3955 {
3956 	struct mlx5_core_dev *mdev = priv->mdev;
3957 	bool enable = *(bool *)ctx;
3958 
3959 	return mlx5e_set_rx_port_ts(mdev, enable);
3960 }
3961 
set_feature_rx_fcs(struct net_device * netdev,bool enable)3962 static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3963 {
3964 	struct mlx5e_priv *priv = netdev_priv(netdev);
3965 	struct mlx5e_channels *chs = &priv->channels;
3966 	struct mlx5e_params new_params;
3967 	int err;
3968 	bool rx_ts_over_crc = !enable;
3969 
3970 	mutex_lock(&priv->state_lock);
3971 
3972 	new_params = chs->params;
3973 	new_params.scatter_fcs_en = enable;
3974 	err = mlx5e_safe_switch_params(priv, &new_params, mlx5e_set_rx_port_ts_wrap,
3975 				       &rx_ts_over_crc, true);
3976 	mutex_unlock(&priv->state_lock);
3977 	return err;
3978 }
3979 
set_feature_rx_vlan(struct net_device * netdev,bool enable)3980 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3981 {
3982 	struct mlx5e_priv *priv = netdev_priv(netdev);
3983 	int err = 0;
3984 
3985 	mutex_lock(&priv->state_lock);
3986 
3987 	mlx5e_fs_set_vlan_strip_disable(priv->fs, !enable);
3988 	priv->channels.params.vlan_strip_disable = !enable;
3989 
3990 	if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3991 		goto unlock;
3992 
3993 	err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
3994 	if (err) {
3995 		mlx5e_fs_set_vlan_strip_disable(priv->fs, enable);
3996 		priv->channels.params.vlan_strip_disable = enable;
3997 	}
3998 unlock:
3999 	mutex_unlock(&priv->state_lock);
4000 
4001 	return err;
4002 }
4003 
mlx5e_vlan_rx_add_vid(struct net_device * dev,__be16 proto,u16 vid)4004 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid)
4005 {
4006 	struct mlx5e_priv *priv = netdev_priv(dev);
4007 	struct mlx5e_flow_steering *fs = priv->fs;
4008 
4009 	if (mlx5e_is_uplink_rep(priv))
4010 		return 0; /* no vlan table for uplink rep */
4011 
4012 	return mlx5e_fs_vlan_rx_add_vid(fs, dev, proto, vid);
4013 }
4014 
mlx5e_vlan_rx_kill_vid(struct net_device * dev,__be16 proto,u16 vid)4015 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid)
4016 {
4017 	struct mlx5e_priv *priv = netdev_priv(dev);
4018 	struct mlx5e_flow_steering *fs = priv->fs;
4019 
4020 	if (mlx5e_is_uplink_rep(priv))
4021 		return 0; /* no vlan table for uplink rep */
4022 
4023 	return mlx5e_fs_vlan_rx_kill_vid(fs, dev, proto, vid);
4024 }
4025 
4026 #ifdef CONFIG_MLX5_EN_ARFS
set_feature_arfs(struct net_device * netdev,bool enable)4027 static int set_feature_arfs(struct net_device *netdev, bool enable)
4028 {
4029 	struct mlx5e_priv *priv = netdev_priv(netdev);
4030 	int err;
4031 
4032 	if (enable)
4033 		err = mlx5e_arfs_enable(priv->fs);
4034 	else
4035 		err = mlx5e_arfs_disable(priv->fs);
4036 
4037 	return err;
4038 }
4039 #endif
4040 
mlx5e_handle_feature(struct net_device * netdev,netdev_features_t * features,netdev_features_t feature,mlx5e_feature_handler feature_handler)4041 static int mlx5e_handle_feature(struct net_device *netdev,
4042 				netdev_features_t *features,
4043 				netdev_features_t feature,
4044 				mlx5e_feature_handler feature_handler)
4045 {
4046 	netdev_features_t changes = *features ^ netdev->features;
4047 	bool enable = !!(*features & feature);
4048 	int err;
4049 
4050 	if (!(changes & feature))
4051 		return 0;
4052 
4053 	err = feature_handler(netdev, enable);
4054 	if (err) {
4055 		MLX5E_SET_FEATURE(features, feature, !enable);
4056 		netdev_err(netdev, "%s feature %pNF failed, err %d\n",
4057 			   enable ? "Enable" : "Disable", &feature, err);
4058 		return err;
4059 	}
4060 
4061 	return 0;
4062 }
4063 
mlx5e_set_xdp_feature(struct net_device * netdev)4064 void mlx5e_set_xdp_feature(struct net_device *netdev)
4065 {
4066 	struct mlx5e_priv *priv = netdev_priv(netdev);
4067 	struct mlx5e_params *params = &priv->channels.params;
4068 	xdp_features_t val;
4069 
4070 	if (params->packet_merge.type != MLX5E_PACKET_MERGE_NONE) {
4071 		xdp_clear_features_flag(netdev);
4072 		return;
4073 	}
4074 
4075 	val = NETDEV_XDP_ACT_BASIC | NETDEV_XDP_ACT_REDIRECT |
4076 	      NETDEV_XDP_ACT_XSK_ZEROCOPY |
4077 	      NETDEV_XDP_ACT_RX_SG |
4078 	      NETDEV_XDP_ACT_NDO_XMIT |
4079 	      NETDEV_XDP_ACT_NDO_XMIT_SG;
4080 	xdp_set_features_flag(netdev, val);
4081 }
4082 
mlx5e_set_features(struct net_device * netdev,netdev_features_t features)4083 int mlx5e_set_features(struct net_device *netdev, netdev_features_t features)
4084 {
4085 	netdev_features_t oper_features = features;
4086 	int err = 0;
4087 
4088 #define MLX5E_HANDLE_FEATURE(feature, handler) \
4089 	mlx5e_handle_feature(netdev, &oper_features, feature, handler)
4090 
4091 	err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro);
4092 	err |= MLX5E_HANDLE_FEATURE(NETIF_F_GRO_HW, set_feature_hw_gro);
4093 	err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_FILTER,
4094 				    set_feature_cvlan_filter);
4095 	err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TC, set_feature_hw_tc);
4096 	err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXALL, set_feature_rx_all);
4097 	err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs);
4098 	err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan);
4099 #ifdef CONFIG_MLX5_EN_ARFS
4100 	err |= MLX5E_HANDLE_FEATURE(NETIF_F_NTUPLE, set_feature_arfs);
4101 #endif
4102 	err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TLS_RX, mlx5e_ktls_set_feature_rx);
4103 
4104 	if (err) {
4105 		netdev->features = oper_features;
4106 		return -EINVAL;
4107 	}
4108 
4109 	/* update XDP supported features */
4110 	mlx5e_set_xdp_feature(netdev);
4111 
4112 	return 0;
4113 }
4114 
mlx5e_fix_uplink_rep_features(struct net_device * netdev,netdev_features_t features)4115 static netdev_features_t mlx5e_fix_uplink_rep_features(struct net_device *netdev,
4116 						       netdev_features_t features)
4117 {
4118 	features &= ~NETIF_F_HW_TLS_RX;
4119 	if (netdev->features & NETIF_F_HW_TLS_RX)
4120 		netdev_warn(netdev, "Disabling hw_tls_rx, not supported in switchdev mode\n");
4121 
4122 	features &= ~NETIF_F_HW_TLS_TX;
4123 	if (netdev->features & NETIF_F_HW_TLS_TX)
4124 		netdev_warn(netdev, "Disabling hw_tls_tx, not supported in switchdev mode\n");
4125 
4126 	features &= ~NETIF_F_NTUPLE;
4127 	if (netdev->features & NETIF_F_NTUPLE)
4128 		netdev_warn(netdev, "Disabling ntuple, not supported in switchdev mode\n");
4129 
4130 	features &= ~NETIF_F_GRO_HW;
4131 	if (netdev->features & NETIF_F_GRO_HW)
4132 		netdev_warn(netdev, "Disabling HW_GRO, not supported in switchdev mode\n");
4133 
4134 	features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4135 	if (netdev->features & NETIF_F_HW_VLAN_CTAG_FILTER)
4136 		netdev_warn(netdev, "Disabling HW_VLAN CTAG FILTERING, not supported in switchdev mode\n");
4137 
4138 	return features;
4139 }
4140 
mlx5e_fix_features(struct net_device * netdev,netdev_features_t features)4141 static netdev_features_t mlx5e_fix_features(struct net_device *netdev,
4142 					    netdev_features_t features)
4143 {
4144 	struct mlx5e_priv *priv = netdev_priv(netdev);
4145 	struct mlx5e_vlan_table *vlan;
4146 	struct mlx5e_params *params;
4147 
4148 	if (!netif_device_present(netdev))
4149 		return features;
4150 
4151 	vlan = mlx5e_fs_get_vlan(priv->fs);
4152 	mutex_lock(&priv->state_lock);
4153 	params = &priv->channels.params;
4154 	if (!vlan ||
4155 	    !bitmap_empty(mlx5e_vlan_get_active_svlans(vlan), VLAN_N_VID)) {
4156 		/* HW strips the outer C-tag header, this is a problem
4157 		 * for S-tag traffic.
4158 		 */
4159 		features &= ~NETIF_F_HW_VLAN_CTAG_RX;
4160 		if (!params->vlan_strip_disable)
4161 			netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
4162 	}
4163 
4164 	if (!MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
4165 		if (features & NETIF_F_LRO) {
4166 			netdev_warn(netdev, "Disabling LRO, not supported in legacy RQ\n");
4167 			features &= ~NETIF_F_LRO;
4168 		}
4169 		if (features & NETIF_F_GRO_HW) {
4170 			netdev_warn(netdev, "Disabling HW-GRO, not supported in legacy RQ\n");
4171 			features &= ~NETIF_F_GRO_HW;
4172 		}
4173 	}
4174 
4175 	if (params->xdp_prog) {
4176 		if (features & NETIF_F_LRO) {
4177 			netdev_warn(netdev, "LRO is incompatible with XDP\n");
4178 			features &= ~NETIF_F_LRO;
4179 		}
4180 		if (features & NETIF_F_GRO_HW) {
4181 			netdev_warn(netdev, "HW GRO is incompatible with XDP\n");
4182 			features &= ~NETIF_F_GRO_HW;
4183 		}
4184 	}
4185 
4186 	if (priv->xsk.refcnt) {
4187 		if (features & NETIF_F_LRO) {
4188 			netdev_warn(netdev, "LRO is incompatible with AF_XDP (%u XSKs are active)\n",
4189 				    priv->xsk.refcnt);
4190 			features &= ~NETIF_F_LRO;
4191 		}
4192 		if (features & NETIF_F_GRO_HW) {
4193 			netdev_warn(netdev, "HW GRO is incompatible with AF_XDP (%u XSKs are active)\n",
4194 				    priv->xsk.refcnt);
4195 			features &= ~NETIF_F_GRO_HW;
4196 		}
4197 	}
4198 
4199 	if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
4200 		features &= ~NETIF_F_RXHASH;
4201 		if (netdev->features & NETIF_F_RXHASH)
4202 			netdev_warn(netdev, "Disabling rxhash, not supported when CQE compress is active\n");
4203 
4204 		if (features & NETIF_F_GRO_HW) {
4205 			netdev_warn(netdev, "Disabling HW-GRO, not supported when CQE compress is active\n");
4206 			features &= ~NETIF_F_GRO_HW;
4207 		}
4208 	}
4209 
4210 	if (mlx5e_is_uplink_rep(priv)) {
4211 		features = mlx5e_fix_uplink_rep_features(netdev, features);
4212 		features |= NETIF_F_NETNS_LOCAL;
4213 	} else {
4214 		features &= ~NETIF_F_NETNS_LOCAL;
4215 	}
4216 
4217 	mutex_unlock(&priv->state_lock);
4218 
4219 	return features;
4220 }
4221 
mlx5e_xsk_validate_mtu(struct net_device * netdev,struct mlx5e_channels * chs,struct mlx5e_params * new_params,struct mlx5_core_dev * mdev)4222 static bool mlx5e_xsk_validate_mtu(struct net_device *netdev,
4223 				   struct mlx5e_channels *chs,
4224 				   struct mlx5e_params *new_params,
4225 				   struct mlx5_core_dev *mdev)
4226 {
4227 	u16 ix;
4228 
4229 	for (ix = 0; ix < chs->params.num_channels; ix++) {
4230 		struct xsk_buff_pool *xsk_pool =
4231 			mlx5e_xsk_get_pool(&chs->params, chs->params.xsk, ix);
4232 		struct mlx5e_xsk_param xsk;
4233 		int max_xdp_mtu;
4234 
4235 		if (!xsk_pool)
4236 			continue;
4237 
4238 		mlx5e_build_xsk_param(xsk_pool, &xsk);
4239 		max_xdp_mtu = mlx5e_xdp_max_mtu(new_params, &xsk);
4240 
4241 		/* Validate XSK params and XDP MTU in advance */
4242 		if (!mlx5e_validate_xsk_param(new_params, &xsk, mdev) ||
4243 		    new_params->sw_mtu > max_xdp_mtu) {
4244 			u32 hr = mlx5e_get_linear_rq_headroom(new_params, &xsk);
4245 			int max_mtu_frame, max_mtu_page, max_mtu;
4246 
4247 			/* Two criteria must be met:
4248 			 * 1. HW MTU + all headrooms <= XSK frame size.
4249 			 * 2. Size of SKBs allocated on XDP_PASS <= PAGE_SIZE.
4250 			 */
4251 			max_mtu_frame = MLX5E_HW2SW_MTU(new_params, xsk.chunk_size - hr);
4252 			max_mtu_page = MLX5E_HW2SW_MTU(new_params, SKB_MAX_HEAD(0));
4253 			max_mtu = min3(max_mtu_frame, max_mtu_page, max_xdp_mtu);
4254 
4255 			netdev_err(netdev, "MTU %d is too big for an XSK running on channel %u or its redirection XDP program. Try MTU <= %d\n",
4256 				   new_params->sw_mtu, ix, max_mtu);
4257 			return false;
4258 		}
4259 	}
4260 
4261 	return true;
4262 }
4263 
mlx5e_params_validate_xdp(struct net_device * netdev,struct mlx5_core_dev * mdev,struct mlx5e_params * params)4264 static bool mlx5e_params_validate_xdp(struct net_device *netdev,
4265 				      struct mlx5_core_dev *mdev,
4266 				      struct mlx5e_params *params)
4267 {
4268 	bool is_linear;
4269 
4270 	/* No XSK params: AF_XDP can't be enabled yet at the point of setting
4271 	 * the XDP program.
4272 	 */
4273 	is_linear = params->rq_wq_type == MLX5_WQ_TYPE_CYCLIC ?
4274 		mlx5e_rx_is_linear_skb(mdev, params, NULL) :
4275 		mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL);
4276 
4277 	if (!is_linear) {
4278 		if (!params->xdp_prog->aux->xdp_has_frags) {
4279 			netdev_warn(netdev, "MTU(%d) > %d, too big for an XDP program not aware of multi buffer\n",
4280 				    params->sw_mtu,
4281 				    mlx5e_xdp_max_mtu(params, NULL));
4282 			return false;
4283 		}
4284 		if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ &&
4285 		    !mlx5e_verify_params_rx_mpwqe_strides(mdev, params, NULL)) {
4286 			netdev_warn(netdev, "XDP is not allowed with striding RQ and MTU(%d) > %d\n",
4287 				    params->sw_mtu,
4288 				    mlx5e_xdp_max_mtu(params, NULL));
4289 			return false;
4290 		}
4291 	}
4292 
4293 	return true;
4294 }
4295 
mlx5e_change_mtu(struct net_device * netdev,int new_mtu,mlx5e_fp_preactivate preactivate)4296 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
4297 		     mlx5e_fp_preactivate preactivate)
4298 {
4299 	struct mlx5e_priv *priv = netdev_priv(netdev);
4300 	struct mlx5e_params new_params;
4301 	struct mlx5e_params *params;
4302 	bool reset = true;
4303 	int err = 0;
4304 
4305 	mutex_lock(&priv->state_lock);
4306 
4307 	params = &priv->channels.params;
4308 
4309 	new_params = *params;
4310 	new_params.sw_mtu = new_mtu;
4311 	err = mlx5e_validate_params(priv->mdev, &new_params);
4312 	if (err)
4313 		goto out;
4314 
4315 	if (new_params.xdp_prog && !mlx5e_params_validate_xdp(netdev, priv->mdev,
4316 							      &new_params)) {
4317 		err = -EINVAL;
4318 		goto out;
4319 	}
4320 
4321 	if (priv->xsk.refcnt &&
4322 	    !mlx5e_xsk_validate_mtu(netdev, &priv->channels,
4323 				    &new_params, priv->mdev)) {
4324 		err = -EINVAL;
4325 		goto out;
4326 	}
4327 
4328 	if (params->packet_merge.type == MLX5E_PACKET_MERGE_LRO)
4329 		reset = false;
4330 
4331 	if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ &&
4332 	    params->packet_merge.type != MLX5E_PACKET_MERGE_SHAMPO) {
4333 		bool is_linear_old = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev, params, NULL);
4334 		bool is_linear_new = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev,
4335 								  &new_params, NULL);
4336 		u8 sz_old = mlx5e_mpwqe_get_log_rq_size(priv->mdev, params, NULL);
4337 		u8 sz_new = mlx5e_mpwqe_get_log_rq_size(priv->mdev, &new_params, NULL);
4338 
4339 		/* Always reset in linear mode - hw_mtu is used in data path.
4340 		 * Check that the mode was non-linear and didn't change.
4341 		 * If XSK is active, XSK RQs are linear.
4342 		 * Reset if the RQ size changed, even if it's non-linear.
4343 		 */
4344 		if (!is_linear_old && !is_linear_new && !priv->xsk.refcnt &&
4345 		    sz_old == sz_new)
4346 			reset = false;
4347 	}
4348 
4349 	err = mlx5e_safe_switch_params(priv, &new_params, preactivate, NULL, reset);
4350 
4351 out:
4352 	netdev->mtu = params->sw_mtu;
4353 	mutex_unlock(&priv->state_lock);
4354 	return err;
4355 }
4356 
mlx5e_change_nic_mtu(struct net_device * netdev,int new_mtu)4357 static int mlx5e_change_nic_mtu(struct net_device *netdev, int new_mtu)
4358 {
4359 	return mlx5e_change_mtu(netdev, new_mtu, mlx5e_set_dev_port_mtu_ctx);
4360 }
4361 
mlx5e_ptp_rx_manage_fs_ctx(struct mlx5e_priv * priv,void * ctx)4362 int mlx5e_ptp_rx_manage_fs_ctx(struct mlx5e_priv *priv, void *ctx)
4363 {
4364 	bool set  = *(bool *)ctx;
4365 
4366 	return mlx5e_ptp_rx_manage_fs(priv, set);
4367 }
4368 
mlx5e_hwstamp_config_no_ptp_rx(struct mlx5e_priv * priv,bool rx_filter)4369 static int mlx5e_hwstamp_config_no_ptp_rx(struct mlx5e_priv *priv, bool rx_filter)
4370 {
4371 	bool rx_cqe_compress_def = priv->channels.params.rx_cqe_compress_def;
4372 	int err;
4373 
4374 	if (!rx_filter)
4375 		/* Reset CQE compression to Admin default */
4376 		return mlx5e_modify_rx_cqe_compression_locked(priv, rx_cqe_compress_def, false);
4377 
4378 	if (!MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS))
4379 		return 0;
4380 
4381 	/* Disable CQE compression */
4382 	netdev_warn(priv->netdev, "Disabling RX cqe compression\n");
4383 	err = mlx5e_modify_rx_cqe_compression_locked(priv, false, true);
4384 	if (err)
4385 		netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
4386 
4387 	return err;
4388 }
4389 
mlx5e_hwstamp_config_ptp_rx(struct mlx5e_priv * priv,bool ptp_rx)4390 static int mlx5e_hwstamp_config_ptp_rx(struct mlx5e_priv *priv, bool ptp_rx)
4391 {
4392 	struct mlx5e_params new_params;
4393 
4394 	if (ptp_rx == priv->channels.params.ptp_rx)
4395 		return 0;
4396 
4397 	new_params = priv->channels.params;
4398 	new_params.ptp_rx = ptp_rx;
4399 	return mlx5e_safe_switch_params(priv, &new_params, mlx5e_ptp_rx_manage_fs_ctx,
4400 					&new_params.ptp_rx, true);
4401 }
4402 
mlx5e_hwstamp_set(struct mlx5e_priv * priv,struct ifreq * ifr)4403 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
4404 {
4405 	struct hwtstamp_config config;
4406 	bool rx_cqe_compress_def;
4407 	bool ptp_rx;
4408 	int err;
4409 
4410 	if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
4411 	    (mlx5_clock_get_ptp_index(priv->mdev) == -1))
4412 		return -EOPNOTSUPP;
4413 
4414 	if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
4415 		return -EFAULT;
4416 
4417 	/* TX HW timestamp */
4418 	switch (config.tx_type) {
4419 	case HWTSTAMP_TX_OFF:
4420 	case HWTSTAMP_TX_ON:
4421 		break;
4422 	default:
4423 		return -ERANGE;
4424 	}
4425 
4426 	mutex_lock(&priv->state_lock);
4427 	rx_cqe_compress_def = priv->channels.params.rx_cqe_compress_def;
4428 
4429 	/* RX HW timestamp */
4430 	switch (config.rx_filter) {
4431 	case HWTSTAMP_FILTER_NONE:
4432 		ptp_rx = false;
4433 		break;
4434 	case HWTSTAMP_FILTER_ALL:
4435 	case HWTSTAMP_FILTER_SOME:
4436 	case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
4437 	case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
4438 	case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
4439 	case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
4440 	case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
4441 	case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
4442 	case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
4443 	case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
4444 	case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
4445 	case HWTSTAMP_FILTER_PTP_V2_EVENT:
4446 	case HWTSTAMP_FILTER_PTP_V2_SYNC:
4447 	case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
4448 	case HWTSTAMP_FILTER_NTP_ALL:
4449 		config.rx_filter = HWTSTAMP_FILTER_ALL;
4450 		/* ptp_rx is set if both HW TS is set and CQE
4451 		 * compression is set
4452 		 */
4453 		ptp_rx = rx_cqe_compress_def;
4454 		break;
4455 	default:
4456 		err = -ERANGE;
4457 		goto err_unlock;
4458 	}
4459 
4460 	if (!mlx5e_profile_feature_cap(priv->profile, PTP_RX))
4461 		err = mlx5e_hwstamp_config_no_ptp_rx(priv,
4462 						     config.rx_filter != HWTSTAMP_FILTER_NONE);
4463 	else
4464 		err = mlx5e_hwstamp_config_ptp_rx(priv, ptp_rx);
4465 	if (err)
4466 		goto err_unlock;
4467 
4468 	memcpy(&priv->tstamp, &config, sizeof(config));
4469 	mutex_unlock(&priv->state_lock);
4470 
4471 	/* might need to fix some features */
4472 	netdev_update_features(priv->netdev);
4473 
4474 	return copy_to_user(ifr->ifr_data, &config,
4475 			    sizeof(config)) ? -EFAULT : 0;
4476 err_unlock:
4477 	mutex_unlock(&priv->state_lock);
4478 	return err;
4479 }
4480 
mlx5e_hwstamp_get(struct mlx5e_priv * priv,struct ifreq * ifr)4481 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
4482 {
4483 	struct hwtstamp_config *cfg = &priv->tstamp;
4484 
4485 	if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
4486 		return -EOPNOTSUPP;
4487 
4488 	return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
4489 }
4490 
mlx5e_ioctl(struct net_device * dev,struct ifreq * ifr,int cmd)4491 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4492 {
4493 	struct mlx5e_priv *priv = netdev_priv(dev);
4494 
4495 	switch (cmd) {
4496 	case SIOCSHWTSTAMP:
4497 		return mlx5e_hwstamp_set(priv, ifr);
4498 	case SIOCGHWTSTAMP:
4499 		return mlx5e_hwstamp_get(priv, ifr);
4500 	default:
4501 		return -EOPNOTSUPP;
4502 	}
4503 }
4504 
4505 #ifdef CONFIG_MLX5_ESWITCH
mlx5e_set_vf_mac(struct net_device * dev,int vf,u8 * mac)4506 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
4507 {
4508 	struct mlx5e_priv *priv = netdev_priv(dev);
4509 	struct mlx5_core_dev *mdev = priv->mdev;
4510 
4511 	return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
4512 }
4513 
mlx5e_set_vf_vlan(struct net_device * dev,int vf,u16 vlan,u8 qos,__be16 vlan_proto)4514 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
4515 			     __be16 vlan_proto)
4516 {
4517 	struct mlx5e_priv *priv = netdev_priv(dev);
4518 	struct mlx5_core_dev *mdev = priv->mdev;
4519 
4520 	if (vlan_proto != htons(ETH_P_8021Q))
4521 		return -EPROTONOSUPPORT;
4522 
4523 	return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
4524 					   vlan, qos);
4525 }
4526 
mlx5e_set_vf_spoofchk(struct net_device * dev,int vf,bool setting)4527 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
4528 {
4529 	struct mlx5e_priv *priv = netdev_priv(dev);
4530 	struct mlx5_core_dev *mdev = priv->mdev;
4531 
4532 	return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
4533 }
4534 
mlx5e_set_vf_trust(struct net_device * dev,int vf,bool setting)4535 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
4536 {
4537 	struct mlx5e_priv *priv = netdev_priv(dev);
4538 	struct mlx5_core_dev *mdev = priv->mdev;
4539 
4540 	return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
4541 }
4542 
mlx5e_set_vf_rate(struct net_device * dev,int vf,int min_tx_rate,int max_tx_rate)4543 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
4544 		      int max_tx_rate)
4545 {
4546 	struct mlx5e_priv *priv = netdev_priv(dev);
4547 	struct mlx5_core_dev *mdev = priv->mdev;
4548 
4549 	return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
4550 					   max_tx_rate, min_tx_rate);
4551 }
4552 
mlx5_vport_link2ifla(u8 esw_link)4553 static int mlx5_vport_link2ifla(u8 esw_link)
4554 {
4555 	switch (esw_link) {
4556 	case MLX5_VPORT_ADMIN_STATE_DOWN:
4557 		return IFLA_VF_LINK_STATE_DISABLE;
4558 	case MLX5_VPORT_ADMIN_STATE_UP:
4559 		return IFLA_VF_LINK_STATE_ENABLE;
4560 	}
4561 	return IFLA_VF_LINK_STATE_AUTO;
4562 }
4563 
mlx5_ifla_link2vport(u8 ifla_link)4564 static int mlx5_ifla_link2vport(u8 ifla_link)
4565 {
4566 	switch (ifla_link) {
4567 	case IFLA_VF_LINK_STATE_DISABLE:
4568 		return MLX5_VPORT_ADMIN_STATE_DOWN;
4569 	case IFLA_VF_LINK_STATE_ENABLE:
4570 		return MLX5_VPORT_ADMIN_STATE_UP;
4571 	}
4572 	return MLX5_VPORT_ADMIN_STATE_AUTO;
4573 }
4574 
mlx5e_set_vf_link_state(struct net_device * dev,int vf,int link_state)4575 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
4576 				   int link_state)
4577 {
4578 	struct mlx5e_priv *priv = netdev_priv(dev);
4579 	struct mlx5_core_dev *mdev = priv->mdev;
4580 
4581 	if (mlx5e_is_uplink_rep(priv))
4582 		return -EOPNOTSUPP;
4583 
4584 	return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
4585 					    mlx5_ifla_link2vport(link_state));
4586 }
4587 
mlx5e_get_vf_config(struct net_device * dev,int vf,struct ifla_vf_info * ivi)4588 int mlx5e_get_vf_config(struct net_device *dev,
4589 			int vf, struct ifla_vf_info *ivi)
4590 {
4591 	struct mlx5e_priv *priv = netdev_priv(dev);
4592 	struct mlx5_core_dev *mdev = priv->mdev;
4593 	int err;
4594 
4595 	if (!netif_device_present(dev))
4596 		return -EOPNOTSUPP;
4597 
4598 	err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
4599 	if (err)
4600 		return err;
4601 	ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
4602 	return 0;
4603 }
4604 
mlx5e_get_vf_stats(struct net_device * dev,int vf,struct ifla_vf_stats * vf_stats)4605 int mlx5e_get_vf_stats(struct net_device *dev,
4606 		       int vf, struct ifla_vf_stats *vf_stats)
4607 {
4608 	struct mlx5e_priv *priv = netdev_priv(dev);
4609 	struct mlx5_core_dev *mdev = priv->mdev;
4610 
4611 	return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
4612 					    vf_stats);
4613 }
4614 
4615 static bool
mlx5e_has_offload_stats(const struct net_device * dev,int attr_id)4616 mlx5e_has_offload_stats(const struct net_device *dev, int attr_id)
4617 {
4618 	struct mlx5e_priv *priv = netdev_priv(dev);
4619 
4620 	if (!netif_device_present(dev))
4621 		return false;
4622 
4623 	if (!mlx5e_is_uplink_rep(priv))
4624 		return false;
4625 
4626 	return mlx5e_rep_has_offload_stats(dev, attr_id);
4627 }
4628 
4629 static int
mlx5e_get_offload_stats(int attr_id,const struct net_device * dev,void * sp)4630 mlx5e_get_offload_stats(int attr_id, const struct net_device *dev,
4631 			void *sp)
4632 {
4633 	struct mlx5e_priv *priv = netdev_priv(dev);
4634 
4635 	if (!mlx5e_is_uplink_rep(priv))
4636 		return -EOPNOTSUPP;
4637 
4638 	return mlx5e_rep_get_offload_stats(attr_id, dev, sp);
4639 }
4640 #endif
4641 
mlx5e_tunnel_proto_supported_tx(struct mlx5_core_dev * mdev,u8 proto_type)4642 static bool mlx5e_tunnel_proto_supported_tx(struct mlx5_core_dev *mdev, u8 proto_type)
4643 {
4644 	switch (proto_type) {
4645 	case IPPROTO_GRE:
4646 		return MLX5_CAP_ETH(mdev, tunnel_stateless_gre);
4647 	case IPPROTO_IPIP:
4648 	case IPPROTO_IPV6:
4649 		return (MLX5_CAP_ETH(mdev, tunnel_stateless_ip_over_ip) ||
4650 			MLX5_CAP_ETH(mdev, tunnel_stateless_ip_over_ip_tx));
4651 	default:
4652 		return false;
4653 	}
4654 }
4655 
mlx5e_gre_tunnel_inner_proto_offload_supported(struct mlx5_core_dev * mdev,struct sk_buff * skb)4656 static bool mlx5e_gre_tunnel_inner_proto_offload_supported(struct mlx5_core_dev *mdev,
4657 							   struct sk_buff *skb)
4658 {
4659 	switch (skb->inner_protocol) {
4660 	case htons(ETH_P_IP):
4661 	case htons(ETH_P_IPV6):
4662 	case htons(ETH_P_TEB):
4663 		return true;
4664 	case htons(ETH_P_MPLS_UC):
4665 	case htons(ETH_P_MPLS_MC):
4666 		return MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre);
4667 	}
4668 	return false;
4669 }
4670 
mlx5e_tunnel_features_check(struct mlx5e_priv * priv,struct sk_buff * skb,netdev_features_t features)4671 static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
4672 						     struct sk_buff *skb,
4673 						     netdev_features_t features)
4674 {
4675 	unsigned int offset = 0;
4676 	struct udphdr *udph;
4677 	u8 proto;
4678 	u16 port;
4679 
4680 	switch (vlan_get_protocol(skb)) {
4681 	case htons(ETH_P_IP):
4682 		proto = ip_hdr(skb)->protocol;
4683 		break;
4684 	case htons(ETH_P_IPV6):
4685 		proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);
4686 		break;
4687 	default:
4688 		goto out;
4689 	}
4690 
4691 	switch (proto) {
4692 	case IPPROTO_GRE:
4693 		if (mlx5e_gre_tunnel_inner_proto_offload_supported(priv->mdev, skb))
4694 			return features;
4695 		break;
4696 	case IPPROTO_IPIP:
4697 	case IPPROTO_IPV6:
4698 		if (mlx5e_tunnel_proto_supported_tx(priv->mdev, IPPROTO_IPIP))
4699 			return features;
4700 		break;
4701 	case IPPROTO_UDP:
4702 		udph = udp_hdr(skb);
4703 		port = be16_to_cpu(udph->dest);
4704 
4705 		/* Verify if UDP port is being offloaded by HW */
4706 		if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, port))
4707 			return features;
4708 
4709 #if IS_ENABLED(CONFIG_GENEVE)
4710 		/* Support Geneve offload for default UDP port */
4711 		if (port == GENEVE_UDP_PORT && mlx5_geneve_tx_allowed(priv->mdev))
4712 			return features;
4713 #endif
4714 		break;
4715 #ifdef CONFIG_MLX5_EN_IPSEC
4716 	case IPPROTO_ESP:
4717 		return mlx5e_ipsec_feature_check(skb, features);
4718 #endif
4719 	}
4720 
4721 out:
4722 	/* Disable CSUM and GSO if the udp dport is not offloaded by HW */
4723 	return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
4724 }
4725 
mlx5e_features_check(struct sk_buff * skb,struct net_device * netdev,netdev_features_t features)4726 netdev_features_t mlx5e_features_check(struct sk_buff *skb,
4727 				       struct net_device *netdev,
4728 				       netdev_features_t features)
4729 {
4730 	struct mlx5e_priv *priv = netdev_priv(netdev);
4731 
4732 	features = vlan_features_check(skb, features);
4733 	features = vxlan_features_check(skb, features);
4734 
4735 	/* Validate if the tunneled packet is being offloaded by HW */
4736 	if (skb->encapsulation &&
4737 	    (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
4738 		return mlx5e_tunnel_features_check(priv, skb, features);
4739 
4740 	return features;
4741 }
4742 
mlx5e_tx_timeout_work(struct work_struct * work)4743 static void mlx5e_tx_timeout_work(struct work_struct *work)
4744 {
4745 	struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
4746 					       tx_timeout_work);
4747 	struct net_device *netdev = priv->netdev;
4748 	int i;
4749 
4750 	/* Take rtnl_lock to ensure no change in netdev->real_num_tx_queues
4751 	 * through this flow. However, channel closing flows have to wait for
4752 	 * this work to finish while holding rtnl lock too. So either get the
4753 	 * lock or find that channels are being closed for other reason and
4754 	 * this work is not relevant anymore.
4755 	 */
4756 	while (!rtnl_trylock()) {
4757 		if (!test_bit(MLX5E_STATE_CHANNELS_ACTIVE, &priv->state))
4758 			return;
4759 		msleep(20);
4760 	}
4761 
4762 	if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
4763 		goto unlock;
4764 
4765 	for (i = 0; i < netdev->real_num_tx_queues; i++) {
4766 		struct netdev_queue *dev_queue =
4767 			netdev_get_tx_queue(netdev, i);
4768 		struct mlx5e_txqsq *sq = priv->txq2sq[i];
4769 
4770 		if (!netif_xmit_stopped(dev_queue))
4771 			continue;
4772 
4773 		if (mlx5e_reporter_tx_timeout(sq))
4774 		/* break if tried to reopened channels */
4775 			break;
4776 	}
4777 
4778 unlock:
4779 	rtnl_unlock();
4780 }
4781 
mlx5e_tx_timeout(struct net_device * dev,unsigned int txqueue)4782 static void mlx5e_tx_timeout(struct net_device *dev, unsigned int txqueue)
4783 {
4784 	struct mlx5e_priv *priv = netdev_priv(dev);
4785 
4786 	netdev_err(dev, "TX timeout detected\n");
4787 	queue_work(priv->wq, &priv->tx_timeout_work);
4788 }
4789 
mlx5e_xdp_allowed(struct net_device * netdev,struct mlx5_core_dev * mdev,struct mlx5e_params * params)4790 static int mlx5e_xdp_allowed(struct net_device *netdev, struct mlx5_core_dev *mdev,
4791 			     struct mlx5e_params *params)
4792 {
4793 	if (params->packet_merge.type != MLX5E_PACKET_MERGE_NONE) {
4794 		netdev_warn(netdev, "can't set XDP while HW-GRO/LRO is on, disable them first\n");
4795 		return -EINVAL;
4796 	}
4797 
4798 	if (!mlx5e_params_validate_xdp(netdev, mdev, params))
4799 		return -EINVAL;
4800 
4801 	return 0;
4802 }
4803 
mlx5e_rq_replace_xdp_prog(struct mlx5e_rq * rq,struct bpf_prog * prog)4804 static void mlx5e_rq_replace_xdp_prog(struct mlx5e_rq *rq, struct bpf_prog *prog)
4805 {
4806 	struct bpf_prog *old_prog;
4807 
4808 	old_prog = rcu_replace_pointer(rq->xdp_prog, prog,
4809 				       lockdep_is_held(&rq->priv->state_lock));
4810 	if (old_prog)
4811 		bpf_prog_put(old_prog);
4812 }
4813 
mlx5e_xdp_set(struct net_device * netdev,struct bpf_prog * prog)4814 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
4815 {
4816 	struct mlx5e_priv *priv = netdev_priv(netdev);
4817 	struct mlx5e_params new_params;
4818 	struct bpf_prog *old_prog;
4819 	int err = 0;
4820 	bool reset;
4821 	int i;
4822 
4823 	mutex_lock(&priv->state_lock);
4824 
4825 	new_params = priv->channels.params;
4826 	new_params.xdp_prog = prog;
4827 
4828 	if (prog) {
4829 		err = mlx5e_xdp_allowed(netdev, priv->mdev, &new_params);
4830 		if (err)
4831 			goto unlock;
4832 	}
4833 
4834 	/* no need for full reset when exchanging programs */
4835 	reset = (!priv->channels.params.xdp_prog || !prog);
4836 
4837 	old_prog = priv->channels.params.xdp_prog;
4838 
4839 	err = mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, reset);
4840 	if (err)
4841 		goto unlock;
4842 
4843 	if (old_prog)
4844 		bpf_prog_put(old_prog);
4845 
4846 	if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
4847 		goto unlock;
4848 
4849 	/* exchanging programs w/o reset, we update ref counts on behalf
4850 	 * of the channels RQs here.
4851 	 */
4852 	bpf_prog_add(prog, priv->channels.num);
4853 	for (i = 0; i < priv->channels.num; i++) {
4854 		struct mlx5e_channel *c = priv->channels.c[i];
4855 
4856 		mlx5e_rq_replace_xdp_prog(&c->rq, prog);
4857 		if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state)) {
4858 			bpf_prog_inc(prog);
4859 			mlx5e_rq_replace_xdp_prog(&c->xskrq, prog);
4860 		}
4861 	}
4862 
4863 unlock:
4864 	mutex_unlock(&priv->state_lock);
4865 
4866 	/* Need to fix some features. */
4867 	if (!err)
4868 		netdev_update_features(netdev);
4869 
4870 	return err;
4871 }
4872 
mlx5e_xdp(struct net_device * dev,struct netdev_bpf * xdp)4873 static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp)
4874 {
4875 	switch (xdp->command) {
4876 	case XDP_SETUP_PROG:
4877 		return mlx5e_xdp_set(dev, xdp->prog);
4878 	case XDP_SETUP_XSK_POOL:
4879 		return mlx5e_xsk_setup_pool(dev, xdp->xsk.pool,
4880 					    xdp->xsk.queue_id);
4881 	default:
4882 		return -EINVAL;
4883 	}
4884 }
4885 
4886 #ifdef CONFIG_MLX5_ESWITCH
mlx5e_bridge_getlink(struct sk_buff * skb,u32 pid,u32 seq,struct net_device * dev,u32 filter_mask,int nlflags)4887 static int mlx5e_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
4888 				struct net_device *dev, u32 filter_mask,
4889 				int nlflags)
4890 {
4891 	struct mlx5e_priv *priv = netdev_priv(dev);
4892 	struct mlx5_core_dev *mdev = priv->mdev;
4893 	u8 mode, setting;
4894 	int err;
4895 
4896 	err = mlx5_eswitch_get_vepa(mdev->priv.eswitch, &setting);
4897 	if (err)
4898 		return err;
4899 	mode = setting ? BRIDGE_MODE_VEPA : BRIDGE_MODE_VEB;
4900 	return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
4901 				       mode,
4902 				       0, 0, nlflags, filter_mask, NULL);
4903 }
4904 
mlx5e_bridge_setlink(struct net_device * dev,struct nlmsghdr * nlh,u16 flags,struct netlink_ext_ack * extack)4905 static int mlx5e_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
4906 				u16 flags, struct netlink_ext_ack *extack)
4907 {
4908 	struct mlx5e_priv *priv = netdev_priv(dev);
4909 	struct mlx5_core_dev *mdev = priv->mdev;
4910 	struct nlattr *attr, *br_spec;
4911 	u16 mode = BRIDGE_MODE_UNDEF;
4912 	u8 setting;
4913 	int rem;
4914 
4915 	br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
4916 	if (!br_spec)
4917 		return -EINVAL;
4918 
4919 	nla_for_each_nested(attr, br_spec, rem) {
4920 		if (nla_type(attr) != IFLA_BRIDGE_MODE)
4921 			continue;
4922 
4923 		mode = nla_get_u16(attr);
4924 		if (mode > BRIDGE_MODE_VEPA)
4925 			return -EINVAL;
4926 
4927 		break;
4928 	}
4929 
4930 	if (mode == BRIDGE_MODE_UNDEF)
4931 		return -EINVAL;
4932 
4933 	setting = (mode == BRIDGE_MODE_VEPA) ?  1 : 0;
4934 	return mlx5_eswitch_set_vepa(mdev->priv.eswitch, setting);
4935 }
4936 #endif
4937 
4938 const struct net_device_ops mlx5e_netdev_ops = {
4939 	.ndo_open                = mlx5e_open,
4940 	.ndo_stop                = mlx5e_close,
4941 	.ndo_start_xmit          = mlx5e_xmit,
4942 	.ndo_setup_tc            = mlx5e_setup_tc,
4943 	.ndo_select_queue        = mlx5e_select_queue,
4944 	.ndo_get_stats64         = mlx5e_get_stats,
4945 	.ndo_set_rx_mode         = mlx5e_set_rx_mode,
4946 	.ndo_set_mac_address     = mlx5e_set_mac,
4947 	.ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
4948 	.ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
4949 	.ndo_set_features        = mlx5e_set_features,
4950 	.ndo_fix_features        = mlx5e_fix_features,
4951 	.ndo_change_mtu          = mlx5e_change_nic_mtu,
4952 	.ndo_eth_ioctl            = mlx5e_ioctl,
4953 	.ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
4954 	.ndo_features_check      = mlx5e_features_check,
4955 	.ndo_tx_timeout          = mlx5e_tx_timeout,
4956 	.ndo_bpf		 = mlx5e_xdp,
4957 	.ndo_xdp_xmit            = mlx5e_xdp_xmit,
4958 	.ndo_xsk_wakeup          = mlx5e_xsk_wakeup,
4959 #ifdef CONFIG_MLX5_EN_ARFS
4960 	.ndo_rx_flow_steer	 = mlx5e_rx_flow_steer,
4961 #endif
4962 #ifdef CONFIG_MLX5_ESWITCH
4963 	.ndo_bridge_setlink      = mlx5e_bridge_setlink,
4964 	.ndo_bridge_getlink      = mlx5e_bridge_getlink,
4965 
4966 	/* SRIOV E-Switch NDOs */
4967 	.ndo_set_vf_mac          = mlx5e_set_vf_mac,
4968 	.ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
4969 	.ndo_set_vf_spoofchk     = mlx5e_set_vf_spoofchk,
4970 	.ndo_set_vf_trust        = mlx5e_set_vf_trust,
4971 	.ndo_set_vf_rate         = mlx5e_set_vf_rate,
4972 	.ndo_get_vf_config       = mlx5e_get_vf_config,
4973 	.ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
4974 	.ndo_get_vf_stats        = mlx5e_get_vf_stats,
4975 	.ndo_has_offload_stats   = mlx5e_has_offload_stats,
4976 	.ndo_get_offload_stats   = mlx5e_get_offload_stats,
4977 #endif
4978 };
4979 
mlx5e_choose_lro_timeout(struct mlx5_core_dev * mdev,u32 wanted_timeout)4980 static u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
4981 {
4982 	int i;
4983 
4984 	/* The supported periods are organized in ascending order */
4985 	for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
4986 		if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
4987 			break;
4988 
4989 	return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
4990 }
4991 
mlx5e_build_nic_params(struct mlx5e_priv * priv,struct mlx5e_xsk * xsk,u16 mtu)4992 void mlx5e_build_nic_params(struct mlx5e_priv *priv, struct mlx5e_xsk *xsk, u16 mtu)
4993 {
4994 	struct mlx5e_params *params = &priv->channels.params;
4995 	struct mlx5_core_dev *mdev = priv->mdev;
4996 	u8 rx_cq_period_mode;
4997 
4998 	params->sw_mtu = mtu;
4999 	params->hard_mtu = MLX5E_ETH_HARD_MTU;
5000 	params->num_channels = min_t(unsigned int, MLX5E_MAX_NUM_CHANNELS / 2,
5001 				     priv->max_nch);
5002 	mlx5e_params_mqprio_reset(params);
5003 
5004 	/* SQ */
5005 	params->log_sq_size = is_kdump_kernel() ?
5006 		MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
5007 		MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
5008 	MLX5E_SET_PFLAG(params, MLX5E_PFLAG_SKB_TX_MPWQE, mlx5e_tx_mpwqe_supported(mdev));
5009 
5010 	/* XDP SQ */
5011 	MLX5E_SET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE, mlx5e_tx_mpwqe_supported(mdev));
5012 
5013 	/* set CQE compression */
5014 	params->rx_cqe_compress_def = false;
5015 	if (MLX5_CAP_GEN(mdev, cqe_compression) &&
5016 	    MLX5_CAP_GEN(mdev, vport_group_manager))
5017 		params->rx_cqe_compress_def = slow_pci_heuristic(mdev);
5018 
5019 	MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
5020 	MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE, false);
5021 
5022 	/* RQ */
5023 	mlx5e_build_rq_params(mdev, params);
5024 
5025 	params->terminate_lkey_be = mlx5_core_get_terminate_scatter_list_mkey(mdev);
5026 
5027 	params->packet_merge.timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
5028 
5029 	/* CQ moderation params */
5030 	rx_cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
5031 			MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
5032 			MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
5033 	params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
5034 	params->tx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
5035 	mlx5e_set_rx_cq_mode_params(params, rx_cq_period_mode);
5036 	mlx5e_set_tx_cq_mode_params(params, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
5037 
5038 	/* TX inline */
5039 	mlx5_query_min_inline(mdev, &params->tx_min_inline_mode);
5040 
5041 	/* AF_XDP */
5042 	params->xsk = xsk;
5043 
5044 	/* Do not update netdev->features directly in here
5045 	 * on mlx5e_attach_netdev() we will call mlx5e_update_features()
5046 	 * To update netdev->features please modify mlx5e_fix_features()
5047 	 */
5048 }
5049 
mlx5e_set_netdev_dev_addr(struct net_device * netdev)5050 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
5051 {
5052 	struct mlx5e_priv *priv = netdev_priv(netdev);
5053 	u8 addr[ETH_ALEN];
5054 
5055 	mlx5_query_mac_address(priv->mdev, addr);
5056 	if (is_zero_ether_addr(addr) &&
5057 	    !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
5058 		eth_hw_addr_random(netdev);
5059 		mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
5060 		return;
5061 	}
5062 
5063 	eth_hw_addr_set(netdev, addr);
5064 }
5065 
mlx5e_vxlan_set_port(struct net_device * netdev,unsigned int table,unsigned int entry,struct udp_tunnel_info * ti)5066 static int mlx5e_vxlan_set_port(struct net_device *netdev, unsigned int table,
5067 				unsigned int entry, struct udp_tunnel_info *ti)
5068 {
5069 	struct mlx5e_priv *priv = netdev_priv(netdev);
5070 
5071 	return mlx5_vxlan_add_port(priv->mdev->vxlan, ntohs(ti->port));
5072 }
5073 
mlx5e_vxlan_unset_port(struct net_device * netdev,unsigned int table,unsigned int entry,struct udp_tunnel_info * ti)5074 static int mlx5e_vxlan_unset_port(struct net_device *netdev, unsigned int table,
5075 				  unsigned int entry, struct udp_tunnel_info *ti)
5076 {
5077 	struct mlx5e_priv *priv = netdev_priv(netdev);
5078 
5079 	return mlx5_vxlan_del_port(priv->mdev->vxlan, ntohs(ti->port));
5080 }
5081 
mlx5e_vxlan_set_netdev_info(struct mlx5e_priv * priv)5082 void mlx5e_vxlan_set_netdev_info(struct mlx5e_priv *priv)
5083 {
5084 	if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
5085 		return;
5086 
5087 	priv->nic_info.set_port = mlx5e_vxlan_set_port;
5088 	priv->nic_info.unset_port = mlx5e_vxlan_unset_port;
5089 	priv->nic_info.flags = UDP_TUNNEL_NIC_INFO_MAY_SLEEP |
5090 				UDP_TUNNEL_NIC_INFO_STATIC_IANA_VXLAN;
5091 	priv->nic_info.tables[0].tunnel_types = UDP_TUNNEL_TYPE_VXLAN;
5092 	/* Don't count the space hard-coded to the IANA port */
5093 	priv->nic_info.tables[0].n_entries =
5094 		mlx5_vxlan_max_udp_ports(priv->mdev) - 1;
5095 
5096 	priv->netdev->udp_tunnel_nic_info = &priv->nic_info;
5097 }
5098 
mlx5e_tunnel_any_tx_proto_supported(struct mlx5_core_dev * mdev)5099 static bool mlx5e_tunnel_any_tx_proto_supported(struct mlx5_core_dev *mdev)
5100 {
5101 	int tt;
5102 
5103 	for (tt = 0; tt < MLX5_NUM_TUNNEL_TT; tt++) {
5104 		if (mlx5e_tunnel_proto_supported_tx(mdev, mlx5_get_proto_by_tunnel_type(tt)))
5105 			return true;
5106 	}
5107 	return (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev));
5108 }
5109 
mlx5e_build_nic_netdev(struct net_device * netdev)5110 static void mlx5e_build_nic_netdev(struct net_device *netdev)
5111 {
5112 	struct mlx5e_priv *priv = netdev_priv(netdev);
5113 	struct mlx5_core_dev *mdev = priv->mdev;
5114 	bool fcs_supported;
5115 	bool fcs_enabled;
5116 
5117 	SET_NETDEV_DEV(netdev, mdev->device);
5118 
5119 	netdev->netdev_ops = &mlx5e_netdev_ops;
5120 	netdev->xdp_metadata_ops = &mlx5e_xdp_metadata_ops;
5121 
5122 	mlx5e_dcbnl_build_netdev(netdev);
5123 
5124 	netdev->watchdog_timeo    = 15 * HZ;
5125 
5126 	netdev->ethtool_ops	  = &mlx5e_ethtool_ops;
5127 
5128 	netdev->vlan_features    |= NETIF_F_SG;
5129 	netdev->vlan_features    |= NETIF_F_HW_CSUM;
5130 	netdev->vlan_features    |= NETIF_F_HW_MACSEC;
5131 	netdev->vlan_features    |= NETIF_F_GRO;
5132 	netdev->vlan_features    |= NETIF_F_TSO;
5133 	netdev->vlan_features    |= NETIF_F_TSO6;
5134 	netdev->vlan_features    |= NETIF_F_RXCSUM;
5135 	netdev->vlan_features    |= NETIF_F_RXHASH;
5136 	netdev->vlan_features    |= NETIF_F_GSO_PARTIAL;
5137 
5138 	netdev->mpls_features    |= NETIF_F_SG;
5139 	netdev->mpls_features    |= NETIF_F_HW_CSUM;
5140 	netdev->mpls_features    |= NETIF_F_TSO;
5141 	netdev->mpls_features    |= NETIF_F_TSO6;
5142 
5143 	netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_TX;
5144 	netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_RX;
5145 
5146 	/* Tunneled LRO is not supported in the driver, and the same RQs are
5147 	 * shared between inner and outer TIRs, so the driver can't disable LRO
5148 	 * for inner TIRs while having it enabled for outer TIRs. Due to this,
5149 	 * block LRO altogether if the firmware declares tunneled LRO support.
5150 	 */
5151 	if (!!MLX5_CAP_ETH(mdev, lro_cap) &&
5152 	    !MLX5_CAP_ETH(mdev, tunnel_lro_vxlan) &&
5153 	    !MLX5_CAP_ETH(mdev, tunnel_lro_gre) &&
5154 	    mlx5e_check_fragmented_striding_rq_cap(mdev, PAGE_SHIFT,
5155 						   MLX5E_MPWRQ_UMR_MODE_ALIGNED))
5156 		netdev->vlan_features    |= NETIF_F_LRO;
5157 
5158 	netdev->hw_features       = netdev->vlan_features;
5159 	netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
5160 	netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
5161 	netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
5162 	netdev->hw_features      |= NETIF_F_HW_VLAN_STAG_TX;
5163 
5164 	if (mlx5e_tunnel_any_tx_proto_supported(mdev)) {
5165 		netdev->hw_enc_features |= NETIF_F_HW_CSUM;
5166 		netdev->hw_enc_features |= NETIF_F_TSO;
5167 		netdev->hw_enc_features |= NETIF_F_TSO6;
5168 		netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
5169 	}
5170 
5171 	if (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev)) {
5172 		netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL |
5173 					   NETIF_F_GSO_UDP_TUNNEL_CSUM;
5174 		netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL |
5175 					   NETIF_F_GSO_UDP_TUNNEL_CSUM;
5176 		netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
5177 		netdev->vlan_features |= NETIF_F_GSO_UDP_TUNNEL |
5178 					 NETIF_F_GSO_UDP_TUNNEL_CSUM;
5179 	}
5180 
5181 	if (mlx5e_tunnel_proto_supported_tx(mdev, IPPROTO_GRE)) {
5182 		netdev->hw_features     |= NETIF_F_GSO_GRE |
5183 					   NETIF_F_GSO_GRE_CSUM;
5184 		netdev->hw_enc_features |= NETIF_F_GSO_GRE |
5185 					   NETIF_F_GSO_GRE_CSUM;
5186 		netdev->gso_partial_features |= NETIF_F_GSO_GRE |
5187 						NETIF_F_GSO_GRE_CSUM;
5188 	}
5189 
5190 	if (mlx5e_tunnel_proto_supported_tx(mdev, IPPROTO_IPIP)) {
5191 		netdev->hw_features |= NETIF_F_GSO_IPXIP4 |
5192 				       NETIF_F_GSO_IPXIP6;
5193 		netdev->hw_enc_features |= NETIF_F_GSO_IPXIP4 |
5194 					   NETIF_F_GSO_IPXIP6;
5195 		netdev->gso_partial_features |= NETIF_F_GSO_IPXIP4 |
5196 						NETIF_F_GSO_IPXIP6;
5197 	}
5198 
5199 	netdev->gso_partial_features             |= NETIF_F_GSO_UDP_L4;
5200 	netdev->hw_features                      |= NETIF_F_GSO_UDP_L4;
5201 	netdev->features                         |= NETIF_F_GSO_UDP_L4;
5202 
5203 	mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
5204 
5205 	if (fcs_supported)
5206 		netdev->hw_features |= NETIF_F_RXALL;
5207 
5208 	if (MLX5_CAP_ETH(mdev, scatter_fcs))
5209 		netdev->hw_features |= NETIF_F_RXFCS;
5210 
5211 	if (mlx5_qos_is_supported(mdev))
5212 		netdev->hw_features |= NETIF_F_HW_TC;
5213 
5214 	netdev->features          = netdev->hw_features;
5215 
5216 	/* Defaults */
5217 	if (fcs_enabled)
5218 		netdev->features  &= ~NETIF_F_RXALL;
5219 	netdev->features  &= ~NETIF_F_LRO;
5220 	netdev->features  &= ~NETIF_F_GRO_HW;
5221 	netdev->features  &= ~NETIF_F_RXFCS;
5222 
5223 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
5224 	if (FT_CAP(flow_modify_en) &&
5225 	    FT_CAP(modify_root) &&
5226 	    FT_CAP(identified_miss_table_mode) &&
5227 	    FT_CAP(flow_table_modify)) {
5228 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
5229 		netdev->hw_features      |= NETIF_F_HW_TC;
5230 #endif
5231 #ifdef CONFIG_MLX5_EN_ARFS
5232 		netdev->hw_features	 |= NETIF_F_NTUPLE;
5233 #endif
5234 	}
5235 
5236 	netdev->features         |= NETIF_F_HIGHDMA;
5237 	netdev->features         |= NETIF_F_HW_VLAN_STAG_FILTER;
5238 
5239 	netdev->priv_flags       |= IFF_UNICAST_FLT;
5240 
5241 	netif_set_tso_max_size(netdev, GSO_MAX_SIZE);
5242 	mlx5e_set_xdp_feature(netdev);
5243 	mlx5e_set_netdev_dev_addr(netdev);
5244 	mlx5e_macsec_build_netdev(priv);
5245 	mlx5e_ipsec_build_netdev(priv);
5246 	mlx5e_ktls_build_netdev(priv);
5247 }
5248 
mlx5e_create_q_counters(struct mlx5e_priv * priv)5249 void mlx5e_create_q_counters(struct mlx5e_priv *priv)
5250 {
5251 	u32 out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {};
5252 	u32 in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {};
5253 	struct mlx5_core_dev *mdev = priv->mdev;
5254 	int err;
5255 
5256 	MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER);
5257 	err = mlx5_cmd_exec_inout(mdev, alloc_q_counter, in, out);
5258 	if (!err)
5259 		priv->q_counter =
5260 			MLX5_GET(alloc_q_counter_out, out, counter_set_id);
5261 
5262 	err = mlx5_cmd_exec_inout(mdev, alloc_q_counter, in, out);
5263 	if (!err)
5264 		priv->drop_rq_q_counter =
5265 			MLX5_GET(alloc_q_counter_out, out, counter_set_id);
5266 }
5267 
mlx5e_destroy_q_counters(struct mlx5e_priv * priv)5268 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv)
5269 {
5270 	u32 in[MLX5_ST_SZ_DW(dealloc_q_counter_in)] = {};
5271 
5272 	MLX5_SET(dealloc_q_counter_in, in, opcode,
5273 		 MLX5_CMD_OP_DEALLOC_Q_COUNTER);
5274 	if (priv->q_counter) {
5275 		MLX5_SET(dealloc_q_counter_in, in, counter_set_id,
5276 			 priv->q_counter);
5277 		mlx5_cmd_exec_in(priv->mdev, dealloc_q_counter, in);
5278 	}
5279 
5280 	if (priv->drop_rq_q_counter) {
5281 		MLX5_SET(dealloc_q_counter_in, in, counter_set_id,
5282 			 priv->drop_rq_q_counter);
5283 		mlx5_cmd_exec_in(priv->mdev, dealloc_q_counter, in);
5284 	}
5285 }
5286 
mlx5e_nic_init(struct mlx5_core_dev * mdev,struct net_device * netdev)5287 static int mlx5e_nic_init(struct mlx5_core_dev *mdev,
5288 			  struct net_device *netdev)
5289 {
5290 	const bool take_rtnl = netdev->reg_state == NETREG_REGISTERED;
5291 	struct mlx5e_priv *priv = netdev_priv(netdev);
5292 	struct mlx5e_flow_steering *fs;
5293 	int err;
5294 
5295 	mlx5e_build_nic_params(priv, &priv->xsk, netdev->mtu);
5296 	mlx5e_vxlan_set_netdev_info(priv);
5297 
5298 	mlx5e_timestamp_init(priv);
5299 
5300 	priv->dfs_root = debugfs_create_dir("nic",
5301 					    mlx5_debugfs_get_dev_root(mdev));
5302 
5303 	fs = mlx5e_fs_init(priv->profile, mdev,
5304 			   !test_bit(MLX5E_STATE_DESTROYING, &priv->state),
5305 			   priv->dfs_root);
5306 	if (!fs) {
5307 		err = -ENOMEM;
5308 		mlx5_core_err(mdev, "FS initialization failed, %d\n", err);
5309 		debugfs_remove_recursive(priv->dfs_root);
5310 		return err;
5311 	}
5312 	priv->fs = fs;
5313 
5314 	err = mlx5e_ktls_init(priv);
5315 	if (err)
5316 		mlx5_core_err(mdev, "TLS initialization failed, %d\n", err);
5317 
5318 	mlx5e_health_create_reporters(priv);
5319 
5320 	/* If netdev is already registered (e.g. move from uplink to nic profile),
5321 	 * RTNL lock must be held before triggering netdev notifiers.
5322 	 */
5323 	if (take_rtnl)
5324 		rtnl_lock();
5325 
5326 	/* update XDP supported features */
5327 	mlx5e_set_xdp_feature(netdev);
5328 
5329 	if (take_rtnl)
5330 		rtnl_unlock();
5331 
5332 	return 0;
5333 }
5334 
mlx5e_nic_cleanup(struct mlx5e_priv * priv)5335 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
5336 {
5337 	mlx5e_health_destroy_reporters(priv);
5338 	mlx5e_ktls_cleanup(priv);
5339 	mlx5e_fs_cleanup(priv->fs);
5340 	debugfs_remove_recursive(priv->dfs_root);
5341 	priv->fs = NULL;
5342 }
5343 
mlx5e_init_nic_rx(struct mlx5e_priv * priv)5344 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
5345 {
5346 	struct mlx5_core_dev *mdev = priv->mdev;
5347 	enum mlx5e_rx_res_features features;
5348 	int err;
5349 
5350 	priv->rx_res = mlx5e_rx_res_alloc();
5351 	if (!priv->rx_res)
5352 		return -ENOMEM;
5353 
5354 	mlx5e_create_q_counters(priv);
5355 
5356 	err = mlx5e_open_drop_rq(priv, &priv->drop_rq);
5357 	if (err) {
5358 		mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
5359 		goto err_destroy_q_counters;
5360 	}
5361 
5362 	features = MLX5E_RX_RES_FEATURE_PTP;
5363 	if (mlx5_tunnel_inner_ft_supported(mdev))
5364 		features |= MLX5E_RX_RES_FEATURE_INNER_FT;
5365 	err = mlx5e_rx_res_init(priv->rx_res, priv->mdev, features,
5366 				priv->max_nch, priv->drop_rq.rqn,
5367 				&priv->channels.params.packet_merge,
5368 				priv->channels.params.num_channels);
5369 	if (err)
5370 		goto err_close_drop_rq;
5371 
5372 	err = mlx5e_create_flow_steering(priv->fs, priv->rx_res, priv->profile,
5373 					 priv->netdev);
5374 	if (err) {
5375 		mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
5376 		goto err_destroy_rx_res;
5377 	}
5378 
5379 	err = mlx5e_tc_nic_init(priv);
5380 	if (err)
5381 		goto err_destroy_flow_steering;
5382 
5383 	err = mlx5e_accel_init_rx(priv);
5384 	if (err)
5385 		goto err_tc_nic_cleanup;
5386 
5387 #ifdef CONFIG_MLX5_EN_ARFS
5388 	priv->netdev->rx_cpu_rmap =  mlx5_eq_table_get_rmap(priv->mdev);
5389 #endif
5390 
5391 	return 0;
5392 
5393 err_tc_nic_cleanup:
5394 	mlx5e_tc_nic_cleanup(priv);
5395 err_destroy_flow_steering:
5396 	mlx5e_destroy_flow_steering(priv->fs, !!(priv->netdev->hw_features & NETIF_F_NTUPLE),
5397 				    priv->profile);
5398 err_destroy_rx_res:
5399 	mlx5e_rx_res_destroy(priv->rx_res);
5400 err_close_drop_rq:
5401 	mlx5e_close_drop_rq(&priv->drop_rq);
5402 err_destroy_q_counters:
5403 	mlx5e_destroy_q_counters(priv);
5404 	mlx5e_rx_res_free(priv->rx_res);
5405 	priv->rx_res = NULL;
5406 	return err;
5407 }
5408 
mlx5e_cleanup_nic_rx(struct mlx5e_priv * priv)5409 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
5410 {
5411 	mlx5e_accel_cleanup_rx(priv);
5412 	mlx5e_tc_nic_cleanup(priv);
5413 	mlx5e_destroy_flow_steering(priv->fs, !!(priv->netdev->hw_features & NETIF_F_NTUPLE),
5414 				    priv->profile);
5415 	mlx5e_rx_res_destroy(priv->rx_res);
5416 	mlx5e_close_drop_rq(&priv->drop_rq);
5417 	mlx5e_destroy_q_counters(priv);
5418 	mlx5e_rx_res_free(priv->rx_res);
5419 	priv->rx_res = NULL;
5420 }
5421 
mlx5e_set_mqprio_rl(struct mlx5e_priv * priv)5422 static void mlx5e_set_mqprio_rl(struct mlx5e_priv *priv)
5423 {
5424 	struct mlx5e_params *params;
5425 	struct mlx5e_mqprio_rl *rl;
5426 
5427 	params = &priv->channels.params;
5428 	if (params->mqprio.mode != TC_MQPRIO_MODE_CHANNEL)
5429 		return;
5430 
5431 	rl = mlx5e_mqprio_rl_create(priv->mdev, params->mqprio.num_tc,
5432 				    params->mqprio.channel.max_rate);
5433 	if (IS_ERR(rl))
5434 		rl = NULL;
5435 	priv->mqprio_rl = rl;
5436 	mlx5e_mqprio_rl_update_params(params, rl);
5437 }
5438 
mlx5e_init_nic_tx(struct mlx5e_priv * priv)5439 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
5440 {
5441 	int err;
5442 
5443 	err = mlx5e_create_tises(priv);
5444 	if (err) {
5445 		mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
5446 		return err;
5447 	}
5448 
5449 	err = mlx5e_accel_init_tx(priv);
5450 	if (err)
5451 		goto err_destroy_tises;
5452 
5453 	mlx5e_set_mqprio_rl(priv);
5454 	mlx5e_dcbnl_initialize(priv);
5455 	return 0;
5456 
5457 err_destroy_tises:
5458 	mlx5e_destroy_tises(priv);
5459 	return err;
5460 }
5461 
mlx5e_nic_enable(struct mlx5e_priv * priv)5462 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
5463 {
5464 	struct net_device *netdev = priv->netdev;
5465 	struct mlx5_core_dev *mdev = priv->mdev;
5466 	int err;
5467 
5468 	mlx5e_fs_init_l2_addr(priv->fs, netdev);
5469 	mlx5e_ipsec_init(priv);
5470 
5471 	err = mlx5e_macsec_init(priv);
5472 	if (err)
5473 		mlx5_core_err(mdev, "MACsec initialization failed, %d\n", err);
5474 
5475 	/* Marking the link as currently not needed by the Driver */
5476 	if (!netif_running(netdev))
5477 		mlx5e_modify_admin_state(mdev, MLX5_PORT_DOWN);
5478 
5479 	mlx5e_set_netdev_mtu_boundaries(priv);
5480 	mlx5e_set_dev_port_mtu(priv);
5481 
5482 	mlx5_lag_add_netdev(mdev, netdev);
5483 
5484 	mlx5e_enable_async_events(priv);
5485 	mlx5e_enable_blocking_events(priv);
5486 	if (mlx5e_monitor_counter_supported(priv))
5487 		mlx5e_monitor_counter_init(priv);
5488 
5489 	mlx5e_hv_vhca_stats_create(priv);
5490 	if (netdev->reg_state != NETREG_REGISTERED)
5491 		return;
5492 	mlx5e_dcbnl_init_app(priv);
5493 
5494 	mlx5e_nic_set_rx_mode(priv);
5495 
5496 	rtnl_lock();
5497 	if (netif_running(netdev))
5498 		mlx5e_open(netdev);
5499 	udp_tunnel_nic_reset_ntf(priv->netdev);
5500 	netif_device_attach(netdev);
5501 	rtnl_unlock();
5502 }
5503 
mlx5e_nic_disable(struct mlx5e_priv * priv)5504 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
5505 {
5506 	struct mlx5_core_dev *mdev = priv->mdev;
5507 
5508 	if (priv->netdev->reg_state == NETREG_REGISTERED)
5509 		mlx5e_dcbnl_delete_app(priv);
5510 
5511 	rtnl_lock();
5512 	if (netif_running(priv->netdev))
5513 		mlx5e_close(priv->netdev);
5514 	netif_device_detach(priv->netdev);
5515 	rtnl_unlock();
5516 
5517 	mlx5e_nic_set_rx_mode(priv);
5518 
5519 	mlx5e_hv_vhca_stats_destroy(priv);
5520 	if (mlx5e_monitor_counter_supported(priv))
5521 		mlx5e_monitor_counter_cleanup(priv);
5522 
5523 	mlx5e_disable_blocking_events(priv);
5524 	if (priv->en_trap) {
5525 		mlx5e_deactivate_trap(priv);
5526 		mlx5e_close_trap(priv->en_trap);
5527 		priv->en_trap = NULL;
5528 	}
5529 	mlx5e_disable_async_events(priv);
5530 	mlx5_lag_remove_netdev(mdev, priv->netdev);
5531 	mlx5_vxlan_reset_to_default(mdev->vxlan);
5532 	mlx5e_macsec_cleanup(priv);
5533 	mlx5e_ipsec_cleanup(priv);
5534 }
5535 
mlx5e_update_nic_rx(struct mlx5e_priv * priv)5536 int mlx5e_update_nic_rx(struct mlx5e_priv *priv)
5537 {
5538 	return mlx5e_refresh_tirs(priv, false, false);
5539 }
5540 
5541 static const struct mlx5e_profile mlx5e_nic_profile = {
5542 	.init		   = mlx5e_nic_init,
5543 	.cleanup	   = mlx5e_nic_cleanup,
5544 	.init_rx	   = mlx5e_init_nic_rx,
5545 	.cleanup_rx	   = mlx5e_cleanup_nic_rx,
5546 	.init_tx	   = mlx5e_init_nic_tx,
5547 	.cleanup_tx	   = mlx5e_cleanup_nic_tx,
5548 	.enable		   = mlx5e_nic_enable,
5549 	.disable	   = mlx5e_nic_disable,
5550 	.update_rx	   = mlx5e_update_nic_rx,
5551 	.update_stats	   = mlx5e_stats_update_ndo_stats,
5552 	.update_carrier	   = mlx5e_update_carrier,
5553 	.rx_handlers       = &mlx5e_rx_handlers_nic,
5554 	.max_tc		   = MLX5E_MAX_NUM_TC,
5555 	.stats_grps	   = mlx5e_nic_stats_grps,
5556 	.stats_grps_num	   = mlx5e_nic_stats_grps_num,
5557 	.features          = BIT(MLX5E_PROFILE_FEATURE_PTP_RX) |
5558 		BIT(MLX5E_PROFILE_FEATURE_PTP_TX) |
5559 		BIT(MLX5E_PROFILE_FEATURE_QOS_HTB) |
5560 		BIT(MLX5E_PROFILE_FEATURE_FS_VLAN) |
5561 		BIT(MLX5E_PROFILE_FEATURE_FS_TC),
5562 };
5563 
mlx5e_profile_max_num_channels(struct mlx5_core_dev * mdev,const struct mlx5e_profile * profile)5564 static int mlx5e_profile_max_num_channels(struct mlx5_core_dev *mdev,
5565 					  const struct mlx5e_profile *profile)
5566 {
5567 	int nch;
5568 
5569 	nch = mlx5e_get_max_num_channels(mdev);
5570 
5571 	if (profile->max_nch_limit)
5572 		nch = min_t(int, nch, profile->max_nch_limit(mdev));
5573 	return nch;
5574 }
5575 
5576 static unsigned int
mlx5e_calc_max_nch(struct mlx5_core_dev * mdev,struct net_device * netdev,const struct mlx5e_profile * profile)5577 mlx5e_calc_max_nch(struct mlx5_core_dev *mdev, struct net_device *netdev,
5578 		   const struct mlx5e_profile *profile)
5579 
5580 {
5581 	unsigned int max_nch, tmp;
5582 
5583 	/* core resources */
5584 	max_nch = mlx5e_profile_max_num_channels(mdev, profile);
5585 
5586 	/* netdev rx queues */
5587 	max_nch = min_t(unsigned int, max_nch, netdev->num_rx_queues);
5588 
5589 	/* netdev tx queues */
5590 	tmp = netdev->num_tx_queues;
5591 	if (mlx5_qos_is_supported(mdev))
5592 		tmp -= mlx5e_qos_max_leaf_nodes(mdev);
5593 	if (MLX5_CAP_GEN(mdev, ts_cqe_to_dest_cqn))
5594 		tmp -= profile->max_tc;
5595 	tmp = tmp / profile->max_tc;
5596 	max_nch = min_t(unsigned int, max_nch, tmp);
5597 
5598 	return max_nch;
5599 }
5600 
mlx5e_get_pf_num_tirs(struct mlx5_core_dev * mdev)5601 int mlx5e_get_pf_num_tirs(struct mlx5_core_dev *mdev)
5602 {
5603 	/* Indirect TIRS: 2 sets of TTCs (inner + outer steering)
5604 	 * and 1 set of direct TIRS
5605 	 */
5606 	return 2 * MLX5E_NUM_INDIR_TIRS
5607 		+ mlx5e_profile_max_num_channels(mdev, &mlx5e_nic_profile);
5608 }
5609 
mlx5e_set_rx_mode_work(struct work_struct * work)5610 void mlx5e_set_rx_mode_work(struct work_struct *work)
5611 {
5612 	struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
5613 					       set_rx_mode_work);
5614 
5615 	return mlx5e_fs_set_rx_mode_work(priv->fs, priv->netdev);
5616 }
5617 
5618 /* mlx5e generic netdev management API (move to en_common.c) */
mlx5e_priv_init(struct mlx5e_priv * priv,const struct mlx5e_profile * profile,struct net_device * netdev,struct mlx5_core_dev * mdev)5619 int mlx5e_priv_init(struct mlx5e_priv *priv,
5620 		    const struct mlx5e_profile *profile,
5621 		    struct net_device *netdev,
5622 		    struct mlx5_core_dev *mdev)
5623 {
5624 	int nch, num_txqs, node;
5625 	int err;
5626 
5627 	num_txqs = netdev->num_tx_queues;
5628 	nch = mlx5e_calc_max_nch(mdev, netdev, profile);
5629 	node = dev_to_node(mlx5_core_dma_dev(mdev));
5630 
5631 	/* priv init */
5632 	priv->mdev        = mdev;
5633 	priv->netdev      = netdev;
5634 	priv->max_nch     = nch;
5635 	priv->max_opened_tc = 1;
5636 
5637 	if (!alloc_cpumask_var(&priv->scratchpad.cpumask, GFP_KERNEL))
5638 		return -ENOMEM;
5639 
5640 	mutex_init(&priv->state_lock);
5641 
5642 	err = mlx5e_selq_init(&priv->selq, &priv->state_lock);
5643 	if (err)
5644 		goto err_free_cpumask;
5645 
5646 	INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
5647 	INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
5648 	INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
5649 	INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
5650 
5651 	priv->wq = create_singlethread_workqueue("mlx5e");
5652 	if (!priv->wq)
5653 		goto err_free_selq;
5654 
5655 	priv->txq2sq = kcalloc_node(num_txqs, sizeof(*priv->txq2sq), GFP_KERNEL, node);
5656 	if (!priv->txq2sq)
5657 		goto err_destroy_workqueue;
5658 
5659 	priv->tx_rates = kcalloc_node(num_txqs, sizeof(*priv->tx_rates), GFP_KERNEL, node);
5660 	if (!priv->tx_rates)
5661 		goto err_free_txq2sq;
5662 
5663 	priv->channel_stats =
5664 		kcalloc_node(nch, sizeof(*priv->channel_stats), GFP_KERNEL, node);
5665 	if (!priv->channel_stats)
5666 		goto err_free_tx_rates;
5667 
5668 	return 0;
5669 
5670 err_free_tx_rates:
5671 	kfree(priv->tx_rates);
5672 err_free_txq2sq:
5673 	kfree(priv->txq2sq);
5674 err_destroy_workqueue:
5675 	destroy_workqueue(priv->wq);
5676 err_free_selq:
5677 	mlx5e_selq_cleanup(&priv->selq);
5678 err_free_cpumask:
5679 	free_cpumask_var(priv->scratchpad.cpumask);
5680 	return -ENOMEM;
5681 }
5682 
mlx5e_priv_cleanup(struct mlx5e_priv * priv)5683 void mlx5e_priv_cleanup(struct mlx5e_priv *priv)
5684 {
5685 	int i;
5686 
5687 	/* bail if change profile failed and also rollback failed */
5688 	if (!priv->mdev)
5689 		return;
5690 
5691 	for (i = 0; i < priv->stats_nch; i++)
5692 		kvfree(priv->channel_stats[i]);
5693 	kfree(priv->channel_stats);
5694 	kfree(priv->tx_rates);
5695 	kfree(priv->txq2sq);
5696 	destroy_workqueue(priv->wq);
5697 	mutex_lock(&priv->state_lock);
5698 	mlx5e_selq_cleanup(&priv->selq);
5699 	mutex_unlock(&priv->state_lock);
5700 	free_cpumask_var(priv->scratchpad.cpumask);
5701 
5702 	for (i = 0; i < priv->htb_max_qos_sqs; i++)
5703 		kfree(priv->htb_qos_sq_stats[i]);
5704 	kvfree(priv->htb_qos_sq_stats);
5705 
5706 	memset(priv, 0, sizeof(*priv));
5707 }
5708 
mlx5e_get_max_num_txqs(struct mlx5_core_dev * mdev,const struct mlx5e_profile * profile)5709 static unsigned int mlx5e_get_max_num_txqs(struct mlx5_core_dev *mdev,
5710 					   const struct mlx5e_profile *profile)
5711 {
5712 	unsigned int nch, ptp_txqs, qos_txqs;
5713 
5714 	nch = mlx5e_profile_max_num_channels(mdev, profile);
5715 
5716 	ptp_txqs = MLX5_CAP_GEN(mdev, ts_cqe_to_dest_cqn) &&
5717 		mlx5e_profile_feature_cap(profile, PTP_TX) ?
5718 		profile->max_tc : 0;
5719 
5720 	qos_txqs = mlx5_qos_is_supported(mdev) &&
5721 		mlx5e_profile_feature_cap(profile, QOS_HTB) ?
5722 		mlx5e_qos_max_leaf_nodes(mdev) : 0;
5723 
5724 	return nch * profile->max_tc + ptp_txqs + qos_txqs;
5725 }
5726 
mlx5e_get_max_num_rxqs(struct mlx5_core_dev * mdev,const struct mlx5e_profile * profile)5727 static unsigned int mlx5e_get_max_num_rxqs(struct mlx5_core_dev *mdev,
5728 					   const struct mlx5e_profile *profile)
5729 {
5730 	return mlx5e_profile_max_num_channels(mdev, profile);
5731 }
5732 
5733 struct net_device *
mlx5e_create_netdev(struct mlx5_core_dev * mdev,const struct mlx5e_profile * profile)5734 mlx5e_create_netdev(struct mlx5_core_dev *mdev, const struct mlx5e_profile *profile)
5735 {
5736 	struct net_device *netdev;
5737 	unsigned int txqs, rxqs;
5738 	int err;
5739 
5740 	txqs = mlx5e_get_max_num_txqs(mdev, profile);
5741 	rxqs = mlx5e_get_max_num_rxqs(mdev, profile);
5742 
5743 	netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv), txqs, rxqs);
5744 	if (!netdev) {
5745 		mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
5746 		return NULL;
5747 	}
5748 
5749 	err = mlx5e_priv_init(netdev_priv(netdev), profile, netdev, mdev);
5750 	if (err) {
5751 		mlx5_core_err(mdev, "mlx5e_priv_init failed, err=%d\n", err);
5752 		goto err_free_netdev;
5753 	}
5754 
5755 	netif_carrier_off(netdev);
5756 	netif_tx_disable(netdev);
5757 	dev_net_set(netdev, mlx5_core_net(mdev));
5758 
5759 	return netdev;
5760 
5761 err_free_netdev:
5762 	free_netdev(netdev);
5763 
5764 	return NULL;
5765 }
5766 
mlx5e_update_features(struct net_device * netdev)5767 static void mlx5e_update_features(struct net_device *netdev)
5768 {
5769 	if (netdev->reg_state != NETREG_REGISTERED)
5770 		return; /* features will be updated on netdev registration */
5771 
5772 	rtnl_lock();
5773 	netdev_update_features(netdev);
5774 	rtnl_unlock();
5775 }
5776 
mlx5e_reset_channels(struct net_device * netdev)5777 static void mlx5e_reset_channels(struct net_device *netdev)
5778 {
5779 	netdev_reset_tc(netdev);
5780 }
5781 
mlx5e_attach_netdev(struct mlx5e_priv * priv)5782 int mlx5e_attach_netdev(struct mlx5e_priv *priv)
5783 {
5784 	const bool take_rtnl = priv->netdev->reg_state == NETREG_REGISTERED;
5785 	const struct mlx5e_profile *profile = priv->profile;
5786 	int max_nch;
5787 	int err;
5788 
5789 	clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
5790 	if (priv->fs)
5791 		mlx5e_fs_set_state_destroy(priv->fs,
5792 					   !test_bit(MLX5E_STATE_DESTROYING, &priv->state));
5793 
5794 	/* Validate the max_wqe_size_sq capability. */
5795 	if (WARN_ON_ONCE(mlx5e_get_max_sq_wqebbs(priv->mdev) < MLX5E_MAX_TX_WQEBBS)) {
5796 		mlx5_core_warn(priv->mdev, "MLX5E: Max SQ WQEBBs firmware capability: %u, needed %u\n",
5797 			       mlx5e_get_max_sq_wqebbs(priv->mdev), (unsigned int)MLX5E_MAX_TX_WQEBBS);
5798 		return -EIO;
5799 	}
5800 
5801 	/* max number of channels may have changed */
5802 	max_nch = mlx5e_calc_max_nch(priv->mdev, priv->netdev, profile);
5803 	if (priv->channels.params.num_channels > max_nch) {
5804 		mlx5_core_warn(priv->mdev, "MLX5E: Reducing number of channels to %d\n", max_nch);
5805 		/* Reducing the number of channels - RXFH has to be reset, and
5806 		 * mlx5e_num_channels_changed below will build the RQT.
5807 		 */
5808 		priv->netdev->priv_flags &= ~IFF_RXFH_CONFIGURED;
5809 		priv->channels.params.num_channels = max_nch;
5810 		if (priv->channels.params.mqprio.mode == TC_MQPRIO_MODE_CHANNEL) {
5811 			mlx5_core_warn(priv->mdev, "MLX5E: Disabling MQPRIO channel mode\n");
5812 			mlx5e_params_mqprio_reset(&priv->channels.params);
5813 		}
5814 	}
5815 	if (max_nch != priv->max_nch) {
5816 		mlx5_core_warn(priv->mdev,
5817 			       "MLX5E: Updating max number of channels from %u to %u\n",
5818 			       priv->max_nch, max_nch);
5819 		priv->max_nch = max_nch;
5820 	}
5821 
5822 	/* 1. Set the real number of queues in the kernel the first time.
5823 	 * 2. Set our default XPS cpumask.
5824 	 * 3. Build the RQT.
5825 	 *
5826 	 * rtnl_lock is required by netif_set_real_num_*_queues in case the
5827 	 * netdev has been registered by this point (if this function was called
5828 	 * in the reload or resume flow).
5829 	 */
5830 	if (take_rtnl)
5831 		rtnl_lock();
5832 	err = mlx5e_num_channels_changed(priv);
5833 	if (take_rtnl)
5834 		rtnl_unlock();
5835 	if (err)
5836 		goto out;
5837 
5838 	err = profile->init_tx(priv);
5839 	if (err)
5840 		goto out;
5841 
5842 	err = profile->init_rx(priv);
5843 	if (err)
5844 		goto err_cleanup_tx;
5845 
5846 	if (profile->enable)
5847 		profile->enable(priv);
5848 
5849 	mlx5e_update_features(priv->netdev);
5850 
5851 	return 0;
5852 
5853 err_cleanup_tx:
5854 	profile->cleanup_tx(priv);
5855 
5856 out:
5857 	mlx5e_reset_channels(priv->netdev);
5858 	set_bit(MLX5E_STATE_DESTROYING, &priv->state);
5859 	if (priv->fs)
5860 		mlx5e_fs_set_state_destroy(priv->fs,
5861 					   !test_bit(MLX5E_STATE_DESTROYING, &priv->state));
5862 	cancel_work_sync(&priv->update_stats_work);
5863 	return err;
5864 }
5865 
mlx5e_detach_netdev(struct mlx5e_priv * priv)5866 void mlx5e_detach_netdev(struct mlx5e_priv *priv)
5867 {
5868 	const struct mlx5e_profile *profile = priv->profile;
5869 
5870 	set_bit(MLX5E_STATE_DESTROYING, &priv->state);
5871 	if (priv->fs)
5872 		mlx5e_fs_set_state_destroy(priv->fs,
5873 					   !test_bit(MLX5E_STATE_DESTROYING, &priv->state));
5874 
5875 	if (profile->disable)
5876 		profile->disable(priv);
5877 	flush_workqueue(priv->wq);
5878 
5879 	profile->cleanup_rx(priv);
5880 	profile->cleanup_tx(priv);
5881 	mlx5e_reset_channels(priv->netdev);
5882 	cancel_work_sync(&priv->update_stats_work);
5883 }
5884 
5885 static int
mlx5e_netdev_init_profile(struct net_device * netdev,struct mlx5_core_dev * mdev,const struct mlx5e_profile * new_profile,void * new_ppriv)5886 mlx5e_netdev_init_profile(struct net_device *netdev, struct mlx5_core_dev *mdev,
5887 			  const struct mlx5e_profile *new_profile, void *new_ppriv)
5888 {
5889 	struct mlx5e_priv *priv = netdev_priv(netdev);
5890 	int err;
5891 
5892 	err = mlx5e_priv_init(priv, new_profile, netdev, mdev);
5893 	if (err) {
5894 		mlx5_core_err(mdev, "mlx5e_priv_init failed, err=%d\n", err);
5895 		return err;
5896 	}
5897 	netif_carrier_off(netdev);
5898 	priv->profile = new_profile;
5899 	priv->ppriv = new_ppriv;
5900 	err = new_profile->init(priv->mdev, priv->netdev);
5901 	if (err)
5902 		goto priv_cleanup;
5903 
5904 	return 0;
5905 
5906 priv_cleanup:
5907 	mlx5e_priv_cleanup(priv);
5908 	return err;
5909 }
5910 
5911 static int
mlx5e_netdev_attach_profile(struct net_device * netdev,struct mlx5_core_dev * mdev,const struct mlx5e_profile * new_profile,void * new_ppriv)5912 mlx5e_netdev_attach_profile(struct net_device *netdev, struct mlx5_core_dev *mdev,
5913 			    const struct mlx5e_profile *new_profile, void *new_ppriv)
5914 {
5915 	struct mlx5e_priv *priv = netdev_priv(netdev);
5916 	int err;
5917 
5918 	err = mlx5e_netdev_init_profile(netdev, mdev, new_profile, new_ppriv);
5919 	if (err)
5920 		return err;
5921 
5922 	err = mlx5e_attach_netdev(priv);
5923 	if (err)
5924 		goto profile_cleanup;
5925 	return err;
5926 
5927 profile_cleanup:
5928 	new_profile->cleanup(priv);
5929 	mlx5e_priv_cleanup(priv);
5930 	return err;
5931 }
5932 
mlx5e_netdev_change_profile(struct mlx5e_priv * priv,const struct mlx5e_profile * new_profile,void * new_ppriv)5933 int mlx5e_netdev_change_profile(struct mlx5e_priv *priv,
5934 				const struct mlx5e_profile *new_profile, void *new_ppriv)
5935 {
5936 	const struct mlx5e_profile *orig_profile = priv->profile;
5937 	struct net_device *netdev = priv->netdev;
5938 	struct mlx5_core_dev *mdev = priv->mdev;
5939 	void *orig_ppriv = priv->ppriv;
5940 	int err, rollback_err;
5941 
5942 	/* cleanup old profile */
5943 	mlx5e_detach_netdev(priv);
5944 	priv->profile->cleanup(priv);
5945 	mlx5e_priv_cleanup(priv);
5946 
5947 	if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
5948 		mlx5e_netdev_init_profile(netdev, mdev, new_profile, new_ppriv);
5949 		set_bit(MLX5E_STATE_DESTROYING, &priv->state);
5950 		return -EIO;
5951 	}
5952 
5953 	err = mlx5e_netdev_attach_profile(netdev, mdev, new_profile, new_ppriv);
5954 	if (err) { /* roll back to original profile */
5955 		netdev_warn(netdev, "%s: new profile init failed, %d\n", __func__, err);
5956 		goto rollback;
5957 	}
5958 
5959 	return 0;
5960 
5961 rollback:
5962 	rollback_err = mlx5e_netdev_attach_profile(netdev, mdev, orig_profile, orig_ppriv);
5963 	if (rollback_err)
5964 		netdev_err(netdev, "%s: failed to rollback to orig profile, %d\n",
5965 			   __func__, rollback_err);
5966 	return err;
5967 }
5968 
mlx5e_netdev_attach_nic_profile(struct mlx5e_priv * priv)5969 void mlx5e_netdev_attach_nic_profile(struct mlx5e_priv *priv)
5970 {
5971 	mlx5e_netdev_change_profile(priv, &mlx5e_nic_profile, NULL);
5972 }
5973 
mlx5e_destroy_netdev(struct mlx5e_priv * priv)5974 void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
5975 {
5976 	struct net_device *netdev = priv->netdev;
5977 
5978 	mlx5e_priv_cleanup(priv);
5979 	free_netdev(netdev);
5980 }
5981 
mlx5e_resume(struct auxiliary_device * adev)5982 static int mlx5e_resume(struct auxiliary_device *adev)
5983 {
5984 	struct mlx5_adev *edev = container_of(adev, struct mlx5_adev, adev);
5985 	struct mlx5e_dev *mlx5e_dev = auxiliary_get_drvdata(adev);
5986 	struct mlx5e_priv *priv = mlx5e_dev->priv;
5987 	struct net_device *netdev = priv->netdev;
5988 	struct mlx5_core_dev *mdev = edev->mdev;
5989 	int err;
5990 
5991 	if (netif_device_present(netdev))
5992 		return 0;
5993 
5994 	err = mlx5e_create_mdev_resources(mdev);
5995 	if (err)
5996 		return err;
5997 
5998 	err = mlx5e_attach_netdev(priv);
5999 	if (err) {
6000 		mlx5e_destroy_mdev_resources(mdev);
6001 		return err;
6002 	}
6003 
6004 	return 0;
6005 }
6006 
mlx5e_suspend(struct auxiliary_device * adev,pm_message_t state)6007 static int mlx5e_suspend(struct auxiliary_device *adev, pm_message_t state)
6008 {
6009 	struct mlx5e_dev *mlx5e_dev = auxiliary_get_drvdata(adev);
6010 	struct mlx5e_priv *priv = mlx5e_dev->priv;
6011 	struct net_device *netdev = priv->netdev;
6012 	struct mlx5_core_dev *mdev = priv->mdev;
6013 
6014 	if (!netif_device_present(netdev)) {
6015 		if (test_bit(MLX5E_STATE_DESTROYING, &priv->state))
6016 			mlx5e_destroy_mdev_resources(mdev);
6017 		return -ENODEV;
6018 	}
6019 
6020 	mlx5e_detach_netdev(priv);
6021 	mlx5e_destroy_mdev_resources(mdev);
6022 	return 0;
6023 }
6024 
mlx5e_probe(struct auxiliary_device * adev,const struct auxiliary_device_id * id)6025 static int mlx5e_probe(struct auxiliary_device *adev,
6026 		       const struct auxiliary_device_id *id)
6027 {
6028 	struct mlx5_adev *edev = container_of(adev, struct mlx5_adev, adev);
6029 	const struct mlx5e_profile *profile = &mlx5e_nic_profile;
6030 	struct mlx5_core_dev *mdev = edev->mdev;
6031 	struct mlx5e_dev *mlx5e_dev;
6032 	struct net_device *netdev;
6033 	pm_message_t state = {};
6034 	struct mlx5e_priv *priv;
6035 	int err;
6036 
6037 	mlx5e_dev = mlx5e_create_devlink(&adev->dev, mdev);
6038 	if (IS_ERR(mlx5e_dev))
6039 		return PTR_ERR(mlx5e_dev);
6040 	auxiliary_set_drvdata(adev, mlx5e_dev);
6041 
6042 	err = mlx5e_devlink_port_register(mlx5e_dev, mdev);
6043 	if (err) {
6044 		mlx5_core_err(mdev, "mlx5e_devlink_port_register failed, %d\n", err);
6045 		goto err_devlink_unregister;
6046 	}
6047 
6048 	netdev = mlx5e_create_netdev(mdev, profile);
6049 	if (!netdev) {
6050 		mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
6051 		err = -ENOMEM;
6052 		goto err_devlink_port_unregister;
6053 	}
6054 	SET_NETDEV_DEVLINK_PORT(netdev, &mlx5e_dev->dl_port);
6055 
6056 	mlx5e_build_nic_netdev(netdev);
6057 
6058 	priv = netdev_priv(netdev);
6059 	mlx5e_dev->priv = priv;
6060 
6061 	priv->profile = profile;
6062 	priv->ppriv = NULL;
6063 
6064 	err = profile->init(mdev, netdev);
6065 	if (err) {
6066 		mlx5_core_err(mdev, "mlx5e_nic_profile init failed, %d\n", err);
6067 		goto err_destroy_netdev;
6068 	}
6069 
6070 	err = mlx5e_resume(adev);
6071 	if (err) {
6072 		mlx5_core_err(mdev, "mlx5e_resume failed, %d\n", err);
6073 		goto err_profile_cleanup;
6074 	}
6075 
6076 	err = register_netdev(netdev);
6077 	if (err) {
6078 		mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
6079 		goto err_resume;
6080 	}
6081 
6082 	mlx5e_dcbnl_init_app(priv);
6083 	mlx5_core_uplink_netdev_set(mdev, netdev);
6084 	mlx5e_params_print_info(mdev, &priv->channels.params);
6085 	return 0;
6086 
6087 err_resume:
6088 	mlx5e_suspend(adev, state);
6089 err_profile_cleanup:
6090 	profile->cleanup(priv);
6091 err_destroy_netdev:
6092 	mlx5e_destroy_netdev(priv);
6093 err_devlink_port_unregister:
6094 	mlx5e_devlink_port_unregister(mlx5e_dev);
6095 err_devlink_unregister:
6096 	mlx5e_destroy_devlink(mlx5e_dev);
6097 	return err;
6098 }
6099 
mlx5e_remove(struct auxiliary_device * adev)6100 static void mlx5e_remove(struct auxiliary_device *adev)
6101 {
6102 	struct mlx5e_dev *mlx5e_dev = auxiliary_get_drvdata(adev);
6103 	struct mlx5e_priv *priv = mlx5e_dev->priv;
6104 	pm_message_t state = {};
6105 
6106 	mlx5_core_uplink_netdev_set(priv->mdev, NULL);
6107 	mlx5e_dcbnl_delete_app(priv);
6108 	unregister_netdev(priv->netdev);
6109 	mlx5e_suspend(adev, state);
6110 	priv->profile->cleanup(priv);
6111 	mlx5e_destroy_netdev(priv);
6112 	mlx5e_devlink_port_unregister(mlx5e_dev);
6113 	mlx5e_destroy_devlink(mlx5e_dev);
6114 }
6115 
6116 static const struct auxiliary_device_id mlx5e_id_table[] = {
6117 	{ .name = MLX5_ADEV_NAME ".eth", },
6118 	{},
6119 };
6120 
6121 MODULE_DEVICE_TABLE(auxiliary, mlx5e_id_table);
6122 
6123 static struct auxiliary_driver mlx5e_driver = {
6124 	.name = "eth",
6125 	.probe = mlx5e_probe,
6126 	.remove = mlx5e_remove,
6127 	.suspend = mlx5e_suspend,
6128 	.resume = mlx5e_resume,
6129 	.id_table = mlx5e_id_table,
6130 };
6131 
mlx5e_init(void)6132 int mlx5e_init(void)
6133 {
6134 	int ret;
6135 
6136 	mlx5e_build_ptys2ethtool_map();
6137 	ret = auxiliary_driver_register(&mlx5e_driver);
6138 	if (ret)
6139 		return ret;
6140 
6141 	ret = mlx5e_rep_init();
6142 	if (ret)
6143 		auxiliary_driver_unregister(&mlx5e_driver);
6144 	return ret;
6145 }
6146 
mlx5e_cleanup(void)6147 void mlx5e_cleanup(void)
6148 {
6149 	mlx5e_rep_cleanup();
6150 	auxiliary_driver_unregister(&mlx5e_driver);
6151 }
6152