1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * TI Camera Access Layer (CAL)
4  *
5  * Copyright (c) 2015-2020 Texas Instruments Inc.
6  *
7  * Authors:
8  *	Benoit Parrot <bparrot@ti.com>
9  *	Laurent Pinchart <laurent.pinchart@ideasonboard.com>
10  */
11 #ifndef __TI_CAL_H__
12 #define __TI_CAL_H__
13 
14 #include <linux/bitfield.h>
15 #include <linux/io.h>
16 #include <linux/list.h>
17 #include <linux/mutex.h>
18 #include <linux/spinlock.h>
19 #include <linux/videodev2.h>
20 #include <linux/wait.h>
21 
22 #include <media/media-device.h>
23 #include <media/v4l2-async.h>
24 #include <media/v4l2-ctrls.h>
25 #include <media/v4l2-dev.h>
26 #include <media/v4l2-device.h>
27 #include <media/v4l2-fwnode.h>
28 #include <media/v4l2-subdev.h>
29 #include <media/videobuf2-v4l2.h>
30 
31 #define CAL_MODULE_NAME			"cal"
32 #define CAL_MAX_NUM_CONTEXT		8
33 #define CAL_NUM_CSI2_PORTS		2
34 
35 /*
36  * The width is limited by the size of the CAL_WR_DMA_XSIZE_j.XSIZE field,
37  * expressed in multiples of 64 bits. The height is limited by the size of the
38  * CAL_CSI2_CTXi_j.CTXi_LINES and CAL_WR_DMA_CTRL_j.YSIZE fields, expressed in
39  * lines.
40  */
41 #define CAL_MIN_WIDTH_BYTES		16
42 #define CAL_MAX_WIDTH_BYTES		(8192 * 8)
43 #define CAL_MIN_HEIGHT_LINES		1
44 #define CAL_MAX_HEIGHT_LINES		16383
45 
46 #define CAL_CAMERARX_PAD_SINK		0
47 #define CAL_CAMERARX_PAD_FIRST_SOURCE	1
48 #define CAL_CAMERARX_NUM_SOURCE_PADS	1
49 #define CAL_CAMERARX_NUM_PADS		(1 + CAL_CAMERARX_NUM_SOURCE_PADS)
50 
cal_rx_pad_is_sink(u32 pad)51 static inline bool cal_rx_pad_is_sink(u32 pad)
52 {
53 	/* Camera RX has 1 sink pad, and N source pads */
54 	return pad == 0;
55 }
56 
cal_rx_pad_is_source(u32 pad)57 static inline bool cal_rx_pad_is_source(u32 pad)
58 {
59 	/* Camera RX has 1 sink pad, and N source pads */
60 	return pad >= CAL_CAMERARX_PAD_FIRST_SOURCE &&
61 	       pad <= CAL_CAMERARX_NUM_SOURCE_PADS;
62 }
63 
64 struct device;
65 struct device_node;
66 struct resource;
67 struct regmap;
68 struct regmap_fied;
69 
70 /* CTRL_CORE_CAMERRX_CONTROL register field id */
71 enum cal_camerarx_field {
72 	F_CTRLCLKEN,
73 	F_CAMMODE,
74 	F_LANEENABLE,
75 	F_CSI_MODE,
76 	F_MAX_FIELDS,
77 };
78 
79 enum cal_dma_state {
80 	CAL_DMA_RUNNING,
81 	CAL_DMA_STOP_REQUESTED,
82 	CAL_DMA_STOP_PENDING,
83 	CAL_DMA_STOPPED,
84 };
85 
86 struct cal_format_info {
87 	u32	fourcc;
88 	u32	code;
89 	/* Bits per pixel */
90 	u8	bpp;
91 	bool	meta;
92 };
93 
94 /* buffer for one video frame */
95 struct cal_buffer {
96 	/* common v4l buffer stuff -- must be first */
97 	struct vb2_v4l2_buffer	vb;
98 	struct list_head	list;
99 };
100 
101 /**
102  * struct cal_dmaqueue - Queue of DMA buffers
103  */
104 struct cal_dmaqueue {
105 	/**
106 	 * @lock: Protects all fields in the cal_dmaqueue.
107 	 */
108 	spinlock_t		lock;
109 
110 	/**
111 	 * @queue: Buffers queued to the driver and waiting for DMA processing.
112 	 * Buffers are added to the list by the vb2 .buffer_queue() operation,
113 	 * and move to @pending when they are scheduled for the next frame.
114 	 */
115 	struct list_head	queue;
116 	/**
117 	 * @pending: Buffer provided to the hardware to DMA the next frame.
118 	 * Will move to @active at the end of the current frame.
119 	 */
120 	struct cal_buffer	*pending;
121 	/**
122 	 * @active: Buffer being DMA'ed to for the current frame. Will be
123 	 * retired and given back to vb2 at the end of the current frame if
124 	 * a @pending buffer has been scheduled to replace it.
125 	 */
126 	struct cal_buffer	*active;
127 
128 	/** @state: State of the DMA engine. */
129 	enum cal_dma_state	state;
130 	/** @wait: Wait queue to signal a @state transition to CAL_DMA_STOPPED. */
131 	struct wait_queue_head	wait;
132 };
133 
134 struct cal_camerarx_data {
135 	struct {
136 		unsigned int lsb;
137 		unsigned int msb;
138 	} fields[F_MAX_FIELDS];
139 	unsigned int num_lanes;
140 };
141 
142 struct cal_data {
143 	const struct cal_camerarx_data *camerarx;
144 	unsigned int num_csi2_phy;
145 	unsigned int flags;
146 };
147 
148 /*
149  * The Camera Adaptation Layer (CAL) module is paired with one or more complex
150  * I/O PHYs (CAMERARX). It contains multiple instances of CSI-2, processing and
151  * DMA contexts.
152  *
153  * The cal_dev structure represents the whole subsystem, including the CAL and
154  * the CAMERARX instances. Instances of struct cal_dev are named cal through the
155  * driver.
156  *
157  * The cal_camerarx structure represents one CAMERARX instance. Instances of
158  * cal_camerarx are named phy through the driver.
159  *
160  * The cal_ctx structure represents the combination of one CSI-2 context, one
161  * processing context and one DMA context. Instance of struct cal_ctx are named
162  * ctx through the driver.
163  */
164 
165 struct cal_camerarx {
166 	void __iomem		*base;
167 	struct resource		*res;
168 	struct regmap_field	*fields[F_MAX_FIELDS];
169 
170 	struct cal_dev		*cal;
171 	unsigned int		instance;
172 
173 	struct v4l2_fwnode_endpoint	endpoint;
174 	struct device_node	*source_ep_node;
175 	struct device_node	*source_node;
176 	struct v4l2_subdev	*source;
177 
178 	struct v4l2_subdev	subdev;
179 	struct media_pad	pads[CAL_CAMERARX_NUM_PADS];
180 
181 	/* protects the vc_* fields below */
182 	spinlock_t		vc_lock;
183 	u8			vc_enable_count[4];
184 	u16			vc_frame_number[4];
185 	u32			vc_sequence[4];
186 
187 	unsigned int		enable_count;
188 };
189 
190 struct cal_dev {
191 	struct clk		*fclk;
192 	int			irq;
193 	void __iomem		*base;
194 	struct resource		*res;
195 	struct device		*dev;
196 
197 	const struct cal_data	*data;
198 	u32			revision;
199 
200 	/* Control Module handle */
201 	struct regmap		*syscon_camerrx;
202 	u32			syscon_camerrx_offset;
203 
204 	/* Camera Core Module handle */
205 	struct cal_camerarx	*phy[CAL_NUM_CSI2_PORTS];
206 
207 	u32 num_contexts;
208 	struct cal_ctx		*ctx[CAL_MAX_NUM_CONTEXT];
209 
210 	struct media_device	mdev;
211 	struct v4l2_device	v4l2_dev;
212 	struct v4l2_async_notifier notifier;
213 
214 	unsigned long		reserved_pix_proc_mask;
215 };
216 
217 /*
218  * There is one cal_ctx structure for each camera core context.
219  */
220 struct cal_ctx {
221 	struct v4l2_ctrl_handler ctrl_handler;
222 	struct video_device	vdev;
223 	struct media_pad	pad;
224 
225 	struct cal_dev		*cal;
226 	struct cal_camerarx	*phy;
227 
228 	/* v4l2_ioctl mutex */
229 	struct mutex		mutex;
230 
231 	struct cal_dmaqueue	dma;
232 
233 	/* video capture */
234 	const struct cal_format_info	*fmtinfo;
235 	/* Used to store current pixel format */
236 	struct v4l2_format	v_fmt;
237 
238 	/* Current subdev enumerated format (legacy) */
239 	const struct cal_format_info	**active_fmt;
240 	unsigned int		num_active_fmt;
241 
242 	struct vb2_queue	vb_vidq;
243 	u8			dma_ctx;
244 	u8			cport;
245 	u8			csi2_ctx;
246 	u8			pix_proc;
247 	u8			vc;
248 	u8			datatype;
249 
250 	bool			use_pix_proc;
251 };
252 
253 extern unsigned int cal_debug;
254 extern int cal_video_nr;
255 extern bool cal_mc_api;
256 
257 #define cal_dbg(level, cal, fmt, arg...)				\
258 	do {								\
259 		if (cal_debug >= (level))				\
260 			dev_printk(KERN_DEBUG, (cal)->dev, fmt, ##arg);	\
261 	} while (0)
262 #define cal_info(cal, fmt, arg...)					\
263 	dev_info((cal)->dev, fmt, ##arg)
264 #define cal_err(cal, fmt, arg...)					\
265 	dev_err((cal)->dev, fmt, ##arg)
266 
267 #define ctx_dbg(level, ctx, fmt, arg...)				\
268 	cal_dbg(level, (ctx)->cal, "ctx%u: " fmt, (ctx)->dma_ctx, ##arg)
269 #define ctx_info(ctx, fmt, arg...)					\
270 	cal_info((ctx)->cal, "ctx%u: " fmt, (ctx)->dma_ctx, ##arg)
271 #define ctx_err(ctx, fmt, arg...)					\
272 	cal_err((ctx)->cal, "ctx%u: " fmt, (ctx)->dma_ctx, ##arg)
273 
274 #define phy_dbg(level, phy, fmt, arg...)				\
275 	cal_dbg(level, (phy)->cal, "phy%u: " fmt, (phy)->instance, ##arg)
276 #define phy_info(phy, fmt, arg...)					\
277 	cal_info((phy)->cal, "phy%u: " fmt, (phy)->instance, ##arg)
278 #define phy_err(phy, fmt, arg...)					\
279 	cal_err((phy)->cal, "phy%u: " fmt, (phy)->instance, ##arg)
280 
cal_read(struct cal_dev * cal,u32 offset)281 static inline u32 cal_read(struct cal_dev *cal, u32 offset)
282 {
283 	return ioread32(cal->base + offset);
284 }
285 
cal_write(struct cal_dev * cal,u32 offset,u32 val)286 static inline void cal_write(struct cal_dev *cal, u32 offset, u32 val)
287 {
288 	iowrite32(val, cal->base + offset);
289 }
290 
cal_read_field(struct cal_dev * cal,u32 offset,u32 mask)291 static __always_inline u32 cal_read_field(struct cal_dev *cal, u32 offset, u32 mask)
292 {
293 	return FIELD_GET(mask, cal_read(cal, offset));
294 }
295 
cal_write_field(struct cal_dev * cal,u32 offset,u32 value,u32 mask)296 static inline void cal_write_field(struct cal_dev *cal, u32 offset, u32 value,
297 				   u32 mask)
298 {
299 	u32 val = cal_read(cal, offset);
300 
301 	val &= ~mask;
302 	val |= (value << __ffs(mask)) & mask;
303 	cal_write(cal, offset, val);
304 }
305 
cal_set_field(u32 * valp,u32 field,u32 mask)306 static inline void cal_set_field(u32 *valp, u32 field, u32 mask)
307 {
308 	u32 val = *valp;
309 
310 	val &= ~mask;
311 	val |= (field << __ffs(mask)) & mask;
312 	*valp = val;
313 }
314 
315 extern const struct cal_format_info cal_formats[];
316 extern const unsigned int cal_num_formats;
317 const struct cal_format_info *cal_format_by_fourcc(u32 fourcc);
318 const struct cal_format_info *cal_format_by_code(u32 code);
319 
320 void cal_quickdump_regs(struct cal_dev *cal);
321 
322 void cal_camerarx_disable(struct cal_camerarx *phy);
323 void cal_camerarx_i913_errata(struct cal_camerarx *phy);
324 struct cal_camerarx *cal_camerarx_create(struct cal_dev *cal,
325 					 unsigned int instance);
326 void cal_camerarx_destroy(struct cal_camerarx *phy);
327 
328 int cal_ctx_prepare(struct cal_ctx *ctx);
329 void cal_ctx_unprepare(struct cal_ctx *ctx);
330 void cal_ctx_set_dma_addr(struct cal_ctx *ctx, dma_addr_t addr);
331 void cal_ctx_start(struct cal_ctx *ctx);
332 void cal_ctx_stop(struct cal_ctx *ctx);
333 
334 int cal_ctx_v4l2_register(struct cal_ctx *ctx);
335 void cal_ctx_v4l2_unregister(struct cal_ctx *ctx);
336 int cal_ctx_v4l2_init(struct cal_ctx *ctx);
337 void cal_ctx_v4l2_cleanup(struct cal_ctx *ctx);
338 
339 #endif /* __TI_CAL_H__ */
340