1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Driver for Renesas RZ/G2L CRU
4  *
5  * Copyright (C) 2022 Renesas Electronics Corp.
6  */
7 
8 #ifndef __RZG2L_CRU__
9 #define __RZG2L_CRU__
10 
11 #include <linux/reset.h>
12 
13 #include <media/v4l2-async.h>
14 #include <media/v4l2-dev.h>
15 #include <media/v4l2-device.h>
16 #include <media/videobuf2-v4l2.h>
17 
18 /* Number of HW buffers */
19 #define RZG2L_CRU_HW_BUFFER_MAX		8
20 #define RZG2L_CRU_HW_BUFFER_DEFAULT	3
21 
22 /* Address alignment mask for HW buffers */
23 #define RZG2L_CRU_HW_BUFFER_MASK	0x1ff
24 
25 /* Maximum number of CSI2 virtual channels */
26 #define RZG2L_CRU_CSI2_VCHANNEL		4
27 
28 #define RZG2L_CRU_MIN_INPUT_WIDTH	320
29 #define RZG2L_CRU_MAX_INPUT_WIDTH	2800
30 #define RZG2L_CRU_MIN_INPUT_HEIGHT	240
31 #define RZG2L_CRU_MAX_INPUT_HEIGHT	4095
32 
33 /**
34  * enum rzg2l_cru_dma_state - DMA states
35  * @RZG2L_CRU_DMA_STOPPED:   No operation in progress
36  * @RZG2L_CRU_DMA_STARTING:  Capture starting up
37  * @RZG2L_CRU_DMA_RUNNING:   Operation in progress have buffers
38  * @RZG2L_CRU_DMA_STOPPING:  Stopping operation
39  */
40 enum rzg2l_cru_dma_state {
41 	RZG2L_CRU_DMA_STOPPED = 0,
42 	RZG2L_CRU_DMA_STARTING,
43 	RZG2L_CRU_DMA_RUNNING,
44 	RZG2L_CRU_DMA_STOPPING,
45 };
46 
47 struct rzg2l_cru_csi {
48 	struct v4l2_async_connection *asd;
49 	struct v4l2_subdev *subdev;
50 	u32 channel;
51 };
52 
53 struct rzg2l_cru_ip {
54 	struct v4l2_subdev subdev;
55 	struct media_pad pads[2];
56 	struct v4l2_async_notifier notifier;
57 	struct v4l2_subdev *remote;
58 };
59 
60 /**
61  * struct rzg2l_cru_dev - Renesas CRU device structure
62  * @dev:		(OF) device
63  * @base:		device I/O register space remapped to virtual memory
64  * @info:		info about CRU instance
65  *
66  * @presetn:		CRU_PRESETN reset line
67  * @aresetn:		CRU_ARESETN reset line
68  *
69  * @vclk:		CRU Main clock
70  *
71  * @image_conv_irq:	Holds image conversion interrupt number
72  *
73  * @vdev:		V4L2 video device associated with CRU
74  * @v4l2_dev:		V4L2 device
75  * @num_buf:		Holds the current number of buffers enabled
76  * @notifier:		V4L2 asynchronous subdevs notifier
77  *
78  * @ip:			Image processing subdev info
79  * @csi:		CSI info
80  * @mdev:		media device
81  * @mdev_lock:		protects the count, notifier and csi members
82  * @pad:		media pad for the video device entity
83  *
84  * @lock:		protects @queue
85  * @queue:		vb2 buffers queue
86  * @scratch:		cpu address for scratch buffer
87  * @scratch_phys:	physical address of the scratch buffer
88  *
89  * @qlock:		protects @queue_buf, @buf_list, @sequence
90  *			@state
91  * @queue_buf:		Keeps track of buffers given to HW slot
92  * @buf_list:		list of queued buffers
93  * @sequence:		V4L2 buffers sequence number
94  * @state:		keeps track of operation state
95  *
96  * @format:		active V4L2 pixel format
97  */
98 struct rzg2l_cru_dev {
99 	struct device *dev;
100 	void __iomem *base;
101 	const struct rzg2l_cru_info *info;
102 
103 	struct reset_control *presetn;
104 	struct reset_control *aresetn;
105 
106 	struct clk *vclk;
107 
108 	int image_conv_irq;
109 
110 	struct video_device vdev;
111 	struct v4l2_device v4l2_dev;
112 	u8 num_buf;
113 
114 	struct v4l2_async_notifier notifier;
115 
116 	struct rzg2l_cru_ip ip;
117 	struct rzg2l_cru_csi csi;
118 	struct media_device mdev;
119 	struct mutex mdev_lock;
120 	struct media_pad pad;
121 
122 	struct mutex lock;
123 	struct vb2_queue queue;
124 	void *scratch;
125 	dma_addr_t scratch_phys;
126 
127 	spinlock_t qlock;
128 	struct vb2_v4l2_buffer *queue_buf[RZG2L_CRU_HW_BUFFER_MAX];
129 	struct list_head buf_list;
130 	unsigned int sequence;
131 	enum rzg2l_cru_dma_state state;
132 
133 	struct v4l2_pix_format format;
134 };
135 
136 void rzg2l_cru_vclk_unprepare(struct rzg2l_cru_dev *cru);
137 int rzg2l_cru_vclk_prepare(struct rzg2l_cru_dev *cru);
138 
139 int rzg2l_cru_start_image_processing(struct rzg2l_cru_dev *cru);
140 void rzg2l_cru_stop_image_processing(struct rzg2l_cru_dev *cru);
141 
142 int rzg2l_cru_dma_register(struct rzg2l_cru_dev *cru);
143 void rzg2l_cru_dma_unregister(struct rzg2l_cru_dev *cru);
144 
145 int rzg2l_cru_video_register(struct rzg2l_cru_dev *cru);
146 void rzg2l_cru_video_unregister(struct rzg2l_cru_dev *cru);
147 
148 const struct v4l2_format_info *rzg2l_cru_format_from_pixel(u32 format);
149 
150 int rzg2l_cru_ip_subdev_register(struct rzg2l_cru_dev *cru);
151 void rzg2l_cru_ip_subdev_unregister(struct rzg2l_cru_dev *cru);
152 struct v4l2_mbus_framefmt *rzg2l_cru_ip_get_src_fmt(struct rzg2l_cru_dev *cru);
153 
154 #endif
155