1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2021 Sieć Badawcza Łukasiewicz
4 * - Przemysłowy Instytut Automatyki i Pomiarów PIAP
5 * Written by Krzysztof Hałasa
6 */
7
8 #include <linux/clk.h>
9 #include <linux/delay.h>
10 #include <linux/pm_runtime.h>
11
12 #include <media/v4l2-ctrls.h>
13 #include <media/v4l2-fwnode.h>
14 #include <media/v4l2-subdev.h>
15
16 /* External clock (extclk) frequencies */
17 #define AR0521_EXTCLK_MIN (10 * 1000 * 1000)
18 #define AR0521_EXTCLK_MAX (48 * 1000 * 1000)
19
20 /* PLL and PLL2 */
21 #define AR0521_PLL_MIN (320 * 1000 * 1000)
22 #define AR0521_PLL_MAX (1280 * 1000 * 1000)
23
24 /* Effective pixel sample rate on the pixel array. */
25 #define AR0521_PIXEL_CLOCK_RATE (184 * 1000 * 1000)
26 #define AR0521_PIXEL_CLOCK_MIN (168 * 1000 * 1000)
27 #define AR0521_PIXEL_CLOCK_MAX (414 * 1000 * 1000)
28
29 #define AR0521_NATIVE_WIDTH 2604u
30 #define AR0521_NATIVE_HEIGHT 1964u
31 #define AR0521_MIN_X_ADDR_START 0u
32 #define AR0521_MIN_Y_ADDR_START 0u
33 #define AR0521_MAX_X_ADDR_END 2603u
34 #define AR0521_MAX_Y_ADDR_END 1955u
35
36 #define AR0521_WIDTH_MIN 8u
37 #define AR0521_WIDTH_MAX 2592u
38 #define AR0521_HEIGHT_MIN 8u
39 #define AR0521_HEIGHT_MAX 1944u
40
41 #define AR0521_WIDTH_BLANKING_MIN 572u
42 #define AR0521_HEIGHT_BLANKING_MIN 38u /* must be even */
43 #define AR0521_TOTAL_HEIGHT_MAX 65535u /* max_frame_length_lines */
44 #define AR0521_TOTAL_WIDTH_MAX 65532u /* max_line_length_pck */
45
46 #define AR0521_ANA_GAIN_MIN 0x00
47 #define AR0521_ANA_GAIN_MAX 0x3f
48 #define AR0521_ANA_GAIN_STEP 0x01
49 #define AR0521_ANA_GAIN_DEFAULT 0x00
50
51 /* AR0521 registers */
52 #define AR0521_REG_VT_PIX_CLK_DIV 0x0300
53 #define AR0521_REG_FRAME_LENGTH_LINES 0x0340
54
55 #define AR0521_REG_CHIP_ID 0x3000
56 #define AR0521_REG_COARSE_INTEGRATION_TIME 0x3012
57 #define AR0521_REG_ROW_SPEED 0x3016
58 #define AR0521_REG_EXTRA_DELAY 0x3018
59 #define AR0521_REG_RESET 0x301A
60 #define AR0521_REG_RESET_DEFAULTS 0x0238
61 #define AR0521_REG_RESET_GROUP_PARAM_HOLD 0x8000
62 #define AR0521_REG_RESET_STREAM BIT(2)
63 #define AR0521_REG_RESET_RESTART BIT(1)
64 #define AR0521_REG_RESET_INIT BIT(0)
65
66 #define AR0521_REG_ANA_GAIN_CODE_GLOBAL 0x3028
67
68 #define AR0521_REG_GREEN1_GAIN 0x3056
69 #define AR0521_REG_BLUE_GAIN 0x3058
70 #define AR0521_REG_RED_GAIN 0x305A
71 #define AR0521_REG_GREEN2_GAIN 0x305C
72 #define AR0521_REG_GLOBAL_GAIN 0x305E
73
74 #define AR0521_REG_HISPI_TEST_MODE 0x3066
75 #define AR0521_REG_HISPI_TEST_MODE_LP11 0x0004
76
77 #define AR0521_REG_TEST_PATTERN_MODE 0x3070
78
79 #define AR0521_REG_SERIAL_FORMAT 0x31AE
80 #define AR0521_REG_SERIAL_FORMAT_MIPI 0x0200
81
82 #define AR0521_REG_HISPI_CONTROL_STATUS 0x31C6
83 #define AR0521_REG_HISPI_CONTROL_STATUS_FRAMER_TEST_MODE_ENABLE 0x80
84
85 #define be cpu_to_be16
86
87 static const char * const ar0521_supply_names[] = {
88 "vdd_io", /* I/O (1.8V) supply */
89 "vdd", /* Core, PLL and MIPI (1.2V) supply */
90 "vaa", /* Analog (2.7V) supply */
91 };
92
93 static const s64 ar0521_link_frequencies[] = {
94 184000000,
95 };
96
97 struct ar0521_ctrls {
98 struct v4l2_ctrl_handler handler;
99 struct {
100 struct v4l2_ctrl *gain;
101 struct v4l2_ctrl *red_balance;
102 struct v4l2_ctrl *blue_balance;
103 };
104 struct {
105 struct v4l2_ctrl *hblank;
106 struct v4l2_ctrl *vblank;
107 };
108 struct v4l2_ctrl *pixrate;
109 struct v4l2_ctrl *exposure;
110 struct v4l2_ctrl *test_pattern;
111 };
112
113 struct ar0521_dev {
114 struct i2c_client *i2c_client;
115 struct v4l2_subdev sd;
116 struct media_pad pad;
117 struct clk *extclk;
118 u32 extclk_freq;
119
120 struct regulator *supplies[ARRAY_SIZE(ar0521_supply_names)];
121 struct gpio_desc *reset_gpio;
122
123 /* lock to protect all members below */
124 struct mutex lock;
125
126 struct v4l2_mbus_framefmt fmt;
127 struct ar0521_ctrls ctrls;
128 unsigned int lane_count;
129 struct {
130 u16 pre;
131 u16 mult;
132 u16 pre2;
133 u16 mult2;
134 u16 vt_pix;
135 } pll;
136
137 bool streaming;
138 };
139
to_ar0521_dev(struct v4l2_subdev * sd)140 static inline struct ar0521_dev *to_ar0521_dev(struct v4l2_subdev *sd)
141 {
142 return container_of(sd, struct ar0521_dev, sd);
143 }
144
ctrl_to_sd(struct v4l2_ctrl * ctrl)145 static inline struct v4l2_subdev *ctrl_to_sd(struct v4l2_ctrl *ctrl)
146 {
147 return &container_of(ctrl->handler, struct ar0521_dev,
148 ctrls.handler)->sd;
149 }
150
div64_round(u64 v,u32 d)151 static u32 div64_round(u64 v, u32 d)
152 {
153 return div_u64(v + (d >> 1), d);
154 }
155
div64_round_up(u64 v,u32 d)156 static u32 div64_round_up(u64 v, u32 d)
157 {
158 return div_u64(v + d - 1, d);
159 }
160
ar0521_code_to_bpp(struct ar0521_dev * sensor)161 static int ar0521_code_to_bpp(struct ar0521_dev *sensor)
162 {
163 switch (sensor->fmt.code) {
164 case MEDIA_BUS_FMT_SGRBG8_1X8:
165 return 8;
166 }
167
168 return -EINVAL;
169 }
170
171 /* Data must be BE16, the first value is the register address */
ar0521_write_regs(struct ar0521_dev * sensor,const __be16 * data,unsigned int count)172 static int ar0521_write_regs(struct ar0521_dev *sensor, const __be16 *data,
173 unsigned int count)
174 {
175 struct i2c_client *client = sensor->i2c_client;
176 struct i2c_msg msg;
177 int ret;
178
179 msg.addr = client->addr;
180 msg.flags = client->flags;
181 msg.buf = (u8 *)data;
182 msg.len = count * sizeof(*data);
183
184 ret = i2c_transfer(client->adapter, &msg, 1);
185
186 if (ret < 0) {
187 v4l2_err(&sensor->sd, "%s: I2C write error\n", __func__);
188 return ret;
189 }
190
191 return 0;
192 }
193
ar0521_write_reg(struct ar0521_dev * sensor,u16 reg,u16 val)194 static int ar0521_write_reg(struct ar0521_dev *sensor, u16 reg, u16 val)
195 {
196 __be16 buf[2] = {be(reg), be(val)};
197
198 return ar0521_write_regs(sensor, buf, 2);
199 }
200
ar0521_set_geometry(struct ar0521_dev * sensor)201 static int ar0521_set_geometry(struct ar0521_dev *sensor)
202 {
203 /* Center the image in the visible output window. */
204 u16 x = clamp((AR0521_WIDTH_MAX - sensor->fmt.width) / 2,
205 AR0521_MIN_X_ADDR_START, AR0521_MAX_X_ADDR_END);
206 u16 y = clamp(((AR0521_HEIGHT_MAX - sensor->fmt.height) / 2) & ~1,
207 AR0521_MIN_Y_ADDR_START, AR0521_MAX_Y_ADDR_END);
208
209 /* All dimensions are unsigned 12-bit integers */
210 __be16 regs[] = {
211 be(AR0521_REG_FRAME_LENGTH_LINES),
212 be(sensor->fmt.height + sensor->ctrls.vblank->val),
213 be(sensor->fmt.width + sensor->ctrls.hblank->val),
214 be(x),
215 be(y),
216 be(x + sensor->fmt.width - 1),
217 be(y + sensor->fmt.height - 1),
218 be(sensor->fmt.width),
219 be(sensor->fmt.height)
220 };
221
222 return ar0521_write_regs(sensor, regs, ARRAY_SIZE(regs));
223 }
224
ar0521_set_gains(struct ar0521_dev * sensor)225 static int ar0521_set_gains(struct ar0521_dev *sensor)
226 {
227 int green = sensor->ctrls.gain->val;
228 int red = max(green + sensor->ctrls.red_balance->val, 0);
229 int blue = max(green + sensor->ctrls.blue_balance->val, 0);
230 unsigned int gain = min(red, min(green, blue));
231 unsigned int analog = min(gain, 64u); /* range is 0 - 127 */
232 __be16 regs[5];
233
234 red = min(red - analog + 64, 511u);
235 green = min(green - analog + 64, 511u);
236 blue = min(blue - analog + 64, 511u);
237 regs[0] = be(AR0521_REG_GREEN1_GAIN);
238 regs[1] = be(green << 7 | analog);
239 regs[2] = be(blue << 7 | analog);
240 regs[3] = be(red << 7 | analog);
241 regs[4] = be(green << 7 | analog);
242
243 return ar0521_write_regs(sensor, regs, ARRAY_SIZE(regs));
244 }
245
calc_pll(struct ar0521_dev * sensor,u32 freq,u16 * pre_ptr,u16 * mult_ptr)246 static u32 calc_pll(struct ar0521_dev *sensor, u32 freq, u16 *pre_ptr, u16 *mult_ptr)
247 {
248 u16 pre = 1, mult = 1, new_pre;
249 u32 pll = AR0521_PLL_MAX + 1;
250
251 for (new_pre = 1; new_pre < 64; new_pre++) {
252 u32 new_pll;
253 u32 new_mult = div64_round_up((u64)freq * new_pre,
254 sensor->extclk_freq);
255
256 if (new_mult < 32)
257 continue; /* Minimum value */
258 if (new_mult > 254)
259 break; /* Maximum, larger pre won't work either */
260 if (sensor->extclk_freq * (u64)new_mult < AR0521_PLL_MIN *
261 new_pre)
262 continue;
263 if (sensor->extclk_freq * (u64)new_mult > AR0521_PLL_MAX *
264 new_pre)
265 break; /* Larger pre won't work either */
266 new_pll = div64_round_up(sensor->extclk_freq * (u64)new_mult,
267 new_pre);
268 if (new_pll < pll) {
269 pll = new_pll;
270 pre = new_pre;
271 mult = new_mult;
272 }
273 }
274
275 pll = div64_round(sensor->extclk_freq * (u64)mult, pre);
276 *pre_ptr = pre;
277 *mult_ptr = mult;
278 return pll;
279 }
280
ar0521_calc_pll(struct ar0521_dev * sensor)281 static void ar0521_calc_pll(struct ar0521_dev *sensor)
282 {
283 unsigned int pixel_clock;
284 u16 pre, mult;
285 u32 vco;
286 int bpp;
287
288 /*
289 * PLL1 and PLL2 are computed equally even if the application note
290 * suggests a slower PLL1 clock. Maintain pll1 and pll2 divider and
291 * multiplier separated to later specialize the calculation procedure.
292 *
293 * PLL1:
294 * - mclk -> / pre_div1 * pre_mul1 = VCO1 = COUNTER_CLOCK
295 *
296 * PLL2:
297 * - mclk -> / pre_div * pre_mul = VCO
298 *
299 * VCO -> / vt_pix = PIXEL_CLOCK
300 * VCO -> / vt_pix / 2 = WORD_CLOCK
301 * VCO -> / op_sys = SERIAL_CLOCK
302 *
303 * With:
304 * - vt_pix = bpp / 2
305 * - WORD_CLOCK = PIXEL_CLOCK / 2
306 * - SERIAL_CLOCK = MIPI data rate (Mbps / lane) = WORD_CLOCK * bpp
307 * NOTE: this implies the MIPI clock is divided internally by 2
308 * to account for DDR.
309 *
310 * As op_sys_div is fixed to 1:
311 *
312 * SERIAL_CLOCK = VCO
313 * VCO = 2 * MIPI_CLK
314 * VCO = PIXEL_CLOCK * bpp / 2
315 *
316 * In the clock tree:
317 * MIPI_CLK = PIXEL_CLOCK * bpp / 2 / 2
318 *
319 * Generic pixel_rate to bus clock frequencey equation:
320 * MIPI_CLK = V4L2_CID_PIXEL_RATE * bpp / lanes / 2
321 *
322 * From which we derive the PIXEL_CLOCK to use in the clock tree:
323 * PIXEL_CLOCK = V4L2_CID_PIXEL_RATE * 2 / lanes
324 *
325 * Documented clock ranges:
326 * WORD_CLOCK = (35MHz - 120 MHz)
327 * PIXEL_CLOCK = (84MHz - 207MHz)
328 * VCO = (320MHz - 1280MHz)
329 *
330 * TODO: in case we have less data lanes we have to reduce the desired
331 * VCO not to exceed the limits specified by the datasheet and
332 * consequentially reduce the obtained pixel clock.
333 */
334 pixel_clock = AR0521_PIXEL_CLOCK_RATE * 2 / sensor->lane_count;
335 bpp = ar0521_code_to_bpp(sensor);
336 sensor->pll.vt_pix = bpp / 2;
337 vco = pixel_clock * sensor->pll.vt_pix;
338
339 calc_pll(sensor, vco, &pre, &mult);
340
341 sensor->pll.pre = sensor->pll.pre2 = pre;
342 sensor->pll.mult = sensor->pll.mult2 = mult;
343 }
344
ar0521_pll_config(struct ar0521_dev * sensor)345 static int ar0521_pll_config(struct ar0521_dev *sensor)
346 {
347 __be16 pll_regs[] = {
348 be(AR0521_REG_VT_PIX_CLK_DIV),
349 /* 0x300 */ be(sensor->pll.vt_pix), /* vt_pix_clk_div = bpp / 2 */
350 /* 0x302 */ be(1), /* vt_sys_clk_div */
351 /* 0x304 */ be((sensor->pll.pre2 << 8) | sensor->pll.pre),
352 /* 0x306 */ be((sensor->pll.mult2 << 8) | sensor->pll.mult),
353 /* 0x308 */ be(sensor->pll.vt_pix * 2), /* op_pix_clk_div = 2 * vt_pix_clk_div */
354 /* 0x30A */ be(1) /* op_sys_clk_div */
355 };
356
357 ar0521_calc_pll(sensor);
358 return ar0521_write_regs(sensor, pll_regs, ARRAY_SIZE(pll_regs));
359 }
360
ar0521_set_stream(struct ar0521_dev * sensor,bool on)361 static int ar0521_set_stream(struct ar0521_dev *sensor, bool on)
362 {
363 int ret;
364
365 if (on) {
366 ret = pm_runtime_resume_and_get(&sensor->i2c_client->dev);
367 if (ret < 0)
368 return ret;
369
370 /* Stop streaming for just a moment */
371 ret = ar0521_write_reg(sensor, AR0521_REG_RESET,
372 AR0521_REG_RESET_DEFAULTS);
373 if (ret)
374 return ret;
375
376 ret = ar0521_set_geometry(sensor);
377 if (ret)
378 return ret;
379
380 ret = ar0521_pll_config(sensor);
381 if (ret)
382 goto err;
383
384 ret = __v4l2_ctrl_handler_setup(&sensor->ctrls.handler);
385 if (ret)
386 goto err;
387
388 /* Exit LP-11 mode on clock and data lanes */
389 ret = ar0521_write_reg(sensor, AR0521_REG_HISPI_CONTROL_STATUS,
390 0);
391 if (ret)
392 goto err;
393
394 /* Start streaming */
395 ret = ar0521_write_reg(sensor, AR0521_REG_RESET,
396 AR0521_REG_RESET_DEFAULTS |
397 AR0521_REG_RESET_STREAM);
398 if (ret)
399 goto err;
400
401 return 0;
402
403 err:
404 pm_runtime_put(&sensor->i2c_client->dev);
405 return ret;
406
407 } else {
408 /*
409 * Reset gain, the sensor may produce all white pixels without
410 * this
411 */
412 ret = ar0521_write_reg(sensor, AR0521_REG_GLOBAL_GAIN, 0x2000);
413 if (ret)
414 return ret;
415
416 /* Stop streaming */
417 ret = ar0521_write_reg(sensor, AR0521_REG_RESET,
418 AR0521_REG_RESET_DEFAULTS);
419 if (ret)
420 return ret;
421
422 pm_runtime_put(&sensor->i2c_client->dev);
423 return 0;
424 }
425 }
426
ar0521_adj_fmt(struct v4l2_mbus_framefmt * fmt)427 static void ar0521_adj_fmt(struct v4l2_mbus_framefmt *fmt)
428 {
429 fmt->width = clamp(ALIGN(fmt->width, 4), AR0521_WIDTH_MIN,
430 AR0521_WIDTH_MAX);
431 fmt->height = clamp(ALIGN(fmt->height, 4), AR0521_HEIGHT_MIN,
432 AR0521_HEIGHT_MAX);
433 fmt->code = MEDIA_BUS_FMT_SGRBG8_1X8;
434 fmt->field = V4L2_FIELD_NONE;
435 fmt->colorspace = V4L2_COLORSPACE_SRGB;
436 fmt->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
437 fmt->quantization = V4L2_QUANTIZATION_FULL_RANGE;
438 fmt->xfer_func = V4L2_XFER_FUNC_DEFAULT;
439 }
440
ar0521_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * format)441 static int ar0521_get_fmt(struct v4l2_subdev *sd,
442 struct v4l2_subdev_state *sd_state,
443 struct v4l2_subdev_format *format)
444 {
445 struct ar0521_dev *sensor = to_ar0521_dev(sd);
446 struct v4l2_mbus_framefmt *fmt;
447
448 mutex_lock(&sensor->lock);
449
450 if (format->which == V4L2_SUBDEV_FORMAT_TRY)
451 fmt = v4l2_subdev_get_try_format(&sensor->sd, sd_state, 0
452 /* pad */);
453 else
454 fmt = &sensor->fmt;
455
456 format->format = *fmt;
457
458 mutex_unlock(&sensor->lock);
459 return 0;
460 }
461
ar0521_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * format)462 static int ar0521_set_fmt(struct v4l2_subdev *sd,
463 struct v4l2_subdev_state *sd_state,
464 struct v4l2_subdev_format *format)
465 {
466 struct ar0521_dev *sensor = to_ar0521_dev(sd);
467 int max_vblank, max_hblank, exposure_max;
468 int ret;
469
470 ar0521_adj_fmt(&format->format);
471
472 mutex_lock(&sensor->lock);
473
474 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
475 struct v4l2_mbus_framefmt *fmt;
476
477 fmt = v4l2_subdev_get_try_format(sd, sd_state, 0 /* pad */);
478 *fmt = format->format;
479
480 mutex_unlock(&sensor->lock);
481
482 return 0;
483 }
484
485 sensor->fmt = format->format;
486 ar0521_calc_pll(sensor);
487
488 /*
489 * Update the exposure and blankings limits. Blankings are also reset
490 * to the minimum.
491 */
492 max_hblank = AR0521_TOTAL_WIDTH_MAX - sensor->fmt.width;
493 ret = __v4l2_ctrl_modify_range(sensor->ctrls.hblank,
494 sensor->ctrls.hblank->minimum,
495 max_hblank, sensor->ctrls.hblank->step,
496 sensor->ctrls.hblank->minimum);
497 if (ret)
498 goto unlock;
499
500 ret = __v4l2_ctrl_s_ctrl(sensor->ctrls.hblank,
501 sensor->ctrls.hblank->minimum);
502 if (ret)
503 goto unlock;
504
505 max_vblank = AR0521_TOTAL_HEIGHT_MAX - sensor->fmt.height;
506 ret = __v4l2_ctrl_modify_range(sensor->ctrls.vblank,
507 sensor->ctrls.vblank->minimum,
508 max_vblank, sensor->ctrls.vblank->step,
509 sensor->ctrls.vblank->minimum);
510 if (ret)
511 goto unlock;
512
513 ret = __v4l2_ctrl_s_ctrl(sensor->ctrls.vblank,
514 sensor->ctrls.vblank->minimum);
515 if (ret)
516 goto unlock;
517
518 exposure_max = sensor->fmt.height + AR0521_HEIGHT_BLANKING_MIN - 4;
519 ret = __v4l2_ctrl_modify_range(sensor->ctrls.exposure,
520 sensor->ctrls.exposure->minimum,
521 exposure_max,
522 sensor->ctrls.exposure->step,
523 sensor->ctrls.exposure->default_value);
524 unlock:
525 mutex_unlock(&sensor->lock);
526
527 return ret;
528 }
529
ar0521_s_ctrl(struct v4l2_ctrl * ctrl)530 static int ar0521_s_ctrl(struct v4l2_ctrl *ctrl)
531 {
532 struct v4l2_subdev *sd = ctrl_to_sd(ctrl);
533 struct ar0521_dev *sensor = to_ar0521_dev(sd);
534 int exp_max;
535 int ret;
536
537 /* v4l2_ctrl_lock() locks our own mutex */
538
539 switch (ctrl->id) {
540 case V4L2_CID_VBLANK:
541 exp_max = sensor->fmt.height + ctrl->val - 4;
542 __v4l2_ctrl_modify_range(sensor->ctrls.exposure,
543 sensor->ctrls.exposure->minimum,
544 exp_max, sensor->ctrls.exposure->step,
545 sensor->ctrls.exposure->default_value);
546 break;
547 }
548
549 /* access the sensor only if it's powered up */
550 if (!pm_runtime_get_if_in_use(&sensor->i2c_client->dev))
551 return 0;
552
553 switch (ctrl->id) {
554 case V4L2_CID_HBLANK:
555 case V4L2_CID_VBLANK:
556 ret = ar0521_set_geometry(sensor);
557 break;
558 case V4L2_CID_ANALOGUE_GAIN:
559 ret = ar0521_write_reg(sensor, AR0521_REG_ANA_GAIN_CODE_GLOBAL,
560 ctrl->val);
561 break;
562 case V4L2_CID_GAIN:
563 case V4L2_CID_RED_BALANCE:
564 case V4L2_CID_BLUE_BALANCE:
565 ret = ar0521_set_gains(sensor);
566 break;
567 case V4L2_CID_EXPOSURE:
568 ret = ar0521_write_reg(sensor,
569 AR0521_REG_COARSE_INTEGRATION_TIME,
570 ctrl->val);
571 break;
572 case V4L2_CID_TEST_PATTERN:
573 ret = ar0521_write_reg(sensor, AR0521_REG_TEST_PATTERN_MODE,
574 ctrl->val);
575 break;
576 default:
577 dev_err(&sensor->i2c_client->dev,
578 "Unsupported control %x\n", ctrl->id);
579 ret = -EINVAL;
580 break;
581 }
582
583 pm_runtime_put(&sensor->i2c_client->dev);
584 return ret;
585 }
586
587 static const struct v4l2_ctrl_ops ar0521_ctrl_ops = {
588 .s_ctrl = ar0521_s_ctrl,
589 };
590
591 static const char * const test_pattern_menu[] = {
592 "Disabled",
593 "Solid color",
594 "Color bars",
595 "Faded color bars"
596 };
597
ar0521_init_controls(struct ar0521_dev * sensor)598 static int ar0521_init_controls(struct ar0521_dev *sensor)
599 {
600 const struct v4l2_ctrl_ops *ops = &ar0521_ctrl_ops;
601 struct ar0521_ctrls *ctrls = &sensor->ctrls;
602 struct v4l2_ctrl_handler *hdl = &ctrls->handler;
603 int max_vblank, max_hblank, exposure_max;
604 struct v4l2_ctrl *link_freq;
605 int ret;
606
607 v4l2_ctrl_handler_init(hdl, 32);
608
609 /* We can use our own mutex for the ctrl lock */
610 hdl->lock = &sensor->lock;
611
612 /* Analog gain */
613 v4l2_ctrl_new_std(hdl, ops, V4L2_CID_ANALOGUE_GAIN,
614 AR0521_ANA_GAIN_MIN, AR0521_ANA_GAIN_MAX,
615 AR0521_ANA_GAIN_STEP, AR0521_ANA_GAIN_DEFAULT);
616
617 /* Manual gain */
618 ctrls->gain = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAIN, 0, 511, 1, 0);
619 ctrls->red_balance = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_RED_BALANCE,
620 -512, 511, 1, 0);
621 ctrls->blue_balance = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BLUE_BALANCE,
622 -512, 511, 1, 0);
623 v4l2_ctrl_cluster(3, &ctrls->gain);
624
625 /* Initialize blanking limits using the default 2592x1944 format. */
626 max_hblank = AR0521_TOTAL_WIDTH_MAX - AR0521_WIDTH_MAX;
627 ctrls->hblank = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_HBLANK,
628 AR0521_WIDTH_BLANKING_MIN,
629 max_hblank, 1,
630 AR0521_WIDTH_BLANKING_MIN);
631
632 max_vblank = AR0521_TOTAL_HEIGHT_MAX - AR0521_HEIGHT_MAX;
633 ctrls->vblank = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_VBLANK,
634 AR0521_HEIGHT_BLANKING_MIN,
635 max_vblank, 2,
636 AR0521_HEIGHT_BLANKING_MIN);
637 v4l2_ctrl_cluster(2, &ctrls->hblank);
638
639 /* Read-only */
640 ctrls->pixrate = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_PIXEL_RATE,
641 AR0521_PIXEL_CLOCK_MIN,
642 AR0521_PIXEL_CLOCK_MAX, 1,
643 AR0521_PIXEL_CLOCK_RATE);
644
645 /* Manual exposure time: max exposure time = visible + blank - 4 */
646 exposure_max = AR0521_HEIGHT_MAX + AR0521_HEIGHT_BLANKING_MIN - 4;
647 ctrls->exposure = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_EXPOSURE, 0,
648 exposure_max, 1, 0x70);
649
650 link_freq = v4l2_ctrl_new_int_menu(hdl, ops, V4L2_CID_LINK_FREQ,
651 ARRAY_SIZE(ar0521_link_frequencies) - 1,
652 0, ar0521_link_frequencies);
653 if (link_freq)
654 link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
655
656 ctrls->test_pattern = v4l2_ctrl_new_std_menu_items(hdl, ops,
657 V4L2_CID_TEST_PATTERN,
658 ARRAY_SIZE(test_pattern_menu) - 1,
659 0, 0, test_pattern_menu);
660
661 if (hdl->error) {
662 ret = hdl->error;
663 goto free_ctrls;
664 }
665
666 sensor->sd.ctrl_handler = hdl;
667 return 0;
668
669 free_ctrls:
670 v4l2_ctrl_handler_free(hdl);
671 return ret;
672 }
673
674 #define REGS_ENTRY(a) {(a), ARRAY_SIZE(a)}
675 #define REGS(...) REGS_ENTRY(((const __be16[]){__VA_ARGS__}))
676
677 static const struct initial_reg {
678 const __be16 *data; /* data[0] is register address */
679 unsigned int count;
680 } initial_regs[] = {
681 REGS(be(0x0112), be(0x0808)), /* 8-bit/8-bit mode */
682
683 /* PEDESTAL+2 :+2 is a workaround for 10bit mode +0.5 rounding */
684 REGS(be(0x301E), be(0x00AA)),
685
686 /* corrections_recommended_bayer */
687 REGS(be(0x3042),
688 be(0x0004), /* 3042: RNC: enable b/w rnc mode */
689 be(0x4580)), /* 3044: RNC: enable row noise correction */
690
691 REGS(be(0x30D2),
692 be(0x0000), /* 30D2: CRM/CC: enable crm on Visible and CC rows */
693 be(0x0000), /* 30D4: CC: CC enabled with 16 samples per column */
694 /* 30D6: CC: bw mode enabled/12 bit data resolution/bw mode */
695 be(0x2FFF)),
696
697 REGS(be(0x30DA),
698 be(0x0FFF), /* 30DA: CC: column correction clip level 2 is 0 */
699 be(0x0FFF), /* 30DC: CC: column correction clip level 3 is 0 */
700 be(0x0000)), /* 30DE: CC: Group FPN correction */
701
702 /* RNC: rnc scaling factor = * 54 / 64 (32 / 38 * 64 = 53.9) */
703 REGS(be(0x30EE), be(0x1136)),
704 REGS(be(0x30FA), be(0xFD00)), /* GPIO0 = flash, GPIO1 = shutter */
705 REGS(be(0x3120), be(0x0005)), /* p1 dither enabled for 10bit mode */
706 REGS(be(0x3172), be(0x0206)), /* txlo clk divider options */
707 /* FDOC:fdoc settings with fdoc every frame turned of */
708 REGS(be(0x3180), be(0x9434)),
709
710 REGS(be(0x31B0),
711 be(0x008B), /* 31B0: frame_preamble - FIXME check WRT lanes# */
712 be(0x0050)), /* 31B2: line_preamble - FIXME check WRT lanes# */
713
714 /* don't use continuous clock mode while shut down */
715 REGS(be(0x31BC), be(0x068C)),
716 REGS(be(0x31E0), be(0x0781)), /* Fuse/2DDC: enable 2ddc */
717
718 /* analog_setup_recommended_10bit */
719 REGS(be(0x341A), be(0x4735)), /* Samp&Hold pulse in ADC */
720 REGS(be(0x3420), be(0x4735)), /* Samp&Hold pulse in ADC */
721 REGS(be(0x3426), be(0x8A1A)), /* ADC offset distribution pulse */
722 REGS(be(0x342A), be(0x0018)), /* pulse_config */
723
724 /* pixel_timing_recommended */
725 REGS(be(0x3D00),
726 /* 3D00 */ be(0x043E), be(0x4760), be(0xFFFF), be(0xFFFF),
727 /* 3D08 */ be(0x8000), be(0x0510), be(0xAF08), be(0x0252),
728 /* 3D10 */ be(0x486F), be(0x5D5D), be(0x8056), be(0x8313),
729 /* 3D18 */ be(0x0087), be(0x6A48), be(0x6982), be(0x0280),
730 /* 3D20 */ be(0x8359), be(0x8D02), be(0x8020), be(0x4882),
731 /* 3D28 */ be(0x4269), be(0x6A95), be(0x5988), be(0x5A83),
732 /* 3D30 */ be(0x5885), be(0x6280), be(0x6289), be(0x6097),
733 /* 3D38 */ be(0x5782), be(0x605C), be(0xBF18), be(0x0961),
734 /* 3D40 */ be(0x5080), be(0x2090), be(0x4390), be(0x4382),
735 /* 3D48 */ be(0x5F8A), be(0x5D5D), be(0x9C63), be(0x8063),
736 /* 3D50 */ be(0xA960), be(0x9757), be(0x8260), be(0x5CFF),
737 /* 3D58 */ be(0xBF10), be(0x1681), be(0x0802), be(0x8000),
738 /* 3D60 */ be(0x141C), be(0x6000), be(0x6022), be(0x4D80),
739 /* 3D68 */ be(0x5C97), be(0x6A69), be(0xAC6F), be(0x4645),
740 /* 3D70 */ be(0x4400), be(0x0513), be(0x8069), be(0x6AC6),
741 /* 3D78 */ be(0x5F95), be(0x5F70), be(0x8040), be(0x4A81),
742 /* 3D80 */ be(0x0300), be(0xE703), be(0x0088), be(0x4A83),
743 /* 3D88 */ be(0x40FF), be(0xFFFF), be(0xFD70), be(0x8040),
744 /* 3D90 */ be(0x4A85), be(0x4FA8), be(0x4F8C), be(0x0070),
745 /* 3D98 */ be(0xBE47), be(0x8847), be(0xBC78), be(0x6B89),
746 /* 3DA0 */ be(0x6A80), be(0x6986), be(0x6B8E), be(0x6B80),
747 /* 3DA8 */ be(0x6980), be(0x6A88), be(0x7C9F), be(0x866B),
748 /* 3DB0 */ be(0x8765), be(0x46FF), be(0xE365), be(0xA679),
749 /* 3DB8 */ be(0x4A40), be(0x4580), be(0x44BC), be(0x7000),
750 /* 3DC0 */ be(0x8040), be(0x0802), be(0x10EF), be(0x0104),
751 /* 3DC8 */ be(0x3860), be(0x5D5D), be(0x5682), be(0x1300),
752 /* 3DD0 */ be(0x8648), be(0x8202), be(0x8082), be(0x598A),
753 /* 3DD8 */ be(0x0280), be(0x2048), be(0x3060), be(0x8042),
754 /* 3DE0 */ be(0x9259), be(0x865A), be(0x8258), be(0x8562),
755 /* 3DE8 */ be(0x8062), be(0x8560), be(0x9257), be(0x8221),
756 /* 3DF0 */ be(0x10FF), be(0xB757), be(0x9361), be(0x1019),
757 /* 3DF8 */ be(0x8020), be(0x9043), be(0x8E43), be(0x845F),
758 /* 3E00 */ be(0x835D), be(0x805D), be(0x8163), be(0x8063),
759 /* 3E08 */ be(0xA060), be(0x9157), be(0x8260), be(0x5CFF),
760 /* 3E10 */ be(0xFFFF), be(0xFFE5), be(0x1016), be(0x2048),
761 /* 3E18 */ be(0x0802), be(0x1C60), be(0x0014), be(0x0060),
762 /* 3E20 */ be(0x2205), be(0x8120), be(0x908F), be(0x6A80),
763 /* 3E28 */ be(0x6982), be(0x5F9F), be(0x6F46), be(0x4544),
764 /* 3E30 */ be(0x0005), be(0x8013), be(0x8069), be(0x6A80),
765 /* 3E38 */ be(0x7000), be(0x0000), be(0x0000), be(0x0000),
766 /* 3E40 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
767 /* 3E48 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
768 /* 3E50 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
769 /* 3E58 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
770 /* 3E60 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
771 /* 3E68 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
772 /* 3E70 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
773 /* 3E78 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
774 /* 3E80 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
775 /* 3E88 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
776 /* 3E90 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
777 /* 3E98 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
778 /* 3EA0 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
779 /* 3EA8 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
780 /* 3EB0 */ be(0x0000), be(0x0000), be(0x0000)),
781
782 REGS(be(0x3EB6), be(0x004C)), /* ECL */
783
784 REGS(be(0x3EBA),
785 be(0xAAAD), /* 3EBA */
786 be(0x0086)), /* 3EBC: Bias currents for FSC/ECL */
787
788 REGS(be(0x3EC0),
789 be(0x1E00), /* 3EC0: SFbin/SH mode settings */
790 be(0x100A), /* 3EC2: CLK divider for ramp for 10 bit 400MH */
791 /* 3EC4: FSC clamps for HDR mode and adc comp power down co */
792 be(0x3300),
793 be(0xEA44), /* 3EC6: VLN and clk gating controls */
794 be(0x6F6F), /* 3EC8: Txl0 and Txlo1 settings for normal mode */
795 be(0x2F4A), /* 3ECA: CDAC/Txlo2/RSTGHI/RSTGLO settings */
796 be(0x0506), /* 3ECC: RSTDHI/RSTDLO/CDAC/TXHI settings */
797 /* 3ECE: Ramp buffer settings and Booster enable (bits 0-5) */
798 be(0x203B),
799 be(0x13F0), /* 3ED0: TXLO from atest/sf bin settings */
800 be(0xA53D), /* 3ED2: Ramp offset */
801 be(0x862F), /* 3ED4: TXLO open loop/row driver settings */
802 be(0x4081), /* 3ED6: Txlatch fr cfpn rows/vln bias */
803 be(0x8003), /* 3ED8: Ramp step setting for 10 bit 400 Mhz */
804 be(0xA580), /* 3EDA: Ramp Offset */
805 be(0xC000), /* 3EDC: over range for rst and under range for sig */
806 be(0xC103)), /* 3EDE: over range for sig and col dec clk settings */
807
808 /* corrections_recommended_bayer */
809 REGS(be(0x3F00),
810 be(0x0017), /* 3F00: BM_T0 */
811 be(0x02DD), /* 3F02: BM_T1 */
812 /* 3F04: if Ana_gain less than 2, use noise_floor0, multipl */
813 be(0x0020),
814 /* 3F06: if Ana_gain between 4 and 7, use noise_floor2 and */
815 be(0x0040),
816 /* 3F08: if Ana_gain between 4 and 7, use noise_floor2 and */
817 be(0x0070),
818 /* 3F0A: Define noise_floor0(low address) and noise_floor1 */
819 be(0x0101),
820 be(0x0302)), /* 3F0C: Define noise_floor2 and noise_floor3 */
821
822 REGS(be(0x3F10),
823 be(0x0505), /* 3F10: single k factor 0 */
824 be(0x0505), /* 3F12: single k factor 1 */
825 be(0x0505), /* 3F14: single k factor 2 */
826 be(0x01FF), /* 3F16: cross factor 0 */
827 be(0x01FF), /* 3F18: cross factor 1 */
828 be(0x01FF), /* 3F1A: cross factor 2 */
829 be(0x0022)), /* 3F1E */
830
831 /* GTH_THRES_RTN: 4max,4min filtered out of every 46 samples and */
832 REGS(be(0x3F2C), be(0x442E)),
833
834 REGS(be(0x3F3E),
835 be(0x0000), /* 3F3E: Switch ADC from 12 bit to 10 bit mode */
836 be(0x1511), /* 3F40: couple k factor 0 */
837 be(0x1511), /* 3F42: couple k factor 1 */
838 be(0x0707)), /* 3F44: couple k factor 2 */
839 };
840
ar0521_power_off(struct device * dev)841 static int ar0521_power_off(struct device *dev)
842 {
843 struct v4l2_subdev *sd = dev_get_drvdata(dev);
844 struct ar0521_dev *sensor = to_ar0521_dev(sd);
845 int i;
846
847 clk_disable_unprepare(sensor->extclk);
848
849 if (sensor->reset_gpio)
850 gpiod_set_value(sensor->reset_gpio, 1); /* assert RESET signal */
851
852 for (i = ARRAY_SIZE(ar0521_supply_names) - 1; i >= 0; i--) {
853 if (sensor->supplies[i])
854 regulator_disable(sensor->supplies[i]);
855 }
856 return 0;
857 }
858
ar0521_power_on(struct device * dev)859 static int ar0521_power_on(struct device *dev)
860 {
861 struct v4l2_subdev *sd = dev_get_drvdata(dev);
862 struct ar0521_dev *sensor = to_ar0521_dev(sd);
863 unsigned int cnt;
864 int ret;
865
866 for (cnt = 0; cnt < ARRAY_SIZE(ar0521_supply_names); cnt++)
867 if (sensor->supplies[cnt]) {
868 ret = regulator_enable(sensor->supplies[cnt]);
869 if (ret < 0)
870 goto off;
871
872 usleep_range(1000, 1500); /* min 1 ms */
873 }
874
875 ret = clk_prepare_enable(sensor->extclk);
876 if (ret < 0) {
877 v4l2_err(&sensor->sd, "error enabling sensor clock\n");
878 goto off;
879 }
880 usleep_range(1000, 1500); /* min 1 ms */
881
882 if (sensor->reset_gpio)
883 /* deassert RESET signal */
884 gpiod_set_value(sensor->reset_gpio, 0);
885 usleep_range(4500, 5000); /* min 45000 clocks */
886
887 for (cnt = 0; cnt < ARRAY_SIZE(initial_regs); cnt++) {
888 ret = ar0521_write_regs(sensor, initial_regs[cnt].data,
889 initial_regs[cnt].count);
890 if (ret)
891 goto off;
892 }
893
894 ret = ar0521_write_reg(sensor, AR0521_REG_SERIAL_FORMAT,
895 AR0521_REG_SERIAL_FORMAT_MIPI |
896 sensor->lane_count);
897 if (ret)
898 goto off;
899
900 /* set MIPI test mode - disabled for now */
901 ret = ar0521_write_reg(sensor, AR0521_REG_HISPI_TEST_MODE,
902 ((0x40 << sensor->lane_count) - 0x40) |
903 AR0521_REG_HISPI_TEST_MODE_LP11);
904 if (ret)
905 goto off;
906
907 ret = ar0521_write_reg(sensor, AR0521_REG_ROW_SPEED, 0x110 |
908 4 / sensor->lane_count);
909 if (ret)
910 goto off;
911
912 return 0;
913 off:
914 ar0521_power_off(dev);
915 return ret;
916 }
917
ar0521_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_mbus_code_enum * code)918 static int ar0521_enum_mbus_code(struct v4l2_subdev *sd,
919 struct v4l2_subdev_state *sd_state,
920 struct v4l2_subdev_mbus_code_enum *code)
921 {
922 struct ar0521_dev *sensor = to_ar0521_dev(sd);
923
924 if (code->index)
925 return -EINVAL;
926
927 code->code = sensor->fmt.code;
928 return 0;
929 }
930
ar0521_enum_frame_size(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_frame_size_enum * fse)931 static int ar0521_enum_frame_size(struct v4l2_subdev *sd,
932 struct v4l2_subdev_state *sd_state,
933 struct v4l2_subdev_frame_size_enum *fse)
934 {
935 if (fse->index)
936 return -EINVAL;
937
938 if (fse->code != MEDIA_BUS_FMT_SGRBG8_1X8)
939 return -EINVAL;
940
941 fse->min_width = AR0521_WIDTH_MIN;
942 fse->max_width = AR0521_WIDTH_MAX;
943 fse->min_height = AR0521_HEIGHT_MIN;
944 fse->max_height = AR0521_HEIGHT_MAX;
945
946 return 0;
947 }
948
ar0521_pre_streamon(struct v4l2_subdev * sd,u32 flags)949 static int ar0521_pre_streamon(struct v4l2_subdev *sd, u32 flags)
950 {
951 struct ar0521_dev *sensor = to_ar0521_dev(sd);
952 int ret;
953
954 if (!(flags & V4L2_SUBDEV_PRE_STREAMON_FL_MANUAL_LP))
955 return -EACCES;
956
957 ret = pm_runtime_resume_and_get(&sensor->i2c_client->dev);
958 if (ret < 0)
959 return ret;
960
961 /* Set LP-11 on clock and data lanes */
962 ret = ar0521_write_reg(sensor, AR0521_REG_HISPI_CONTROL_STATUS,
963 AR0521_REG_HISPI_CONTROL_STATUS_FRAMER_TEST_MODE_ENABLE);
964 if (ret)
965 goto err;
966
967 /* Start streaming LP-11 */
968 ret = ar0521_write_reg(sensor, AR0521_REG_RESET,
969 AR0521_REG_RESET_DEFAULTS |
970 AR0521_REG_RESET_STREAM);
971 if (ret)
972 goto err;
973 return 0;
974
975 err:
976 pm_runtime_put(&sensor->i2c_client->dev);
977 return ret;
978 }
979
ar0521_post_streamoff(struct v4l2_subdev * sd)980 static int ar0521_post_streamoff(struct v4l2_subdev *sd)
981 {
982 struct ar0521_dev *sensor = to_ar0521_dev(sd);
983
984 pm_runtime_put(&sensor->i2c_client->dev);
985 return 0;
986 }
987
ar0521_s_stream(struct v4l2_subdev * sd,int enable)988 static int ar0521_s_stream(struct v4l2_subdev *sd, int enable)
989 {
990 struct ar0521_dev *sensor = to_ar0521_dev(sd);
991 int ret;
992
993 mutex_lock(&sensor->lock);
994
995 ret = ar0521_set_stream(sensor, enable);
996 if (!ret)
997 sensor->streaming = enable;
998
999 mutex_unlock(&sensor->lock);
1000 return ret;
1001 }
1002
1003 static const struct v4l2_subdev_core_ops ar0521_core_ops = {
1004 .log_status = v4l2_ctrl_subdev_log_status,
1005 };
1006
1007 static const struct v4l2_subdev_video_ops ar0521_video_ops = {
1008 .s_stream = ar0521_s_stream,
1009 .pre_streamon = ar0521_pre_streamon,
1010 .post_streamoff = ar0521_post_streamoff,
1011 };
1012
1013 static const struct v4l2_subdev_pad_ops ar0521_pad_ops = {
1014 .enum_mbus_code = ar0521_enum_mbus_code,
1015 .enum_frame_size = ar0521_enum_frame_size,
1016 .get_fmt = ar0521_get_fmt,
1017 .set_fmt = ar0521_set_fmt,
1018 };
1019
1020 static const struct v4l2_subdev_ops ar0521_subdev_ops = {
1021 .core = &ar0521_core_ops,
1022 .video = &ar0521_video_ops,
1023 .pad = &ar0521_pad_ops,
1024 };
1025
ar0521_suspend(struct device * dev)1026 static int __maybe_unused ar0521_suspend(struct device *dev)
1027 {
1028 struct v4l2_subdev *sd = dev_get_drvdata(dev);
1029 struct ar0521_dev *sensor = to_ar0521_dev(sd);
1030
1031 if (sensor->streaming)
1032 ar0521_set_stream(sensor, 0);
1033
1034 return 0;
1035 }
1036
ar0521_resume(struct device * dev)1037 static int __maybe_unused ar0521_resume(struct device *dev)
1038 {
1039 struct v4l2_subdev *sd = dev_get_drvdata(dev);
1040 struct ar0521_dev *sensor = to_ar0521_dev(sd);
1041
1042 if (sensor->streaming)
1043 return ar0521_set_stream(sensor, 1);
1044
1045 return 0;
1046 }
1047
ar0521_probe(struct i2c_client * client)1048 static int ar0521_probe(struct i2c_client *client)
1049 {
1050 struct v4l2_fwnode_endpoint ep = {
1051 .bus_type = V4L2_MBUS_CSI2_DPHY
1052 };
1053 struct device *dev = &client->dev;
1054 struct fwnode_handle *endpoint;
1055 struct ar0521_dev *sensor;
1056 unsigned int cnt;
1057 int ret;
1058
1059 sensor = devm_kzalloc(dev, sizeof(*sensor), GFP_KERNEL);
1060 if (!sensor)
1061 return -ENOMEM;
1062
1063 sensor->i2c_client = client;
1064 sensor->fmt.width = AR0521_WIDTH_MAX;
1065 sensor->fmt.height = AR0521_HEIGHT_MAX;
1066
1067 endpoint = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev), 0, 0,
1068 FWNODE_GRAPH_ENDPOINT_NEXT);
1069 if (!endpoint) {
1070 dev_err(dev, "endpoint node not found\n");
1071 return -EINVAL;
1072 }
1073
1074 ret = v4l2_fwnode_endpoint_parse(endpoint, &ep);
1075 fwnode_handle_put(endpoint);
1076 if (ret) {
1077 dev_err(dev, "could not parse endpoint\n");
1078 return ret;
1079 }
1080
1081 if (ep.bus_type != V4L2_MBUS_CSI2_DPHY) {
1082 dev_err(dev, "invalid bus type, must be MIPI CSI2\n");
1083 return -EINVAL;
1084 }
1085
1086 sensor->lane_count = ep.bus.mipi_csi2.num_data_lanes;
1087 switch (sensor->lane_count) {
1088 case 1:
1089 case 2:
1090 case 4:
1091 break;
1092 default:
1093 dev_err(dev, "invalid number of MIPI data lanes\n");
1094 return -EINVAL;
1095 }
1096
1097 /* Get master clock (extclk) */
1098 sensor->extclk = devm_clk_get(dev, "extclk");
1099 if (IS_ERR(sensor->extclk)) {
1100 dev_err(dev, "failed to get extclk\n");
1101 return PTR_ERR(sensor->extclk);
1102 }
1103
1104 sensor->extclk_freq = clk_get_rate(sensor->extclk);
1105
1106 if (sensor->extclk_freq < AR0521_EXTCLK_MIN ||
1107 sensor->extclk_freq > AR0521_EXTCLK_MAX) {
1108 dev_err(dev, "extclk frequency out of range: %u Hz\n",
1109 sensor->extclk_freq);
1110 return -EINVAL;
1111 }
1112
1113 /* Request optional reset pin (usually active low) and assert it */
1114 sensor->reset_gpio = devm_gpiod_get_optional(dev, "reset",
1115 GPIOD_OUT_HIGH);
1116
1117 v4l2_i2c_subdev_init(&sensor->sd, client, &ar0521_subdev_ops);
1118
1119 sensor->sd.flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
1120 sensor->pad.flags = MEDIA_PAD_FL_SOURCE;
1121 sensor->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1122 ret = media_entity_pads_init(&sensor->sd.entity, 1, &sensor->pad);
1123 if (ret)
1124 return ret;
1125
1126 for (cnt = 0; cnt < ARRAY_SIZE(ar0521_supply_names); cnt++) {
1127 struct regulator *supply = devm_regulator_get(dev,
1128 ar0521_supply_names[cnt]);
1129
1130 if (IS_ERR(supply)) {
1131 dev_info(dev, "no %s regulator found: %li\n",
1132 ar0521_supply_names[cnt], PTR_ERR(supply));
1133 return PTR_ERR(supply);
1134 }
1135 sensor->supplies[cnt] = supply;
1136 }
1137
1138 mutex_init(&sensor->lock);
1139
1140 ret = ar0521_init_controls(sensor);
1141 if (ret)
1142 goto entity_cleanup;
1143
1144 ar0521_adj_fmt(&sensor->fmt);
1145
1146 ret = v4l2_async_register_subdev(&sensor->sd);
1147 if (ret)
1148 goto free_ctrls;
1149
1150 /* Turn on the device and enable runtime PM */
1151 ret = ar0521_power_on(&client->dev);
1152 if (ret)
1153 goto disable;
1154 pm_runtime_set_active(&client->dev);
1155 pm_runtime_enable(&client->dev);
1156 pm_runtime_idle(&client->dev);
1157 return 0;
1158
1159 disable:
1160 v4l2_async_unregister_subdev(&sensor->sd);
1161 media_entity_cleanup(&sensor->sd.entity);
1162 free_ctrls:
1163 v4l2_ctrl_handler_free(&sensor->ctrls.handler);
1164 entity_cleanup:
1165 media_entity_cleanup(&sensor->sd.entity);
1166 mutex_destroy(&sensor->lock);
1167 return ret;
1168 }
1169
ar0521_remove(struct i2c_client * client)1170 static void ar0521_remove(struct i2c_client *client)
1171 {
1172 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1173 struct ar0521_dev *sensor = to_ar0521_dev(sd);
1174
1175 v4l2_async_unregister_subdev(&sensor->sd);
1176 media_entity_cleanup(&sensor->sd.entity);
1177 v4l2_ctrl_handler_free(&sensor->ctrls.handler);
1178 pm_runtime_disable(&client->dev);
1179 if (!pm_runtime_status_suspended(&client->dev))
1180 ar0521_power_off(&client->dev);
1181 pm_runtime_set_suspended(&client->dev);
1182 mutex_destroy(&sensor->lock);
1183 }
1184
1185 static const struct dev_pm_ops ar0521_pm_ops = {
1186 SET_SYSTEM_SLEEP_PM_OPS(ar0521_suspend, ar0521_resume)
1187 SET_RUNTIME_PM_OPS(ar0521_power_off, ar0521_power_on, NULL)
1188 };
1189 static const struct of_device_id ar0521_dt_ids[] = {
1190 {.compatible = "onnn,ar0521"},
1191 {}
1192 };
1193 MODULE_DEVICE_TABLE(of, ar0521_dt_ids);
1194
1195 static struct i2c_driver ar0521_i2c_driver = {
1196 .driver = {
1197 .name = "ar0521",
1198 .pm = &ar0521_pm_ops,
1199 .of_match_table = ar0521_dt_ids,
1200 },
1201 .probe = ar0521_probe,
1202 .remove = ar0521_remove,
1203 };
1204
1205 module_i2c_driver(ar0521_i2c_driver);
1206
1207 MODULE_DESCRIPTION("AR0521 MIPI Camera subdev driver");
1208 MODULE_AUTHOR("Krzysztof Hałasa <khalasa@piap.pl>");
1209 MODULE_LICENSE("GPL");
1210