1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
4  * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
5  */
6 
7 #include <drm/drm_atomic.h>
8 #include <drm/drm_atomic_helper.h>
9 #include <drm/drm_blend.h>
10 #include <drm/drm_crtc.h>
11 #include <drm/drm_fourcc.h>
12 #include <drm/drm_framebuffer.h>
13 #include <drm/drm_gem_atomic_helper.h>
14 
15 #include "tidss_crtc.h"
16 #include "tidss_dispc.h"
17 #include "tidss_drv.h"
18 #include "tidss_plane.h"
19 
20 /* drm_plane_helper_funcs */
21 
tidss_plane_atomic_check(struct drm_plane * plane,struct drm_atomic_state * state)22 static int tidss_plane_atomic_check(struct drm_plane *plane,
23 				    struct drm_atomic_state *state)
24 {
25 	struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
26 										 plane);
27 	struct drm_device *ddev = plane->dev;
28 	struct tidss_device *tidss = to_tidss(ddev);
29 	struct tidss_plane *tplane = to_tidss_plane(plane);
30 	const struct drm_format_info *finfo;
31 	struct drm_crtc_state *crtc_state;
32 	u32 hw_plane = tplane->hw_plane_id;
33 	u32 hw_videoport;
34 	int ret;
35 
36 	dev_dbg(ddev->dev, "%s\n", __func__);
37 
38 	if (!new_plane_state->crtc) {
39 		/*
40 		 * The visible field is not reset by the DRM core but only
41 		 * updated by drm_atomic_helper_check_plane_state(), set it
42 		 * manually.
43 		 */
44 		new_plane_state->visible = false;
45 		return 0;
46 	}
47 
48 	crtc_state = drm_atomic_get_crtc_state(state,
49 					       new_plane_state->crtc);
50 	if (IS_ERR(crtc_state))
51 		return PTR_ERR(crtc_state);
52 
53 	ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,
54 						  0,
55 						  INT_MAX, true, true);
56 	if (ret < 0)
57 		return ret;
58 
59 	/*
60 	 * The HW is only able to start drawing at subpixel boundary
61 	 * (the two first checks bellow). At the end of a row the HW
62 	 * can only jump integer number of subpixels forward to the
63 	 * beginning of the next row. So we can only show picture with
64 	 * integer subpixel width (the third check). However, after
65 	 * reaching the end of the drawn picture the drawing starts
66 	 * again at the absolute memory address where top left corner
67 	 * position of the drawn picture is (so there is no need to
68 	 * check for odd height).
69 	 */
70 
71 	finfo = drm_format_info(new_plane_state->fb->format->format);
72 
73 	if ((new_plane_state->src_x >> 16) % finfo->hsub != 0) {
74 		dev_dbg(ddev->dev,
75 			"%s: x-position %u not divisible subpixel size %u\n",
76 			__func__, (new_plane_state->src_x >> 16), finfo->hsub);
77 		return -EINVAL;
78 	}
79 
80 	if ((new_plane_state->src_y >> 16) % finfo->vsub != 0) {
81 		dev_dbg(ddev->dev,
82 			"%s: y-position %u not divisible subpixel size %u\n",
83 			__func__, (new_plane_state->src_y >> 16), finfo->vsub);
84 		return -EINVAL;
85 	}
86 
87 	if ((new_plane_state->src_w >> 16) % finfo->hsub != 0) {
88 		dev_dbg(ddev->dev,
89 			"%s: src width %u not divisible by subpixel size %u\n",
90 			 __func__, (new_plane_state->src_w >> 16),
91 			 finfo->hsub);
92 		return -EINVAL;
93 	}
94 
95 	if (!new_plane_state->visible)
96 		return 0;
97 
98 	hw_videoport = to_tidss_crtc(new_plane_state->crtc)->hw_videoport;
99 
100 	ret = dispc_plane_check(tidss->dispc, hw_plane, new_plane_state,
101 				hw_videoport);
102 	if (ret)
103 		return ret;
104 
105 	return 0;
106 }
107 
tidss_plane_atomic_update(struct drm_plane * plane,struct drm_atomic_state * state)108 static void tidss_plane_atomic_update(struct drm_plane *plane,
109 				      struct drm_atomic_state *state)
110 {
111 	struct drm_device *ddev = plane->dev;
112 	struct tidss_device *tidss = to_tidss(ddev);
113 	struct tidss_plane *tplane = to_tidss_plane(plane);
114 	struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
115 									   plane);
116 	u32 hw_videoport;
117 
118 	dev_dbg(ddev->dev, "%s\n", __func__);
119 
120 	if (!new_state->visible) {
121 		dispc_plane_enable(tidss->dispc, tplane->hw_plane_id, false);
122 		return;
123 	}
124 
125 	hw_videoport = to_tidss_crtc(new_state->crtc)->hw_videoport;
126 
127 	dispc_plane_setup(tidss->dispc, tplane->hw_plane_id, new_state, hw_videoport);
128 }
129 
tidss_plane_atomic_enable(struct drm_plane * plane,struct drm_atomic_state * state)130 static void tidss_plane_atomic_enable(struct drm_plane *plane,
131 				      struct drm_atomic_state *state)
132 {
133 	struct drm_device *ddev = plane->dev;
134 	struct tidss_device *tidss = to_tidss(ddev);
135 	struct tidss_plane *tplane = to_tidss_plane(plane);
136 
137 	dev_dbg(ddev->dev, "%s\n", __func__);
138 
139 	dispc_plane_enable(tidss->dispc, tplane->hw_plane_id, true);
140 }
141 
tidss_plane_atomic_disable(struct drm_plane * plane,struct drm_atomic_state * state)142 static void tidss_plane_atomic_disable(struct drm_plane *plane,
143 				       struct drm_atomic_state *state)
144 {
145 	struct drm_device *ddev = plane->dev;
146 	struct tidss_device *tidss = to_tidss(ddev);
147 	struct tidss_plane *tplane = to_tidss_plane(plane);
148 
149 	dev_dbg(ddev->dev, "%s\n", __func__);
150 
151 	dispc_plane_enable(tidss->dispc, tplane->hw_plane_id, false);
152 }
153 
drm_plane_destroy(struct drm_plane * plane)154 static void drm_plane_destroy(struct drm_plane *plane)
155 {
156 	struct tidss_plane *tplane = to_tidss_plane(plane);
157 
158 	drm_plane_cleanup(plane);
159 	kfree(tplane);
160 }
161 
162 static const struct drm_plane_helper_funcs tidss_plane_helper_funcs = {
163 	.atomic_check = tidss_plane_atomic_check,
164 	.atomic_update = tidss_plane_atomic_update,
165 	.atomic_enable = tidss_plane_atomic_enable,
166 	.atomic_disable = tidss_plane_atomic_disable,
167 };
168 
169 static const struct drm_plane_funcs tidss_plane_funcs = {
170 	.update_plane = drm_atomic_helper_update_plane,
171 	.disable_plane = drm_atomic_helper_disable_plane,
172 	.reset = drm_atomic_helper_plane_reset,
173 	.destroy = drm_plane_destroy,
174 	.atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
175 	.atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
176 };
177 
tidss_plane_create(struct tidss_device * tidss,u32 hw_plane_id,u32 plane_type,u32 crtc_mask,const u32 * formats,u32 num_formats)178 struct tidss_plane *tidss_plane_create(struct tidss_device *tidss,
179 				       u32 hw_plane_id, u32 plane_type,
180 				       u32 crtc_mask, const u32 *formats,
181 				       u32 num_formats)
182 {
183 	struct tidss_plane *tplane;
184 	enum drm_plane_type type;
185 	u32 possible_crtcs;
186 	u32 num_planes = tidss->feat->num_planes;
187 	u32 color_encodings = (BIT(DRM_COLOR_YCBCR_BT601) |
188 			       BIT(DRM_COLOR_YCBCR_BT709));
189 	u32 color_ranges = (BIT(DRM_COLOR_YCBCR_FULL_RANGE) |
190 			    BIT(DRM_COLOR_YCBCR_LIMITED_RANGE));
191 	u32 default_encoding = DRM_COLOR_YCBCR_BT601;
192 	u32 default_range = DRM_COLOR_YCBCR_FULL_RANGE;
193 	u32 blend_modes = (BIT(DRM_MODE_BLEND_PREMULTI) |
194 			   BIT(DRM_MODE_BLEND_COVERAGE));
195 	int ret;
196 
197 	tplane = kzalloc(sizeof(*tplane), GFP_KERNEL);
198 	if (!tplane)
199 		return ERR_PTR(-ENOMEM);
200 
201 	tplane->hw_plane_id = hw_plane_id;
202 
203 	possible_crtcs = crtc_mask;
204 	type = plane_type;
205 
206 	ret = drm_universal_plane_init(&tidss->ddev, &tplane->plane,
207 				       possible_crtcs,
208 				       &tidss_plane_funcs,
209 				       formats, num_formats,
210 				       NULL, type, NULL);
211 	if (ret < 0)
212 		goto err;
213 
214 	drm_plane_helper_add(&tplane->plane, &tidss_plane_helper_funcs);
215 
216 	drm_plane_create_zpos_property(&tplane->plane, hw_plane_id, 0,
217 				       num_planes - 1);
218 
219 	ret = drm_plane_create_color_properties(&tplane->plane,
220 						color_encodings,
221 						color_ranges,
222 						default_encoding,
223 						default_range);
224 	if (ret)
225 		goto err;
226 
227 	ret = drm_plane_create_alpha_property(&tplane->plane);
228 	if (ret)
229 		goto err;
230 
231 	ret = drm_plane_create_blend_mode_property(&tplane->plane, blend_modes);
232 	if (ret)
233 		goto err;
234 
235 	return tplane;
236 
237 err:
238 	kfree(tplane);
239 	return ERR_PTR(ret);
240 }
241