1 /*
2 * Copyright 2007 Matthieu CASTET <castet.matthieu@free.fr>
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragr) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24 #include "nv10.h"
25
26 static const struct nvkm_gr_func
27 nv15_gr = {
28 .init = nv10_gr_init,
29 .intr = nv10_gr_intr,
30 .tile = nv10_gr_tile,
31 .chan_new = nv10_gr_chan_new,
32 .sclass = {
33 { -1, -1, 0x0012, &nv04_gr_object }, /* beta1 */
34 { -1, -1, 0x0019, &nv04_gr_object }, /* clip */
35 { -1, -1, 0x0030, &nv04_gr_object }, /* null */
36 { -1, -1, 0x0039, &nv04_gr_object }, /* m2mf */
37 { -1, -1, 0x0043, &nv04_gr_object }, /* rop */
38 { -1, -1, 0x0044, &nv04_gr_object }, /* pattern */
39 { -1, -1, 0x004a, &nv04_gr_object }, /* gdi */
40 { -1, -1, 0x0052, &nv04_gr_object }, /* swzsurf */
41 { -1, -1, 0x005f, &nv04_gr_object }, /* blit */
42 { -1, -1, 0x0062, &nv04_gr_object }, /* surf2d */
43 { -1, -1, 0x0072, &nv04_gr_object }, /* beta4 */
44 { -1, -1, 0x0089, &nv04_gr_object }, /* sifm */
45 { -1, -1, 0x008a, &nv04_gr_object }, /* ifc */
46 { -1, -1, 0x009f, &nv04_gr_object }, /* blit */
47 { -1, -1, 0x0093, &nv04_gr_object }, /* surf3d */
48 { -1, -1, 0x0094, &nv04_gr_object }, /* ttri */
49 { -1, -1, 0x0095, &nv04_gr_object }, /* mtri */
50 { -1, -1, 0x0096, &nv04_gr_object }, /* celcius */
51 {}
52 }
53 };
54
55 int
nv15_gr_new(struct nvkm_device * device,enum nvkm_subdev_type type,int inst,struct nvkm_gr ** pgr)56 nv15_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
57 {
58 return nv10_gr_new_(&nv15_gr, device, type, inst, pgr);
59 }
60