1 // SPDX-License-Identifier: MIT
2 /*
3  * Copyright © 2015 Intel Corporation
4  */
5 
6 #include "i915_drv.h"
7 
8 #include "intel_engine.h"
9 #include "intel_gt.h"
10 #include "intel_gt_mcr.h"
11 #include "intel_gt_regs.h"
12 #include "intel_mocs.h"
13 #include "intel_ring.h"
14 
15 /* structures required */
16 struct drm_i915_mocs_entry {
17 	u32 control_value;
18 	u16 l3cc_value;
19 	u16 used;
20 };
21 
22 struct drm_i915_mocs_table {
23 	unsigned int size;
24 	unsigned int n_entries;
25 	const struct drm_i915_mocs_entry *table;
26 	u8 uc_index;
27 	u8 wb_index; /* Only used on HAS_L3_CCS_READ() platforms */
28 	u8 unused_entries_index;
29 };
30 
31 /* Defines for the tables (XXX_MOCS_0 - XXX_MOCS_63) */
32 #define _LE_CACHEABILITY(value)	((value) << 0)
33 #define _LE_TGT_CACHE(value)	((value) << 2)
34 #define LE_LRUM(value)		((value) << 4)
35 #define LE_AOM(value)		((value) << 6)
36 #define LE_RSC(value)		((value) << 7)
37 #define LE_SCC(value)		((value) << 8)
38 #define LE_PFM(value)		((value) << 11)
39 #define LE_SCF(value)		((value) << 14)
40 #define LE_COS(value)		((value) << 15)
41 #define LE_SSE(value)		((value) << 17)
42 
43 /* Defines for the tables (GLOB_MOCS_0 - GLOB_MOCS_16) */
44 #define _L4_CACHEABILITY(value)	((value) << 2)
45 #define IG_PAT(value)		((value) << 8)
46 
47 /* Defines for the tables (LNCFMOCS0 - LNCFMOCS31) - two entries per word */
48 #define L3_ESC(value)		((value) << 0)
49 #define L3_SCC(value)		((value) << 1)
50 #define _L3_CACHEABILITY(value)	((value) << 4)
51 #define L3_GLBGO(value)		((value) << 6)
52 #define L3_LKUP(value)		((value) << 7)
53 
54 /* Helper defines */
55 #define GEN9_NUM_MOCS_ENTRIES	64  /* 63-64 are reserved, but configured. */
56 #define PVC_NUM_MOCS_ENTRIES	3
57 #define MTL_NUM_MOCS_ENTRIES	16
58 
59 /* (e)LLC caching options */
60 /*
61  * Note: LE_0_PAGETABLE works only up to Gen11; for newer gens it means
62  * the same as LE_UC
63  */
64 #define LE_0_PAGETABLE		_LE_CACHEABILITY(0)
65 #define LE_1_UC			_LE_CACHEABILITY(1)
66 #define LE_2_WT			_LE_CACHEABILITY(2)
67 #define LE_3_WB			_LE_CACHEABILITY(3)
68 
69 /* Target cache */
70 #define LE_TC_0_PAGETABLE	_LE_TGT_CACHE(0)
71 #define LE_TC_1_LLC		_LE_TGT_CACHE(1)
72 #define LE_TC_2_LLC_ELLC	_LE_TGT_CACHE(2)
73 #define LE_TC_3_LLC_ELLC_ALT	_LE_TGT_CACHE(3)
74 
75 /* L3 caching options */
76 #define L3_0_DIRECT		_L3_CACHEABILITY(0)
77 #define L3_1_UC			_L3_CACHEABILITY(1)
78 #define L3_2_RESERVED		_L3_CACHEABILITY(2)
79 #define L3_3_WB			_L3_CACHEABILITY(3)
80 
81 /* L4 caching options */
82 #define L4_0_WB			_L4_CACHEABILITY(0)
83 #define L4_1_WT			_L4_CACHEABILITY(1)
84 #define L4_2_RESERVED		_L4_CACHEABILITY(2)
85 #define L4_3_UC			_L4_CACHEABILITY(3)
86 
87 #define MOCS_ENTRY(__idx, __control_value, __l3cc_value) \
88 	[__idx] = { \
89 		.control_value = __control_value, \
90 		.l3cc_value = __l3cc_value, \
91 		.used = 1, \
92 	}
93 
94 /*
95  * MOCS tables
96  *
97  * These are the MOCS tables that are programmed across all the rings.
98  * The control value is programmed to all the rings that support the
99  * MOCS registers. While the l3cc_values are only programmed to the
100  * LNCFCMOCS0 - LNCFCMOCS32 registers.
101  *
102  * These tables are intended to be kept reasonably consistent across
103  * HW platforms, and for ICL+, be identical across OSes. To achieve
104  * that, for Icelake and above, list of entries is published as part
105  * of bspec.
106  *
107  * Entries not part of the following tables are undefined as far as
108  * userspace is concerned and shouldn't be relied upon.  For Gen < 12
109  * they will be initialized to PTE. Gen >= 12 don't have a setting for
110  * PTE and those platforms except TGL/RKL will be initialized L3 WB to
111  * catch accidental use of reserved and unused mocs indexes.
112  *
113  * The last few entries are reserved by the hardware. For ICL+ they
114  * should be initialized according to bspec and never used, for older
115  * platforms they should never be written to.
116  *
117  * NOTE1: These tables are part of bspec and defined as part of hardware
118  *       interface for ICL+. For older platforms, they are part of kernel
119  *       ABI. It is expected that, for specific hardware platform, existing
120  *       entries will remain constant and the table will only be updated by
121  *       adding new entries, filling unused positions.
122  *
123  * NOTE2: For GEN >= 12 except TGL and RKL, reserved and unspecified MOCS
124  *       indices have been set to L3 WB. These reserved entries should never
125  *       be used, they may be changed to low performant variants with better
126  *       coherency in the future if more entries are needed.
127  *       For TGL/RKL, all the unspecified MOCS indexes are mapped to L3 UC.
128  */
129 #define GEN9_MOCS_ENTRIES \
130 	MOCS_ENTRY(I915_MOCS_UNCACHED, \
131 		   LE_1_UC | LE_TC_2_LLC_ELLC, \
132 		   L3_1_UC), \
133 	MOCS_ENTRY(I915_MOCS_PTE, \
134 		   LE_0_PAGETABLE | LE_TC_0_PAGETABLE | LE_LRUM(3), \
135 		   L3_3_WB)
136 
137 static const struct drm_i915_mocs_entry skl_mocs_table[] = {
138 	GEN9_MOCS_ENTRIES,
139 	MOCS_ENTRY(I915_MOCS_CACHED,
140 		   LE_3_WB | LE_TC_2_LLC_ELLC | LE_LRUM(3),
141 		   L3_3_WB),
142 
143 	/*
144 	 * mocs:63
145 	 * - used by the L3 for all of its evictions.
146 	 *   Thus it is expected to allow LLC cacheability to enable coherent
147 	 *   flows to be maintained.
148 	 * - used to force L3 uncachable cycles.
149 	 *   Thus it is expected to make the surface L3 uncacheable.
150 	 */
151 	MOCS_ENTRY(63,
152 		   LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
153 		   L3_1_UC)
154 };
155 
156 /* NOTE: the LE_TGT_CACHE is not used on Broxton */
157 static const struct drm_i915_mocs_entry broxton_mocs_table[] = {
158 	GEN9_MOCS_ENTRIES,
159 	MOCS_ENTRY(I915_MOCS_CACHED,
160 		   LE_1_UC | LE_TC_2_LLC_ELLC | LE_LRUM(3),
161 		   L3_3_WB)
162 };
163 
164 #define GEN11_MOCS_ENTRIES \
165 	/* Entries 0 and 1 are defined per-platform */ \
166 	/* Base - L3 + LLC */ \
167 	MOCS_ENTRY(2, \
168 		   LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
169 		   L3_3_WB), \
170 	/* Base - Uncached */ \
171 	MOCS_ENTRY(3, \
172 		   LE_1_UC | LE_TC_1_LLC, \
173 		   L3_1_UC), \
174 	/* Base - L3 */ \
175 	MOCS_ENTRY(4, \
176 		   LE_1_UC | LE_TC_1_LLC, \
177 		   L3_3_WB), \
178 	/* Base - LLC */ \
179 	MOCS_ENTRY(5, \
180 		   LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
181 		   L3_1_UC), \
182 	/* Age 0 - LLC */ \
183 	MOCS_ENTRY(6, \
184 		   LE_3_WB | LE_TC_1_LLC | LE_LRUM(1), \
185 		   L3_1_UC), \
186 	/* Age 0 - L3 + LLC */ \
187 	MOCS_ENTRY(7, \
188 		   LE_3_WB | LE_TC_1_LLC | LE_LRUM(1), \
189 		   L3_3_WB), \
190 	/* Age: Don't Chg. - LLC */ \
191 	MOCS_ENTRY(8, \
192 		   LE_3_WB | LE_TC_1_LLC | LE_LRUM(2), \
193 		   L3_1_UC), \
194 	/* Age: Don't Chg. - L3 + LLC */ \
195 	MOCS_ENTRY(9, \
196 		   LE_3_WB | LE_TC_1_LLC | LE_LRUM(2), \
197 		   L3_3_WB), \
198 	/* No AOM - LLC */ \
199 	MOCS_ENTRY(10, \
200 		   LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_AOM(1), \
201 		   L3_1_UC), \
202 	/* No AOM - L3 + LLC */ \
203 	MOCS_ENTRY(11, \
204 		   LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_AOM(1), \
205 		   L3_3_WB), \
206 	/* No AOM; Age 0 - LLC */ \
207 	MOCS_ENTRY(12, \
208 		   LE_3_WB | LE_TC_1_LLC | LE_LRUM(1) | LE_AOM(1), \
209 		   L3_1_UC), \
210 	/* No AOM; Age 0 - L3 + LLC */ \
211 	MOCS_ENTRY(13, \
212 		   LE_3_WB | LE_TC_1_LLC | LE_LRUM(1) | LE_AOM(1), \
213 		   L3_3_WB), \
214 	/* No AOM; Age:DC - LLC */ \
215 	MOCS_ENTRY(14, \
216 		   LE_3_WB | LE_TC_1_LLC | LE_LRUM(2) | LE_AOM(1), \
217 		   L3_1_UC), \
218 	/* No AOM; Age:DC - L3 + LLC */ \
219 	MOCS_ENTRY(15, \
220 		   LE_3_WB | LE_TC_1_LLC | LE_LRUM(2) | LE_AOM(1), \
221 		   L3_3_WB), \
222 	/* Bypass LLC - Uncached (EHL+) */ \
223 	MOCS_ENTRY(16, \
224 		   LE_1_UC | LE_TC_1_LLC | LE_SCF(1), \
225 		   L3_1_UC), \
226 	/* Bypass LLC - L3 (Read-Only) (EHL+) */ \
227 	MOCS_ENTRY(17, \
228 		   LE_1_UC | LE_TC_1_LLC | LE_SCF(1), \
229 		   L3_3_WB), \
230 	/* Self-Snoop - L3 + LLC */ \
231 	MOCS_ENTRY(18, \
232 		   LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_SSE(3), \
233 		   L3_3_WB), \
234 	/* Skip Caching - L3 + LLC(12.5%) */ \
235 	MOCS_ENTRY(19, \
236 		   LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_SCC(7), \
237 		   L3_3_WB), \
238 	/* Skip Caching - L3 + LLC(25%) */ \
239 	MOCS_ENTRY(20, \
240 		   LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_SCC(3), \
241 		   L3_3_WB), \
242 	/* Skip Caching - L3 + LLC(50%) */ \
243 	MOCS_ENTRY(21, \
244 		   LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_SCC(1), \
245 		   L3_3_WB), \
246 	/* Skip Caching - L3 + LLC(75%) */ \
247 	MOCS_ENTRY(22, \
248 		   LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_RSC(1) | LE_SCC(3), \
249 		   L3_3_WB), \
250 	/* Skip Caching - L3 + LLC(87.5%) */ \
251 	MOCS_ENTRY(23, \
252 		   LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_RSC(1) | LE_SCC(7), \
253 		   L3_3_WB), \
254 	/* HW Reserved - SW program but never use */ \
255 	MOCS_ENTRY(62, \
256 		   LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
257 		   L3_1_UC), \
258 	/* HW Reserved - SW program but never use */ \
259 	MOCS_ENTRY(63, \
260 		   LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
261 		   L3_1_UC)
262 
263 static const struct drm_i915_mocs_entry tgl_mocs_table[] = {
264 	/*
265 	 * NOTE:
266 	 * Reserved and unspecified MOCS indices have been set to (L3 + LCC).
267 	 * These reserved entries should never be used, they may be changed
268 	 * to low performant variants with better coherency in the future if
269 	 * more entries are needed. We are programming index I915_MOCS_PTE(1)
270 	 * only, __init_mocs_table() take care to program unused index with
271 	 * this entry.
272 	 */
273 	MOCS_ENTRY(I915_MOCS_PTE,
274 		   LE_0_PAGETABLE | LE_TC_0_PAGETABLE,
275 		   L3_1_UC),
276 	GEN11_MOCS_ENTRIES,
277 
278 	/* Implicitly enable L1 - HDC:L1 + L3 + LLC */
279 	MOCS_ENTRY(48,
280 		   LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
281 		   L3_3_WB),
282 	/* Implicitly enable L1 - HDC:L1 + L3 */
283 	MOCS_ENTRY(49,
284 		   LE_1_UC | LE_TC_1_LLC,
285 		   L3_3_WB),
286 	/* Implicitly enable L1 - HDC:L1 + LLC */
287 	MOCS_ENTRY(50,
288 		   LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
289 		   L3_1_UC),
290 	/* Implicitly enable L1 - HDC:L1 */
291 	MOCS_ENTRY(51,
292 		   LE_1_UC | LE_TC_1_LLC,
293 		   L3_1_UC),
294 	/* HW Special Case (CCS) */
295 	MOCS_ENTRY(60,
296 		   LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
297 		   L3_1_UC),
298 	/* HW Special Case (Displayable) */
299 	MOCS_ENTRY(61,
300 		   LE_1_UC | LE_TC_1_LLC,
301 		   L3_3_WB),
302 };
303 
304 static const struct drm_i915_mocs_entry icl_mocs_table[] = {
305 	/* Base - Uncached (Deprecated) */
306 	MOCS_ENTRY(I915_MOCS_UNCACHED,
307 		   LE_1_UC | LE_TC_1_LLC,
308 		   L3_1_UC),
309 	/* Base - L3 + LeCC:PAT (Deprecated) */
310 	MOCS_ENTRY(I915_MOCS_PTE,
311 		   LE_0_PAGETABLE | LE_TC_0_PAGETABLE,
312 		   L3_3_WB),
313 
314 	GEN11_MOCS_ENTRIES
315 };
316 
317 static const struct drm_i915_mocs_entry dg1_mocs_table[] = {
318 
319 	/* UC */
320 	MOCS_ENTRY(1, 0, L3_1_UC),
321 	/* WB - L3 */
322 	MOCS_ENTRY(5, 0, L3_3_WB),
323 	/* WB - L3 50% */
324 	MOCS_ENTRY(6, 0, L3_ESC(1) | L3_SCC(1) | L3_3_WB),
325 	/* WB - L3 25% */
326 	MOCS_ENTRY(7, 0, L3_ESC(1) | L3_SCC(3) | L3_3_WB),
327 	/* WB - L3 12.5% */
328 	MOCS_ENTRY(8, 0, L3_ESC(1) | L3_SCC(7) | L3_3_WB),
329 
330 	/* HDC:L1 + L3 */
331 	MOCS_ENTRY(48, 0, L3_3_WB),
332 	/* HDC:L1 */
333 	MOCS_ENTRY(49, 0, L3_1_UC),
334 
335 	/* HW Reserved */
336 	MOCS_ENTRY(60, 0, L3_1_UC),
337 	MOCS_ENTRY(61, 0, L3_1_UC),
338 	MOCS_ENTRY(62, 0, L3_1_UC),
339 	MOCS_ENTRY(63, 0, L3_1_UC),
340 };
341 
342 static const struct drm_i915_mocs_entry gen12_mocs_table[] = {
343 	GEN11_MOCS_ENTRIES,
344 	/* Implicitly enable L1 - HDC:L1 + L3 + LLC */
345 	MOCS_ENTRY(48,
346 		   LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
347 		   L3_3_WB),
348 	/* Implicitly enable L1 - HDC:L1 + L3 */
349 	MOCS_ENTRY(49,
350 		   LE_1_UC | LE_TC_1_LLC,
351 		   L3_3_WB),
352 	/* Implicitly enable L1 - HDC:L1 + LLC */
353 	MOCS_ENTRY(50,
354 		   LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
355 		   L3_1_UC),
356 	/* Implicitly enable L1 - HDC:L1 */
357 	MOCS_ENTRY(51,
358 		   LE_1_UC | LE_TC_1_LLC,
359 		   L3_1_UC),
360 	/* HW Special Case (CCS) */
361 	MOCS_ENTRY(60,
362 		   LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
363 		   L3_1_UC),
364 	/* HW Special Case (Displayable) */
365 	MOCS_ENTRY(61,
366 		   LE_1_UC | LE_TC_1_LLC,
367 		   L3_3_WB),
368 };
369 
370 static const struct drm_i915_mocs_entry xehpsdv_mocs_table[] = {
371 	/* wa_1608975824 */
372 	MOCS_ENTRY(0, 0, L3_3_WB | L3_LKUP(1)),
373 
374 	/* UC - Coherent; GO:L3 */
375 	MOCS_ENTRY(1, 0, L3_1_UC | L3_LKUP(1)),
376 	/* UC - Coherent; GO:Memory */
377 	MOCS_ENTRY(2, 0, L3_1_UC | L3_GLBGO(1) | L3_LKUP(1)),
378 	/* UC - Non-Coherent; GO:Memory */
379 	MOCS_ENTRY(3, 0, L3_1_UC | L3_GLBGO(1)),
380 	/* UC - Non-Coherent; GO:L3 */
381 	MOCS_ENTRY(4, 0, L3_1_UC),
382 
383 	/* WB */
384 	MOCS_ENTRY(5, 0, L3_3_WB | L3_LKUP(1)),
385 
386 	/* HW Reserved - SW program but never use. */
387 	MOCS_ENTRY(48, 0, L3_3_WB | L3_LKUP(1)),
388 	MOCS_ENTRY(49, 0, L3_1_UC | L3_LKUP(1)),
389 	MOCS_ENTRY(60, 0, L3_1_UC),
390 	MOCS_ENTRY(61, 0, L3_1_UC),
391 	MOCS_ENTRY(62, 0, L3_1_UC),
392 	MOCS_ENTRY(63, 0, L3_1_UC),
393 };
394 
395 static const struct drm_i915_mocs_entry dg2_mocs_table[] = {
396 	/* UC - Coherent; GO:L3 */
397 	MOCS_ENTRY(0, 0, L3_1_UC | L3_LKUP(1)),
398 	/* UC - Coherent; GO:Memory */
399 	MOCS_ENTRY(1, 0, L3_1_UC | L3_GLBGO(1) | L3_LKUP(1)),
400 	/* UC - Non-Coherent; GO:Memory */
401 	MOCS_ENTRY(2, 0, L3_1_UC | L3_GLBGO(1)),
402 
403 	/* WB - LC */
404 	MOCS_ENTRY(3, 0, L3_3_WB | L3_LKUP(1)),
405 };
406 
407 static const struct drm_i915_mocs_entry dg2_mocs_table_g10_ax[] = {
408 	/* Wa_14011441408: Set Go to Memory for MOCS#0 */
409 	MOCS_ENTRY(0, 0, L3_1_UC | L3_GLBGO(1) | L3_LKUP(1)),
410 	/* UC - Coherent; GO:Memory */
411 	MOCS_ENTRY(1, 0, L3_1_UC | L3_GLBGO(1) | L3_LKUP(1)),
412 	/* UC - Non-Coherent; GO:Memory */
413 	MOCS_ENTRY(2, 0, L3_1_UC | L3_GLBGO(1)),
414 
415 	/* WB - LC */
416 	MOCS_ENTRY(3, 0, L3_3_WB | L3_LKUP(1)),
417 };
418 
419 static const struct drm_i915_mocs_entry pvc_mocs_table[] = {
420 	/* Error */
421 	MOCS_ENTRY(0, 0, L3_3_WB),
422 
423 	/* UC */
424 	MOCS_ENTRY(1, 0, L3_1_UC),
425 
426 	/* WB */
427 	MOCS_ENTRY(2, 0, L3_3_WB),
428 };
429 
430 static const struct drm_i915_mocs_entry mtl_mocs_table[] = {
431 	/* Error - Reserved for Non-Use */
432 	MOCS_ENTRY(0,
433 		   IG_PAT(0),
434 		   L3_LKUP(1) | L3_3_WB),
435 	/* Cached - L3 + L4 */
436 	MOCS_ENTRY(1,
437 		   IG_PAT(1),
438 		   L3_LKUP(1) | L3_3_WB),
439 	/* L4 - GO:L3 */
440 	MOCS_ENTRY(2,
441 		   IG_PAT(1),
442 		   L3_LKUP(1) | L3_1_UC),
443 	/* Uncached - GO:L3 */
444 	MOCS_ENTRY(3,
445 		   IG_PAT(1) | L4_3_UC,
446 		   L3_LKUP(1) | L3_1_UC),
447 	/* L4 - GO:Mem */
448 	MOCS_ENTRY(4,
449 		   IG_PAT(1),
450 		   L3_LKUP(1) | L3_GLBGO(1) | L3_1_UC),
451 	/* Uncached - GO:Mem */
452 	MOCS_ENTRY(5,
453 		   IG_PAT(1) | L4_3_UC,
454 		   L3_LKUP(1) | L3_GLBGO(1) | L3_1_UC),
455 	/* L4 - L3:NoLKUP; GO:L3 */
456 	MOCS_ENTRY(6,
457 		   IG_PAT(1),
458 		   L3_1_UC),
459 	/* Uncached - L3:NoLKUP; GO:L3 */
460 	MOCS_ENTRY(7,
461 		   IG_PAT(1) | L4_3_UC,
462 		   L3_1_UC),
463 	/* L4 - L3:NoLKUP; GO:Mem */
464 	MOCS_ENTRY(8,
465 		   IG_PAT(1),
466 		   L3_GLBGO(1) | L3_1_UC),
467 	/* Uncached - L3:NoLKUP; GO:Mem */
468 	MOCS_ENTRY(9,
469 		   IG_PAT(1) | L4_3_UC,
470 		   L3_GLBGO(1) | L3_1_UC),
471 	/* Display - L3; L4:WT */
472 	MOCS_ENTRY(14,
473 		   IG_PAT(1) | L4_1_WT,
474 		   L3_LKUP(1) | L3_3_WB),
475 	/* CCS - Non-Displayable */
476 	MOCS_ENTRY(15,
477 		   IG_PAT(1),
478 		   L3_GLBGO(1) | L3_1_UC),
479 };
480 
481 enum {
482 	HAS_GLOBAL_MOCS = BIT(0),
483 	HAS_ENGINE_MOCS = BIT(1),
484 	HAS_RENDER_L3CC = BIT(2),
485 };
486 
has_l3cc(const struct drm_i915_private * i915)487 static bool has_l3cc(const struct drm_i915_private *i915)
488 {
489 	return true;
490 }
491 
has_global_mocs(const struct drm_i915_private * i915)492 static bool has_global_mocs(const struct drm_i915_private *i915)
493 {
494 	return HAS_GLOBAL_MOCS_REGISTERS(i915);
495 }
496 
has_mocs(const struct drm_i915_private * i915)497 static bool has_mocs(const struct drm_i915_private *i915)
498 {
499 	return !IS_DGFX(i915);
500 }
501 
get_mocs_settings(const struct drm_i915_private * i915,struct drm_i915_mocs_table * table)502 static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
503 				      struct drm_i915_mocs_table *table)
504 {
505 	unsigned int flags;
506 
507 	memset(table, 0, sizeof(struct drm_i915_mocs_table));
508 
509 	table->unused_entries_index = I915_MOCS_PTE;
510 	if (IS_METEORLAKE(i915)) {
511 		table->size = ARRAY_SIZE(mtl_mocs_table);
512 		table->table = mtl_mocs_table;
513 		table->n_entries = MTL_NUM_MOCS_ENTRIES;
514 		table->uc_index = 9;
515 		table->unused_entries_index = 1;
516 	} else if (IS_PONTEVECCHIO(i915)) {
517 		table->size = ARRAY_SIZE(pvc_mocs_table);
518 		table->table = pvc_mocs_table;
519 		table->n_entries = PVC_NUM_MOCS_ENTRIES;
520 		table->uc_index = 1;
521 		table->wb_index = 2;
522 		table->unused_entries_index = 2;
523 	} else if (IS_DG2(i915)) {
524 		if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0)) {
525 			table->size = ARRAY_SIZE(dg2_mocs_table_g10_ax);
526 			table->table = dg2_mocs_table_g10_ax;
527 		} else {
528 			table->size = ARRAY_SIZE(dg2_mocs_table);
529 			table->table = dg2_mocs_table;
530 		}
531 		table->uc_index = 1;
532 		table->n_entries = GEN9_NUM_MOCS_ENTRIES;
533 		table->unused_entries_index = 3;
534 	} else if (IS_XEHPSDV(i915)) {
535 		table->size = ARRAY_SIZE(xehpsdv_mocs_table);
536 		table->table = xehpsdv_mocs_table;
537 		table->uc_index = 2;
538 		table->n_entries = GEN9_NUM_MOCS_ENTRIES;
539 		table->unused_entries_index = 5;
540 	} else if (IS_DG1(i915)) {
541 		table->size = ARRAY_SIZE(dg1_mocs_table);
542 		table->table = dg1_mocs_table;
543 		table->uc_index = 1;
544 		table->n_entries = GEN9_NUM_MOCS_ENTRIES;
545 		table->uc_index = 1;
546 		table->unused_entries_index = 5;
547 	} else if (IS_TIGERLAKE(i915) || IS_ROCKETLAKE(i915)) {
548 		/* For TGL/RKL, Can't be changed now for ABI reasons */
549 		table->size  = ARRAY_SIZE(tgl_mocs_table);
550 		table->table = tgl_mocs_table;
551 		table->n_entries = GEN9_NUM_MOCS_ENTRIES;
552 		table->uc_index = 3;
553 	} else if (GRAPHICS_VER(i915) >= 12) {
554 		table->size  = ARRAY_SIZE(gen12_mocs_table);
555 		table->table = gen12_mocs_table;
556 		table->n_entries = GEN9_NUM_MOCS_ENTRIES;
557 		table->uc_index = 3;
558 		table->unused_entries_index = 2;
559 	} else if (GRAPHICS_VER(i915) == 11) {
560 		table->size  = ARRAY_SIZE(icl_mocs_table);
561 		table->table = icl_mocs_table;
562 		table->n_entries = GEN9_NUM_MOCS_ENTRIES;
563 	} else if (IS_GEN9_BC(i915)) {
564 		table->size  = ARRAY_SIZE(skl_mocs_table);
565 		table->n_entries = GEN9_NUM_MOCS_ENTRIES;
566 		table->table = skl_mocs_table;
567 	} else if (IS_GEN9_LP(i915)) {
568 		table->size  = ARRAY_SIZE(broxton_mocs_table);
569 		table->n_entries = GEN9_NUM_MOCS_ENTRIES;
570 		table->table = broxton_mocs_table;
571 	} else {
572 		drm_WARN_ONCE(&i915->drm, GRAPHICS_VER(i915) >= 9,
573 			      "Platform that should have a MOCS table does not.\n");
574 		return 0;
575 	}
576 
577 	if (GEM_DEBUG_WARN_ON(table->size > table->n_entries))
578 		return 0;
579 
580 	/* WaDisableSkipCaching:skl,bxt,kbl,glk */
581 	if (GRAPHICS_VER(i915) == 9) {
582 		int i;
583 
584 		for (i = 0; i < table->size; i++)
585 			if (GEM_DEBUG_WARN_ON(table->table[i].l3cc_value &
586 					      (L3_ESC(1) | L3_SCC(0x7))))
587 				return 0;
588 	}
589 
590 	flags = 0;
591 	if (has_mocs(i915)) {
592 		if (has_global_mocs(i915))
593 			flags |= HAS_GLOBAL_MOCS;
594 		else
595 			flags |= HAS_ENGINE_MOCS;
596 	}
597 	if (has_l3cc(i915))
598 		flags |= HAS_RENDER_L3CC;
599 
600 	return flags;
601 }
602 
603 /*
604  * Get control_value from MOCS entry taking into account when it's not used
605  * then if unused_entries_index is non-zero then its value will be returned
606  * otherwise I915_MOCS_PTE's value is returned in this case.
607  */
get_entry_control(const struct drm_i915_mocs_table * table,unsigned int index)608 static u32 get_entry_control(const struct drm_i915_mocs_table *table,
609 			     unsigned int index)
610 {
611 	if (index < table->size && table->table[index].used)
612 		return table->table[index].control_value;
613 	return table->table[table->unused_entries_index].control_value;
614 }
615 
616 #define for_each_mocs(mocs, t, i) \
617 	for (i = 0; \
618 	     i < (t)->n_entries ? (mocs = get_entry_control((t), i)), 1 : 0;\
619 	     i++)
620 
__init_mocs_table(struct intel_uncore * uncore,const struct drm_i915_mocs_table * table,u32 addr)621 static void __init_mocs_table(struct intel_uncore *uncore,
622 			      const struct drm_i915_mocs_table *table,
623 			      u32 addr)
624 {
625 	unsigned int i;
626 	u32 mocs;
627 
628 	drm_WARN_ONCE(&uncore->i915->drm, !table->unused_entries_index,
629 		      "Unused entries index should have been defined\n");
630 	for_each_mocs(mocs, table, i)
631 		intel_uncore_write_fw(uncore, _MMIO(addr + i * 4), mocs);
632 }
633 
mocs_offset(const struct intel_engine_cs * engine)634 static u32 mocs_offset(const struct intel_engine_cs *engine)
635 {
636 	static const u32 offset[] = {
637 		[RCS0]  =  __GEN9_RCS0_MOCS0,
638 		[VCS0]  =  __GEN9_VCS0_MOCS0,
639 		[VCS1]  =  __GEN9_VCS1_MOCS0,
640 		[VECS0] =  __GEN9_VECS0_MOCS0,
641 		[BCS0]  =  __GEN9_BCS0_MOCS0,
642 		[VCS2]  = __GEN11_VCS2_MOCS0,
643 	};
644 
645 	GEM_BUG_ON(engine->id >= ARRAY_SIZE(offset));
646 	return offset[engine->id];
647 }
648 
init_mocs_table(struct intel_engine_cs * engine,const struct drm_i915_mocs_table * table)649 static void init_mocs_table(struct intel_engine_cs *engine,
650 			    const struct drm_i915_mocs_table *table)
651 {
652 	__init_mocs_table(engine->uncore, table, mocs_offset(engine));
653 }
654 
655 /*
656  * Get l3cc_value from MOCS entry taking into account when it's not used
657  * then if unused_entries_index is not zero then its value will be returned
658  * otherwise I915_MOCS_PTE's value is returned in this case.
659  */
get_entry_l3cc(const struct drm_i915_mocs_table * table,unsigned int index)660 static u16 get_entry_l3cc(const struct drm_i915_mocs_table *table,
661 			  unsigned int index)
662 {
663 	if (index < table->size && table->table[index].used)
664 		return table->table[index].l3cc_value;
665 	return table->table[table->unused_entries_index].l3cc_value;
666 }
667 
l3cc_combine(u16 low,u16 high)668 static u32 l3cc_combine(u16 low, u16 high)
669 {
670 	return low | (u32)high << 16;
671 }
672 
673 #define for_each_l3cc(l3cc, t, i) \
674 	for (i = 0; \
675 	     i < ((t)->n_entries + 1) / 2 ? \
676 	     (l3cc = l3cc_combine(get_entry_l3cc((t), 2 * i), \
677 				  get_entry_l3cc((t), 2 * i + 1))), 1 : \
678 	     0; \
679 	     i++)
680 
init_l3cc_table(struct intel_gt * gt,const struct drm_i915_mocs_table * table)681 static void init_l3cc_table(struct intel_gt *gt,
682 			    const struct drm_i915_mocs_table *table)
683 {
684 	unsigned long flags;
685 	unsigned int i;
686 	u32 l3cc;
687 
688 	intel_gt_mcr_lock(gt, &flags);
689 	for_each_l3cc(l3cc, table, i)
690 		if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 50))
691 			intel_gt_mcr_multicast_write_fw(gt, XEHP_LNCFCMOCS(i), l3cc);
692 		else
693 			intel_uncore_write_fw(gt->uncore, GEN9_LNCFCMOCS(i), l3cc);
694 	intel_gt_mcr_unlock(gt, flags);
695 }
696 
intel_mocs_init_engine(struct intel_engine_cs * engine)697 void intel_mocs_init_engine(struct intel_engine_cs *engine)
698 {
699 	struct drm_i915_mocs_table table;
700 	unsigned int flags;
701 
702 	/* Called under a blanket forcewake */
703 	assert_forcewakes_active(engine->uncore, FORCEWAKE_ALL);
704 
705 	flags = get_mocs_settings(engine->i915, &table);
706 	if (!flags)
707 		return;
708 
709 	/* Platforms with global MOCS do not need per-engine initialization. */
710 	if (flags & HAS_ENGINE_MOCS)
711 		init_mocs_table(engine, &table);
712 
713 	if (flags & HAS_RENDER_L3CC && engine->class == RENDER_CLASS)
714 		init_l3cc_table(engine->gt, &table);
715 }
716 
global_mocs_offset(void)717 static u32 global_mocs_offset(void)
718 {
719 	return i915_mmio_reg_offset(GEN12_GLOBAL_MOCS(0));
720 }
721 
intel_set_mocs_index(struct intel_gt * gt)722 void intel_set_mocs_index(struct intel_gt *gt)
723 {
724 	struct drm_i915_mocs_table table;
725 
726 	get_mocs_settings(gt->i915, &table);
727 	gt->mocs.uc_index = table.uc_index;
728 	if (HAS_L3_CCS_READ(gt->i915))
729 		gt->mocs.wb_index = table.wb_index;
730 }
731 
intel_mocs_init(struct intel_gt * gt)732 void intel_mocs_init(struct intel_gt *gt)
733 {
734 	struct drm_i915_mocs_table table;
735 	unsigned int flags;
736 
737 	/*
738 	 * LLC and eDRAM control values are not applicable to dgfx
739 	 */
740 	flags = get_mocs_settings(gt->i915, &table);
741 	if (flags & HAS_GLOBAL_MOCS)
742 		__init_mocs_table(gt->uncore, &table, global_mocs_offset());
743 
744 	/*
745 	 * Initialize the L3CC table as part of mocs initalization to make
746 	 * sure the LNCFCMOCSx registers are programmed for the subsequent
747 	 * memory transactions including guc transactions
748 	 */
749 	if (flags & HAS_RENDER_L3CC)
750 		init_l3cc_table(gt, &table);
751 }
752 
753 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
754 #include "selftest_mocs.c"
755 #endif
756